SEMICONDUCTOR DEVICE

Abstract

Semiconductor device (10), comprising: an oxide insulating layer (120); an oxide semiconductor layer (140) on the oxide insulating layer (120); a gate insulating layer (150) on the oxide insulating layer (120) and the oxide semiconductor layer (140), wherein the gate insulating layer (150) covers the oxide semiconductor layer (140); a gate electrode (160) on the gate insulating layer (150); and a protective insulating layer (170) on the gate insulating layer (150) and the gate electrode (160), wherein the gate insulating layer (150) comprises the following: a first area (150-1) that overlaps the gate electrode (160), and a second area (150-2) that does not overlap the gate electrode (160) and is in contact with the protective insulating layer (170), the oxide insulating layer (120) comprises: a third area (120-1) that overlaps the gate electrode (160), and a fourth area (120-2) that does not overlap the gate electrode (160) and the oxide semiconductor layer (140) and is in contact with the gate insulating layer (150), the oxide semiconductor layer (140) comprises: a channel area (CH) and a source area (S) and a drain area (D) with a higher carrier concentration than the channel area (CH), wherein the source area (S), the drain area (D), the second area (150-2), the fourth area (120-2) and the protective insulating layer (170) each contain an implanted contaminant, a hydrogen concentration of the second range (150-2) is greater than a hydrogen concentration of the first range (150-1), and a hydrogen concentration of the fourth range (120-2) is greater than a hydrogen concentration of the third range (120-1).

Description

TECHNICAL AREA

[0001] One embodiment of the present invention relates to a semiconductor device that uses an oxide semiconductor as a channel. TECHNICAL BACKGROUND

[0002] In recent years, a semiconductor device has been developed in which an oxide semiconductor, such as amorphous silicon, low-temperature polysilicon, and single-crystal silicon, is used for a channel instead of a silicon semiconductor (see, for example, patent literature 1 to 6). A semiconductor device with such an oxide semiconductor can be fabricated with a simple structure and a low-temperature process, similar to a semiconductor device with amorphous silicon. It is known that the semiconductor device containing the oxide semiconductor exhibits a higher field-effect mobility than the semiconductor device containing amorphous silicon. Furthermore, patent literature 7 discloses a semiconductor device with an oxide semiconductor. To improve electrical stability, it is proposed to selectively create regions with increased hydrogen and impurity concentrations in the insulating layers.These areas overlap the source and drain regions to capture hydrogen and thus protect the underlying channel area. CITATION LIST PATENT LITERATURE Patent Literature 1: JP 2021-141 338 A Patent literature 2: JP 2014-099 601 A Patent literature 3: JP 2021-153 196 A Patent literature 4: JP 2018-006 730 A Patent Literature 5: JP 2016-184 771 A Patent Literature 6: JP 2021-108 405 A Patent literature 7: US 2015 / 236 165 A1 SUMMARY OF THE INVENTIONAL PROBLEM

[0003] In an oxide semiconductor, a carrier is generated when hydrogen is trapped in an oxygen defect. Using this mechanism, an oxygen defect is formed in an oxide semiconductor layer within a semiconductor device. Hydrogen is supplied to this oxygen defect, creating a source region and a drain region. These regions are electrically connected to a source electrode and a drain electrode, respectively, and exhibit a higher charge carrier concentration than a channel region within the oxide semiconductor layer. However, when hydrogen diffuses into the channel region of the oxide semiconductor layer, the oxide semiconductor layer no longer functions as a channel. This means that because the threshold voltage in the electrical properties of the semiconductor device changes due to hydrogen diffusion into the channel region, the threshold voltage fluctuations increase, and the fabrication yield of the semiconductor device decreases.Therefore, an oxide containing excess oxygen and capable of trapping hydrogen is used as an insulating layer in contact with the oxide semiconductor layer to prevent hydrogen from entering the channel area.

[0004] However, since the oxide containing excess oxygen acts as an electron trap, the reliability of the semiconductor device containing such an oxide is significantly reduced. Therefore, there is a need for a semiconductor device that can supply hydrogen to the source and drain regions of the oxide semiconductor layer and prevent hydrogen from entering the channel region of the oxide semiconductor layer without reducing reliability.

[0005] In view of the above-mentioned problem, one object of an embodiment of the present invention is to provide a semiconductor device comprising a hydrogen trap region that prevents hydrogen from entering a channel region. SOLUTION TO THE PROBLEM

[0006] The present invention relates to a semiconductor device having the features of claim 1. Advantageous embodiments are defined in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. Fig. Figure 2 is a schematic top view showing a configuration of a semiconductor device according to an embodiment of the present invention. Fig.Figure 3 is a schematic, partially enlarged cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. Fig. Figure 4 is a diagram showing concentration profiles of the ion implantation of an impurity into a second region and a fourth region in a semiconductor device according to an embodiment of the present invention. Fig. Figure 5 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 6 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 7 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 8 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to , an embodiment of the present invention. Fig. Figure 9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 10 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 11 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 12 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig.Figure 13 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 14 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 15 is a schematic cross-sectional view illustrating a hydrogen capture function of a second region and a fourth region in a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 16 is a schematic cross-sectional view illustrating a hydrogen capture function of a second region and a fourth region in a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig.Figure 17 is a schematic cross-sectional view illustrating a hydrogen trapping function of a protective insulating layer in a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 18 is a schematic top view showing a configuration of a semiconductor device according to an embodiment of the present invention. Fig. Figure 19 is a diagram showing the electrical properties of semiconductor devices of Examples 1 and 2. Fig. Figure 20 is a diagram showing concentration profiles of boron during ion implantation carried out in the manufacture of semiconductor devices of Examples 3 to 8. Fig. Figure 21 is a diagram showing concentration profiles of boron during ion implantation carried out in the manufacture of semiconductor devices of Examples 9 to 14. Fig.22A is a diagram showing the electrical properties of semiconductor devices of Examples 3 to 5. Fig. Figure 22B is a diagram showing the electrical properties of semiconductor devices of Examples 6 to 8. Fig. Figure 22C is a diagram showing the electrical properties of the semiconductor devices of Examples 9 to 11. Fig. Figure 22D is a diagram showing the electrical properties of semiconductor devices of Examples 12 to 14. Fig. Figure 23 is a diagram showing the electrical properties of semiconductor devices of comparison examples 1 and 2. Fig. Figure 24 is a diagram showing concentration profiles of boron during ion implantation, which is carried out in the manufacture of semiconductor devices of comparison examples 3 to 5. Fig.Figure 25 is a diagram showing concentration profiles of boron during ion implantation, which is carried out in the manufacture of semiconductor devices of comparison examples 6 to 8. Fig. 26A is a diagram showing the electrical properties of semiconductor devices of comparison examples 3 to 5. Fig. Figure 26B is a diagram showing the electrical properties of semiconductor devices of comparison examples 6 to 8. DESCRIPTION OF EXECUTION FORMS

[0007] Each embodiment of the present invention is described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can readily imagine by modifying the configuration of the embodiment accordingly, while retaining the core of the invention, is of course included within the scope of the present invention. For the sake of clarity, the drawings may be presented schematically with regard to widths, thicknesses, shapes, and the like of the respective sections in comparison to actual embodiments. However, the shape shown is merely an example and does not limit the interpretation of the present invention.In this specification and each of the drawings, the same symbols are assigned to the same components as previously described with reference to the preceding drawings, and a detailed description thereof may be omitted if necessary.

[0008] In this description, a direction from a substrate to an oxide semiconductor layer is referred to as "on" or "above." Conversely, a direction from the oxide semiconductor layer to the substrate is referred to as "below" or "under." As described above, while the expressions "above (on)" or "below (under)" can be used for simplicity, a vertical relationship between the substrate and the oxide semiconductor layer, for example, may be oriented differently from the direction shown in the diagram. In the following description, for instance, the expression "the oxide semiconductor layer on the substrate" simply describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other elements may be located between the substrate and the oxide semiconductor layer."Above" or "below" refers to a stacking order in a structure where multiple layers are stacked. When expressed as a pixel electrode above a semiconductor device, it can refer to a positional relationship where the semiconductor device and the pixel electrode do not overlap in a top view. Conversely, when expressed as a pixel electrode vertically above a semiconductor device, it refers to a positional relationship where the semiconductor device and the pixel electrode overlap in a top view.

[0009] In the description, the terms "film" and "layer" can be used interchangeably.

[0010] In the specification, "display device" refers to a structure configured to display an image using an electro-optic layer. For example, the term "display device" may refer to a display panel containing the electro-optic layer, or it may refer to a structure in which other optical elements (e.g., a polarizing element, a backlight, or a touch panel, etc.) are connected to a display cell. The "electro-optic layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, or an electrophoretic layer, provided there is no technical contradiction.Although the following embodiments describe examples of a liquid crystal display device with a liquid crystal layer and an organic EL display device with an organic EL layer as the display device, the structure of the present embodiment can be applied to the above display device including any electro-optical layer.

[0011] The expressions “α includes A, B, or C”, “α includes one of A, B, and C”, and “α includes one selected from a group consisting of A, B, and C” do not preclude the case that α includes multiple combinations of A to C, unless otherwise specified. Furthermore, these expressions do not preclude the case that α contains other elements.

[0012] Furthermore, the following embodiments can be combined with each other, provided there is no technical contradiction. <Erste Ausführungsform>

[0013] A semiconductor device 10 according to an embodiment of the present invention is described with reference to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 to Fig. 15 described. The semiconductor device 10 can be used, for example, in a display device, an integrated circuit (IC) such as a microprocessor unit (MPU) or a memory circuit. [1. Configuration of the semiconductor device 10]

[0014] A configuration of the semiconductor device 10 according to an embodiment of the present invention is described with reference to the Fig. 1 and Fig. 2 described. Fig.Figure 1 is a schematic cross-sectional view showing a configuration of the semiconductor device 10 according to an embodiment of the present invention. Fig. Figure 2 is a schematic top view showing a configuration of the semiconductor device 10 according to an embodiment of the present invention. In particular, it shows Fig. 1 a cross-sectional view, cut along line AA' of Fig. 2.

[0015] As in Fig.As shown in Figure 1, the semiconductor device 10 comprises a substrate 100, a light-shielding layer 105, a nitride insulating layer 110, an oxide insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a protective insulating layer 170, a source electrode 201, and a drain electrode 203. The light-shielding layer 105 is provided on the substrate 100. The nitride insulating layer 110 is provided on the substrate 100 to cover a top surface and a bottom surface of the light-shielding layer 105. The oxide insulating layer 120 is provided on the nitride insulating layer 110. The oxide semiconductor layer 140 is provided on the oxide insulating layer 120. The gate insulating layer 150 is provided on the second insulating layer 120 to cover an upper surface and an end surface of the oxide semiconductor layer 140.The gate electrode 160 is positioned on the gate insulating layer 150 such that it overlaps the oxide semiconductor layer 140. The protective insulating layer 170 is positioned on the gate insulating layer 150 to cover a top surface and a bottom surface of the gate electrode 160. Openings 171 and 173, through which a portion of the top surface of the oxide semiconductor layer is exposed, are provided in the gate insulating layer 150 and the protective insulating layer 170. The source electrode 201 is positioned on the protective insulating layer 170 and within the opening 171 and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is positioned on the protective insulating layer 170 and within the opening 173 and is in contact with the oxide semiconductor layer 140.Furthermore, if the source electrode 201 and the drain electrode 203 are not specifically distinguished, they may be referred to collectively as source / drain electrode 200.

[0016] The oxide semiconductor layer 140 is subdivided into a source region S, a drain region D, and a channel region CH based on the gate electrode 160. That is, the oxide semiconductor layer 140 comprises the channel region CH, which overlaps the gate electrode 160, and the source region S and the drain region D, which do not overlap the gate electrode 160. In the thickness direction of the oxide semiconductor layer 140, an edge portion of the channel region CH essentially coincides with an edge portion of the gate electrode 160. The channel region CH exhibits semiconductor properties. Both the source region S and the drain region D have conductor properties. Therefore, the electrical conductivities of the source region S and the drain region D are greater than the electrical conductivity of the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the source region S and the drain region D, respectively.the drain region D and are electrically connected to the oxide semiconductor layer 140. Furthermore, the oxide semiconductor layer 140 can have a single-layer structure or a laminated structure.

[0017] As in Fig. As shown in Figure 2, both the light-shielding layer 105 and the gate electrode 160 have a predetermined width in direction D1 and extend orthogonally to direction D1 in direction D2. The width of the light-shielding layer 105 is greater than the width of the gate electrode 160 in direction D1. The channel region CH completely overlaps the light-shielding layer 105. In the semiconductor device 10, direction D1 corresponds to the direction in which current flows from the source electrode 201 to the drain electrode 203 through the oxide semiconductor layer 140. Therefore, the length of the channel region CH in direction D1 is a channel length L, and the width of the channel region CH in direction D2 is a channel width W.

[0018] The substrate 100 can support any layer in the semiconductor device 10. For example, a rigid, transmissive substrate such as a glass, quartz, or sapphire substrate can be used as substrate 100. Alternatively, a rigid, non-transmissive substrate such as a silicon substrate can be used. A flexible, transmissive substrate such as a polyimide resin, acrylic resin, siloxane resin, or fluorinated resin can also be used as substrate 100. To improve the heat resistance of substrate 100, impurities can be incorporated into the resin substrate. Finally, a substrate consisting of a silicon oxide film or a silicon nitride film overlying the rigid or flexible substrate described above can also be used as substrate 100.

[0019] The light-shielding layer 105 can reflect or absorb external light. Since the light-shielding layer 105 has a larger area than the channel region CH of the oxide semiconductor layer 140, as described above, the light-shielding layer 105 can block the penetration of external light into the channel region CH. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or alloys or compounds thereof can be used for the light-shielding layer 105. Furthermore, the light-shielding layer 105 does not necessarily have to contain a metal if conductivity is not required. For example, a black resin matrix can be used for the light-shielding layer 105. Additionally, the light-shielding layer 105 can have a single-layer or a laminated structure.For example, the light shielding layer 105 can have a laminated structure consisting of a red color filter, a green color filter and a blue color filter.

[0020] The nitride insulating layer 110 can prevent the diffusion of impurities contained in the substrate 100 (e.g., sodium, etc.) or of impurities penetrating the oxide semiconductor layer 140 from the outside (e.g., water, etc.). For example, a nitride containing silicon or aluminum is used for the nitride insulating layer 110. In particular, silicon nitride (SiN₂) is used. x ), silicon nitride oxide (SiN x O y ), Aluminum nitride (AlN x ) or aluminium nitride oxide (AlN x O y ) and the like for the nitride insulating layer 110. In addition, the nitride insulating layer 110 can have a single-layer structure or a laminated structure.

[0021] Both the oxide insulating layer 120 and the gate insulating layer 150 comprise a hydrogen trap region and can prevent hydrogen from entering the channel region CH. The details of the hydrogen trap region are described later. For example, an oxide containing silicon or aluminum is used for both the oxide insulating layer 120 and the gate insulating layer 150. In particular, silicon oxide (SiO₂) is used. x ), silicon oxynitride (SiO₂) x N y ), aluminum oxide (AlO x ) or aluminum oxynitride (AlO₂) x N y ) and the like for the oxide insulating layer 120. Both the oxide insulating layer 120 and the gate insulating layer 150 can have a single-layer structure or a laminated structure.

[0022] The protective insulating layer 170 can prevent the diffusion of impurities (e.g., water, etc.) that penetrate the oxide semiconductor layer 140 from the outside. Furthermore, the protective insulating layer 170 can serve as a hydrogen supply source for the source region S and the drain region D. For example, an oxide or nitride containing silicon or aluminum is used for the protective layer 170. In particular, an oxide such as silicon dioxide (SiO₂) is suitable. x ), silicon oxynitride (SiO₂) x N y ), aluminum oxide (AlO x ) or aluminum oxynitride (AlO₂) x N y ) or the nitride such as silicon nitride (SiN x ), silicon nitride oxide (SiN x O y ), Aluminum For the protective layer 170, for example nitride (AlN ) is used. x ) or aluminium nitride oxide (AlN x O y) and the like. The protective layer 170 can have a single-layer structure or a laminated structure. If the protective layer 170 also has a laminated structure, it is preferable that the protective layer 170 has a laminated structure (nitride / oxide) in which the nitride is stacked on the oxide.

[0023] These are silicon oxynitride (SiOxNy) and aluminum oxynitride (AlO₂). x N y ) around oxides that contain a lower proportion (x > y) of nitrogen (N) than oxygen (O). Silicon nitride oxide (SiN) x O y ) and aluminium nitride oxide (AlN x O y ) are nitrides that contain a lower proportion (x > y) of oxygen than nitrogen.

[0024] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys or compounds thereof, can be used for the gate electrode 160, the source electrode 201, and the drain electrode 203. The gate electrode 160, the source electrode 201, and the drain electrode 203 can each have a single-layer or a laminated structure.

[0025] The oxide semiconductor layer 140 can have an amorphous structure or a polycrystalline structure.

[0026] Although a detailed procedure for fabricating the oxide semiconductor layer 140 will be described later, the oxide semiconductor layer 140 can be formed using a sputtering process. The composition of the oxide semiconductor layer 140 formed by sputtering depends on the composition of the sputtering target. In this case, the composition of the metal elements in the oxide semiconductor layer 140 can be specified based on the composition of the metal elements in the sputtering target. Furthermore, if the oxide semiconductor layer 140 has a polycrystalline structure, its composition can be specified by an X-ray diffraction (XRD) method. In particular, the composition of the metal elements in the oxide semiconductor layer 140 can be specified based on the crystal structure and the lattice constant of the oxide semiconductor layer 140 obtained by the XRD method.Furthermore, the composition of the metal elements of the oxide semiconductor layer 140 can also be identified using fluorescence X-ray analysis, EPMA analysis (electron probe microanalyzer), or similar methods. Moreover, the oxygen content of the oxide semiconductor layer 140 is not limited to this, as it changes depending on the conditions of the sputtering process and similar factors. [2. Configuration of the hydrogen trap region]

[0027] A hydrogen trap region is formed in the oxide insulating layer 120 and the gate insulating layer 150. Here, the structures of the oxide insulating layer 120 and the gate insulating layer 150 are described with reference to the Fig. 3 and Fig. 4 described. Fig. Figure 3 is a schematic, partially enlarged cross-sectional view showing a configuration of the semiconductor device 10 according to an embodiment of the present invention. Specifically, it shows Fig. 3 an enlarged cross-sectional view of an area P in Fig. 1. Although, in addition, the area in Fig. As shown in Figure 3 near the drain area D, the area near the source area S also has the same structure as area P.

[0028] The gate insulating layer 150 comprises a first region 150-1 and a second region 150-2. The first region 150-1 is a region that overlaps the gate electrode 160 in the film thickness direction of the gate insulating layer 150 (in the top view of the semiconductor device 10). In other words, the first region 150-1 is a region in contact with the channel region CH of the oxide semiconductor layer 140 and the gate electrode 160. The second region 150-2 is a region that does not overlap the gate electrode 160 and the oxide semiconductor layer 140 in the film thickness direction of the gate insulating layer 150 (or in the top view of the semiconductor device 10). In other words, the second region 150-2 is a region located outside the drain region D of the oxide semiconductor layer 140 and in contact with the protective insulating layer 170 and the oxide insulating layer 120.

[0029] The oxide insulating layer 120 comprises a third region 120-1 and a fourth region 120-2. The third region 120-1 is a region that overlaps the gate electrode 160 in the thickness direction of the oxide insulating layer 120 (or in the top view of the semiconductor device 10). In other words, the third region 120-1 is a region in contact with the channel region CH of the oxide semiconductor layer 140. The fourth region 120-2 is a region that does not overlap the gate electrode 160 and the oxide semiconductor layer 140 in the thickness direction of the oxide insulating layer 120 (or in the top view of the semiconductor device 10). In other words, the fourth region 120-2 is a region that lies outside the drain region D of the oxide semiconductor layer 140 and is in contact with the gate insulating layer 150.

[0030] The first region 150-1 and the third region 120-1 are opposite each other, with the channel region CH of the oxide semiconductor layer 140 lying between them. Furthermore, the second region 150-2 and the fourth region 120-2 are in contact with each other outside the drain region D of the oxide semiconductor layer 140.

[0031] Although the details will be described later, the source region S and the drain region D of the oxide semiconductor layer 140 are formed by ion implantation of an impurity using the gate electrode 160 as a mask. Examples of impurities used include boron (B), phosphorus (P), argon (Ar), nitrogen (N), or similar elements. The ion implantation creates oxygen defects in the source region S and the drain region D of the oxide semiconductor layer 140. The resistance of the source region S and the drain region D is reduced by the trapping of hydrogen in the generated oxygen defects.

[0032] Since ion implantation occurs through the gate insulating layer 150, it creates free bond defects (DB) in the gate insulating layer 150. Ion implantation also creates dangling bond defects (DB) in the oxide insulating layer 120. However, because, as described above, the ion implantation of the contaminant is performed using the gate electrode 160 as a mask, the contaminant is not implanted into the area overlapping the gate electrode 160, and the dangling bond defects (DB) are not created in that area. That is, as described in Fig.As shown in Figure 3, the first region 150-1 and the third region 120-1, which overlap the gate electrode 160, do not contain the dangling bond defects DB. On the other hand, the second region 150-2 and the fourth region 120-2, which do not overlap the gate electrode 160, do contain the dangling bond defects DB. For example, if silicon oxide is used as the gate insulating layer 150 and the oxide insulating layer 120, the dangling bond defects DB are formed from silicon in the second region 150-2 and the fourth region 120-2.

[0033] The dangling bond defects DB in the second region 150-2 and the fourth region 120-2 can trap hydrogen. This means that in the semiconductor device 10, the second region 150-2 and the fourth region 120-2 can act as hydrogen trap regions. Therefore, the hydrogen concentration in the second region 150-2 is higher than the hydrogen concentration in the first region 150-1. Likewise, the hydrogen concentration in the fourth region 120-2 is higher than the hydrogen concentration in the third region 120-1.

[0034] The second compartment 150-2 and the fourth compartment 120-2 contain the impurities implanted by ion implantation. Ion implantation is performed based on the concentration profile of the impurity, and the concentration distribution of the impurity in the second compartment 150-2 and the fourth compartment 120-2 corresponds to this concentration profile. Therefore, the amount of dangling bond defects in the second compartment 150-2 and the fourth compartment 120-2 can be controlled based on the concentration profile.

[0035] Fig. Figure 4 is a diagram showing the concentration profiles of the ion implantation of an impurity in the second region 150-2 and the fourth region 120-2 in the semiconductor device 10 according to an embodiment of the present invention. On the horizontal axis of Fig.4 corresponds to 0 nm of the interface between the second region 150-2 and the fourth region 120-2 (or the interface between the gate insulating layer 150 and the oxide insulating layer 120). The depth of the fourth region 120-2 is shown in the positive direction, and the depth of the second region 150-2 is shown in the negative direction. In other words, the positive direction represents the position of the interface in the fourth region 120-2, and the negative direction represents the position of the interface in the second region 150-2. Fig. Figure 4 shows four different concentration profiles (a) to (d).

[0036] It is necessary to form the dangling bond defects DB with a predetermined number of defects so that the hydrogen trap region functions in such a way as to suppress the entry of hydrogen into the channel region CH of the oxide semiconductor layer 140. Furthermore, it is preferable that the impurity be implanted not only in the gate insulating layer 150, which is located above the oxide semiconductor layer 140, but also in the oxide insulating layer 120, which is located below the oxide semiconductor layer 140, in order to form the dangling bond defects DB. That is, by forming hydrogen trap regions, including the dangling bond defects DB with a predetermined number of defects in the gate insulating layer 150 and the oxide insulating layer 120, the electrical properties of the semiconductor device 10 can be improved.

[0037] A peak value in the concentration profile of the impurity can be found in the second range (150-2) or in the fourth range (120-2). Fig. 4. Concentration profile (a) has a peak value in the second range 150-2 and concentration profiles (b) to (d) have peak values ​​in the fourth range 120-2.

[0038] In the fourth region 120-2, the concentration of the impurity at the position of +16 nm (i.e., the position 16 nm away from the interface in the thickness direction of the oxide insulating layer 120) is greater than or equal to 1×10 18 / cm 3 (see concentration profiles (a) to (d)) and preferably 5×10 18 / cm 3 (see concentration profiles (a) to (c)).

[0039] Furthermore, in the fourth region 120-2, the concentration of the impurity at the position +40 nm (i.e., the position 40 nm away from the interface in the thickness direction of the oxide insulating layer 120) is greater than or equal to 1×10 16 / cm 3 , preferably greater than or equal to 1×10 17 / cm 3 and especially preferably greater than or equal to 1×10 18 / cm 3 . Alone Fig. The concentration profiles shown (a) to (d) meet the above-mentioned requirements.

[0040] Furthermore, in the fourth region 120-2, the concentration of the impurity in the range from 0 nm to +40 nm (i.e., in the range from the interface to the position that is 40 nm away in the thickness direction of the oxide insulating layer 120) is greater than or equal to 1×10 16 / cm 3Preferably, in the fourth region, the concentration of the impurity in the range from 0 nm to +100 nm (i.e., in the region from the interface to the position 100 nm away in the thickness direction of the oxide insulating layer 120) is greater than or equal to 1×10 16 / cm 3 . Even more preferably, in the fourth region, the concentration of the impurity in the range from 0 nm to +150 nm (i.e., in the region from the interface to the position 120–150 nm away in the film thickness direction of the oxide insulating layer) is greater than or equal to 1 × 10 16 / cm 3 . Alone Fig.The concentration profiles shown in (a) to (d) meet the aforementioned ranges. Furthermore, if the thickness of the oxide insulating layer 120 is less than 100 nm, the aforementioned range may exceed the thickness of the oxide insulating layer 120. In this case, the total film thickness of the oxide insulating layer 120 and the nitride insulating layer 110 may lie within the aforementioned ranges. That is, the impurity can be implanted into the nitride insulating layer 110. However, it is preferable to adjust the ion implantation conditions so that the maximum concentration of the impurity in the nitride insulating layer 110 is less than or equal to 1 × 10⁻⁶. 19 / cm 3 is.

[0041] If the concentration of the impurity in the fourth region 120-2 is within the range mentioned above, the dangling bond defects DB with a sufficient defect quantity are formed in the gate insulating layer 150 and the oxide insulating layer 120. That is, since the gate insulating layer 150 and the oxide insulating layer 120 comprise hydrogen trap regions, the electrical properties of the semiconductor device 10 can be improved.

[0042] The configuration of the semiconductor device 10 is described above, and the semiconductor device 10 described above is a so-called top-gate transistor. Various modifications can be made to the semiconductor device 10. For example, if the light-shielding layer 105 is conductive, the semiconductor device 10 can have a configuration in which the light-shielding layer 105 acts as the gate electrode, and the nitride insulating layer 110 and the oxide insulating layer 120 act as gate insulating layers. In this case, the semiconductor device 10 is a so-called dual-gate transistor. Furthermore, if the light-shielding layer 105 is conductive, it can be a floating electrode and can be connected to the source electrode 201.Furthermore, the semiconductor device 10 can be a so-called bottom-gate transistor, in which the light-shielding layer 105 acts as the main gate electrode. [3. Manufacturing process of the semiconductor device 10]

[0043] A method for manufacturing the semiconductor device 10 according to an embodiment of the present invention is described with reference to the Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12 to Fig. 13 described. Fig. Figure 5 is a flowchart showing a method for manufacturing the semiconductor device 10 according to an embodiment of the present invention. Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12 to Fig.Figure 13 are schematic cross-sectional views showing a method for manufacturing the semiconductor device 10 according to an embodiment of the present invention.

[0044] As in Fig. As shown in Figure 5, the method for fabricating the semiconductor device 10 comprises steps S1010 to S1120. Although the following description presents steps S1010 to S1120 in sequence, the order of the steps in the method for fabricating the semiconductor device 10 can be reversed. Furthermore, the method for fabricating the semiconductor device 10 may include additional steps.

[0045] In step S1010, the light shielding layer 105 is formed on the substrate 100 with a predetermined pattern (see Fig. 6) The structuring of the light shielding layer 105 is carried out using a photolithographic process.

[0046] In step S1020, the nitride insulating layer 110 and the oxide insulating layer 120 are formed successively on the light-shielding layer 105 (see Fig. 7) The nitride insulating layer 110 and the oxide insulating layer 120 are deposited using a CVD process. For example, a silicon nitride film and a silicon oxide film are deposited as the nitride insulating layer 110 and the oxide insulating layer 120, respectively. The silicon nitride film and the silicon oxide film can also be formed continuously in the same chamber by changing the reactive gas.

[0047] In a step described later, dangling-bond defects with a hydrogen-trapping function are formed in a predetermined region of the oxide insulating layer 120. Therefore, the oxide insulating layer 120 need not be a film containing excess oxygen that traps hydrogen; and is preferably a dense film with few defects, formed at a temperature of 350 °C or higher. If the oxide insulating layer 120 is a film containing excess oxygen, the reliability of the semiconductor device 10 is reduced. Conversely, the reliability of the semiconductor device 10 can be improved by forming the oxide insulating layer 120 as a dense film.

[0048] For example, the thickness of the nitride insulating layer 110 is greater than or equal to 50 nm and less than or equal to 500 nm, and preferably greater than or equal to 150 nm and less than or equal to 300 nm. Furthermore, for example, the thickness of the oxide insulating layer 120 is greater than or equal to 50 nm and less than or equal to 500 nm, and preferably greater than or equal to 150 nm and less than or equal to 300 nm.

[0049] In step S1030, an oxide semiconductor film 145 is formed on the oxide insulating layer 120 (see Fig. 8) The oxide semiconductor film 145 is deposited by a sputtering process. For example, the thickness of the oxide semiconductor film 145 is greater than or equal to 10 nm and less than or equal to 100 nm, preferably greater than or equal to 15 nm and less than or equal to 70 nm, and even more preferably greater than or equal to 15 nm and less than or equal to 40 nm.

[0050] The oxide semiconductor film 145 in step S1030 is amorphous. When the oxide semiconductor film 145 is formed by the sputtering process, it is deposited while the temperature of the object to be deposited (the substrate 100 and the layers formed thereon) is controlled to less than or equal to 100 °C, preferably less than or equal to 80 °C, and more preferably less than or equal to 50 °C. Furthermore, the oxide semiconductor film 145 is deposited under the condition of a low oxygen partial pressure. The oxygen partial pressure is greater than or equal to 2% and less than or equal to 20%, preferably greater than or equal to 3% and less than or equal to 15%, and particularly preferably greater than or equal to 3% and less than or equal to 10%.

[0051] In step S1040, the oxide semiconductor film 145 is structured (see Fig.9) The structuring of the oxide semiconductor film 145 is carried out using a photolithography process. Wet or dry etching can be used to etch the oxide semiconductor film 145. Wet etching can be performed with an acidic etchant. Examples of suitable etchants include oxalic acid, PAN, sulfuric acid, hydrogen peroxide solution, hydrofluoric acid, or similar substances.

[0052] In step S1050, a heat treatment is performed on the oxide semiconductor layer 145. Hereinafter, the heat treatment performed in step S1050 is referred to as "OS annealing." During OS annealing, the oxide semiconductor film 145 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is higher than or equal to 300 °C and lower than or equal to 500 °C, and preferably higher than or equal to 350 °C and lower than or equal to 450 °C. Furthermore, the holding time at the target temperature is more than or equal to 15 minutes and less than or equal to 120 minutes, and preferably more than or equal to 30 minutes and less than or equal to 60 minutes. The oxide semiconductor film 145 is crystallized by OS annealing to form the oxide semiconductor layer 140 with a polycrystalline structure.

[0053] In step S1060, the gate insulating layer 150 is deposited on the oxide semiconductor layer 140 (see Fig. 10) The gate insulating layer 150 is deposited using the CVD process. For example, silicon dioxide is deposited for the gate insulating layer 150. To reduce defects in the gate insulating layer 150, the gate insulating layer 150 can be deposited at a deposition temperature of more than or equal to 350 °C. The thickness of the gate insulating layer 150 is greater than or equal to 50 nm and less than or equal to 300 nm, preferably greater than or equal to 60 nm and less than or equal to 200 nm, and even more preferably greater than or equal to 70 nm and less than or equal to 150 nm.

[0054] In step S1070, a heat treatment is performed on the oxide semiconductor layer 140. The heat treatment performed in step S100 is subsequently referred to as "oxidation annealing." When the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen defects are created on the top and side surfaces of the oxide semiconductor layer 140. During oxidation annealing, oxygen is supplied to the oxide semiconductor layer 140 through the oxide insulating layer 120 and the gate insulating layer 150, and the oxygen defects are repaired.

[0055] In step S1080, the gate electrode 160 is formed with a predetermined pattern on the gate insulating layer 150 (see Fig. 11) The gate electrode 160 is deposited by the sputtering process or an atomic layer deposition process and the structuring of the gate electrode 160 is carried out using the photolithographic process.

[0056] In step S1090, the source region S and the drain region D are formed in the oxide semiconductor layer 140 (see Fig.12) The source region S and the drain region D are formed by ion implantation. Ion implantation can be performed using an ion doping device or an ion implantation device. Specifically, an impurity is implanted through the gate insulating layer 150 into the oxide semiconductor layer 140 using the gate electrode 160 as a mask. Examples of implanted impurities include boron (B), phosphorus (P), argon (Ar), nitrogen (N), or the like. Ion implantation in the source region S and the drain region D creates oxygen vacancies that do not overlap the gate electrode 160, allowing hydrogen to be trapped in these oxygen vacancies. This reduces the resistance of the source region S and the drain region D.On the other hand, no contamination is implanted in the channel area CH, which overlaps the gate electrode 160, so that no oxygen deficiencies are created and the resistance of the channel area CH does not decrease.

[0057] Furthermore, in step S1090, the contaminant is also implanted through the gate insulating layer 150 into the oxide insulating layer 120. The dangling bond defects DB are created in the gate insulating layer 150 and the oxide insulating layer 120 by ion implantation. In addition, the gate insulating layer 150 and the oxide insulating layer 120 contain contaminants such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N).

[0058] In step S1100, the protective insulating layer 170 is formed on the gate insulating layer 150 and the gate electrode 160 (see Fig.13) The protective insulating layer 170 is deposited using the CVD process. For example, a silicon oxide film and a silicon nitride film are deposited as the protective insulating layer 170. The thickness of the protective insulating layer 170 is greater than or equal to 50 nm and less than or equal to 500 nm.

[0059] Here, steps S1090 and S1100 are described with reference to the Fig. 15 and Fig. 16 described in more detail. Fig. 15 and Fig. Figure 16 are schematic cross-sectional views illustrating the hydrogen trap function of the second region 150-2 and the fourth region 120-2 in the method for manufacturing the semiconductor device 10 according to an embodiment of the present invention.

[0060] As in Fig.Figure 15 shows that when step S1090 is executed, the second region 150-2 and the fourth region 120-2 are formed in Figure 15, containing dangling bond defects DB in the gate insulating layer 150 and the oxide insulating layer 120, respectively. The position and number of dangling bond defects DB can be controlled by adjusting the parameters of the ion implantation process (e.g., dose, acceleration voltage, plasma power, etc.). Although the dose is greater than or equal to 1 × 10 14 / cm 2 , preferably greater than or equal to 5×10 14 / cm 2 and even more preferably greater than or equal to 1×10 15 / cm 2The dose quantity is not limited to this area. Furthermore, the accelerating voltage is greater than 10 keV, preferably greater than or equal to 15 keV, and particularly preferably greater than or equal to 20 keV. In the second region 150-2 and the fourth region 120-2, the free bond defects DB can trap hydrogen. That is, the second region 150-2 and the fourth region 120-2 can act as hydrogen trap regions.

[0061] To prevent the diffusion of external contaminants, the protective insulating layer 170 is preferably a dense film with few defects, which form at a temperature of 350 °C or higher. The protective insulating layer 170 deposited under the conditions described above typically contains a large amount of hydrogen. Since the film formation temperature is high, hydrogen also diffuses into the gate insulating layer 150 during the formation of the protective insulating layer 170. Therefore, if a hydrogen trap region is not formed, at least in the gate insulating layer 150, hydrogen diffuses not only into the source region S and the drain region D of the oxide semiconductor layer 140, but also through the gate insulation into the channel region CH of layer 150.

[0062] As in Fig.Figure 16 shows that in step S1100, the second region 150-2 and the fourth region 120-2 are formed in the gate insulating layer 150 and the oxide insulating layer 120, respectively. The dangling bond defects DB in the second region 150-2 and the fourth region 120-2 trap hydrogen that diffuses from the protective insulating layer 170 during its deposition. Therefore, the entry of hydrogen into the channel region CH of the oxide semiconductor layer 140 can be suppressed in step S1100. Furthermore, since a dense hydrogen-containing film can be used as the protective insulating layer 170, a sufficient amount of hydrogen can be supplied to the source region S and the drain region D with oxygen defects.

[0063] As described above, in step S1090, hydrogen trap regions are formed in the gate insulating layer 150 and the oxide insulating layer 120, thus suppressing the entry of hydrogen into the channel region CH after step S1100. Conversely, the oxygen defects in the source region S and the drain region D can be supplied with a sufficient amount of hydrogen. Since process-related variations are reduced, variations in the electrical properties of the semiconductor device 10 can therefore be suppressed. In other words, the manufacturing yield of the semiconductor device 10 is improved.

[0064] Back to Fig. The steps following step S1110 are now described.

[0065] In step S1110, the opening sections 171 and 173 are formed in the gate insulating layer 150 and the protective insulating layer 170 (see Fig.14). The source region S and the drain region D of the oxide semiconductor layer 140 are exposed by forming the opening sections 171 and 173.

[0066] In step S1120, the source electrode 201 is formed on the protective insulating layer 170 and within the opening 171, and the drain electrode 203 is formed on the protective insulating layer 170 and within the opening 173. The source electrode 201 and the drain electrode 203 are formed as the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by structuring a deposited conductive film. The above steps result in the Fig. 1 Semiconductor device 10 shown was manufactured.

[0067] Although the method for manufacturing the semiconductor device 10 has been described above, the method for manufacturing the semiconductor device 10 is not limited to this method. For example, it may include a step of implanting an impurity into the protective insulating layer 170. Here, the step of implanting an impurity into the protective insulating layer 170 is described with reference to Fig. 17 described. Fig. Figure 17 is a schematic cross-sectional view illustrating a hydrogen trapping function of the protective insulating layer 170 in a method for manufacturing the semiconductor device 10 according to an embodiment of the present invention.

[0068] As in Fig.As shown in Figure 17, when an impurity is implanted into the protective insulating layer 170, free bond defects DB are formed in the protective insulating layer 170. In this case, hydrogen is not only trapped in the dangling bond defects DB in the second region 150-2 and the fourth region 120-2, but also in the dangling bond defects DB in the protective insulating layer 170. That is, the protective insulating layer 170 has the function of trapping hydrogen. Therefore, hydrogen contained in the protective insulating layer 170 can be trapped by the free bond defects DB in the protective insulating layer 170, and it can be prevented from diffusing hydrogen into the gate insulating layer 150. In addition, the protective insulating layer 170 can also trap hydrogen that penetrates the protective insulating layer 170 from the outside.By preventing hydrogen from diffusing into the CH channel area, the reliability of the semiconductor device 10 is further improved.

[0069] In the semiconductor device 10 according to the present embodiment, hydrogen trap regions are formed in the gate insulating layer 150 above the oxide semiconductor layer 140 and in the oxide insulating layer 120 below the oxide semiconductor layer 140. Therefore, in the semiconductor device 10, the entry of hydrogen into the channel region CH of the oxide semiconductor layer 140 can be suppressed. Since the carrier concentration in the channel region CH can thus be sufficiently reduced, fluctuations in the threshold voltage in the electrical properties of the semiconductor device 10 can be suppressed. <Zweite Ausführungsform>

[0070] A semiconductor device 10A according to an embodiment of the present invention is described with reference to Fig. 18 described. Fig.Figure 18 is a schematic top view showing a configuration of the semiconductor device 10A according to one embodiment of the invention. If the configuration of the semiconductor device 10A is identical to the configuration of the semiconductor device 10, the description of the configuration of the semiconductor device 10A can be omitted.

[0071] As in Fig.As shown in Figure 18, the semiconductor device 10A comprises a light-shielding layer 105A, an oxide semiconductor layer 140A, a gate electrode 160A, a source electrode 201A, and a drain electrode 203A. A nitride insulating layer and an oxide insulating layer are formed between the light-shielding layer 105A and the oxide semiconductor layer 140A. A gate insulating layer is formed between the oxide semiconductor layer 140A and the gate electrode 160A. A protective insulating layer is formed between the gate electrode 160A and the source electrode 201A as well as the drain electrode 203A. Since the nitride insulating layer, the oxide insulating layer, the gate insulating layer and the protective insulating layer are the same as the nitride insulating layer 110, the oxide insulating layer 120, the gate insulating layer 150 and the protective insulating layer 170 in the first embodiment, their description is omitted.

[0072] Openings 171A and 173A are provided in the gate insulating layer and the protective insulating layer. The source electrode 201A is electrically connected via opening 171A to the source region S of the oxide semiconductor layer 140A. Similarly, the drain electrode 203A is electrically connected via opening 173A to the drain region D of the oxide semiconductor layer 140A. The planar shape of the gate electrode 160A on the oxide semiconductor layer 140A is a U-shape. In the top view, the source electrode 201A is located inside the U-shape and the drain electrode 203A is located outside the U-shape. In the channel region CH, the width of the gate electrode 160A corresponds to the channel length L, and the length along the U-shape of the gate electrode 160A corresponds to the channel width W. As shown in Fig. As shown in Figure 18, the current in the semiconductor device 10A can be increased because the channel width W can be made larger than the channel length L.

[0073] In semiconductor device 10A, ion implantation of the impurity through the gate insulating layer is also carried out using the gate electrode 160A as a mask to form a hydrogen trap region in the gate insulating layer and the oxide insulating layer. Since hydrogen penetration into the oxide semiconductor layer 140A can be prevented, the fluctuations in the electrical properties of semiconductor device 10A are small. In particular, fluctuations in the threshold voltage in the electrical properties can be suppressed. [Examples]

[0074] The semiconductor device 10 is described in more detail using the manufactured samples. [1. Difference due to the presence or absence of ion implantation][1-1. Preparation of example samples]

[0075] For samples of Examples 1 and 2, semiconductor devices were fabricated using the fabrication method described in the first embodiment. That is, in Examples 1 and 2, the ion implantation of boron through the gate insulating layer 150 was carried out during the fabrication of the semiconductor device. Although the oxide semiconductor layer of Example 1 had an amorphous structure before OS annealing, the oxide semiconductor layer was crystallized after OS annealing and had a polycrystalline structure. The oxide semiconductor layer of Example 2 also had an amorphous structure after OS annealing. [1-2. Sample preparation for comparison samples]

[0076] For samples from Comparative Example 1 and Comparative Example 2, semiconductor devices were fabricated using the manufacturing process described in the first embodiment without ion implantation. The oxide semiconductor layer of Comparative Example 2 had an amorphous structure. [1-3. Electrical properties]

[0077] Fig. Figure 19 is a diagram showing the electrical properties of the semiconductor devices of Examples 1 and 2. Fig. Figure 23 is a diagram showing the electrical properties of the semiconductor devices in comparison examples 1 and 2. Each of the graphs in the Fig. 19 and Fig. Figure 23 shows the electrical properties of 26 samples with channel width W / channel length L = 4.5 µm / 3.0 µm. In the graph showing the electrical properties, the vertical axis represents the drain current Id and the horizontal axis the gate voltage Vg. Table 1 shows the measurement conditions for the electrical properties of each sample. [Table 1] Source-drain voltage 0.1 V (dashed line), 10 V (solid line) Gate voltage -15 V to +15 V Measurement environment Room temperature, darkroom

[0078] As from Fig. As can be seen in section 19, electrical properties with small fluctuations in the threshold voltage were obtained for the samples in Examples 1 and 2. On the other hand, as in Fig.As shown in Figure 23, the threshold voltage shifted to the negative side in the samples from Comparison Example 1, and electrical properties with large fluctuations were observed. Furthermore, the threshold voltage in the gate voltage range of -15 V to +15 V could not be confirmed for the sample from Comparison Example 2.

[0079] As from the Fig. 19 and Fig.As shown in Figure 23, regardless of whether the oxide semiconductor layer has a polycrystalline or amorphous structure, when ion implantation is performed through the gate insulating layer, the electrical properties indicate that switching performance is achieved with a sharp increase in current at a gate voltage near 0 V. Conversely, if ion implantation is not performed through the gate insulating layer, the electrical properties that demonstrate switching performance cannot be obtained. This appears to be the reason why the insulating properties of the channel region are reduced due to the increase in charge carrier concentration in the channel region of the oxide semiconductor layer. In contrast to the samples in Examples 1 and 2, no hydrogen trap regions are formed in the gate insulating layer and the oxide semiconductor layer by ion implantation in the samples of Comparison Examples 1 and 2.Therefore, it is assumed that hydrogen readily penetrates the gate insulating layer and the oxide insulating layer into the channel region of the oxide semiconductor layer. The incoming hydrogen is trapped by the oxygen defects in the channel region and generates charge carriers, thus increasing the charge carrier concentration in the channel region. [2. Differences due to ion implantation conditions][2-1. Preparation of example samples]

[0080] Semiconductor devices were fabricated using the manufacturing process described in the first embodiment, as shown in Examples 3 to 14. The samples in Examples 3 to 8 have structure A. The samples in Examples 9 to 14 have structure B. The conditions for structure A and structure B are listed in Table 2. [Table 2] Structure A Structure B Nitride insulating layer 300nm 200 nm oxide insulating layer 200 nm 100 nm oxide semiconductor layer 30nm 15nm Gate insulating layer 100nm 125nm

[0081] Table 3 shows the conditions for the ion implantation of boron through the gate insulating layer. Fig. 20 and Fig. Figure 21 shows concentration profiles of boron in each sample. Fig. Figure 20 is a diagram showing concentration profiles of boron during ion implantation carried out in the manufacture of semiconductor devices of Examples 3 to 8. Fig. Figure 21 is a diagram showing boron concentration profiles during ion implantation performed in the fabrication of semiconductor devices of Examples 9 to 14. Furthermore, the Fig. 20 and Fig.21 the horizontal axis of the diagrams represents the distance from the interface between the gate insulating layer and the oxide insulating layer when the interface is 0 nm (the side of the oxide insulating layer points in the positive direction and the side of the gate insulating layer points in the negative direction) and the vertical axis of the diagram represents the boron concentration. [Table 3] Dosage Acceleration voltage Example 3, Example 9 1×10 14 / cm 2 20 keV Example 4, Example 10 5×10 14 / cm 2 20 keV Example 5, Example 11 1×10 15 / cm 2 20 keV Example 6, Example 12 1×10 14 / cm 2 29 keV Example 7, Example 13 5×10 14 / cm 2 29 keV Example 8, Example 14 1×10 15 / cm 2 29 keV

[0082] The concentration profiles of samples from Examples 3 to 5 show peaks in the gate insulating layer. The concentration profiles of samples from Examples 6 to 14 show peaks in the oxide insulating layer. In samples from Examples 3 to 14, the boron concentration in the oxide insulating layer at a position 16 nm from the interface between the gate insulating layer and the oxide insulating layer, in the thickness direction of the oxide insulating layer, was greater than or equal to 1 × 10⁻⁶. 16 / cm 3Furthermore, in the samples of Examples 3 to 14, the concentration of boron in the oxide insulating layer at a position 40 nm away from the interface between the gate insulating layer and the oxide insulating layer in the thickness direction of the oxide insulating layer was greater than or equal to 1 × 10 17 / cm 3 Therefore, in the samples of Examples 3 to 14, the boron concentration in the region from the interface between the gate insulating layer and the oxide insulating layer to the position 40 nm away in the film thickness direction of the oxide insulating layer was greater than or equal to 1 × 10 10 / cm 3 .

[0083] The boron concentration in the oxide insulating layer is described in more detail. In the samples of Examples 3 to 14, the boron concentration in the oxide insulating layer at a position 16 nm from the interface between the gate insulating layer and the oxide insulating layer, in the thickness direction of the oxide insulating layer, is greater than or equal to 5 × 10⁻⁶. 18 / cm 3 In particular, in the samples of Examples 4, 5, 7, 8, 10, 11, 13 and 14, the boron concentration in the oxide insulating layer at a position 16 nm away from the interface between the gate insulating layer and the oxide insulating layer in the thickness direction of the oxide insulating layer was greater than or equal to 2 × 10 19 / cm 3Furthermore, in the samples of Examples 3 to 14, the concentration of boron in the oxide insulating layer at a position 40 nm away from the interface between the gate insulating layer and the oxide insulating layer in the thickness direction of the oxide insulating layer is greater than or equal to 1 × 10 18 / cm 3 In particular, in the samples of Examples 4, 5, 7, 8, 13 and 14, the concentration of boron in the oxide insulating layer at a position 40 nm away from the interface between the gate insulating layer and the oxide insulating layer, in the thickness direction of the oxide insulating layer, was greater than or equal to 2 × 10 19 / cm 3 Furthermore, in the samples of Examples 3 to 8 and 12 to 14, the concentration of boron in the oxide insulating layer at a position 100 nm away from the interface between the gate insulating layer and the oxide insulating layer in the thickness direction of the oxide insulating layer was greater than or equal to 1 × 10 16 / cm3 In particular, in Examples 6 to 8, the concentration of boron in the region from the interface between the gate insulating layer and the oxide insulating layer to the position 150 nm away in the thickness direction of the oxide insulating layer is greater than or equal to 1×10 16 / cm 3 . [2-2. Preparation of samples of comparative examples]

[0084] Semiconductor devices were fabricated under different ion implantation conditions than those of Examples 3 to 14 for the comparison examples 3 to 8. The structures and ion implantation conditions of the samples in comparison examples 3 to 8 are shown in Table 4. Furthermore, Fig. 24 and Fig. Figure 25 shows concentration profiles of boron in each sample. Fig.Figure 24 is a diagram showing a boron concentration profile during ion implantation, which is carried out in the fabrication of the semiconductor devices of comparison examples 3 to 5. Fig. Figure 25 is a diagram showing a boron concentration profile during ion implantation, which is carried out in the fabrication of the semiconductor devices in comparative examples 6 to 8. This is further explained in the Fig. 24 and Fig. 25 the horizontal axis of the diagrams represents the distance from the interface between the gate insulating layer and the oxide insulating layer when the interface is 0 nm (the side of the oxide insulating layer points in the positive direction and the side of the gate insulating layer points in the negative direction) and the vertical axis of the diagram represents the boron concentration. [Table 4] structure Dosage Acceleration voltage Comparative example 3 Structure A 1×10 14 / cm 2 10 keV Comparative example 4 Structure.A 5×10 14 / cm 2 10 keV Comparative example 5 Structure A 1×10 15 / cm 2 10 keV Comparative example 6 Structure B 1×10 14 / cm 2 10 keV Comparative example 7 Structure B 5×10 14 / cm 2 10 keV Comparative example 8 Structure B 1×10 15 / cm 2 10 keV

[0085] The concentration profiles of the samples in comparison examples 3 to 8 show peaks in the gate insulating layer. In the samples of comparison examples 3 to 5, the boron concentration in the oxide insulating layer at a position 16 nm from the interface between the gate insulating layer and the oxide insulating layer, in the thickness direction of the oxide insulating layer, is greater than, less than, or equal to 1 × 10⁻⁶. 17 / cm 3 and smaller than 5×10 18 / cm 3 In the samples of comparison examples 6 to 8, the concentration of boron in the oxide insulating layer at a position 16 nm away from the interface between the gate insulating layer and the oxide insulating layer in the thickness direction of the oxide insulating layer is less than 1 × 10 16 / cm 3Furthermore, in the samples of comparison examples 3 to 8, the concentration of boron in the oxide insulating layer at a position 40 nm away from the interface between the gate insulating layer and the oxide insulating layer in the thickness direction of the oxide insulating layer was less than 1×10 16 / cm 3 Therefore, in the samples of comparison examples 3 to 8, the boron concentration in the region from the interface between the gate insulating layer and the oxide insulating layer to the position 40 nm away in the film thickness direction of the oxide insulating layer is not greater than or equal to 1 × 10 16 / cm 3 . [2-3. Electrical properties]

[0086] Fig. Figures 22A to 22D are diagrams showing electrical properties of the semiconductor devices of Examples 3 to 14. Fig. 26A and Fig.Figure 26B contains diagrams showing the electrical properties of the semiconductor devices in comparison examples 3 to 8. Each of the graphs in the Fig. Figures 22A to 22D, 26A and 26B show the electrical properties of 26 samples with a channel width W / channel length L = 4.5 µm / 3.0 µm. The conditions for measuring the electrical properties of each sample are the same as in Table 1.

[0087] As from the Fig. As can be seen from 22A to 22D, transistor characteristics with small fluctuations in the threshold voltage were obtained in the samples of Examples 3 to 14. On the other hand, as can be seen from the Fig. 26A and Fig. As can be seen from 26B, the threshold voltage shifted to the negative side in the samples of comparison examples 3 to 8, and electrical properties with large fluctuations were obtained.

[0088] According to the results as in the Fig.As shown in Figures 22A to 22D, 26A, and 26B, when ion implantation is performed through the gate insulating layer, boron is implanted not only into the gate insulating layer but also to a certain depth into the oxide insulating layer. This allows fluctuations in the threshold voltage of the semiconductor device to be suppressed. In the samples of Examples 3 to 14, the hydrogen trap regions are formed deeper in the oxide insulating layer than in the samples of Comparative Examples 3 to 8. Therefore, it is assumed that the penetration of hydrogen into the channel region of the oxide semiconductor layer is suppressed by the oxide insulating layer.

[0089] Each of the embodiments described above as embodiments of the present invention can be appropriately combined and implemented, provided that no contradiction arises. REFERENCE MARK LIST

[0090] 10, 10A: Semiconductor device, 100: Substrate, 105, 105A: Light shielding layer, 110: Nitride insulating layer, 120: Oxide insulating layer, 120-1: Third region, 120-2: Fourth region, 140, 140A: Oxide semiconductor layer, 145: Oxide semiconductor film, 150: Gate insulating layer, 150-1: First region, 150-2: Second region, 160, 160A: Gate electrode, 170: Protective insulating layer, 171, 171A: Opening section, 173, 173A: Opening section, 200: Source / drain electrode, 201, 201A: Source electrode, 203, 203A: Drain electrode

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