CACHE SYSTEM AND METHOD

Abstract

A cache system 110 is provided for a system having a CPU 102 and a memory 200, wherein the CPU has a stack pointer register 108 for storing a stack pointer, the stack pointer representing an address in main memory 200 at the top of the stack. The cache system 110 includes a cache memory 116 structured into cache lines and cache controller circuitry operable to: Receiving the stack pointer (SP), storing a first cache line containing the contents of a first address range of bytes of main memory, the first address range containing the stack pointer; and locking the first cache line to protect the first cache line from cache eviction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the use of a cache and a processor system that uses a cache. BACKGROUND

[0002] Modern processors use processor cores that access data from memory using a cache. The purpose of the cache is to maintain CPU performance by accelerating access to frequently used data. The cache is a fast memory. Specific data from main memory is stored in the cache so that it can be accessed more quickly than data stored in main memory. The cache size is limited and organized as a set of lines, each of a fixed size.

[0003] The cache may use a cache controller, also simply referred to as a "controller," which reads data from main memory into the cache as needed. Typically, a line of data must be removed from the cache to make room for a new line of data.

[0004] CPU performance depends heavily on cache operation because accessing data causes a performance loss when it has to be read from slow main memory. SUMMARY

[0005] In one example, a cache system is provided for a processor having a stack pointer register for storing a stack pointer, the stack pointer being a main memory address of the top of a stack, comprising: a cache memory structured in cache lines; and a cache controller circuitry operable to: Receiving the stack pointer (SP), Storing a first cache line containing the contents of a first address range of bytes of the main memory, the first address range containing the stack pointer address; and Lock the first cache line to protect the first cache line from cache eviction.

[0006] Note that the stack pointer can point to an address in the device's address space, meaning the address is an address in main memory. By storing a cache line of data containing the data at the address pointed to by the stack pointer, the contents of the stack can be quickly accessed in the cache without having to load the data from main memory. By locking this line of data, this line of data remains in the cache even if it would otherwise have been replaced.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various illustrated examples may be combined, provided they are not mutually exclusive. Fig. 1 illustrates a system including a CPU, a cache, and a memory; Fig. 2 illustrates different parts of a memory address; Fig. 3 illustrates a tag memory; Fig. 4 illustrates a cache line of data; and Fig. Figure 5 illustrates a hardware circuit in a cache controller. DETAILED DESCRIPTIONData Cache

[0009] In one example, a computer system 100 includes a CPU 102. The CPU includes registers 106 that can be accessed very quickly but are of limited size. Thus, a main memory 200 is also provided. The CPU includes a load / store interface 104 connected to a cache 110 by a number of interconnects 118. The cache 110 includes a cache controller 112, a tag RAM 114, and a cache RAM 116. The cache 110 is connected to the main memory 200 by bus 210.

[0010] The cache RAM 116 contains a number of cache lines 400 of data, with each cache line of data containing a number of data words. For example, each data word may contain 32 bits, and each cache line of data may contain 32 such words. In this case, 5 bits are required to identify each individual word within the cache line (2 5 = 32); these five bits can be referred to as the word address.

[0011] Interconnects 118 include an address line 220, a read / write line 222, and an enable line 224, all connected to be driven by the load / store interface. The interconnects also include a data write line 226 and a data read line 228. Note that although address line 220, write line 226, and read line 228 are schematically shown as single lines, they may actually be a plurality of lines, for example, 32 lines in parallel, to carry a 32-bit data item or address.

[0012] To access the contents of memory 200, which may contain either program code or data, CPU 102 outputs an address, for example, a 32-bit address, on address line 220. The CPU also controls read / write line 222 to indicate whether to read or write the contents of this address. The CPU also controls enable line 224 to release the cache.

[0013] At least some, typically most, possible memory locations in main memory 200 are cacheable memory locations, meaning that the data stored in main memory 200 at that memory location can be stored in cache 110 for faster access. When CPU 102 accesses a cacheable memory location for a write or read, the request may be issued through CPU load / store interface 104 and received by cache controller 112. Cache controller 112 checks the memory address to determine if the addressed location already exists in the cache (cache lookup).

[0014] In one example, the memory address 210 in the memory 200 is divided into a tag portion 250, an index portion 252, and a byte address portion 254, see Fig. 2. For example, the 16 most significant bits of the memory address may represent the tag portion 250, the next 11 bits the index portion 252, and the remaining 5 bits the write address portion 254, the latter representing the location within a cache line. Note that these 5 bits correspond to the location within the cache line, i.e., the word address. Cache controller 112 calculates a tag RAM address from the index portion 250 of memory address 210 and compares the contents of this portion of tag RAM with the tag portion 252 of memory address 220. If, and only if, the corresponding tag RAM address contains the tag portion 252, then the cache already contains the contents of the memory address.

[0015] For example, the cache RAM 116 may be a two-way cache containing two cache lines. The tag RAM reflects this in that each tag RAM addressable word 300 specified by the index contains two tags 310, 320 ( Fig. 3). Additionally, each of these two tags corresponds to a separate cache line 400 of data. Those skilled in the art will recognize that, alternatively, a three-way, four-way cache architecture may be used, with each index corresponding to three, four, or more cache lines 400 in cache memory 116, and in such a case, three, four, or more respective tags may be stored in each tag RAM addressable word.

[0016] If the tag matches the tag RAM contents on both paths, this indicates that the requested data is already in the cache (cache hit) and reading or writing can take place immediately using the cached data.

[0017] Alternatively, if the tag does not match, a cache miss has occurred. To access the requested data, the data must be downloaded from memory 200. To do this, the cache controller must first load (backfill) a line of data containing the requested location from main memory into the cache; this line of data is referred to as a cache line 400 and contains a data line containing the data at the requested memory address. Note that the data line is the data stored in an address range of data in main memory 200. The address range has a lower and an upper value. For example, a cache line may contain 32 words of data, each of 32 bits, and the upper value of the address range is 31 times greater than the lower value.

[0018] During a refill, the cache controller allocates one of the available paths at this index to store the newly read data from main memory. Normally, the cache is full, so the cache controller must remove a line already stored in the cache to make room (cache line eviction). The evicted cache data is written back to main memory if it has been modified (writeback); alternatively, the cache line is simply invalidated before being overwritten.

[0019] Cache line eviction can be controlled according to a least-recently-used (LRU) algorithm. The cache controller maintains a flag bit for each index, indicating which path (of the two available) was accessed least recently and should therefore be evicted preferentially. The intention is to keep the most recently accessed data in the cache for performance reasons. program stack

[0020] The program stack is a commonly used data structure in memory. It is maintained by the microprocessor system and operating software to temporarily store data (and program code addresses) and is accessed very frequently. One of the registers 106 is a stack pointer register 108, which is used to store a stack pointer 410, which is an address in main memory at the top of the stack. Data is pushed onto the stack to be stored and pushed off the stack to be restored, as the stack grows and shrinks accordingly in memory. In both cases, the data is stored or accessed at the stack pointer location, and the stack pointer is then incremented or decremented accordingly.

[0021] By keeping the most recently accessed part of the stack (top of stack) in the fast local cache, the system maintains high performance by avoiding the degradation that would occur if the top of the stack were evicted from the cache.

[0022] The top of the stack is accessed very frequently, and therefore, it is often retained in the data cache through the normal operation of the LRU mechanism. However, there is no guarantee that the LRU mechanism will retain the cache line with the top of the stack in the cache. Lock out

[0023] In examples, a portion of the data cache is identified as containing the top of the stack using the stack pointer 410 stored in the stack register 108. This cache line is then locked so that it cannot be evicted, even if it would normally be through the LRU. As the top of the stack moves up and down through the memory address space, the stack pointer automatically indicates the address of data to be locked in the cache. Thus, the cache line, including the data at the stack pointer—that is, at the address in main memory pointed to by the stack pointer—is retained in the cache even if the LRU algorithm would otherwise evict the cache line.

[0024] When a cache line is locked, it is protected from eviction by overriding the LRU flag at that index, and the alternative path is chosen for eviction, even if it has been used recently.

[0025] The benefits of automatically locking the cache line containing the top of the stack, as described here, can be directly measurable in reduced execution times for some test programs.

[0026] The cache line locking function can be performed by the cache controller. It is provided with the tag and index portions of the lock memory address and a flag bit to indicate lock address validity. The cache controller compares the lock tag with the lock index during each cache lookup. If the lock tag matches, the cache controller sets a flag bit to override the LRU if the cache lookup results in a miss, a subsequent refill, and a cache line eviction. Thus, the locked cache line is protected from eviction.

[0027] Fig. Figure 5 illustrates a cache controller design that may be implemented in hardware that implements two-way caching and locking.

[0028] The address line 220 is connected to the index address lines 512, which carry the index part 252, and to the tag address lines 510, which carry the tag part 250.

[0029] The index address lines 512 are connected to the tag RAM 114 and to the LRU 500. The tag RAM 114 has a first write output 506 and a second write output 508 connected to the first tag comparator 502 and the second tag comparator 504, respectively. The tag address lines 510 are also connected to the first and second tag comparators 502, 504.

[0030] A locking subsystem 526 accepts a locking address on the locking address lines 528. The locking subsystem includes a locking tag comparator 530 connected to the address tag lines 510 and a locking index comparator 532 connected to the index tag lines 512. The locking tag and index comparators 530, 532 are also connected to the respective portions of the locking address lines 532. The outputs of the locking comparators 530, 532 are connected to the locking output 536 through gate 534.

[0031] In use, when an address is input, the LRU 500 outputs an LRU signal 520 indicating which of the first and second cache lines corresponding to the address index was most recently used. The tag RAM 114 outputs as tag data on the first write output 506 the tag stored in the first way 310 at the index location and on the second write output 508 the tag stored in the second way 320 at the index location in the tag RAM 114. These are then compared in the first and second comparators 502, 504 to output a first output 522 at the first tag comparator 502 indicating a hit for the first way and a second output 524 at the second tag comparator 504 indicating a hit for the second way.

[0032] Similarly, the lock tag and index comparators 530, 532 compare the input on the lock address lines 528 with the tag and index portions of the address input on the address line 220 and output a locked signal at the lock output 536 if the address is locked. The lock address lines may provide the address that is locked.

[0033] The cache controller can then simply access the data in the cache when a hit is indicated at the first tag output 522 or the second tag output 524.

[0034] If no hit is present, data must be loaded from main memory into the cache. If the locked output indicates no lock, the path of data in cache RAM 116 indicated by the LRU output is cleared and replaced with the data loaded from main memory 200. Conversely, if the locked output indicates that one of the paths is locked, the other path is cleared and replaced with the data loaded from main memory.

[0035] An alternative version of the design allows multiple lines to be locked. Multiple lock memory addresses are provided to the cache controller, and the comparison described above is repeated for each. If a lock tag matches the requested memory address on a cache lookup at the same index, another flag bit is set to indicate that the LRU should be overridden if a cache line miss occurs. If all available ways at that index are locked, the cache controller reverts to using the LRU to select a way for eviction.

[0036] The system can keep track of one or more previous values ​​of the stack pointer. These are reused to selectively and dynamically lock data in the fast local cache so that recently accessed top-of-stack data is not evicted.

[0037] For example, lower and upper limits in the address range of the cache line of data may be predetermined. For example, in the case where a first cache line 400 with a first address range contains 32 words represented by the five-bit word address, as in the example above, the predetermined lower limit may be three times higher than the lower value of the address range, and the predetermined upper limit may be three times lower than the upper value of the address range. See Fig. 4, which illustrates cache line 400, lower value 402, upper value 404, lower threshold 406, and upper threshold 408. The first address range 414 in main memory, corresponding to lower value 402 through upper value 404, is the address range represented in this cache line 400.

[0038] In the case where the stack pointer 410 is between the lower and upper thresholds, the stack pointer is incremented and decremented as data is stored in and popped from the stack, but there is no need to access the main memory 200 because the data in this address range is stored in the cache line 400 in the cache RAM 116.

[0039] However, if the stack pointer 410 passes the upper threshold 408, there is a risk that the stack pointer will continue to increment and pass the upper value 404. This would then cause a stack fault and further delay. To mitigate this risk, the cache controller 110 may be arranged to read another cache line of data corresponding to another address range immediately above the first address range 414. In some examples, this additional line of data may also be locked. In this way, the risk of a cache miss is reduced.

[0040] Similarly, if the stack pointer 410 falls below the lower threshold 406, the cache controller 110 may load another cache line of data, which in this case corresponds to another address range immediately below the first address range. In some examples, this line of data may be locked. In this way, the risk of a cache miss is reduced.

[0041] Although specific examples have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent implementations may be substituted for the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

[0042] In a first example, a cache system is provided for a processor having a stack pointer register for storing a stack pointer, the stack pointer being the address in main memory of the top of a stack, comprising: a cache memory structured into cache lines; and cache controller circuitry operable to: receive the stack pointer (SP), store a first cache line containing the contents of a first address range of bytes of main memory, the first address range including the stack pointer; and lock the first cache line to protect the first cache line from cache eviction.

[0043] The cache controller circuitry may be further operable, when the stack pointer register contains a new stack pointer with an address outside the first address range: storing another cache line in the cache containing the contents of another address range containing the new stack pointer; and The cache system may lock the first cache line and the another cache line, but unlock each previous cache line according to a previous stack pointer address.

[0044] The cache controller circuitry may be further operable to: lock a plurality of addresses of respective cache lines corresponding to the stack pointer.

[0045] The cache controller circuitry may be further operable to: determine a low-threshold address in the first address range; determine a high-threshold address in the first address range; determine whether the stack pointer exceeds the high-threshold address, and if so, prefetch another cache line of data from the address range in main memory immediately above the first address range into the cache; or determine whether the stack pointer is below the second threshold, and if so, prefetch another cache line of data from the address range in main memory immediately below the low-threshold address.

[0046] The cache controller circuitry may be further operable to: lock the address of the further one cache line containing the prefetched data.

[0047] The low-threshold address and / or the high-threshold address may be located at a programmable position within the first cache line.

[0048] The cache controller circuitry may be operable to lock the address of the cache line in a dynamic manner.

[0049] The cache controller circuitry may be operable to: lock the address by overriding an output of least recently used (LRU) logic to protect the cache line from eviction if a cache lookup results in a miss, a cache line eviction, and a cache line refill.

[0050] The cache controller circuitry may include: a lock detection circuit operable to determine whether a request address received from a processor corresponds to the locked address.

[0051] The cache memory can be organized as a multidirectional associative memory.

[0052] In one example, a microcontroller may be provided that includes the cache system as set forth above.

[0053] The microcontroller may further comprise: a processor; and a main memory, wherein the cache system is communicatively coupled between the processor and the main memory to manage data flow therebetween.

[0054] In one example, a method for managing a cache memory structured in cache lines may also be provided, comprising: receiving, by cache controller circuitry from a processor, a stack pointer indicating the address in main memory of the top of a stack; and locking, by the cache controller circuitry, a cache line containing the top of the stack to protect the cache line from cache eviction.

[0055] The method may further comprise: updating the stack pointer to an address not stored in the cache line in the cache memory, storing another cache line corresponding to the updated address; and

[0056] The method may further comprise locking a plurality of cache lines pointed to and / or pointed to by the SP.

[0057] In one example, the cache line corresponds to an address range in main memory, and the method further comprises: determining, when updating the stack pointer, whether the stack pointer passes a predetermined threshold address; and if so, prefetching another cache line of data from main memory.

[0058] The method may further comprise: locking the at least one cache line containing the prefetched data.

[0059] The method may further comprise locking the address by overriding an output of least recently used (LRU) logic to protect the cache line from eviction if a cache lookup results in a miss, a cache line eviction, and a cache line refill.

[0060] The method may further comprise: determining, by a lock detection circuit, whether a request address received by a processor corresponds to the locked address.

[0061] It should be noted that the methods and devices, including their preferred embodiments, as set forth in the present document can be used alone or in combination with the other methods and devices disclosed in this document. In addition, the features set forth in the context of one device are also applicable to a corresponding method, and vice versa. Furthermore, all aspects of the methods and devices set forth in the present document can be combined in any desired manner. In particular, the features of the claims can be combined with one another in any desired manner.

[0062] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments set forth in the present document are generally expressly intended to be for illustrative purposes only to assist the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include equivalents thereof.

Claims

[1] A cache system for a processor having a stack pointer register for storing a stack pointer, the stack pointer being the address in main memory of the top of a stack, comprising: a cache memory structured in cache lines; and a cache controller circuitry operable to: Receiving the stack pointer (SP), Storing a first cache line containing the contents of a first address range of bytes of the main memory, the first address range containing the stack pointer; and Lock the first cache line to protect the first cache line from cache eviction. [2] The cache system of claim 1, wherein the cache controller circuitry is further operable to: if the stack pointer register contains a new stack pointer with an address outside the first address range: Storing another cache line in the cache containing the contents of another address range containing the new stack pointer; and Lock the next cache line. [3] The cache system of claim 2, wherein the cache system locks the first cache line and the further cache line, but unlocks each previous cache line according to a previous stack pointer address. [4] A cache system according to any preceding claim, wherein the cache controller circuitry is further operable to: Locking a plurality of addresses of respective cache lines corresponding to the stack pointer. [5] The cache system of claim 1, wherein the cache controller circuitry is further operable to: Determining a low-threshold address in the first address range; Determining a high-threshold address in the first address range; Determining whether the stack pointer exceeds the high-threshold address, and if so, prefetching another cache line of data from the address range in main memory immediately above the first address range into the cache; or Determining whether the stack pointer is below the second threshold, and if so, prefetching another cache line of data from the address range in main memory immediately below the low-threshold address. [6] The cache system of claim 5, wherein the cache controller circuitry is further operable to: Lock the address of the next cache line containing the prefetched data. [7] The cache system of claim 5 or 6, wherein the low-threshold address and the high-order address are located at a programmable position within the first cache line. [8] A cache system according to any preceding claim, wherein the cache controller circuitry is operable to lock the address of the cache line in a dynamic manner. [9] A cache system according to any preceding claim, wherein the cache controller circuitry is operable to: Lock the address by overriding an output of least recently used (LRU) logic to protect the cache line from eviction if a cache lookup results in a miss, a cache line eviction, and a cache line refill. [10] Cache system according to one of the preceding claims, wherein the cache controller circuitry comprises: a lock detection circuit operable to determine whether a request address received from a processor corresponds to the locked address. [11] A cache system according to any one of the preceding claims, wherein the cache memory is organized as a multidirectional associative memory. [12] Microcontroller, comprising: the cache system according to one of the preceding claims. [13] The microcontroller of claim 12, further comprising: a processor; and a main memory, wherein the cache system is communicatively coupled between the processor and main memory to manage data flow therebetween. [14] A method for managing a cache memory structured in cache lines, comprising: Receiving, by cache controller circuitry from a processor, a stack pointer indicating the address in main memory of the top of a stack; and Locking, by the cache controller circuitry, a cache line containing the top of the stack to protect the cache line from cache eviction. [15] The method of claim 14, further comprising: Updating the stack pointer to an address that is not stored in the cache line in the cache memory, Storing another cache line corresponding to the updated address; and Lock the next cache line. [16] The method of claim 14 or 15, further comprising: Locking a plurality of cache lines pointed to and / or pointed to by the SP. [17] The method of claim 14, 15 or 16, wherein the cache line corresponds to an address range in the main memory, the method further comprising: Determining, when updating the stack pointer, whether the stack pointer passes a predetermined threshold address; and if this is the case, prefetch another cache line of data from main memory. [18] The method of claim 17, further comprising: Locking at least one cache line containing the prefetched data. [19] A method according to any one of claims 14 to 18, further comprising: Lock the address by overriding an output of least recently used (LRU) logic to protect the cache line from eviction if a cache lookup results in a miss, a cache line eviction, and a cache line refill. [20] A method according to any one of claims 14 to 19, further comprising: Determining, by a lock detection circuit, whether a request address received by a processor corresponds to the locked address.

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