Data exchange procedures and information technology systems

Abstract

The invention relates to a data exchange method in which information to be transferred from a first computing unit (RE1) to a second computing unit (RE2) is written in machine-readable form into a first memory (MEM1) of the first computing unit (RE1) and is transferred to the second computing unit (RE2) via a PCIe data line (PCIe-DL) without processing by a first processor of the first computing unit (RE1).The data exchange method according to the invention is characterized in that the first computing unit (RE1) divides the information into payload segments (201), wherein the payload segments (201) are distributed on memory pages (202) of the first memory (MEM1) such that each payload segment (201) begins or ends at the beginning or end of a respective memory page (202), wherein, to mark the memory page (202) to be written to, the writing process is started at the beginning with a mark information (203) or completed at the end of the page; and . The second processing unit (RE2) accesses the first memory (MEM1) via the PCIe data line (PCIe-DL) by reading, examines the memory pages (202) for specified marker information (203), reads the payload segments (201) from such memory pages (202), and stores them in a second memory (MEM2) of the second processing unit (RE2) or a third processing unit (RE3) communicatively connected to the second processing unit (RE2), at the respective beginning or end of which one of the specified marker information (203) is found.

Description

[0001] The invention relates to a data exchange method of the type defined in more detail in the preamble of claim 1 and to an information technology system suitable for carrying out the data exchange method.

[0002] Computer systems are often capable of self-diagnosis, which allows for the verification and monitoring of internal processes and the correct functioning of software and hardware. Information is written to a computer-readable file that documents the corresponding behavior. This enables a process called "debugging," used to further develop hardware and software components, fix bugs, close security gaps, and so on.

[0003] The computing units installed in vehicles, such as control units, can also perform diagnostics. The resulting diagnostic data can be read out using external devices via a suitable data interface on the vehicle. This data can then be transferred from these diagnostic devices to an external PC. However, this process requires significant manual effort, and the comparatively low data transfer rates make reading the diagnostic data time-consuming. Furthermore, a dedicated measuring device is required for data output. If diagnostic data is to be acquired (i.e., measured) and output simultaneously, a memory collision can occur. In this case, the measuring device might access a memory area of ​​the computing unit writing the diagnostic data, while at the same time, the respective computing unit is also accessing this memory area to write new diagnostic data.This either prevents the writing unit from writing the relevant data or prevents the reading unit from reading the old data in a timely manner. Such situations should be avoided.

[0004] The program tool "PCIe Leech" is known from the general state of the art. The program tool can be obtained via the following link: https: / / github.com / ufrisk / pcileech. This program tool allows a PC to read memory controlled by another PC. In the context of processing vehicle diagnostic data, various middleware implementations are also known, in particular Vector Adaptive Autosar.

[0005] Furthermore, WO 2020 / 163128 A1 describes PCI Fabric permitted peer-to-peer communication. The document describes a computing system comprising a processor configured to initiate peer-to-peer communication between two PCI devices. A host processor manages the respective addresses between the PCI devices to which data is to be sent. The data to be transmitted does not need to pass through the host processor itself. The data transfer can be based on Direct Memory Access (DMA).

[0006] Similar data exchange procedures are also known from CN 102255794 B, CN 107368379 B and CN 109508241 A.

[0007] The present invention is based on the objective of providing an improved data exchange method which allows high data transmission rates through efficient use of the underlying hardware components.

[0008] According to the invention, this problem is solved by a data exchange method with the features of claim 1. Advantageous embodiments and further developments, as well as an information technology system for carrying out the data exchange method, are set forth in the dependent claims.

[0009] A generic data exchange method, wherein information to be transferred from a first computing unit to a second computing unit is written in machine-readable form into a first memory of the first computing unit and is transferred to the second computing unit via a PCIe data line without processing by a first processor of the first computing unit, is further developed according to the invention in that the first computing unit divides the information into payload segments, wherein the payload segments are distributed on memory pages of the first memory such that each payload segment begins or ends at the beginning or end of a respective memory page, wherein, to mark the memory page to be written, the writing process is started at the beginning with a marker or completed at the end of the page;and the second processing unit accesses the first memory via the PCIe data line, examines the memory pages for specified marker information, reads the payload segments from such memory pages, and stores them in a second memory of the second processing unit or a third processing unit communicatively connected to the second processing unit, at the respective beginning or end of which one of the specified marker information points is found during read access.

[0010] The data exchange method according to the invention provides for data transfer between the first and second processing units via a PCIe data line, which allows for high data transfer rates. The second processing unit determines which information it should retrieve by reading from the first memory, taking into account the defined marker information, so that the processor of the first processing unit does not need to be active in this process. This allows for particularly efficient use of the underlying hardware.

[0011] An advantageous further development of the data exchange method according to the invention provides that the first processing unit writes a write message at a defined distance from a respective payload segment on a given memory page when the payload segment to be written on that memory page has finished being written. The write message indicates to the second processing unit when a given memory page has been filled with new information, thus enabling coordination between the first and second processing units for memory access.

[0012] This is preferably used to selectively control the read access of the second processing unit. According to a further advantageous embodiment of the data exchange method according to the invention, the second processing unit accesses the first memory multiple times for reading, and only stores the payload segment written on the respective memory page in the second memory if the write information has changed between successive read accesses. For example, the write information can contain an iteration count, an increment, a timestamp, or the like, which allows the second processing unit to track whether the underlying payload segment has already been output or whether a new payload segment has been written by the first processing unit, which now needs to be output.This reduces redundant memory accesses to the memory area where the payload segment is stored. Consequently, the need to retransmit redundant data over the PCIe data line, due to data already being stored in the second memory, is eliminated.

[0013] A further advantageous embodiment of the data exchange method according to the invention provides that the first processing unit writes an information type to a respective memory page at a defined distance from a given payload segment, and the second processing unit stores only those payload segments in the second memory for which a defined information type is read from the respective memory page. Depending on the situation, extensive information can be written to the first memory, while the second processing unit only requires a subset of this information. The information type can be used to define which information is to be transmitted to the second processing unit.For this purpose, the respective information type information is assigned to the payload segments on the respective memory side, and the second processing unit writes only those payload segments to the second memory that correspond to the defined information type information. The defined information type information represents a subset of the information type information on the first processing unit. This defined information type information can be transferred to the second processing unit manually by a developer or automatically by a program.

[0014] According to a further advantageous embodiment of the data exchange method according to the invention, the second processing unit writes priority information to a respective memory page at a defined distance from a given payload segment. This priority information represents a priority for memory pages. If a memory page to be written is blocked by a read access, the first processing unit writes a payload segment to the next available memory page. If no available memory page can be found, the first processing unit writes the payload segment to the memory page with the lowest priority information. This allows the second processing unit to inform the first processing unit which memory areas, and thus which information, are the least important and can be overwritten first.This ensures that, if necessary, only the least important information is lost.

[0015] The first and second processing units therefore share a common memory located in the first processing unit. This is thus a "shared memory" method. The disclosed shared memory method does not require a dedicated "lock," i.e., the locking of a memory area by one of the processing units, which also contributes to efficient hardware utilization.

[0016] An information technology system according to the invention, comprising a first and a second computing unit, provides that the first and second computing units are communicatively connected to each other via a PCI data line and are configured to execute a method described above.

[0017] An advantageous further development of the information technology system according to the invention provides for a third processing unit, wherein the third processing unit is indirectly connected to the first processing unit via the second processing unit. Particularly preferably, the third processing unit is also connected to the second processing unit via a PCIe data line, so that the corresponding forwarding of information to the third processing unit is possible while maintaining a high data rate.

[0018] A further advantageous configuration of the information technology system provides that the first processing unit is integrated into a vehicle. This first processing unit can therefore be an embedded system of the vehicle, such as a control unit. In particular, the embedded system can be a so-called "system-on-a-chip" (SoC).

[0019] A further advantageous embodiment of the information technology system according to the invention provides that the second computing unit is implemented as a PCIe card and is inserted into a PCIe slot in the third computing unit. This ensures particularly simple integration of the second computing unit into the third computing unit and further promotes efficient hardware utilization.

[0020] Further advantageous embodiments of the data exchange method and information technology system according to the invention also result from the exemplary embodiments, which are described in more detail below with reference to the figures.

[0021] This shows: Fig. 1 a schematic structure of an information technology system according to the invention in a first embodiment; Fig. 2 a schematic representation of a described memory page according to the first embodiment; Fig. 3 a schematic detailed representation of a second computing unit according to the first embodiment; Fig. 4 a schematic structure of an information technology system according to the invention in a second embodiment; Fig. 5 a schematic flowchart showing the write operations on a shared first memory according to the second embodiment; Fig. 6 a schematic representation of a first data structure according to the second embodiment; Fig. 7 a schematic representation of a third data structure according to the second embodiment; Fig. 8 a schematic representation of an exemplary system setup according to the second embodiment; Fig. 9 a flowchart showing the steps performed by a first computing unit according to the second embodiment; and Fig. 10 a flowchart showing the steps performed by a second computing unit according to the second embodiment.

[0022] The data exchange method according to the invention is explained using two exemplary embodiments, wherein the Fig. 1 to 3 the first embodiment and the Fig. 4 to 10 relate to the second embodiment.

[0023] Fig. Figure 1 shows a vehicle 101, which includes a first processing unit RE1. For example, the first processing unit RE1 is a control unit of a vehicle subsystem, also known as an "Electronic Control Unit" (ECU). To read out corresponding diagnostic data, a second processing unit RE2, which can also be referred to here as a measurement technology adapter, is connected to the first processing unit RE1 via a PCIe DL data line. The second processing unit RE2, or the measurement technology adapter, serves to extract corresponding diagnostic data from the first processing unit RE1 and transmit it to a third processing unit RE3, which can also be referred to here as a measurement technology PC. The second processing unit RE2 and the third processing unit RE3 are communicatively connected to each other via a DL data line. The DL data line could, for example, be an Ethernet data line.The preferred data line DL is a PCIe data line. This reduces CPU overhead in the measurement PC, and no network stack is required. Ideally, the second processing unit RE2 is implemented as a plug-in card for the third processing unit RE3. However, this connection can also be implemented via USB4 or Thunderbolt.

[0024] The second processing unit, RE2, is capable of accessing the memory of the first processing unit, RE1, via PCIe. The first processing unit, RE1, is configured to read predefined data via the corresponding PCIe bus. The PCIe connection between the first and second processing units, RE1 and RE2, can be implemented via cable, Thunderbolt, or, if necessary, optically. USB4 is also an option. Proprietary SoC interconnect buses are also possible. Crucially, the second processing unit, RE2, can access the memory of the first processing unit, RE1, without the involvement of the first unit's processor.

[0025] The data exchange method according to the invention is further characterized by a special data arrangement on the memory of the first computing unit RE1. A memory page 202 of the memory of the first computing unit RE1 is thereby in Fig. 2 shown. Information is oriented to the page boundaries of each page 202, whereby in Fig. 2. Orientation is shown at the top of the page. It would also be possible to orient the displayed information at the bottom of the page.

[0026] The page size of memory page 202 is coordinated between the second processing unit RE2 and the corresponding memory allocation code in the first processing unit RE1. Typically, this is 4 kilobytes, but it can also be larger or smaller.

[0027] At the beginning of each memory page 202, a marker information 203 is inserted. For example, such a marker could be X6MT. This is followed by four bytes with a process ID 205. The process ID 205 describes the process to which memory page 202 belongs. Next come eight bytes (64 bits) of the virtual address 206 of a variable to be measured in the context of the diagnostic data. These are followed by four bytes describing a variable group. This description of the variable group is an information type 204. Within these four bytes, information can be encoded indicating whether the respective variable is a so-called trigger variable. For example, this information is integrated into the 31st bit. The remaining bits form the ID of the group. Then follow four bytes specifying a period 207. The period 207 defines, in milliseconds, the minimum duration for which a variable must remain stable."Stable" refers to how long the corresponding variable should be retained on memory page 202 after being written, to ensure that it is read by the second computing unit RE2.

[0028] This is followed by the length of variable 208, and then by the actual data of the variable, which is referred to here as payload segment 201.

[0029] The fixed number of bytes for each piece of information thus determines the distance of that piece of information from the beginning of memory page 202. The distance, or memory size, of the length of variable 208 and the data of variable 201, or payload segment 201, is situation-dependent but known.

[0030] The first processing unit, RE1, executes various processes that can write corresponding information to memory pages 202. The first processing unit, RE1, ensures that all processes adhere to the appropriate memory scheme.

[0031] If relevant diagnostic data is collected and written to the memory of the RE1 computing unit, the so-called trigger variable is incremented.

[0032] For each process, there exists a memory page 202 containing the variable group or information type 204 of the form "0xFFFFFFFFF", which has special content. Memory page 202, which contains this special variable group, assigns a process name to the corresponding process ID 205. Using this process name, the third processing unit RE3, for example, the aforementioned measurement technology PC, together with debug information from the binary running on the first processing unit RE1, can decode the structure of the variables. This list is updated periodically.

[0033] Furthermore, the memory management of the first processing unit RE1 ensures that if a memory page 202 is too small to contain all the information relating to a given variable, the information pertaining to that variable is written to the next memory page 202. This ensures that variables to be measured are always contained on contiguous memory pages 202.

[0034] The third processing unit RE3 initializes the second processing unit RE2 by specifying where the information to be captured should be stored within RE3. RE3 can write to registers indicating whether a specific variable group or information type 204 should be excluded from measurement. Furthermore, RE3 can write to registers indicating whether a specific individual variable should be excluded from measurement. Such an exclusion list can also be reset, so that RE3 informs the first processing unit RE1 that all variables should be measured. Based on this, the selection can be further restricted. Alternatively, a so-called positive list can be implemented. In this case, RE2 only provides information pertaining to group 0XFFFFFFFFF.Information about addresses to be measured can be obtained not only via debug symbols, but also via other protocols such as X6MT-ini or ASAN-A2L.

[0035] The information passed from the second processing unit RE2 to the third processing unit RE3 is stored in a ring buffer, also known as a "ring buffer", on the third processing unit RE3. The information can also be written from the ring buffer to a storage medium in the third processing unit RE3.

[0036] The second processing unit RE2 is configured by the third processing unit RE3. Thus, the third processing unit RE3 informs the second processing unit RE2 where the corresponding information should be stored within the third processing unit RE3.

[0037] The second processing unit RE2 continuously scans the memory of the first processing unit RE1 for the aforementioned marker information 203. As soon as such marker information 203 is found, the underlying variable is entered into a corresponding list. For trigger variables, the period 207 for the variable group is adopted. This value is used as the current wait time. Once the second processing unit RE2 has found the process configuration (0XFFFFFFFFFF), the entire memory page 202 is read and written to the ring buffer.

[0038] The following program is executed for all groups of active variables after a defined time interval, for example every millisecond: - If the current waiting time is not zero: decrement; - If the current waiting time is zero: - The trigger variable is read and checked to see if it has changed; - if the trigger variable has changed, all variables from the variable group are read and written to the ring buffer, unless they are on a blacklist; - the current waiting time is set to period 207 of the variable group; - The current trigger value of the variable group is saved.

[0039] After a configurable time period, the corresponding scan of the memory of the first processing unit RE1 is repeated, and the result is updated in the ring buffer of the third processing unit RE3. The trigger variable can also be interpreted here as write information 601, which will be discussed later.

[0040] The second processing unit, RE2, can be, for example, a single- or multi-core SoC or an FPGA (Field-Programmable Gate Array). Depending on whether the cores of the second processing unit, RE2, saturate the PCIe bus, multiple CPU cores can also be used for parallel execution of the variable lists.

[0041] Fig. Figure 3 illustrates an ideal configuration of the second computing unit, RE2. It shows a PCIe endpoint 301, which allows a connection to the first computing unit, RE1, via the PCIe DL data line. Additionally, a PCIe endpoint 302 is present, which allows a corresponding connection to the third computing unit, RE3. Ideally, both PCIe endpoints 301 and 302 have a connection to four PCIe lanes.

[0042] The PCIe endpoints 301 and 302 are addressed via an AXI bus 303. This bus allows access to a configuration memory 304. Configuration memory 304 stores information such as: variables to be excluded, the time interval after which the memory of the first processing unit RE1 should be scanned again, the location and size of the ring buffer in the third processing unit RE3, and similar data. Configuration memory 304 can be written to by the third processing unit RE3.

[0043] Furthermore, a 305 processor is present, which has one or more processing cores. Each processing core can process an individual list of variables. Additionally, a local memory for variable lists 306 is provided. This local memory for variable lists 306 is preferably implemented as so-called Tightly-Coupled Memory (TCM). These variable lists inform the second processing unit RE2 which information should be read from the respective memory pages 202 of the memory of the first processing unit RE1. This information consists of predefined marker information. Examples include the aforementioned period 207, the length of the variable 208, its virtual address 206, especially the trigger variable, or specific memory pages 202 to be read.

[0044] The PCI endpoint 302 to the third computing unit RE3 is connected not only as an AXI slave but as an AXI master, so that the third computing unit RE3 can write to the configuration memory 304.

[0045] Depending on the requirements of the measurement PC, the measurement adapter can take on additional tasks, such as providing a CAN or Automotive Ethernet interface. This allows for the saving of PCIe slots in the measurement PC.

[0046] The in the Fig. The embodiment shown in Figures 1 to 3 is simple and inexpensive to implement. The achievable bandwidth is on the order of a double-digit number of gigabits per second.

[0047] A description of a second embodiment of the invention follows, based on the Fig. 4 to 10. The invention is based, like the one in the Fig. The embodiment shown in Figures 1 to 3 is based on shared storage usage.

[0048] Existing mechanisms for interprocess communication (IPC) are based on so-called atomic operations or locks to sequentialize parallel memory accesses. However, the invention exploits the fact that processes or components only write or read for a comparatively short period and perform no activities for a longer time. According to the invention, this is used to coordinate read and write operations, thus preventing deadlock situations or simultaneous read / write access by different system components as effectively as possible.

[0049] This avoids the disadvantages associated with using atomic operations, such as their failure to function when the memory to be read or written is not located in a cache-coherent memory area. Other shared memory implementations use memory pools to dynamically store relevant data, such as Vector ara:com, Zero Copy, and icyorix.

[0050] This shows Fig. 4 an alternative system architecture of an information technology system according to the invention for carrying out the data exchange method according to the invention.

[0051] The diagram shows the first computing unit RE1, which is preferably a vehicle-integrated computing unit. The first computing unit RE1 comprises a system-on-a-chip, referred to here as an IDC SoC. Also shown is the shared usable memory, i.e., the first memory MEM1 of the first computing unit RE1.

[0052] Furthermore, the second processing unit RE2 is shown, which here also comprises a system-on-a-chip, designated as an IVI SoC. Additionally, a shared memory, MEM2, is shown on the second processing unit RE2. This memory could also be integrated into the respective SoC. Thus, it is possible for the second processing unit RE2 not only to forward information or data received from the first processing unit RE1 to a third processing unit RE3, such as the aforementioned measurement PC, but also to store this data in its own memory. This allows a vehicle-integrated control unit to take over the task of the measurement adapter. Therefore, costly external hardware resources can be saved.

[0053] Of course, it would be possible that such a measurement technology adapter exists, particularly in the development phase, which is optionally indicated here by a dashed line and is referred to as MT SoC.

[0054] Each SoC includes a 401 module for translating PCIe addresses. This allows for connectivity via PCIe-DL data lines.

[0055] The IDC SoC has non-cache-coherent R cores, designated here by reference 402. It also has R cores for address translation (403) and cache-coherent A cores (404).

[0056] The second memory, MEM2, has a memory area 405 that is visible and writable to the IDC SoC. Additionally, the second memory, MEM2, has a memory area 406 that is only visible to the IDC SoC.

[0057] The first memory MEM1 is further subdivided into a memory area 407, which is visible and writable for the IVI SoC, a memory area 408, which is visible and writable for the aforementioned R-cores, a memory area 409, which is writable for the first subset of the A-cores, and a memory area 410, which is writable for a second subset of the A-cores.

[0058] Furthermore, the first memory MEM1 includes a memory area 411, which is visible to the aforementioned R-Cores, a memory area 412, which is visible to the IVI SoC, and a memory area 413, which is visible to the MT SoC.

[0059] The system shown could also include more than one IDC SoC, such as two, three, or even more. The IDC SoCs are each interconnected via a PCIe-DL data lane.

[0060] Each memory area within a given memory structure can only be written to by exactly one core or bus master. Read permissions are assigned in such a way that "secret" information can only be read by those cores that are authorized to do so. One or more processes run on each core, each sharing the core's memory. The memory can be further subdivided so that each process can only write to its assigned memory area. This is based on the principle already discussed in the previous section regarding... Fig. Section 2 explains the description of memory pages 202 with information. For this purpose, the so-called Memory Protection Unit (MPU) or Memory Management Unit (MMU) of the respective kernel is appropriately configured via the operating system.

[0061] The following section describes writable memory contents based on the Fig. 5, Fig. 6 and Fig. 7 explained.

[0062] Fig. Figure 5 illustrates which system component writes which structure to the first memory, MEM1. The first data structure, 501, is written by the first arithmetic unit, RE1. A second data structure, 502, is written by a process, 504, running on the first arithmetic unit, RE1. A third data structure, 503, is written by the second arithmetic unit, RE2. The first data structure, 501, is referred to as the "QueueSocket." The second data structure is also referred to as the "StateStructure." The third data structure, 503, is also referred to as the "ReceiveReader."

[0063] Fig. Figure 6 shows a detailed representation of the first data structure 501. The code element 602 "itemID" assigns a unique ID to each type. This ID allows the measurement technology to later interpret the data structure.

[0064] The code element 603 "queueLength" is also configurable, determining how many payload segments 201 exist. At least two payload segments 201 are provided so that the sender, i.e., the first processing unit RE1, can write new data while other processes, especially a receiver like the second processing unit RE2, can read old data.

[0065] Code element 604, "itemLength", defines the length of each payload segment 201, which is important for specifying the distance to the respective page boundary for the contents of the first data structure 501. Payload segment 201 can optionally be end-to-end encrypted. Code element 605, "sequenceCounter", determines which element of the queue is currently being read or written, i.e., which payload segment 201. This process iterates through each element n of the queue.

[0066] Optionally, the third data structure 503, the "ReceiveReader," is provided for slow receivers. A slow receiver is a second processing unit, RE2, which only reads a payload segment 201 (i.e., element n of the queue) when it should already be overwritten again. If such a receiver also reads the code element 605 "sequenceCounter," the sequence counter is incremented and checked to see if the corresponding block is free. If no free block is found, the first block written by the receiver with the lowest priority is used. The priority is determined by the code element 701 "prio" (see Fig. 7) in the third data structure 503, i.e., the ReceiveReader. The correspondingly overwritten block then becomes corrupt for the recipient of the data. However, the recipient can detect this because, after reading, it reads the code element: "doneCounter", which represents write information 601. The doneCounter is always set to the sequenceCounter when a payload segment 201 has been written. The doneCounter and the sequenceCounter exist n times. A payload segment 201 is always valid if the doneCounter is equal to the sequenceCounter.

[0067] The first data structure, 501, also stores the code element 606: "curCounter". The curCounter is incremented with each write operation. Incrementing continues until a free block is found or the block with the lowest priority of the receiver is retained or overwritten. Additionally, the code element 607: "receiverReading" is included, which describes where the third data structure, 503, can be found. This involves transmitting information about the memory region in which the third data structure, 503, resides and its precise location within that region. An offset or distance within the memory region is specified for this purpose. This can also be interpreted as a pointer.

[0068] Fig. Figure 7 shows the third data structure 503 in detail.

[0069] The third data structure, 503, contains a copy of code element 602: "itemID". This is optional and can be used during development to verify that the respective third data structure, 503, matches the respective first data structure, 501. This is followed by code element 702: "sequenceCounterReading". This indicates whether a payload segment, 201, is currently being read. If a payload segment, 201, is being read (i.e., a read access is occurring), this value is set to the doneCounter of the respective payload segment, i.e., its position in the queue or the write information, 601. If no reading is taking place, the receiver, i.e., the second processing unit, RE2, sets the value to 0.

[0070] Code element 703: “nextReceiveReaderOffset” and code element 704: “nextReceiveReaderMemory” provide a pointer to the next ReceiveReader.

[0071] The respective data structures 501, 502 and 503 are similar to those in Fig. 2. The embodiment shown is oriented at the respective side boundaries.

[0072] Memory areas are allocated statically. The specific memory areas, as well as their size and visibility, are defined during development.

[0073] Fig. Figure 8 shows another possible embodiment of an exemplary arrangement of system components.

[0074] Shown again are the first and second computing units RE1, RE2 in the form of the IDC SoC, the MT SoC, the IVI SoC and a Laptop 801.

[0075] The MT SoC has access to an SSD 802. The IVI SoC has a memory area 803, which is readable by the first core of the IDC SoC, and a memory area 804, which is writable by the IVI SoC. The respective PCIe DL data lines are also shown. The IDC SoC includes a memory area 805, which is visible to the IVI SoC. Additionally, a memory area 806 is present, which is readable but not writable by the MT SoC. Furthermore, a memory area 807 is present, which is readable but not writable by the IVI SoC. Finally, a memory area 808 is present, which is both readable and writable by the IVI SoC.

[0076] Furthermore, there is a memory area 809 that can be read by an FSI SoC and a memory area 810 that can be written by the FSI SoC.

[0077] Furthermore, there is a memory area 811, which is readable by the first core, and a memory area 812, which is writable by the first core. Corresponding memory areas 813 and 814 are available for a second core. Additionally, memory areas 815 may be available for further cores.

[0078] Furthermore, a memory area 816 is present, which is writable by the IDC Core 1 and readable by the IVI SoC. Additionally, a memory area 817 is present, which is accessible by the IVI SoC.

[0079] Fig. Figure 9 illustrates the steps planned by the writing entity, i.e., the first computing unit RE1.

[0080] At compile time, memory locations or areas corresponding to data structures 501 to 503 are allocated. One memory location is selected that is readable by all receivers. Additionally, another memory location is allocated that is writable by receivers, i.e., the second processing unit RE2. The third data structure, 503, is stored here as needed. Based on the information contained in data structures 501 to 503, the corresponding memory locations are then allocated and written. This initializes the variable lists contained within.

[0081] In step 901, the program iterates over the ReceiveReader, i.e., the third data structure 503. In step 902, sections of memory are marked as in use. In step 903, the memory area, i.e., the section in the queue, with the lowest priority for a read slot is determined. In step 904, a free slot or the slot with the lowest priority is used. In step 905, the sequence counter is incremented so that the sequence counter modulus "queueLength" corresponds to the selected slot.

[0082] In step 906, the information to be written for payload segment 201 is written to the selected slot. In step 907, the doneCounter, i.e., the write information 601, is set to the sequenceCounter.

[0083] Fig. 10 illustrates the steps performed by the receiver, i.e., the steps executed by the second computing unit RE2.

[0084] In step 1001, the slot with the highest doneCounter is selected and its value is stored. In step 1002, it is checked whether a fast or slow read is being performed. If a fast read occurs, in step 1003, payload segment 201 in the current slot is read during the cycle time of the first processing unit RE1.

[0085] In step 1004, it is checked whether the sequenceCounter corresponds to the write information 601, specifically whether the doneCounter matches the originally highest doneCounter. This is checked in step 1005. If this is the case, the read operation can be performed in step 1006. If not, an error occurs in step 1007.

[0086] If, however, the read access is slow, a corresponding third data structure 503 is created by the receiver in step 1008. The corresponding ReceiveReader sequence is written with the current doneCounter in step 1009.

[0087] In step 1010, the data is read. In step 1011, the ReceiveReader point sequence is set to zero. In step 1012, it is checked whether the sequenceCounter equals the doneCounter, specifically whether the originally highest doneCounter is present or not. This check is necessary because, although the writer is told that data is being read according to the sequenceCounter, the writer may no longer have any payload segments 201 available.

[0088] This is checked in step 1013. If this is the case, read access is granted in step 1014. If, however, this is not the case, error handling is initiated in step 1015. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 2020 / 163128 A1

[0005] CN 102255794 B

[0006] CN 107368379 B

[0006] CN 109508241

[0006] Cited non-patent literature

[0000] https: / / github.com / ufrisk / pcileech

[0004]

Claims

[1] Data exchange method in which information to be transferred from a first computing unit (RE1) to a second computing unit (RE2) is written in machine-readable form into a first memory (MEM1) of the first computing unit (RE1) and is transferred to the second computing unit (RE2) via a PCIe data line (PCIe-DL) without processing by a first processor of the first computing unit (RE1), characterized by , that The first processing unit (RE1) divides the information into payload segments (201), the payload segments (201) being distributed across memory pages (202) of the first memory (MEM1) such that each payload segment (201) begins or ends at the top or bottom of a respective memory page (202), with the write operation starting at the top of the page (202) with a marker (203) or ending at the bottom of the page to mark the memory page (202) to be written to; and The second processing unit (RE2) accesses the first memory (MEM1) via the PCIe data line (PCIe-DL) for reading, examines the memory pages (202) for specified marker information (203), reads the payload segments (201) from such memory pages (202), and stores them in a second memory (MEM2) of the second processing unit (RE2) or a third processing unit (RE3) communicatively connected to the second processing unit (RE2), at the respective beginning or end of which one of the specified marker information (203) is found during read access. [2] Data exchange method according to claim 1, characterized by , that the first computing unit (RE1) writes a write information (601) at a specified distance to a respective payload segment (201) on a respective memory page (202) when the payload segment (201) to be written on that memory page (202) has finished being written. [3] Data exchange method according to claim 2, characterized by , that the second computing unit (RE2) accesses the first memory (MEM1) multiple times for reading, and only stores the payload segment (201) written on the respective memory page (202) in the second memory (MEM2) if the write information (601) has changed between successive read accesses. [4] Data exchange method according to any one of claims 1 to 3, characterized by , that the first computing unit (RE1) writes an information type information (204) at a defined distance to a respective payload segment (201) on a respective memory page (202), and the second computing unit (RE2) only stores such payload segments (201) in the second memory (MEM2) for which a defined information type information (204) is read from the respective memory page (202). [5] Data exchange method according to any one of claims 1 to 4, characterized by, that the second processing unit (RE2) writes priority information (701) to a respective memory page (202) at a specified distance from a respective payload segment (201), wherein the priority information (701) represents a priority for memory pages (202), and the first processing unit (RE1), should a memory page (202) to be written be blocked by a read access, writes a payload segment (201) to the next free memory page (202), wherein, should no free memory page (202) be found, the first processing unit (RE1) writes the payload segment (201) to the memory page (202) which has the lowest priority information (701). [6] Information technology system comprising a first (RE1) and a second computing unit (RE2), characterized bythat the first (RE1) and second computing unit (RE2) are communicatively connected to each other via a PCIe data line (PCIe-DL) and are configured to execute a method according to one of claims 1 to 5. [7] Information technology system according to claim 6, characterized by a third computing unit (RE3), wherein the third computing unit (RE3) is indirectly communicatively connected to the first computing unit (RE1) via the second computing unit (RE2). [8] Information technology system according to claim 7, characterized by , that the third computing unit (RE3) is connected to the second computing unit (RE2) via a PCle data line (PCle-DL). [9] Information technology system according to one of claims 6 to 8, characterized by , that the first computing unit (RE1) is integrated into a vehicle (101). [10] Information technology system according to any one of claims 6 to 9, characterized by, that the second computing unit (RE2) is designed as a PCIe card and is inserted into a PCIe slot in the third computing unit (RE3).

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