METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND TEMPERATURE MEASURING METHOD

Abstract

A method for manufacturing a semiconductor device, the method comprising: manufacturing a substrate (200), the substrate (200) comprising: a plurality of light-shielding layers (210) arranged at predetermined intervals to shield light of a predetermined wavelength; a workpiece film (110) in which a plurality of different types of layers are stacked in multiple layers and which is located on or above the plurality of light-shielding layers (210); and a mask structure (120p) located on or above the workpiece film (110) and having a plurality of openings; and etching the workpiece film (110) exposed by the plurality of openings, wherein the etching of the workpiece film (110) comprises: irradiating a back side of the substrate (200) with light during the etching of the workpiece film (110);Observing interference light (239sb) generated by interference between first reflected light (238s) reflected by the back of the substrate (200) and second reflected light (238b) transmitted through the substrate (200) and reflected by the undersides of the plurality of light-shielding layers (238b); calculating a temperature of the substrate (200) during etching based on the interference light (239sb); and adjusting the temperature of the substrate (200) during etching based on the temperature of the substrate (200) calculated from the interference light (239sb).

Description

AREA The embodiments described here relate in principle to a method for manufacturing a semiconductor device, a film thickness measurement method, a temperature measurement method and a temperature measurement substrate. BACKGROUND In the manufacturing process of semiconductor devices, plasma etching can be performed on a workpiece film on a substrate. When etching with plasma, it is desirable to achieve a specific etched shape by precisely controlling various etching conditions. Therefore, the challenge lies in accurately acquiring different types of information during the etching process, such as the thickness of the workpiece film on the substrate and the substrate temperature. US 2012 / 0084045A1 describes a temperature measurement method comprising: sending light from a light source to a measurement point on an object to be measured, the object being a substrate on which a thin film is formed; measuring a first interference wave caused by reflected light from a surface of the substrate and a second interference wave caused by reflected light from an interface between the substrate and the thin film, as well as from a back side of the thin film; calculating the optical path length from the first to the second interference wave; calculating the thickness of the thin film based on the intensity of the second interference wave; and calculating the optical path length difference between the optical path length of the substrate and the calculated optical path length based on the calculated thickness of the thin film.Compensating for the optical path length from the first to the second interference wave based on the calculated optical path length difference; and calculating the temperature of the object at the measurement point based on the compensated optical path length. WO 2022 / 163 484 A1 describes a temperature control method comprising: sensing a temperature TB of a temperature control medium before a temperature change during a plurality of processes n in which heat is applied to a substrate placed on the support surface of a table, as well as a pressure Pn of a heat transfer gas supplied to an ejection port of the table, and a temperature TWn of the substrate for each of the processes n; after a temperature change, wherein the temperature of the temperature control medium is the temperature TB, sensing a temperature TW'n,max of the substrate when the pressure of the heat transfer gas is reduced from the pressure Pn, and a temperature TW'n,min of the substrate when the pressure of the heat transfer gas is reduced from the pressure Pn; the temperature of the temperature control medium is set to a temperature TB" that satisfies equation (1).For each process n, the pressure of the heat transfer gas is adjusted so that the substrate temperature reaches the temperature TWn. (1): TB+max(TWn-TW'n,max) ≤ TB" ≤ TB+min(TWn-TW'n,min). US 2007 / 0084847A1 describes a stage onto which a substrate to be processed in a substrate processing device is electrostatically attracted, the stage comprising: a temperature measuring unit that measures the temperature of the substrate to be processed, a temperature setting unit that performs a temperature adjustment on the substrate to be processed to achieve a target temperature based on a preset parameter, and a substrate temperature control unit that controls the temperature of the substrate to be processed by controlling the temperature setting by the temperature setting unit based on a temperature measured by the temperature measuring unit. Brief description of the drawings: Fig. 1 is a cross-sectional view that schematically illustrates an example of a configuration of a plasma processing device according to a first example; Fig.Figure 2 is a schematic graphic representation showing an example of an interferometer configuration according to the first example; Figures 3A and 3B are cross-sectional views illustrating, in turn, some procedures for a method of fabricating a semiconductor device according to the first example; Figures 4A and 4B are cross-sectional views illustrating, in turn, some procedures for a method of fabricating a semiconductor device according to the first example; Figures 5A to 5E are graphic representations to explain data obtained by the interferometer according to the first example; Figure 6 is a cross-sectional view showing an example of a semiconductor device configuration according to the first example; Figure 7 is a flow chart showing an example of plasma processing procedures on a wafer according to the first example; FigureFigure 8 is a cross-sectional view schematically illustrating an example of a configuration of a plasma processing device according to one embodiment; Figures 9A and 9B are schematic views illustrating an example of a mechanism for adjusting the temperature of an electrostatic chuck enclosed in the plasma processing device according to the embodiment; Figures 10A to 10C are cross-sectional views illustrating, in sequence, some procedures for a method of fabricating a semiconductor device according to the embodiment; Figures 11A and 11B are cross-sectional views illustrating, in sequence, some procedures for a method of fabricating a semiconductor device according to the embodiment; Figures 12A and 12B are cross-sectional views illustrating, in sequence, some procedures for a method of fabricating a semiconductor device according to the embodiment; FigureFigure 13 is a schematic graphic representation depicting a light-shielding layer and components positioned on and below the light-shielding layer according to the embodiment; Figures 14A and 14B are schematic graphic representations, each depicting a state of a wafer during plasma processing according to the embodiment; Figure 15 is a flow chart illustrating an example of plasma processing procedures on the wafer according to the embodiment; Figures 16A and 16B are diagrams depicting optical characteristics of materials that are candidates for a light-shielding layer according to a modification of the embodiment; and Figure 17 is a diagram depicting the transmittance of a light-shielding layer according to a modification of the embodiment. DETAILED DESCRIPTION A method for manufacturing a semiconductor device according to claims 1 to 9 and a temperature measurement method according to claims 10 to 15 are disclosed. In principle, a method for manufacturing a semiconductor device according to an example includes the following: fabricating a substrate, wherein the substrate includes: a plurality of light-shielding layers arranged at predetermined intervals to shield light of a predetermined wavelength; a workpiece film located on the plurality of light-shielding layers, comprising a plurality of first insulating layers and a plurality of second insulating layers stacked alternately on top of each other; and a mask structure located on the workpiece film, having a plurality of openings; and etching the workpiece film exposed by the plurality of openings, wherein the etching of the workpiece film includes: irradiating a back side of the substrate with light while the workpiece film is being etched;Observing interference light generated by interference between first reflected light, which is reflected from the back of the substrate, and second reflected light, which passes through the substrate and is reflected from the undersides of the multiple light-shielding layers; calculating a temperature of the substrate during etching based on the interference light; and adjusting the temperature of the substrate during etching based on the temperature of the substrate calculated from the interference light. Embodiments of the present invention are described in detail below with reference to the drawings. It should be noted that the present invention is not limited by the following embodiments. Furthermore, components in the following embodiments include those that can be readily imagined by those skilled in the art or those that are essentially identical. [First example] A first example is described in detail below with reference to the drawings. (Example of a plasma processing unit configuration) Fig. 1 is a cross-sectional view that schematically illustrates an example of a configuration of a plasma processing device 1 according to the first example. The plasma processing device 1 is, for example, configured as a plasma etching device that performs etching on a workpiece film formed on a wafer 100 using plasma. As shown in Fig. 1, the plasma processing device 1 includes a chamber 11, which is a processing vessel for processing the wafer 100. The chamber 11 is made of, for example, aluminum and can be hermetically sealed. A gas supply opening 13 is provided in an upper section of the chamber 11. A gas supply device (not shown) is connected to the gas supply opening 13 via a line to supply a processing gas to be used during the processing of the wafer 100. Below the gas supply opening 13, a nozzle head 18 is provided, which functions as the upper electrode. The nozzle head 18 has a plurality of gas outlet openings 18g that penetrate the nozzle head 18 in the direction of the plate thickness. The processing gas supplied by the gas supply opening 13 is introduced into the chamber 11 through the gas outlet openings 18g. An electrostatic chuck 20 is arranged below the nozzle head 18 such that it faces the nozzle head 18. The electrostatic chuck 20 is configured not only to electrostatically attract and hold the wafer 100 being processed in chamber 11, but also to regulate the temperature of the wafer 100 and additionally functions as the lower electrode. An opening (not shown) for loading / unloading the wafer 100 is provided in a side surface of chamber 11, and the wafer 100 is placed onto the electrostatic chuck 20 in chamber 11 from the loading / unloading opening by a transport arm (not shown). The electrostatic chuck 20 is mounted on a support 12, which projects vertically upwards in a tubular form from a bottom wall near the center of the chamber 11. The support 12 supports the electrostatic chuck 20 near the center of the chamber 11, which is separated from the nozzle head 18 by a predetermined distance, such that it faces parallel to the nozzle head 18. With this configuration, the nozzle head 18 and the electrostatic chuck 20 form a pair of parallel plate electrodes. The electrostatic chuck 20 includes a chuck mechanism that electrostatically attracts the wafer 100. The chuck mechanism includes a chuck electrode 24 serving as a power supply plate, a power supply line 45, and a power supply 46. The power supply 46 is connected to the chuck electrode 24 via the power supply line 45. With this mechanism, direct current from the power supply 46 is supplied to the chuck electrode 24, and one top surface of the electrostatic chuck 20 is electrostatically charged. The power supply line 41 is connected to the electrostatic chuck 20. A decoupling capacitor 42, an adapter 43, and a high-frequency power supply 44 are connected to the power supply line 41. During plasma processing, high-frequency current at a predetermined frequency is supplied from the high-frequency power supply 44 to the electrostatic chuck 20. With this mechanism, the electrostatic chuck 20 also functions as the lower electrode. An insulator ring 15 is arranged on the outer circumference of the electrostatic chuck 20 such that it covers the side surface and a circumferential edge section of the underside of the electrostatic chuck 20. An outer circumferential ring 16 is provided on the insulator ring 15 such that it surrounds the outer circumference of the electrostatic chuck 20. The outer circumferential ring 16 adjusts an electric field such that the electric field at a circumferential edge section of the wafer 100 is not deflected in a vertical direction, i.e., in a direction perpendicular to the surface of the wafer 100, during plasma processing on the wafer 100. A guide plate 17 is provided between the insulator ring 15 and the side wall of the chamber 11. The guide plate 17 has a plurality of gas outlet holes 17e which penetrate the guide plate 17 in the direction of the plate thickness. Below the guide plate 17 in chamber 11, a gas exhaust port 14 is provided. A vacuum pump 14p, which extracts the atmosphere from chamber 11, is connected to the gas exhaust port 14. A region in chamber 11, separated by the electrostatic chuck 20, the guide aperture 17, and the nozzle head 18, is a plasma processing chamber 61. An upper region in chamber 11, separated by the nozzle head 18, is a gas supply chamber 62. A lower region in chamber 11, separated by the electrostatic chuck 20 and the guide aperture 17, is a gas outlet chamber 63. The plasma processing device 1 includes a controller 50 that controls each part of the plasma processing device 1, such as the power supply 46, the adjustment device 43, the high-frequency power supply 44, and the gas supply device. The controller 50 is configured as a computer, including a central processing unit (CPU), read-only memory (ROM), random access memory (RAM), and the like, which are not shown. The controller 50 may be configured as an application-specific integrated circuit (ASIC) or the like, which has a function for use in the plasma processing device 1. During the plasma processing of wafer 100, the wafer to be processed is placed on the electrostatic chuck 20 and attracted by the chuck mechanism under the control of the controller 50. The interior of chamber 11 is emptied by the vacuum pump 14p, which is connected to the gas outlet 14. When the interior of chamber 11 reaches a predetermined pressure, a processing gas is supplied from the gas supply device (not shown) to the gas supply chamber 62 and fed to the plasma processing chamber 61 via the gas outlet openings 18g of the nozzle head 18. Furthermore, by applying a high-frequency voltage to the electrostatic chuck 20 as the lower electrode, plasma is generated in the plasma processing chamber 61 in a state where the nozzle head 18 is grounded as the upper electrode under the control unit 50. On the side of the lower electrode, a potential gradient is created between the plasma and the wafer 100 due to an inherent bias caused by the high-frequency voltage. Ions in the plasma are accelerated towards the electrostatic chuck 20, and anisotropic etching is performed. (Example of an interferometer configuration) In plasma processing device 1, as described in the first example above, processing is carried out, for example, by etching workpiece films of various materials and film thicknesses into a desired shape. The workpiece film is formed from a predetermined material with a predetermined film thickness as the target. However, the film thickness of the workpiece film can vary for each wafer 100. Therefore, in the configuration according to the first example, a film thickness of a workpiece film is measured in advance for each wafer 100 using an interferometer 3, which is described below, and the etching is carried out after an etching condition such as a processing time is optimized based on a result of the measurement of the film thickness. Fig. 2 is a schematic representation showing an example of a configuration of the interferometer 3 according to the first example. The interferometer 3 according to the first example can measure the film thickness of a workpiece film formed on a wafer 100 based on light interference. As shown in Fig. 2, the interferometer 3 includes a light source 31, an optocoupler 32, a collimator objective 33, a placement stage 34, a sensor head 35, a spectroscope 36, a fiber optic cable 37 and an arithmetic device 30. The fiber optic cable 37 connects the light source 31, the optocoupler 32, the collimator lens 33, the sensor head 35 and the spectroscope 36. The light source 31 is a laser diode (LD) or similar device emitting low-coherence laser light. Coherence is an index that indicates the degree of coherence between optical waves, and low-coherence light is light with a small coherence length, i.e., a small difference in optical path length, which causes interference fringes. When performing a measurement using such light, it is possible to observe the target object with a resolution corresponding to the coherence length of the light. With such a light source 31, the interferometer 3 is configured as a low coherence interferometer (LCI) according to the first example. Note that the light emitted by the light source 31 is infrared light, and for example, light with a wavelength of 1200 nm or more, preferably 1250 nm or more and 1350 nm or less, can be used. The optocoupler 32 is a passive optical device that demultiplexes and multiplexes the light from the light source 31. The optocoupler 32 emits the light from the light source 31 to the collimator lens 33. The collimator lens 33 is an aberration-corrected lens, enabling the production of parallel light. The collimator lens 33 focuses the light from the optocoupler 32 to a single point and emits this focused light. The sensor head 35 is provided at the tip of the fiber optic cable 37 and is inserted into a through-hole provided in the placement table 34, on which the wafer 100 can be placed. Thus, the back side of the wafer 100 placed on the placement table 34 is illuminated by the light passing through the light source 31, the optocoupler 32, and the collimator lens 33. The light emitted onto the back side of the wafer 100 is reflected by the wafer 100 itself, a workpiece film placed on the wafer 100, or the like. A multitude of light beams reflected by respective parts of the wafer 100 interfere with each other, are detected by the sensor head 35 as a multitude of types of interference light, and are emitted to the spectroscope 36 via the collimator lens 33 and the optocoupler 32. The spectroscope 36 measures an interference spectrum obtained by performing a spectroscopic analysis of the interference light detected by the sensor head 35 for each wavelength. The interference spectrum obtained by the spectroscope 36 indicates the intensity of the interference light for each wavelength. That is, the interference spectrum is displayed as a diagram in which the horizontal axis represents a wavelength of light and the vertical axis represents light intensity. The spectroscope 36 outputs the measured interference spectrum to the arithmetic device 30. The arithmetic device 30 is configured as a computer, including a CPU, ROM, RAM, and the like (not shown), and performs various calculations based on an interference spectrum. The arithmetic device 30 obtains a correlation signal, for example, by inverse fast Fourier transform (iFFT), and calculates the thickness or similar of each part of the wafer 100 from the optical path length of each part of the wafer 100, which is indicated by a peak of the correlation signal. (Method for manufacturing a semiconductor device) Next, an example of a method for manufacturing a semiconductor device according to the first example is described with reference to Figures 3A to 6. The method for manufacturing the semiconductor device according to the first example includes measuring the film thickness of a workpiece film using the interferometer 3 described above and etching the workpiece film using the plasma processing device 1 described above. Figures 3A and 4B are cross-sectional views illustrating, in turn, some procedures for the method of fabricating the semiconductor device according to the first example. Figures 3A and 4B mainly show how the film thickness of a workpiece film 110 is measured by the interferometer 3 and how the workpiece film 110 is etched by the plasma processing device 1. As shown in Fig. 3A, a workpiece film 110 and a CVD carbon layer 120 are formed in this order on a wafer 100, such as a silicon wafer. A single layer or layered films can be provided between the wafer 100 and the workpiece film 110. For example, workpiece film 110 is a film in which a variety of different types of layers are stacked in multiple layers. For instance, workpiece film 110 is a film in which silicon nitride (SiN) layers NL as the first insulating layer and silicon oxide (SiO) layers OL as the second insulating layer are alternately stacked individually on top of each other. The number of silicon nitride layers NL and the number of silicon oxide layers OL included in workpiece film 110 can range from approximately 50 to 400. The CVD carbon layer 120 is an organic layer consisting primarily of carbon, formed, for example, by plasma chemical vapor deposition (CVD) or similar processes. An example of such a CVD carbon layer 120 is an advanced structuring film (APF) manufactured by Applied Materials, Inc. Furthermore, the thickness of the workpiece film 110 is measured using the interferometer 3 described above. That is, the wafer 100, on which the workpiece film 110 and the CVD carbon layer 120 are formed, is placed on the placement table 34, and the back side of the wafer 100 is irradiated with laser light or the like from the light source 31 via the sensor head 35. Part of the laser light irradiating the back side of wafer 100 is reflected by the back side of wafer 100 and detected as reflected light 38s by the sensor head 35 of interferometer 3. Another part of the laser light passes through wafer 100, is reflected by a bottom surface of the workpiece film 110 (also referred to as the lower surface, i.e., a surface in contact with the front side of wafer 100), and is detected by sensor head 35 as reflected light 38p. A further part of the laser light passes through wafer 100 and the workpiece film 110, is reflected by a bottom surface (also referred to as the lower surface of the CVD carbon layer 120, i.e., a surface in contact with a top surface of the workpiece film 110), and is detected by sensor head 35 as reflected light 38c. The spectroscope 36 of the interferometer 3 measures a spectrum of an interference wave obtained by interference between the reflected light 38s, the reflected light 38p, and the reflected light 38c. The arithmetic device 30 of the interferometer 3 calculates the film thickness of the workpiece film 110 by performing various calculations based on the interference spectrum measured by the spectroscope 36. This means that the optical path length of wafer 100 is obtained from interference light 39sp between the reflected light 38s from the back of wafer 100 and the reflected light 38p from the bottom surface of the workpiece film 110. The optical path length is the distance that light travels in a vacuum in a time equal to the time it takes for the light to travel through a predetermined substance, and is expressed as the product of the refractive index of the target substance and the distance. Since the optical path length of wafer 100 depends on the refractive index and the thickness of wafer 100, the thickness of wafer 100 can be determined from the optical path length of wafer 100 made of a known material. Furthermore, from the interference light 39sc between the reflected light 38s from the back of the wafer 100 and the reflected light 38c from the lower surface of the CVD carbon layer 120, a total optical path length of the wafer 100 and the workpiece film 110 is obtained. If the influence of the optical path length of the wafer 100 described above is subtracted from the total optical path length, the optical path length of the workpiece film 110 alone can be obtained, and the film thickness of the workpiece film 110 can be determined from the optical path length of the workpiece film 110, which is made of a known material. Note that the film thickness measurement is preferably performed at a plurality of points within a plane of the wafer 100. If a plurality of measurement data points are obtained from a wafer 100, a mean value or the like of these measurement data points can be used as the film thickness of the workpiece film 110. As shown in Fig. 3B, a silicon oxynitride (SiON) layer 130 and a resist structure 140p are formed on the CVD carbon layer 120 in that order. The silicon oxynitride layer 130 is formed, for example, by plasma CVD or the like. The resist structure 140p is formed by spin coating, exposure, and development of a resist layer and has a structure corresponding to the shape to be formed on the workpiece film 110 by the plasma processing described below. In the example of Fig. 3B, the resist structure 140p has a structure that includes a plurality of hole-shaped openings to form through holes in the workpiece film 110. The silicon oxynitride layer 130 is then etched using the resist structure 140p as a mask, and the structure of the resist structure 140p is transferred to the silicon oxynitride layer 130. Furthermore, the CVD carbon layer 120 is etched using the silicon oxynitride layer 130, onto which the structure is transferred, as a mask, and the structure of the silicon oxynitride layer 130 is further transferred to the CVD carbon layer 120. As shown in Fig. 4A, a mask structure 120p is formed on the workpiece film 110 by transferring the structure to the CVD carbon layer 120 through etching. Note that the resist structure 140p and the silicon oxynitride layer 130 disappear successively through etching. As shown in Fig. 4B, the workpiece film 110 exposed by the openings of the mask structure 120p is etched and penetrated, for example by the plasma processing device 1 described above. As a result, a plurality of through holes 111 are formed in the workpiece film 110. The front side of the wafer 100 is exposed by the undersides of the through holes 111. Note that the etching of the silicon oxynitride layer 130 and the etching of the CVD carbon layer 120 can also be carried out by the plasma processing device 1. In this case, the silicon oxynitride layer 130, the CVD carbon layer 120 and the workpiece film 110 can be etched sequentially in one go. When the through-holes 111 are formed by the etching of the workpiece film 110 as described above, a film thickness measurement from the interferometer 3 is used. That is, when etching is carried out on the workpiece film 110, an etching condition is used under which the etching time or the like is readjusted based on the film thickness of the workpiece film 110 obtained by the interferometer 3, so that the workpiece film 110 is penetrated more reliably and the exposed front of the wafer 100 is not unnecessarily etched away. Figures 5A to 5E now show more detailed examples of data obtained by the interferometer 3. Figures 5A to 5E are graphical representations illustrating data obtained by the interferometer 3 according to the first example. Figure 5A is an example of spectral data over one optical path length of wafer 100 obtained by the interferometer 3. Each of Figures 5B to 5E represents a state of wafer 100 when the spectral data of Figure 5A are obtained. In particular, Fig. 5B is a cross-sectional view of a wafer 100 alone. Fig. 5C is a cross-sectional view of the wafer 100 after the workpiece film 110 and the CVD carbon layer 120 have been formed. Fig. 5D is a cross-sectional view of the wafer 100 after a structure has been transferred to the CVD carbon layer 120 and a mask structure 120p has been formed. Fig. 5E is a cross-sectional view of the wafer 100 after etching on the workpiece film 110 has been completed and through holes 111 have been formed. This means that the spectral data obtained from wafer 100 in Fig. 5C correspond to data used to measure the film thickness of the workpiece film 110 in the process of manufacturing the semiconductor device according to the first example described above. On the other hand, the spectral data obtained from wafer 100 in Figs. 5B, 5D, and 5E are shown in Fig. 5A for reference. As shown in Fig. 5A, the interferometer 3 obtains spectral data from the wafer 100 in every state, where the horizontal axis represents the optical path length and the vertical axis represents the intensity. The spectrum obtained by the interferometer 3 varies considerably depending on the state of the wafer 100. For example, in a state of wafer 100 alone, when many wafers 100 are fed in, spectral data are obtained that exhibit a peak at a predetermined optical path length. The optical path length peak is obtained from interference light between the light reflected from the back of wafer 100 and the light reflected from the front of wafer 100 but not transmitted. In the case of wafer 100 alone, no workpiece film 110 or similar material is formed on the wafer 100, and the front face of wafer 100 is in contact with the atmosphere, such as air, at the time of measurement by interferometer 3. Since reflection and transmission of light occur at a plane of contact between substances with different refractive indices, interference light is observed due to reflected light being reflected by the front and back faces of wafer 100, even in the case where wafer 100 is alone, as described above. As described above, the peak of the spectral data of wafer 100 alone indicates an optical path length of wafer 100. Furthermore, spectral data with two peaks are obtained from a wafer 100 on which the workpiece film 110 and the CVD carbon layer 120 were formed. One of the two peaks is a peak that indicates an optical path length of the wafer 100 obtained from the interference light 39sp between the reflected light 38s from the back of the wafer 100 and the reflected light 38p from the underside of the workpiece film 110 shown in Fig. 3A. It is assumed that the reason why the intensity of the peak indicating the optical path length of wafer 100 is lower than the intensity of the peak obtained solely from wafer 100 is that the workpiece film 110 formed on wafer 100 attenuates the reflection of light at the front of wafer 100. That is, it is estimated that the reflected light is attenuated 38s from the front of wafer 100 because some of the light is transmitted from wafer 100 to the workpiece film 110. The other of the two peaks included in the spectral data is a peak that indicates a total optical path length of the wafer 100 and the workpiece film 110, obtained from the interference light 39sc between the reflected light 38s from the back of the wafer 100 and the reflected light 38c from the underside of the CVD carbon layer 120. Note that the CVD carbon layer 120 has the property that both its extinction coefficient, which indicates the attenuation of light in a substance, and its refractive index with respect to infrared light with a wavelength of 1200 nm or more are high. This means that the CVD carbon layer 120 can function as a light-shielding layer, exhibiting, for example, low transmittance and high reflectance with respect to infrared light. Therefore, most of the light emitted from the light source 31 of the interferometer 3 to the back of the wafer 100 and transmitted through the wafer 100 and the workpiece film 110 is reflected at an interface between the workpiece film 110 and the CVD carbon layer 120 without passing through the top surface of the workpiece film 110. It can therefore be assumed that the reflected light 38p is detected from the underside of the workpiece film 110 with relatively high intensity. Furthermore, spectral data obtained from wafer 100 after a mask structure 120p has been formed by transferring the resist structure 140p over the silicon oxynitride layer 130 onto the CVD carbon layer 120 are essentially similar to those obtained from wafer 100 provided with the CVD carbon layer 120 before the structure is transferred onto it. However, the mask structure 120p has a multitude of openings. Therefore, the reflected light that is reflected without passing through the top surface of the workpiece film 110 includes light that has passed through the workpiece film 110, reached sections of the mask structure 120p without openings, and has been reflected through the underside of the CVD carbon layer 120 that contacts the workpiece film 110, and light that has passed through the workpiece film 110, reached the openings of the mask structure 120p, and has been reflected through air or the like that touches the top surface of the workpiece film 110 exposed by the openings. This is considered the reason why the spectral data obtained from wafer 100 before the structure is transferred to the CVD carbon layer 120 do not completely match those obtained after the structure has been transferred to the CVD carbon layer 120. Furthermore, after the multitude of through holes 111 in the workpiece film 110 is formed by etching through the mask structure 120p, spectral data with a peak near the optical path length of the wafer 100 are obtained from the wafer 100. The front face of wafer 100 after etching is partially exposed compared to the state in which the front face of wafer 100 is completely covered with the workpiece film 110 before etching. That is, after etching, wafer 100 on the workpiece film 110 is in a state in which the state shown in Fig. 5B and the state shown in Fig. 5C are mixed. Therefore, it can be assumed that spectral data exhibiting a peak as shown in Fig. 5A are obtained when two peak positions caused by the interference light 39sp and the interference light 39sc come close to each other, by amplifying or attenuating the interference light 39sp between the reflected light 38s from the back of the wafer 100 and the reflected light 38p from the underside of the workpiece film 110 and the interference light 39sc between the reflected light 38s from the back of the wafer 100 and the reflected light 38c from the underside of the CVD carbon layer 120. As described above, the spectral data in wafer 100 show a peak at each of the processing stages which, based on the interference light 39sp, indicates an optical path length of wafer 100, and the spectral data in wafer 100 at some of the processing stages show a peak which, based on the interference light 39sc, indicates a total optical path length of wafer 100 and workpiece film 110. Since, as described above, these two peak positions move, the film thickness difference of the workpiece film 110 within the plane of the wafer 100 can be detected for each wafer 100 or for each batch, for example, as an optical path length difference of the workpiece film 110 obtained from spectral data. The peak position, intensity, and other spectral characteristics are determined by the wafer 100, on which the workpiece film 110 and similar components are formed, by complex factors that include the reflection and attenuation of light in each configuration. The workpiece film 110 itself has a multilayered structure that includes the insulating layers NL and OL, and reflection and transmission are repeated for each of a large number of interfaces between the insulating layers NL and OL. The light, which, as described above, has been repeatedly split into transmission and reflection components for all layers, exhibits complex behavior that is also reflected in the peak position, intensity, and other spectral data. Therefore, the arithmetic device 30 of the interferometer 3 can have a database or the like of spectral data for each film thickness of the workpiece film 110. In the actual calculation of a film thickness of the workpiece film 110, the arithmetic device 30 can identify the film thickness of the workpiece film 110 based on the spectral data obtained from the wafer 100 to be measured, referring to the database described above. Subsequently, the formation of various films, etching, and other processing steps are repeated to fabricate the semiconductor device according to the first example. An example of a configuration of a semiconductor device 10 according to the first example is shown in Fig. 6. Fig. 6 is a cross-sectional view showing an example of a configuration of the semiconductor device 10 according to the first example. However, the hatching in Fig. 1 has been omitted to facilitate viewing the drawing. As shown in Fig. 6, the semiconductor device 10 includes an electrode layer EL, a source line SL, and a plurality of word lines WL in that order, starting from the bottom of the paper. The semiconductor device 10 also includes a peripheral circuit CBA, which is provided on a semiconductor substrate SB above the plurality of word lines WL. In the following description, the side on which the semiconductor substrate SB is arranged is referred to as the top of the semiconductor device 10. The source conductor SL is arranged on the electrode layer EL via an insulating film 160. A plurality of plugs PG are arranged in the insulating film 160, and the source conductor SL and the electrode layer EL maintain electrical conductivity via the plugs PG. Consequently, a source potential from outside the semiconductor device 10 can be applied to the source conductor SL via the electrode layer EL and the plugs PG. The plurality of word lines WL is stacked on the source line SL. In the semiconductor device 10, a region in which the plurality of word lines WL is arranged corresponds to an element region ER. A memory region MR is arranged in a central section of each of the plurality of word lines WL, and stage regions SR are arranged at both ends of the memory region MR. Note that, although the semiconductor device 10 in the example of Fig. 6 has only one stacked structure of word lines WL in the element area ER, the semiconductor device 10 can have a plurality of stacked structures of word lines WL in the element area ER, each of which has a storage area MR and stage areas SR. In the memory region MR, a multitude of pillars PL are arranged, which penetrate the word lines WL in a stacking direction. At the intersection points between the pillars PL and the word lines WL, a multitude of memory cells are formed. The semiconductor device 10 is configured, for example, as a three-dimensional non-volatile memory in which the memory cells are arranged three-dimensionally in the memory region MR. In the stage areas SR, the multitude of word lines WL are processed into a stage form and completed. A contact CC, connected to the word line WL of each layer, is located in a terrace section of each of the stages configured by the multitude of word lines WL. The word lines WL, layered in several levels, are individually brought out by these contacts CC. From these contacts CC, a write voltage, a read voltage, and the like are applied to memory cells located in the memory area MR, in the middle section of each of the multitude of word lines WL, at the same height as the memory cells. The multitude of word lines WL, pillars PL, and contacts CC are covered with the insulating film 150. The insulating film 150 also extends around the multitude of word lines WL. The peripheral circuitry CBA, provided on the semiconductor substrate SB, is arranged above the insulating film 150. The semiconductor substrate SB is, for example, a silicon substrate or the like. The peripheral circuit CBA, which includes a transistor TR, wiring, and the like, is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells by the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to the contacts CC. Consequently, the peripheral circuit CBA controls the electrical operation of the memory cell. The peripheral circuit CBA is covered with an insulating film 170, and the semiconductor device 10, which includes the plurality of word lines WL, columns PL, contacts CC and the like, as well as the peripheral circuit CBA, is formed by bonding the insulating film 170 and the insulating film 150, which covers the plurality of word lines WL, together. In the manufacture of such a semiconductor device 10, a layered body in which a plurality of silicon nitride layers and a plurality of silicon oxide layers are alternately layered on top of each other is formed on a predetermined substrate via a source line SL. Furthermore, stepwise etching is performed on a portion of the layered body to form a step region SR. Additionally, storage holes are formed in the layered body by the same etching process to create pillars PL, and these storage holes are filled with a storage layer, a semiconductor layer, or the like. Subsequently, word lines (WL) are formed by a process that replaces the numerous silicon nitride layers of the layered body with conductive layers, a process known as exchange processing. Additionally, a contact (CC) is formed in the step region (SR), and top-layer wiring or similar is formed in an upper layer of the layered body. Here, for example, plasma processing is used during the etching process on the layered body prior to the exchange machining, using the plasma machining device 1 described above. That is, the layered body prior to the exchange machining corresponds to the workpiece film 110 described above, and the silicon nitride layers NL and the silicon oxide layers OL of the workpiece film 110 are subjected to plasma machining to form a variety of storage holes corresponding to the through holes 111 described above. The substrate on which the layered body is formed corresponds to wafer 100 as described above. The source line SL is formed, for example, by diffusion from defects on the surface of wafer 100. Note that even if another layer, such as the source line SL, is inserted between wafer 100 and the workpiece film 110, the thickness of the workpiece film 110 can still be measured by interferometer 3 as described above, as long as the inserted layer is not a light-shielding layer such as the CVD carbon layer 120. After the layered body undergoes exchange processing and a top-layer wiring or similar is formed on the layered body, the semiconductor substrate SB, on which the peripheral circuit CBA has been formed, is bonded to the substrate on which the layered body and similar components are formed, i.e., the wafer 100. The wafer 100 is then removed by reverse looping or similar, leaving the source conductor SL. Furthermore, an insulating film 160 with plug PG, an electrode layer EL, and similar components are formed beneath the source conductor SL. In this way, the semiconductor device 10 is manufactured according to the first example. (Example of plasma processing) Next, with reference to Fig. 7, an example is described in which the wafer 100 is processed using the plasma processing device 1 and the interferometer 3 according to the first example. Fig. 7 is a flowchart illustrating an example of plasma processing procedures for wafer 100 according to the first example. The flowchart in Fig. 7 depicts procedures from the input of a batch until the input batch of wafers 100 is processed by the plasma processing unit 1. As shown in Fig. 7, wafers 100 for a batch containing a predetermined number of wafers 100 are fed into the manufacturing process (step S101). Note that in the process of manufacturing the semiconductor device 10, processing is advanced for each batch. A workpiece film 110, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately layered individually on top of each other, is formed on each of the wafers 100 of a batch (step S102). Furthermore, a CVD carbon layer 120 is formed on the workpiece film 110 (step S103). For example, the film thickness of the workpiece film 110 is measured, for instance, by performing a measurement with respect to the wafer 100 using the interferometer 3 in a state where the CVD carbon layer 120 has formed (step S104). As described above with respect to a wafer 100, film thicknesses can be measured at a multitude of locations in the plane of the wafer 100, and an average or similar value of a multitude of obtained pieces of data can be used as the film thickness of the workpiece film 110 in the wafer 100. The film thickness of the workpiece film 110 is measured with respect to at least one wafer 100 among the wafers 100 of a batch. Alternatively, the film thickness can be measured with respect to several wafers 100, such as the first wafer 100, a middle wafer 100, and the last wafer 100 of the batch. Alternatively, the film thickness can be measured with respect to all wafers 100 of a batch. After measuring the film thickness of the workpiece film 110, a silicon oxynitride layer 130 is formed on the CVD carbon layer 120 (step S105), and furthermore a resist structure 140p is formed on the silicon oxynitride layer 130 (step S106). For each wafer 100, etching is performed on the silicon oxynitride layer 130 using the resist structure 140p as a mask (step S107), and etching is performed on the CVD carbon layer 120 using the silicon oxynitride layer 130 onto which the resist structure 140p has been transferred as a mask (step S108). As a result, a mask structure 120p is formed on each wafer 100 by transferring the structure onto the CVD carbon layer 120. For each wafer 100, etching is performed on the workpiece film 110 exposed at the mask structure 120p (step S109). An etching condition, such as an etching duration, is adjusted based on the film thickness of the workpiece film 110 measured by the interferometer 3, so that the workpiece film 110 is properly penetrated. In a case where the film thickness measurement is performed in relation to a wafer 100, the film thickness of the workpiece film 110 for the wafer 100 is used as a representative value and is applied to all wafer 100s in a batch. In a case where film thickness is measured on a large number of wafers, an average of these thickness measurements can be applied to all wafers in a batch. Alternatively, the wafers in a batch can be grouped according to the number of wafers for which the film thickness measurement was performed. For example, a film thickness obtained from the first wafer in the batch can be applied to the wafers on the front side, a film thickness obtained from a middle wafer in the batch can be applied to wafers near the center, and a film thickness obtained from the last wafer in the batch can be applied to wafers on the back side. In a case where the film thickness measurement is performed in relation to all Wafer 100 in a batch, an etching condition based on the corresponding film thickness can be applied to each Wafer 100. During etching, the control unit 50 determines whether, under the etching condition corresponding to the film thickness of the workpiece film 110, a time has been reached to end the etching of the workpiece film 110 (step S110). The controller 50 continues etching until the point at which etching of the workpiece film 110 is stopped is reached (step S110: No) (step S109). When the point at which etching of the workpiece film 110 is stopped is reached (step S110: Yes), the controller 50 stops the power supply to chamber 11. This concludes the plasma processing on wafer 100, as in the first example. (Overview) In a process for manufacturing a semiconductor device, etching on a workpiece film can be performed using a plasma processing device. The etching on the workpiece film is carried out using an etching condition that is suitably determined in advance. However, while the film thickness of a workpiece film is checked during the formation of each wafer, for example through periodic quality control, the film thickness can vary for each wafer or batch. In a case where the workpiece film has a multilayered structure with a variety of different types of layers, the variation in film thickness between batches is approximately ±10%. If etching is performed uniformly on such workpiece films using the same conditions, in a case where the actual film thickness of a workpiece film is greater than the target film thickness, the etching will stop without achieving the desired etching depth. Furthermore, in a case where the actual film thickness of a workpiece film is less than the target film thickness, excessive etching can cause the base film of the workpiece film to be etched away or alter the processed shape of the workpiece film, such as an extension in one dimension. Therefore, as an example of a countermeasure, a change in the emission wavelength during plasma processing can be monitored, and an endpoint can be detected in real time. However, in a case where the etching area exposed by the mask structure, i.e., the coverage area of ​​the mask structure, is small under a specific etching condition, it is not possible to adequately detect a change in wavelength, and consequently, it is not possible to detect an endpoint. Furthermore, as an example of a countermeasure, one could consider measuring the film thickness using an optical film thickness gauge, such as an ellipsometer, after a workpiece film has formed, and adjusting an etching condition, such as an etching time, based on the measurement result. However, in a case where the workpiece film has, for example, a multilayered structure with a variety of different types of layers, and the total number of layers exceeds 100, it is difficult to measure the film thickness accurately using the optical film thickness gauge. In the method for manufacturing the semiconductor device according to the first example, the back side of the wafer 100 is irradiated with light, and the thickness of the workpiece film 110 is calculated on the basis of interference light 39sp, which is generated by interference between reflected light 38s, which is reflected by the back side of the wafer 100, and reflected light 38p, which is transmitted through the wafer 100 and reflected by the underside of the workpiece film 110, and interference light 39sc, which is generated by interference between the reflected light 38s and the reflected light 38c, which is transmitted through the wafer 100 and the workpiece film 110 and reflected by the underside of the CVD carbon layer 120. Consequently, the film thickness of the workpiece film 110 can be measured with high accuracy. By measuring the film thickness using the interferometer 3, as described above, film thickness information regarding the workpiece film 110 on the wafer 100 can be obtained with high accuracy. In the method for manufacturing the semiconductor device according to the first example, the etching is carried out under an etching condition based on the thickness of the workpiece film 110, which is calculated from the interference light 39sp and the interference light 39sc, such that the workpiece film 110 exposed by the mask structure 120p is penetrated. As a result, the machining can be carried out on the workpiece film 110, which varies in film thickness for each wafer 100 or for each batch, under the appropriate etching conditions. In the method for manufacturing the semiconductor device according to the first example, during the formation of the mask structure 120p, a structure is formed on the CVD carbon layer 120 that shields the light emitted onto the wafer 100 as a mask structure 120p. This allows the intensity of the reflected light 38sc, which is transmitted and reflected through the wafer 100 and the workpiece film 110 without being transmitted through the top surface of the workpiece film 110, to be increased, and the accuracy in measuring the film thickness can be improved. In the method for manufacturing the semiconductor device according to the first example, the workpiece film 110 is a film in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately layered one on top of the other, and the plurality of insulating layers NL enclosed in the workpiece film 110 is 50 or more layers. Therefore, the number of both types of insulating layers NL and OL enclosed in the workpiece film 110 is 100 or more. As described above, the film thickness of the workpiece film 110 can be measured with high accuracy using the interferometer 3, even in cases where the workpiece film 110 has a multilayered structure and measuring the film thickness using an optical film thickness gauge is difficult. Furthermore, for example, even in cases where it is difficult to detect an endpoint by observing plasma emission, an etching condition, such as an etching time, can be optimized by measuring the film thickness of the workpiece film 110 using the interferometer 3. In the first example described above, the thickness of the workpiece film 110 is measured by the interferometer 3 after the CVD carbon layer 120 has formed on the workpiece film 110. However, the thickness of the workpiece film 110 can also be measured, for example, at a time point after the workpiece film 110 has formed and before the CVD carbon layer 120 has formed. At an interface between substances with different refractive indices, transmission and reflection of light occur. Therefore, after the formation of the workpiece film 110, even in a state where the top surface of the workpiece film 110 is in contact with an atmosphere in a measurement environment such as air, the film thickness of the workpiece film 110 can be measured using the interferometer 3. The film thickness of the workpiece film 110 can be measured at any time after the formation of the CVD carbon layer 120, after the formation of the silicon oxynitride layer 130, after the formation of the resist structure 140p, after etching the silicon oxynitride layer 130 or after etching the CVD carbon layer 120. In this way, the film thickness of the workpiece film 110 can be measured at any time after the workpiece film 110 has formed and before the etching of the workpiece film 110 has begun. Note that in a case where the film thickness measurement is carried out after another layer is formed on the workpiece film 110, a layer acting as a light-shielding layer is preferably formed at least directly on the workpiece film 110. For example, the CVD carbon layer 120 exhibits the light-shielding properties described above. Therefore, even in a case where the silicon oxynitride layer 130, the resist structure 140p, and the like are formed on the CVD carbon layer 120, the amount of light transmitted through these layers is extremely small, and it can be assumed that these layers have a negligible influence on the measurement of the film thickness of the workpiece film 110. Furthermore, the layer acting as a light shielding layer can be a titanium layer, a tungsten layer or a nitride layer made of a carbon-based material, titanium or tungsten, as well as the carbon-based layer such as the CVD carbon layer 120 described above. In the first example described above, the interference light 39sp between the reflected light 38s and the reflected light 38p from the front and back of the wafer 100, the wafer on which the workpiece film 110 and the like are formed, is measured, and the influence of the wafer 100 on the interference light 39sc obtained from the workpiece film 110 is estimated. However, for example, an interference spectrum of wafer 100 can be obtained simply by performing a measurement using interferometer 3 in a state where wafer 100 exists alone, before the workpiece film 110 is formed. The film thickness of the workpiece film 110 can then be determined from the analysis of the interference spectrum of wafer 100 alone and the interference spectrum obtained from wafer 100 on which the workpiece film 110 and the like have formed. It can be assumed that a silicon wafer or the like, used to manufacture a semiconductor device, is subject to strict quality control, and that there are almost no deviations in the various specifications of the silicon wafer, including its thickness. However, even in this case, it can be assumed that the film thickness of the workpiece film 110 can be measured more reliably and accurately by considering not only the interference spectrum of wafer 100 after the formation of workpiece film 110, but also the interference spectrum of wafer 100 alone. Measurements can be performed on a single wafer at multiple locations within its plane, for example, when a batch is introduced. Alternatively, measurements can be performed on one or more wafers included in the batch. All wafers within the batch can be inspected. Furthermore, in the first example described above, etching is performed to obtain a desired machined shape, for example by changing the etching time based on the film thickness of the workpiece film 110 obtained by the interferometer 3. However, the etching conditions include various parameters that are capable of controlling an etching rate and a machined shape, such as pressure, radio frequency power value, type and flow rate of a processing gas, and wafer temperature. Therefore, if the etching condition is changed based on the film thickness of the workpiece film 110, other parameters can be changed instead of or in addition to the etching condition. [Version] One embodiment is described in detail below with reference to the drawings. This embodiment differs from the first example in that a wafer temperature is measured during plasma processing using interference light. In the drawings mentioned below, the same reference numerals are used for components identical to those in the first example described above, and their descriptions can be omitted. (Example of a plasma processing unit configuration) Fig. 8 is a cross-sectional view schematically showing an example of a configuration of a plasma processing device 2 according to the embodiment. The plasma processing device 2 according to the embodiment includes components that correspond to the respective components of the interferometer 3 according to the first example described above. That is, the plasma processing device 2 includes a light source 231, an optocoupler 232, a collimator lens 233, a sensor head 235, a spectroscope 236, and an optical fiber 237 as a configuration equivalent to the interferometer 3 according to the first example described above. Furthermore, the plasma processing device 2 includes an electrostatic chuck 220 and a controller 250 instead of the electrostatic chuck 20 and controller 50 according to the first example described above. Similar to the interferometer 3 according to the first example described above, the optical fiber 237 connects the light source 231, the optocoupler 232, the collimator lens 233, the sensor head 235, and the spectroscope 236. The sensor head 235 is inserted into a through-hole provided in the electrostatic chuck 220 in chamber 11 of the plasma processing device 2. Thus, the back side of the wafer 200, placed on the electrostatic chuck 220, can be illuminated with light from the light source 231 via the sensor head 235. Additionally, interference light is emitted from each part of the wafer 200 via the sensor head 235 and the collimator lens 233 to the spectroscope 236, and the spectroscope 236 outputs an interference spectrum obtained by analyzing the interference light to the controller 250. By using the interference spectrum obtained as described above, the temperature of a substance such as wafer 200, which is made of a known material and has a known thickness, can be calculated. The controller 250 of the plasma processing unit 2 also functions as an arithmetic device that analyzes the interference spectrum from the spectroscope 236. Therefore, the controller 250 analyzes the interference spectrum of the wafer 200 output by the spectroscope 236 and calculates the temperature of the wafer 200 during plasma processing in the plasma processing unit 2. (Example of the configuration of an electrostatic chuck) Next, a mechanism for adjusting the temperature of the electrostatic chuck 220 is described with reference to Fig. 9A and 9B. Figures 9A and 9B are schematic views illustrating an example of a mechanism for adjusting the temperature of the electrostatic chuck 220, which is enclosed in the plasma processing device 2 according to the embodiment. Figure 9A is a top view of the electrostatic chuck 220, and Figure 9B is a schematic view of the temperature adjustment mechanism, including a cross-section of the electrostatic chuck 220. A through-hole into which the sensor head 235 is inserted is not shown in Figures 9A and 9B. As shown in Figures 9A and 9B, the electrostatic chuck 220 of the plasma processing device 2 comprises a main body 21, a chuck part 22, and a ceramic plate 23. The main body 21 serves as the base of the electrostatic chuck 220. The chuck part 22 includes the chuck electrode 24 and the like, as described above, and is arranged on the main body 21. The ceramic plate 23 is arranged on the outermost surface of the electrostatic chuck 220 and serves as a surface for placing the wafer 200. Furthermore, the electrostatic chuck 220 includes a coolant flow path 25 and a gas flow path 28, which form part of the temperature control mechanism. In addition to the coolant flow path 25 and the gas flow path 28, the electrostatic chuck 220 is equipped with a cooler 82, a gas supply line 81, a mass flow controller (MFC) 83, a valve 84, a tank 85, and temperature sensors 86 and 87 as a temperature control mechanism. The cooler 82 is connected to the main body 21 of the electrostatic chuck 220 and is configured to circulate the coolant, which is controlled to a predetermined temperature, within the electrostatic chuck 220. Specifically, the coolant is discharged from an outlet port of the cooler 82 towards the electrostatic chuck 220 and flows into an inlet port of the cooler 82, thus circulating between the cooler 82 and the electrostatic chuck 220. The coolant can be, for example, a fluorinated hydrocarbon such as ethylene glycol, water, or another liquid, depending on the desired temperature range. The coolant flow path 25 is provided at a predetermined depth position within the main body 21 of the electrostatic chuck 220 along the surface of the electrostatic chuck 220, i.e., along the ceramic plate 23, which is a surface for placing the wafer 200. The coolant flow path 25 can have any shape, such as meandering within the body 21 or branching into a multitude of paths within the main body 21. The coolant flow path 25 can include a multitude of independent flow paths. Temperature sensor 87 is provided on the inlet side of the coolant flow path 25 to the main body 21, and temperature sensor 86 is provided on the outlet side of the coolant flow path 25. The radiator 82 controls the coolant temperature based on the detection results of temperature sensors 86 and 87. The gas flow path 28 is provided such that it penetrates the electrostatic chuck 220 and has a plurality of openings 28g that are open to the surface of the ceramic plate 23. The plurality of openings 28g are provided in a manner distributed over the entire surface of the ceramic plate 23. In a case where the coolant flow path 25 includes a plurality of independent flow paths, the gas flow path 28 can also include a plurality of independent flow paths. A downstream end of the gas supply line 81, which has an upstream end to which the gas supply source CY is connected, is connected to an upstream end of the gas flow path 28. The gas supply source CY stores a gas with high thermal conductivity, such as helium or argon gas. The gas supply line 81 is equipped with an MFC 83, a valve 84, and a tank 85, in that order from the upstream side. The tank 85 is equipped with a pressure sensor 85p, which measures the pressure in the tank 85. By opening the valve 84 of the gas supply line 81, the flow rate of the gas flowing from the gas supply source CY through the MFC 83 is controlled, the gas is stored once in the tank 85 and the pressure of the gas is readjusted, and the gas is distributed from the multitude of openings 28g of the ceramic plate 23 between the front of the ceramic plate 23 and the back of the wafer 200. The controller 250 of the plasma processing device 2 controls the pressure in tank 85 by changing the gas flow rate through the MFC 83 based on the measurement result of the pressure sensor 85p. As a result, the gas temporarily stored in tank 85 is supplied to the plurality of openings 28g of the ceramic plate 23 at a predetermined pressure. As described above, the gas flow path 28, through which the gas with high thermal conductivity flows, is located near the coolant flow path 25, through which the temperature-controlled coolant flows, on the side which is closer to the ceramic plate 23, which is a surface for placing the wafer 200, than the coolant flow path 25. As a result, heat exchange takes place between the coolant flowing through coolant flow path 25 and the gas flowing through gas flow path 28, and the gas is controlled to a predetermined temperature. The gas, controlled to the predetermined temperature, is distributed to the back side of wafer 200, allowing the temperature of wafer 200 to be adjusted. In a case where each of the coolant flow path 25 and the gas flow path 28 includes a multitude of independent flow paths, as described above, the electrostatic chuck 220 can be divided into a multitude of zones and adjusted to different temperatures for the respective zones. (Method for manufacturing semiconductor devices) Next, an example of a method for manufacturing a semiconductor device according to the embodiment is described with reference to Figures 10A to 14B. The method for manufacturing the semiconductor device according to the embodiment includes plasma processing on the wafer 200 in the plasma processing unit 2 described above. Figures 10A to 12B are cross-sectional views illustrating, in succession, some procedures for the method of manufacturing the semiconductor device according to the embodiment. Figures 10A to 12B mainly depict the state from the input of a batch to the execution of the etching process by the plasma processing unit 2. As shown in Figs. 10A to 10C, in the method for manufacturing the semiconductor device according to the embodiment, a plurality of light-shielding layers 210 are formed on the front side of the wafer 200 after the batch is introduced. That is, as shown in Fig. 10A, a plurality of recesses 201 are formed on the front face of the wafer 200. In a region that vertically overlaps the back face of the wafer 200 in a section to be later illuminated with light by the sensor head 235, the plurality of recesses 201 have substantially identical areas in plan view and are arranged periodically at predetermined intervals. The spacing between the plurality of recesses 201 is set such that it is smaller than the wavelength of the light to be emitted onto the back face of the wafer 200. As shown in Fig. 10B, the plurality of recesses 201 is filled with a CVD carbon layer. Consequently, in the area of ​​the front of the wafer 200, which corresponds to the back of the wafer 200 in the section subsequently irradiated with light, a plurality of light-shielding layers 210 are formed, which are arranged periodically at predetermined intervals. The shape of the multitude of light-shielding layers 210, viewed from above, is, for example, circular, oval, elliptical, polygonal, or the like. The multitude of light-shielding layers 210 can, for example, be arranged in a hexagonally close-packed lattice structure such that the interval between the multitude of light-shielding layers 210 is smaller than the wavelength of light. However, the multitude of recesses 201 and the multitude of light-shielding layers 210 can be formed over the entire surface of the wafer 200. As shown in Fig. 10C, a workpiece film 110 is formed on the wafer 200, in which a plurality of insulating layers NL and OL (see Fig. 3A above) are alternately layered one on top of the other. Thus, the plurality of light-shielding layers 210 formed on the front side of the wafer 200 are covered by the workpiece film 110. As described above, for example, the light-shielding layers 210 are designed such that they do not cover the entire front side of the wafer 200 and are arranged at predetermined intervals, so that peeling of the workpiece film 110 can be suppressed. Furthermore, a CVD carbon layer 120, a silicon oxynitride layer 130 and a resist structure 140p are formed on the workpiece film 110 in this order. As shown in Fig. 11A, the silicon oxynitride layer 130 and the CVD carbon layer 120 are etched successively to form a mask structure 120p of the CVD carbon layer 120 onto which the resist structure 140p has been transferred. As shown in Fig. 11B, etching on the workpiece film 110 is initiated using the plasma processing device 2. That is, a wafer 200 is placed in the chamber 11 of the plasma processing device 2 and positioned on the electrostatic chuck 220. Furthermore, a plasma P is generated in the chamber 11, while the back side of the wafer 200 is irradiated with light from the light source 231 via the sensor head 235 below the electrostatic chuck 220. As a result, etching on the workpiece film 110 is started in sections exposed by the openings of the mask structure 120p. As shown in Fig. 12A, the etched depth of the workpiece film 110 increases as the plasma processing progresses through the plasma processing device 2. As shown in Fig. 12B, after a predetermined time, the exposed sections of the workpiece film 110 are penetrated, and a plurality of through-holes 111 are formed. The light-shielding layers 210 or the front side of the wafer 200 are exposed by the undersides of the through-holes 111. In this process, the wafer 200 is exposed to a high-temperature plasma during the etching of the workpiece film 110. During plasma processing, the temperature of the wafer 200 is controlled by the electrostatic chuck 220 of the plasma processing device 2 such that the temperature of the wafer 200 is kept constant, but the temperature of the wafer 200 gradually increases due to the heat from the plasma. Part of the light illuminating the back side of wafer 200 is reflected by the back side of wafer 200 and detected by sensor head 235 as reflected light 238s. Another part of the light illuminating the back side of wafer 200 is transmitted through wafer 200, reflected by the back side of the light-shielding layer 210, and detected by sensor head 235 as reflected light 238b. The spectrometer 236 described above measures a spectrum of an interference wave obtained by interference between the reflected light 38s and the reflected light 38b. Based on the interference spectrum measured by the spectrometer 236, the controller 250 of the plasma processing device 1 performs various calculations to determine the temperature of the wafer 200 during plasma processing. This means that an optical path length of the wafer 200 is obtained from interference light 39sb between the reflected light 38s from the back of the wafer 200 and the reflected light 38b from the underside, also referred to as the bottom surface, of the light-shielding layer 210. As described above, the optical path length is expressed as the product of a refractive index of a target substance and the distance the light travels in the substance, i.e., the thickness of the substance. Furthermore, both the refractive index and the thickness of the substance change depending on the temperature of the substance at that time. If the temperature of wafer 200 changes during plasma processing, the optical path length of wafer 200 also changes. If the refractive index and thickness are known at each temperature, as is the case with wafer 200 used to fabricate a semiconductor device, the temperature of wafer 200 at that time can be determined from the optical path length of wafer 200. In temperature measurement using such interference light, the interval between the plurality of light-shielding layers 210 is preferably smaller than the wavelength of the light with which the back side of the wafer 200 is irradiated as described above. Consequently, in an area where the structure of the mask 120p is formed and the workpiece film 110 is etched, light is shielded by each of the plurality of light-shielding layers 210, instead of passing between the plurality of light-shielding layers 210, passing through the workpiece film 110, and being detected by the sensor head 235 as reflected light 238b. In an area where the structure of the mask structure 120p is formed and the workpiece film 110 is etched, if part of the light is transmitted through the workpiece film 110, the other part of the light can be reflected through an etched end of the workpiece film 110 and detected by the sensor head 235 as reflected light 238p. As shown in Figs. 11B to 12B, the depth reached by the etched end in the workpiece film 110 changes over time. Therefore, the reflected light 238p at the etched end and the interference light between the reflected light 238p and other reflected light from each section of the wafer 200, such as the reflected light 238s and the reflected light 238b, also change over time and can become interfering factors in the calculation of the temperature of the wafer 200. By arranging the multitude of light-shielding layers 210 in intervals smaller than the wavelength of light, such interfering factors can be eliminated in advance. Note that in the processing described above in Figs. 10A and 10B, when a plurality of light-shielding layers 210 are formed, in an area where the structure of the mask structure 120p is formed and the workpiece film 110 is etched, the light-shielding layers 210 with an area slightly larger than the size of the plurality of through holes 111 can be arranged at positions which vertically overlap the through holes 111 in the top view. As a result, the undersides of the through holes 111 extend completely to the light shielding layers 210, which makes it easier for the workpiece film 110 to have uniform etching marks and for the through holes 111 to have a uniform machined shape. In a case where the through-holes 111 of the workpiece film 110 are, for example, storage holes or the like for forming the pillars PL of the semiconductor device 10 according to the first example described above, these through-holes 111 are arranged closely together, for example in a staggered manner in the top view. Therefore, in a case where the plurality of light-shielding layers 210 are arranged to correspond to the positions at which these through-holes 111 are formed, the interval between the light-shielding layers 210 can be smaller than the wavelength of light. Furthermore, in a case where the through-holes 111 are storage holes or the like for forming pillars PL, the light-shielding layers 210 exposed from the undersides of the through-holes 111 can be removed by etching or ashing after the through-holes 111 have been formed. Now, preferred characteristics of the light-shielding layers 210 will be discussed. Fig. 13 is a schematic graphic representation showing a light-shielding layer 210 and components positioned on and below the light-shielding layer 210 according to the embodiment. As shown in Fig. 13, the refractive indices of the wafer 200, the light-shielding layer 210, and the workpiece film 110 are each denoted by n0, n1, and n2, respectively, and the extinction coefficients of the wafer 200, the light-shielding layer 210, and the workpiece film 110 are k0, k1, and k2. The transmittance values ​​for light falling from the light source 231 onto the wafer 200, the light-shielding layer 210, and the workpiece film 110, i.e., the transmittance values ​​of the light in air, in the wafer 200, and in the light-shielding layer 210, are denoted by T0, T1, and T2, respectively. Furthermore, the reflectance values ​​of the light at an interface between the wafer 200 and the light-shielding layer 210, and at an interface between the light-shielding layer 210 and the workpiece film 110, are denoted by R0 and R1, respectively. In this case, if the transmittance T0 of the light incident on the wafer 200 in the air is 1 (T0=1), the transmittance T1 in the wafer 200 can be expressed by the following formula (1). Furthermore, taking into account the attenuation of the light in the light-shielding layer 210, the transmittance T'1 of the light incident on the light-shielding layer 210 can be expressed by the following formula (2) using a layer thickness d and an absorption coefficient α of the light-shielding layer 210. In formula (2), e is the base of the natural logarithm. The reflectances R0 and R1 at the interface between the wafer 200 and the light shielding layer 210 and at the interface between the light shielding layer 210 and the workpiece film 110 are each expressed by the following formulas (3) and (4): From the above, if the absorption coefficient α of the light-shielding layer 210 is α = 4πk1 / λ using a wavelength λ of the light, the transmittance T2in of the light-shielding layer 210 for the light incident on the workpiece film 110 can be expressed by the following formula (5): λ WAVELENGTH d LAYER THICKNESS OF THE LIGHT-SHIELDING LAYER ni REFRACTIONAL INDEX OF THE LIGHT-SHIELDING LAYER OR OF THE LAYER LOCATED ON OR BELOW THE LIGHT-SHIELDING LAYER k1 EXTINCTION COEFFICIENT OF THE LIGHT-SHIELDING LAYER As described above, the transmittance T2 of the light in the light-shielding layer 210 depends on the values ​​of the physical properties of the light-shielding layer 210, such as the absorption coefficient α and the extinction coefficient k1, and the layer thickness. In the configuration according to the embodiment, the light-shielding layer 210 can be used which has such physical properties and a layer thickness that the transmittance T2 in the light-shielding layer 210 is less than 20%, preferably less than 10%. In this case, the light from the wafer 200 and the workpiece film 110 falls onto the light-shielding layer 210 and returns through the light-shielding layer 210, so that the intensity of the light returning to the sensor head 235 is attenuated to less than 4%. Therefore, it can be said that the light from the workpiece film 110 is sufficiently shielded by such a light-shielding layer 210. For example, in a case where the light-shielding layer 210 is a CVD carbon layer and the light-shielding layer 210, with a thickness of 400 nm, is irradiated with light of a wavelength of 1310 nm, the transmittance T2 of the light-shielding layer 210 is 7.0247%. Furthermore, in a case where light with a wavelength of 1310 nm is irradiated, the light-shielding layer 210 can have a dimension of 100 nm and a grid spacing of 150 nm in the top view. In a state where the light-shielding layer 210, selected as described above, shields the influence of light on the side of the workpiece film 110, the temperature of the wafer 200 can be calculated by a measurement using the interference light during plasma processing. As described above, the optical path length of the wafer 200 is expressed as the product of the refractive index of the silicon or similar material forming the wafer 200 and the thickness of the wafer 200, and both the refractive index and the thickness are expressed as a function of the temperature of the wafer 200. Figures 14A and 14B are schematic diagrams, each showing a state of wafer 200 during plasma processing according to the embodiment. Figure 14A shows wafer 200 at a low temperature, and Figure 14B shows wafer 200 at a high temperature. As shown in Figs. 14A and 14B, the temperature of wafer 200 gradually increases during plasma processing, and wafer 200 expands accordingly. As a result, the thickness of wafer 200 and the distance traveled within wafer 200 by light transmitted through and reflected from its front surface change between the low-temperature and high-temperature states. When measuring using interference light, such a difference is detected as a difference in the optical path length corresponding to the temperature of wafer 200. Since the material and the initial thickness of wafer 200 are known, it is possible to detect a temperature change of wafer 200 during plasma processing by measuring a change in the optical path length of wafer 200. This is achieved by adding a change in the refractive index corresponding to the temperature change to the coefficient of thermal expansion of wafer 200. To maintain a constant temperature of the wafer 200 exposed to the high-temperature plasma during the etching of the workpiece film 110, the coolant, controlled to a predetermined temperature by the cooler 82, is circulated in the coolant flow path 25 of the electrostatic chuck 220. Additionally, a gas with high thermal conductivity, such as helium gas, which is controlled to a predetermined temperature by heat exchange with the coolant, is supplied from the gas supply source CY via the MFC 83, the tank 85, and the openings 28g of the gas flow path 28 to the rear of the wafer 200 placed on the electrostatic chuck 220. This ensures that the temperature of the wafer 200 is controlled to the desired temperature. However, as described above, the temperature of wafer 200 gradually increases due to the heat of the plasma as plasma processing progresses. The controller 250 of the plasma processing device 2 increases the gas pressure supplied to the back side of wafer 200, for example, based on the temperature of wafer 200, which is measured as described above. Specifically, the controller 250, via the MFC 83, increases the flow rate of the gas flowing into tank 85 to increase the pressure in tank 85. As a result, the pressure of the gas supplied to the back of wafer 200 increases, thus lowering the temperature of wafer 200. By controlling the temperature of the wafer 200 by the electrostatic chuck 220 or the like based on the temperature measurement result, as described above, it is easy to suppress an increase in the temperature of the wafer 200 during plasma processing and to keep the temperature of the wafer 200 essentially constant. Then the etching on the workpiece film 110 by the plasma processing device 2 according to the embodiment ends. Then, by repeatedly forming different films, etching and other processing, a semiconductor device similar to the first example described above is produced. (Example of plasma processing) Next, with reference to Fig. 15, an example is described in which the wafer 200 is processed using the plasma processing device 2 according to the embodiment. Fig. 15 is a flowchart illustrating an example of procedures for plasma processing wafer 200 according to the embodiment. The flowchart in Fig. 15 depicts procedures from the input of a batch to the processing of the input batch of wafers 200 by the plasma processing unit 2. As shown in Fig. 15, wafers 200 for a batch which includes a predetermined number of wafers 200 are entered into the manufacturing process (step S201). A multitude of light-shielding layers 210, arranged periodically at predetermined intervals, are formed on the front side of each of the wafers 200 for a batch (step S202). Furthermore, a workpiece film 110 is formed on each of the wafers 200, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately layered individually on top of each other (step S203). Thus, the plurality of light-shielding layers 210 formed on the front side of the wafer 200 is covered by the workpiece film 110. Furthermore, a CVD carbon layer 120 is formed on the workpiece film 110 (step S204), a silicon oxynitride layer 130 is formed on the CVD carbon layer 120 (step S205), and furthermore, a resist structure 140p is formed on the silicon oxynitride layer 130 (step S206). For each wafer 100, etching is performed on the silicon oxynitride layer 130 using the resist structure 140p as a mask (step S207), and etching is performed on the CVD carbon layer 120 using the silicon oxynitride layer 130, onto which the resist structure 140p has been transferred, as a mask (step S208). As a result, a mask structure 120p is formed by transferring the structure onto the CVD carbon layer 120. For each wafer 100, etching is performed on the workpiece film 110 exposed by the mask structure 120p. During plasma processing, the controller 250 irradiates the back of the wafer 200 with light, monitors the temperature of the wafer 200 in the plasma (step S209) and determines whether the temperature of the wafer 200 is changed (step S210). If the temperature of wafer 200 has been changed (step S210: Yes), the controller 250, for example, changes the pressure at which a gas, such as helium gas, is supplied to the electrostatic chuck 220, so that wafer 200 is maintained at a desired temperature (step S211). If wafer 200 is maintained at the desired temperature (step S210: No), the control of step S211 is not performed, and the pressure at which the gas is supplied to the electrostatic chuck 220 remains unchanged. Furthermore, the controller 250 continues the etching (step S209) until a point is reached to stop etching the workpiece film 110 (step S212: No). When the point is reached to stop etching (step S212: Yes), the power supply to chamber 11 is stopped. Then the plasma processing on wafer 200 ends according to the embodiment. (Overview) When etching is performed on the workpiece film using plasma processing equipment, if the wafer temperature is altered by exposure to high-temperature plasma, the etching rate and the processed shape of the workpiece film will also change. Therefore, for example, the temperature of the electrostatic chuck is monitored during plasma processing, and the wafer temperature is controlled. However, there is a difference of 10 °C or more between the temperature of the electrostatic chuck and the actual temperature of the wafer, and it is difficult to control the temperature with sufficiently high accuracy. Therefore, for example, a method for simulating the temperature change of a wafer during plasma processing can be applied using a temperature-measuring wafer. When an actual wafer is processed, its temperature is controlled based on a previously obtained temperature measurement. However, due to its structure, the temperature-measuring wafer is 1.2 mm to 1.4 mm thicker than the actual wafer, and the measurement obtained from the wafer cannot be considered sufficiently precise. Furthermore, etching methods have been available at low temperatures below -10 °C for several years, and existing temperature-measuring wafers have the disadvantage that temperature measurements cannot be performed at temperatures below -10 °C. Therefore, in recent years, a technique for estimating a wafer's temperature by observing interference between reflected beams, such as laser beams emitted onto the wafer, has been investigated. This technique utilizes a phenomenon where the wafer's optical path length changes depending on its temperature. However, for a wafer with a thick, layered workpiece film, the observed optical path length is affected by changes in the film's thickness. Furthermore, when etching is performed on such a film to create a predetermined shape, the observed optical path length also varies depending on the shape being processed. As described above, even with a measurement method using interference light, accurately estimating a wafer's temperature can be challenging. In the method for manufacturing the semiconductor device according to the embodiment, a back side of the wafer 200 is irradiated with light while the workpiece film 110 is etched, interference light 239sb is observed, wherein the interference light 239sb is generated by interference between reflected light 238s, which is reflected by the back side of the wafer 200, and reflected light 238b, which is transmitted through the wafer 200 and reflected by lower surfaces of the plurality of light-shielding layers 210, and a temperature of the wafer 200 is calculated on the basis of the interference light 239sb during the etching process. By forming the multitude of light-shielding layers 210, which shield light with a predetermined wavelength, on the front of the wafer 200 at predetermined intervals, as described above, it is possible to shield the influence of light on the side of the workpiece film 110 and to measure the temperature of the wafer 200 precisely. Furthermore, temperature information regarding wafer 200 can be obtained with high accuracy by measuring the temperature using light interference. In addition, the measurement can be performed at low temperatures, for example, less than -10 °C, and consequently the temperature of wafer 200 can be measured without temperature limitations. In the method for manufacturing the semiconductor device according to the embodiment, a temperature change of the wafer 200 during plasma processing is monitored on the basis of the interference light 239sb between the light 238s reflected by the back of the wafer 200 and the light 238b reflected by the lower surfaces of the plurality of light shielding layers 210, and the temperature of the wafer 200 is adjusted so that the wafer 200 is kept at a predetermined temperature. As a result, the temperature of the wafer 200 can be kept essentially constant during plasma processing, a deviation in the etching rate of the workpiece film 110 can be suppressed, and a desired machined shape can be obtained. In the method for manufacturing the semiconductor device according to the embodiment, the plurality of light-shielding layers 210 are formed on the front side of the wafer 200 in intervals that are smaller than a wavelength of the light with which the wafer 200 is irradiated. As described above, the multitude of light-shielding layers 210 are formed at predetermined intervals, for example, instead of covering the entire surface of the wafer 200, in order to suppress the peeling of the workpiece film 110. In this case as well, light is prevented from passing between the multitude of light-shielding layers 210 by setting the intervals between the multitude of light-shielding layers 210 to be smaller than the wavelength of the light. Therefore, it is possible to suppress light incidence from the wafer 200 into the workpiece film 110 and light incidence from the workpiece film 110 into the wafer 200. In the method for manufacturing the semiconductor device according to the embodiment, the transmittance T2, represented by the formula (5) above, which is a transmittance of light in the plurality of light-shielding layers 210, is less than 20%, and preferably less than 10%. As a result, the influence of light on the side of the workpiece film 110 is sufficiently shielded, and the temperature of the wafer 200 can be measured precisely. In the embodiment described above, a control mechanism is implemented to maintain the temperature of wafer 200 at a constant level by varying the gas pressure of the helium gas or similar substance supplied to the electrostatic chuck 220, based on the temperature of wafer 200 obtained using interference light. However, the temperature of wafer 200 can also be controlled by another method. For example, the temperature of wafer 200 can be rapidly controlled by using a cooler capable of distributing the coolant and controlling the distributed coolant to a variety of setpoints, such as a dual cooler like the cooler 82 described above, and by appropriately switching the coolant circulating in the electrostatic chuck to coolant at different temperatures. In the embodiment described above, the CVD carbon layer is used as the light-shielding layer 210. However, as long as the transmittance T2 represented by the formula (5) above can be reduced to less than 20%, a different material can be used as the light-shielding layer. The following describes data on some materials that are potential candidates. Figures 16A and 16B are diagrams representing the optical characteristics of materials that are candidates for the light-shielding layer according to a modification of the embodiment. Figure 16A is a diagram showing the refractive index of each material, with the horizontal axis representing a wavelength of light. Figure 16B is a diagram showing the extinction coefficient of each material, with the horizontal axis representing a wavelength of light. As shown in Figures 16A and 16B, titanium, titanium nitride, and tungsten all exhibit higher refractive indices and extinction coefficients than carbon, a major component of the CVD carbon layer, with respect to light with a wavelength including one around (1300 ± 50) nm, which is a measurement wavelength. Regarding tungsten nitride, while no data are available at a wavelength of (1300 ± 50) nm, it is reasonable to assume that tungsten nitride has a refractive index and extinction coefficient higher than those of carbon at a measurement wavelength. Fig. 17 is a diagram showing the transmittance of a light-shielding layer according to a modification of the embodiment. In particular, Fig. 17 shows a transmittance T2 of the light-shielding layer of each candidate material obtained from the above formula (5) in a case where the light-shielding layer is formed on the front side of the wafer using the above candidate material. In this case, similar to the light-shielding layer 210 described above using the CVD carbon layer, as discussed above, each light-shielding layer with a thickness of 400 nm is irradiated with light having a wavelength of 1310 nm. As shown in Fig. 17, the transmittance T2 of the light-shielding layer using carbon, as described above, is 7.0247%. Furthermore, the transmittances T2 of the light-shielding layers using titanium, titanium nitride, tungsten, and tungsten nitride are 0.0009%, 1.89 × 10⁻⁶%, 7.18 × 10⁻⁵%, and 5.25 × 10⁻⁵%, respectively. However, the transmittance T2 of the light-shielding layer using tungsten nitride remains as the reference value. As described above, the light-shielding layers using titanium, titanium nitride, tungsten and tungsten nitride also meet the T2<20% transmittance requirement, and it can be assumed that sufficient light-shielding effect can be achieved from them. Examples of materials other than those mentioned above that meet the T2<20% transmittance requirement include metal-based materials that do not transmit infrared light, such as molybdenum, copper, tungsten silicide, aluminum, gold, and silver. For the light-shielding layer, which uses any of the materials described above, it is also desirable to remove the light-shielding layers exposed on the undersides of through holes 111 by etching after the through holes 111 have been formed. However, in a case where the light-shielding layers are conductive, the light-shielding layers do not need to be removed. [Additional notes] The following are supplementary remarks on preferred aspects of the present invention. (Note 1) According to a preferred aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: manufacturing a substrate, the substrate comprising: a workpiece film; and a mask structure formed on the workpiece film, the mask structure comprising a light-shielding layer that shields light; and etching the workpiece film exposed by the mask structure, the etching of the workpiece film comprising: prior irradiation of a back side of the substrate with light; observing first interference light generated by interference between first reflected light reflected through the back side of the substrate and second reflected light transmitted through the substrate and reflected through a bottom side of the workpiece film;Observing the second interference light, which is generated by interference between the first reflected light and the third reflected light, which is transmitted and reflected through the substrate and the workpiece film without passing through a top surface of the workpiece film; calculating a thickness of the workpiece film based on the first interference light and the second interference light; and performing the etching under an etching condition based on the thickness of the workpiece film calculated from the first interference light and the second interference light. (Note 2) In the method for producing a semiconductor device according to Note 1, wherein the mask structure includes at least one of carbon, titanium, tungsten or nitrides as a major component, and during the etching of the workpiece film the thickness of the workpiece film is calculated using the third reflected light, wherein the third reflected light is reflected light that passes through the substrate and the workpiece film and is reflected through a bottom side of the light-shielding layer. (Note 3) In the method for manufacturing a semiconductor device according to Note 1 or Note 2, wherein the workpiece film is a film in which a plurality of first insulating layers and a plurality of second insulating layers are alternately stacked individually on top of each other. (Note 4) In the method for manufacturing a semiconductor device according to Note 3, wherein the plurality of first insulating layers enclosed in the workpiece film is 50 or more layers. (Note 5) In the method for manufacturing a semiconductor device according to any one of Notes 1 to 4, the method further comprises: irradiating the back side of the substrate with light before the workpiece film is formed, and observing third interference light produced by interference between fourth reflected light reflected through the back side of the substrate and fifth reflected light transmitted through and reflected by the substrate without being transmitted through a front side of the substrate, wherein, during etching of the workpiece film, the thickness of the workpiece film is calculated on the basis of the third interference light in addition to the first interference light and the second interference light. (Note 6) According to another preferred aspect of the present invention, a film thickness measurement method is provided, the method comprising: preparing a substrate on which a workpiece film is formed; irradiating a back side of the substrate with light; observing first interference light produced by interference between first reflected light, which is reflected by the back side of the substrate, and second reflected light, which is transmitted through the substrate and reflected by a bottom side of the workpiece film; observing second interference light produced by interference between the first reflected light and the third reflected light, which is transmitted through and reflected by the substrate and the workpiece film without being transmitted through a top side of the workpiece film;and calculating the thickness of the workpiece film based on the first interference light and the second interference light. (Note 7) In the film thickness measurement method according to Note 6, the method further comprising: forming a structure in a light-shielding layer that shields the light irradiating the substrate, wherein the thickness of the workpiece film is calculated using the third reflected light, wherein the third reflected light is reflected light that passes through the substrate and the workpiece film and is reflected through a bottom surface of the light-shielding layer. (Note 8) In the film thickness measurement method according to Note 6 or Note 7, wherein the workpiece film is a film in which a plurality of first insulating layers and a plurality of second insulating layers are alternately layered on top of each other. (Note 9) In the film thickness measurement method according to Note 8, wherein the plurality of first insulating layers enclosed in the workpiece film is 50 or more layers. (Note 10) In the film thickness measurement method according to one of Notes 6 to 9, the method further comprising: irradiating the back of the substrate with the light before the workpiece film is formed, and observing third interference light produced by interference between fourth reflected light reflected through the back of the substrate and fifth reflected light transmitted through and reflected by the substrate without being transmitted through a front of the substrate, wherein the thickness of the workpiece film is calculated on the basis of the third interference light in addition to the first interference light and the second interference light. Different embodiments are defined in the following numbered clauses. Clause 1. Method for manufacturing a semiconductor device, the method comprising: manufacturing a substrate (200), the substrate (200) comprising: a plurality of light-shielding layers (210) arranged at predetermined intervals to shield light of a predetermined wavelength; a workpiece film (110) located on the plurality of light-shielding layers (210) comprising a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL) stacked alternately one on top of the other; and a mask structure (120p) located on the workpiece film (110) having a plurality of openings; and etching the workpiece film (110) exposed by the plurality of openings, wherein the etching of the workpiece film (110) comprises: irradiating a back side of the substrate (200) with light during the etching of the workpiece film (110);Observing interference light (239sb) generated by interference between first reflected light (238s) reflected by the back of the substrate (200) and second reflected light (238b) transmitted through the substrate (200) and reflected by the undersides of the plurality of light-shielding layers (238b); calculating a temperature of the substrate (200) during etching based on the interference light (239sb); and adjusting the temperature of the substrate (200) during etching based on the temperature of the substrate (200) calculated from the interference light (239sb). Clause 2. Method for manufacturing a semiconductor device according to Clause 1, wherein, during the etching of the workpiece film (110), a temperature change of the substrate (200) during the etching process is monitored on the basis of the interference light (239sb), and the temperature of the substrate (200) is adjusted so that the substrate (200) is kept at a predetermined temperature. Clause 3. Method for manufacturing a semiconductor device according to Clause 1 or 2, wherein the plurality of light-shielding layers (210) are formed on a front face of the substrate (200) in intervals, each of which is smaller than the wavelength of the light illuminating the substrate (200). Clause 4. Method for manufacturing a semiconductor device according to any one of Clauses 1 to 3, wherein a transmittance T of the light in the plurality of light-shielding layers (210) is represented by the following formula: λ WAVELENGTH d LAYER THICKNESS OF THE LIGHT-SHIELDING LAYER ni REFRACTIONAL INDEX OF THE LIGHT-SHIELDING LAYER OR OF THE LAYER LOCATED ON OR BELOW THE LIGHT-SHIELDING LAYER k1 EXTINCTION COEFFICIENT OF THE LIGHT-SHIELDING LAYER and the transmittance T is less than 20%. Clause 5. Method for manufacturing a semiconductor device according to any one of Clauses 1 to 4, wherein the plurality of light-shielding layers (210) includes at least one of carbon, titanium, tungsten and nitrides as a principal component. Clause 6. Temperature measurement method, comprising: fabricating a substrate (200) wherein a plurality of light-shielding layers (210) shielding light of a predetermined wavelength are formed on a front side of the substrate (200) at predetermined intervals, wherein a workpiece film (110) is formed by alternately single-layering a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL) on the plurality of light-shielding layers (210), and wherein a mask structure (120p) is formed on the workpiece film (110) having a plurality of openings; irradiating a back side of the substrate (200) with light while the workpiece film (110) exposed by the plurality of openings is etched;Observing interference light (239sb) produced by interference between first reflected light (238s) reflected by the back of the substrate (200) and second reflected light (238b) transmitted through the substrate (200) and reflected by the undersides of the plurality of light-shielding layers (210); and calculating a temperature of the substrate (200) during etching based on the interference light (239sb). Clause 7. Temperature measurement method according to Clause 6, wherein while the temperature of the substrate (200) is being measured, a temperature change of the substrate (200) during the etching process is monitored on the basis of the interference light (239sb), and the substrate (200) is kept at a predetermined temperature. Clause 8. Temperature measurement method according to Clause 6 or 7, wherein the plurality of light-shielding layers (210) on the front of the substrate (200) is formed in intervals, each of which is smaller than the wavelength of the light illuminating the substrate (200). Clause 9. Temperature measurement method according to one of Clauses 6 to 8, wherein a transmittance T of the light in the plurality of light-shielding layers (210) is represented by the following formula: λ WAVELENGTH d LAYER THICKNESS OF THE LIGHT-SHIELDING LAYER ni REFRACTIONAL INDEX OF THE LIGHT-SHIELDING LAYER OR OF THE LAYER LOCATED ON OR BELOW THE LIGHT-SHIELDING LAYER k1 EXTINCTION COEFFICIENT OF THE LIGHT-SHIELDING LAYER and the transmittance T is less than 20%. Clause 10. Temperature measurement method according to Clause 9, wherein the plurality of light-shielding layers (210) includes at least one of carbon, titanium, tungsten or nitrides as a principal component. Clause 11. Temperature measuring substrate, comprising: a substrate (200) having a front face on which a plurality of light-shielding layers (210) shielding light of a predetermined wavelength is arranged at predetermined intervals; and a workpiece film (110) arranged above the substrate (200) and formed by alternating single layering of a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL). Clause 12. Temperature measuring substrate according to Clause 11, further comprising: a mask structure (120p) arranged on the workpiece film (110) and having a plurality of openings. Clause 13. Temperature measuring substrate according to Clause 11 or 12, wherein the plurality of light-shielding layers (210) includes at least one of carbon, titanium, tungsten and nitrides as a major component.

Claims

A method for manufacturing a semiconductor device, the method comprising: manufacturing a substrate (200), the substrate (200) comprising: a plurality of light-shielding layers (210) arranged at predetermined intervals to shield light of a predetermined wavelength; a workpiece film (110) in which a plurality of different types of layers are stacked in multiple layers and which is located on or above the plurality of light-shielding layers (210); and a mask structure (120p) located on or above the workpiece film (110) and having a plurality of openings; and etching the workpiece film (110) exposed by the plurality of openings, wherein the etching of the workpiece film (110) comprises: irradiating a back side of the substrate (200) with light during the etching of the workpiece film (110);Observing interference light (239sb) generated by interference between first reflected light (238s) reflected by the back of the substrate (200) and second reflected light (238b) transmitted through the substrate (200) and reflected by the undersides of the plurality of light-shielding layers (238b); calculating a temperature of the substrate (200) during etching based on the interference light (239sb); and adjusting the temperature of the substrate (200) during etching based on the temperature of the substrate (200) calculated from the interference light (239sb). Method for manufacturing a semiconductor device according to claim 1, wherein the plurality of light-shielding layers (210) are arranged periodically. Method for manufacturing a semiconductor device according to claim 1, wherein one of the forms of the plurality of light-shielding layers (210), viewed from above, is a circular form, an oval form, an elliptical form, or a polygonal form. Method for manufacturing a semiconductor device according to claim 1, wherein upper surfaces of the plurality of light-shielding layers (210) are located on or below a lower surface of the workpiece film (110). Method for manufacturing a semiconductor device according to claim 1, wherein the workpiece film (110) comprises a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL), wherein the plurality of first insulating layers (NL) comprises silicon nitrate and the plurality of second insulating layers (OL) comprises silicon oxide. Method for manufacturing a semiconductor device according to claim 1, wherein during the etching of the workpiece film (110) a temperature change of the substrate (200) during the etching process is monitored on the basis of the interference light (239sb), and the temperature of the substrate (200) is adjusted so that the substrate (200) is kept at a predetermined temperature. Method for manufacturing a semiconductor device according to claim 1, wherein the plurality of light-shielding layers (210) are formed on a front side of the substrate (200) in intervals, each of which is smaller than the wavelength of the light illuminating the substrate (200). Method for manufacturing a semiconductor device according to one of the preceding claims, wherein a transmittance T of the light in the plurality of light-shielding layers (210) is represented by the following formula: T = { 1 − ( n 1 − n 0 n 1 + n 0 ) 2} { 1 − ( n 2 − n 1 n 2 + n 1 ) 2} e − 4 π kd λ λ WAVELENGTH d LAYER THICKNESS OF THE LIGHT SHADING LAYER n i Refractive index of the light-blocking layer or of the layer located on or under the light-blocking layer k 1 EXTINCTION COEFFICIENT OF THE LIGHT SHADING LAYER and the transmittance T is less than 20%. Method for manufacturing a semiconductor device according to one of the preceding claims, wherein the plurality of light-shielding layers (210) includes at least one of carbon, titanium, tungsten and nitrides as a major component. Temperature measurement method comprising: forming a substrate (200) with a plurality of light-shielding layers (210) arranged at predetermined intervals to shield light of a predetermined wavelength formed on a front side of the substrate (200); a workpiece film (110) in which a plurality of different types of layers are arranged in multiple layers and which is formed on or over the plurality of light-shielding layers (210); and a mask structure (120p) formed on or over the workpiece film (110) and having a plurality of openings; irradiating a back side of the substrate (200) with light while the workpiece film (110) exposed by the plurality of openings is etched;Observing interference light (239sb) produced by interference between first reflected light (238s) reflected by the back of the substrate (200) and second reflected light (238b) transmitted through the substrate (200) and reflected by the undersides of the plurality of light-shielding layers (210); and calculating a temperature of the substrate (200) during etching based on the interference light (239sb). Temperature measurement method according to claim 10, wherein while the temperature of the substrate (200) is being measured, a temperature change of the substrate (200) during the etching process is monitored based on the interference light (239sb), and the substrate (200) is kept at a predetermined temperature. Temperature measurement method according to claim 10 or 11, wherein the plurality of light-shielding layers (210) on the front of the substrate (200) is formed in intervals, each of which is smaller than the wavelength of the light irradiating the substrate (200). Temperature measurement method according to one of claims 10 to 12, wherein a transmittance T of the light in the plurality of light-shielding layers (210) is represented by the following formula: T = { 1 − ( n 1 − n 0 n 1 + n 0 ) 2} { 1 − ( n 2 − n 1 n 2 + n 1 ) 2} e − 4 π kd λ λ WAVELENGTH d LAYER THICKNESS OF THE LIGHT SHADING LAYER n i Refractive index of the light-blocking layer or of the layer located on or under the light-blocking layer k 1 EXTINCTION COEFFICIENT OF THE LIGHT SHIELDING LAYER and the transmittance T is less than 20%. Temperature measurement method according to claim 13, wherein the plurality of light-shielding layers (210) includes at least one of carbon, titanium, tungsten or nitrides as a major component. Temperature measurement method according to claim 10, wherein top surfaces of the plurality of light-shielding layers (210) are located on or below a bottom surface of the workpiece film (110).

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