EXTINGUISHING TECHNIQUES THAT USE ANALOGUE BITA SAMPLING IN A STORAGE DEVICE

Abstract

The storage device includes a plurality of memory cells arranged in a plurality of word lines. The plurality of word lines includes a selected group of word lines to be erased in an erasure operation. The storage device also includes switching logic configured to erase the memory cells of the selected group of word lines in at least one erase loop. The at least one erase loop includes an erase pulse, an erase verification operation, and an analog bit sampling operation. The switching logic is configured to determine an output of the analog bit sampling operation, where the output is one of at least three options. The switching logic is also configured to control at least one erase parameter based on the output of the analog bit sampling operation.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 524,015, filed June 29, 2023. The entire disclosure of the above-referenced application is incorporated herein by reference. BACKGROUND1. Area

[0002] The present disclosure relates generally to the operation of non-volatile memory, and more particularly to erasure techniques to improve performance, reliability, and / or endurance. 2. State of the art

[0003] Semiconductor memory is widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memory can comprise non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source, such as a battery.

[0004] NAND memory devices include a chip with a plurality of memory blocks, each of which includes an array of memory cells arranged in a plurality of wordlines. Programming the memory cells of a wordline to store data is typically performed in a plurality of program loops, each of which includes the application of a program pulse to a control gate of the wordline and, optionally, a test operation to detect the threshold voltages of the memory cells being programmed. Each program loop may also include a precharge operation prior to the program pulse to precharge a plurality of channels containing memory cells to be programmed. SUMMARY

[0005] One aspect of the present disclosure relates to a method for performing an erase operation in a memory device. The method includes the step of preparing a memory block including a plurality of memory cells arranged in a plurality of wordlines. The plurality of wordlines includes a selected group of wordlines to be erased. The method proceeds with the step of erasing the memory cells of the selected group of wordlines in at least one erase loop. The at least one erase loop includes an erase pulse, an erase verify operation, and an analog bit strobe operation. The memory performs the step of determining an output of the analog bit strobe operation, wherein the output is one of at least three options.The method continues with the step of setting at least one erase parameter based on the output of the analog bit sampling operation.

[0006] According to another aspect of the present disclosure, in response to the output of the analog bit scan operation being a first output option, the method continues with the step of increasing a voltage of the erase pulse by a first step size. In response to the output of the analog bit scan operation being a second output option, the method continues with the step of increasing the voltage of the erase pulse by a second step size that is different from the first step size.

[0007] According to yet another aspect of the present disclosure, in response to the output of the analog bit scan operation being a third output option, the method continues with the step of terminating the erase operation.

[0008] According to yet another aspect of the present disclosure, the first output option is a significant fail; the second output option is a minor fail or a minor pass; and the third output option is a significant pass.

[0009] According to another aspect of the present disclosure, the second step size is approximately half of the first step size.

[0010] According to yet another aspect of the present disclosure, in response to the output of the analog bit scan operation being a first output option, the method continues with the step of increasing a voltage of the erase pulse by a first step size. In response to the output of the analog bit scan operation being a second output option, the method continues with the step of increasing the voltage of the erase pulse by a second step size different from the first step size and applying an additional erase pulse to the selected group of word lines.

[0011] According to yet another aspect of the present disclosure, in response to the output of the analog bit scan operation being a third output option, the method continues with the step of terminating the erase operation.

[0012] According to another aspect of the present disclosure, the first output option is a major failure, the second output option is a minor failure, and the third output option is a pass.

[0013] Another aspect of the present disclosure relates to a memory device including a plurality of memory cells arranged in a plurality of wordlines. The plurality of wordlines includes a selected group of wordlines to be erased in an erase operation. The memory device also includes circuitry configured to erase the memory cells of the selected group of wordlines in at least one erase loop. The at least one erase loop includes an erase pulse, an erase verify operation, and an analog bit strobe operation. The circuitry is configured to determine an output of the analog bit strobe operation, wherein the output is one of at least three options. The circuitry is also configured to control at least one erase parameter based on the output of the analog bit strobe operation.

[0014] According to another aspect of the present disclosure, in response to the output of the analog bit scan operation being a first output option, the circuit logic is further configured to increase a voltage of the erase pulse by a first step size. In response to the output of the analog bit scan operation being a second output option, the circuit logic is further configured to increase the voltage of the erase pulse by a second step size that is different from the first step size.

[0015] According to yet another aspect of the present disclosure, in response to the output of the analog bit scan operation being a third output option, the circuit logic is configured to terminate the erase operation.

[0016] According to yet another aspect of the present disclosure, the first output option is a significant fail; the second output option is a minor fail or a minor pass; and the third output option is a significant pass.

[0017] According to another aspect of the present disclosure, the second step size is approximately half of the first step size.

[0018] According to yet another aspect of the present disclosure, in response to the output of the analog bit scan operation being a first output option, the circuit logic is further configured to increase a voltage of the erase pulse by a first step size. In response to the output of the analog bit scan operation being a second output option, the circuit logic is further configured to increase the voltage of the erase pulse by a second step size, different from the first step size, and apply an additional erase pulse to the selected group of word lines.

[0019] According to yet another aspect of the present disclosure, in response to the output of the analog bit scan operation being a third output option, the circuit logic is further configured to terminate the erase operation.

[0020] According to another aspect of the present disclosure, the first output option is a major failure, the second output option is a minor failure, and the third output option is a pass.

[0021] Yet another aspect of the present disclosure relates to a device including a memory block having a plurality of memory cells arranged in a plurality of word lines. The plurality of word lines includes a selected group of word lines to be erased in an erase operation. The device also includes erasing means for erasing the memory cells of the selected group of word lines in at least one erase loop. The at least one erase loop includes an erase pulse, an erase verify operation, and an analog bit scan operation. The erasing means is configured to determine an output of the analog bit scan operation, the output being one of at least three options comprising a major fail, a minor fail, and a pass.The erasing means is further configured to increase a voltage of the erase pulse by a first step size in response to the output of the analog bit sampling operation being a significant failure, and to increase the voltage of the erase pulse by a second step size in response to the output of the analog bit sampling operation being a minor failure, wherein the second step size is different from the first step size.

[0022] According to another aspect of the present disclosure, the at least three options for outputting the analog bit sampling operation further comprise a slight pass and a significant pass.

[0023] According to yet another aspect of the present disclosure, the erasing means is further configured to increase the voltage of the erase pulse by the second step size in response to the output of the analog bit scan operation being a slight pass, and to terminate the erasing operation in response to the output of the analog bit scan operation being a clear pass.

[0024] According to yet another aspect of the present disclosure, the erasing means is further configured to apply an additional erase pulse to the selected group of word lines in response to the output of the analog bit scan operation being a minor failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] A more detailed description is set forth below with reference to exemplary embodiments illustrated in the accompanying figures. It is understood that these figures represent only exemplary embodiments of the disclosure and are therefore not to be considered limiting its scope. The disclosure is described and explained with additional specificity and detail through the use of the accompanying drawings, in which: Fig. 1A is a block diagram of an exemplary memory device; Fig. 1B is a block diagram of an exemplary control circuit; Fig. 1C is a block diagram of exemplary programming circuitry of the memory device of Fig. 1A; Fig. 2 Blocks of memory cells in an exemplary two-dimensional configuration of the memory array of Fig. 1A; Fig. 3A and Fig. 3B illustrates cross-sectional views of exemplary floating gate with NAND chains; Fig. 4A and Fig. 4B illustrates cross-sectional views of exemplary charge-trapping memory cells in NAND strings; Fig. 5 an exemplary block diagram of a detection block SB1 of Fig. 1 represents; Fig. 6A is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of Fig. 1; Fig. 6B is an exemplary cross-sectional view of a portion of one of the blocks of Fig. 6A; Fig. 6C is a graphical representation of the storage hole diameter in the stack of Fig. 6B; Fig. 6D a detailed view of region 622 of the stack of Fig. 6B; Fig. 7A is a top view of an exemplary word line layer WL0 of the stack of Fig. 6B; Fig. 7B is a top view of an exemplary upper dielectric layer DL116 of the stack of Fig. 6B; Fig. 8 illustrates a threshold voltage distribution of a page of memory cells programmed to one bit per memory cell (SLC); Fig. 9 illustrates a threshold voltage distribution of a page of memory cells programmed to three bits per memory cell (TLC); Fig. 10 illustrates an exemplary voltage waveform applied to a selected word line during programming of the memory cells of the selected word line; Fig. 11 is a table containing the analog bit sample output options and the corresponding occupancy time calculation resulting in the various options according to one embodiment of the present disclosure; Fig. 12 is a diagram of an occupancy voltage, an oscillator, and a corresponding clock counter according to an exemplary embodiment; Fig. 13 is a table containing the analog bit sample output options and the corresponding parameters that result in the various options according to one embodiment of the present disclosure; Fig. 14 is a table containing the analog bit sample output options and the corresponding parameters that result in the various options according to another embodiment of the present disclosure; Fig. 15 is a table containing the analog bit sample output options and the corresponding parameters that result in the different options according to yet another embodiment of the present disclosure; Fig. 16 is a table containing the analog bit sample output options and the corresponding parameters that result in the various options according to yet another embodiment of the present disclosure; Fig. 17 is a flowchart including the steps of performing an exemplary embodiment of an analog bit sampling operation; Fig. 18 is a flowchart including the steps of performing another exemplary embodiment of an analog bit sampling operation; Fig. 19 is a flowchart including the steps of performing yet another exemplary embodiment of an analog bit sampling operation; Fig. 20 is a graph of the high end of erase versus program and erase cycles during the operational lifetime of a memory block for one example; Fig. Figure 21 is a graph of erase loops versus program and erase cycles during the lifetime of a memory block for the same example of Fig. 20; Fig. 22 is a flowchart including the steps of performing an erase operation that includes an analog bit sampling operation; Fig. 23A is a threshold voltage distribution diagram illustrating a condition that would produce an output of a significant failure of an analog bit sampling operation; Fig. 23B is a threshold voltage distribution diagram illustrating a condition that would produce an output of a slight failure of an analog bit sampling operation; Fig. 23C is a threshold voltage distribution diagram illustrating a condition that would produce an output of a pass of an analog bit scan operation; Fig. 24 is a flowchart including the steps of performing an erase operation that includes an analog bit sampling operation; Fig. Figure 25 is a graph of the high end of erase versus program and erase cycles during the operational lifetime of a memory block for use with analog bit sampling techniques; Fig. 26 is a diagram of the threshold voltage distributions of a plurality of memory cells after a plurality of programming pulses according to an example; Fig. 27 is a table illustrating which data states are verified in which program loops according to the example that shows the result of Fig. 26 generated; Fig. 28 is a flowchart including the steps of performing a programming operation including an analog bit sampling operation according to an exemplary embodiment of the present disclosure; Fig. Figure 29 is a diagram illustrating the programming pulses and verification pulses during and immediately after an exemplary intelligent verification operation; Fig. 30 is a flowchart including the steps of performing an intelligent verification operation including an analog bit sampling operation according to an exemplary embodiment of the present disclosure; Fig. 31A is a threshold voltage distribution of a plurality of memory cells that would produce a slight pass output in an exemplary analog bit sampling operation; Fig. 31B is a threshold voltage distribution of a plurality of memory cells that would produce a clear pass output in an exemplary analog bit sampling operation; Fig. 31C is a threshold voltage distribution of a plurality of memory cells that would produce a slight miss output in an exemplary analog bit scan operation; Fig. 31D is a threshold voltage distribution of a plurality of memory cells that would produce a significant fail output in an exemplary analog bit scan operation; Fig. 32 is a flowchart including the steps of performing an intelligent verification operation including an analog bit sampling operation according to another exemplary embodiment of the present disclosure; Fig. 33 is a flowchart including the steps of performing an intelligent verification operation including an analog bit sampling operation according to yet another exemplary embodiment of the present disclosure; Fig. 34 is a flowchart including the steps of performing an intelligent verification operation including an analog bit sampling operation according to yet another exemplary embodiment of the present disclosure; Fig. 35A is a threshold voltage distribution diagram of a plurality of memory cells in a state that would produce a slight fail for an analog bit sensing operation with a low verify level Vvsl and a clear pass for an analog bit sensing operation with a high verify level Vvsh; Fig. 35B is a threshold voltage distribution diagram of a plurality of memory cells in a state that would produce a clear fail for an analog bit sensing operation with a low verify level Vvsl and a clear pass for an analog bit sensing operation with a high verify level Vvsh; Fig. 35C is a threshold voltage distribution diagram of a plurality of memory cells in a state that would produce a marginal pass for an analog bit sensing operation with a high verify level Vvsh; Fig. 35D is a threshold voltage distribution diagram of a plurality of memory cells in a state that would produce a slight fail for an analog bit sensing operation with a high verify level Vvsh; Fig. 35E is a threshold voltage distribution diagram of a plurality of memory cells in a state that would produce a significant fail for an analog bit sensing operation with a high verify level Vvsh; Fig. 36 is a table identifying which data states are verified in which program loops according to an example programming procedure; Fig. 37 is a table containing actions to be taken in response to various analog bit sample outputs according to an exemplary embodiment of the present disclosure; Fig. 38 is a table identifying which data states are verified in which program loops according to an exemplary embodiment of a programming process; Fig. 39 is a threshold voltage distribution diagram with a plurality of curves identifying significant fail, minor fail, and pass conditions for an exemplary analog bit sampling operation; Fig. 40 is a table identifying which data states are verified in which program loops according to an exemplary embodiment of a programming process; Fig. 41 is a table identifying which data states are verified in which program loops according to another exemplary embodiment of a programming process; Fig. 42 is a diagram of various voltages applied to various components in a memory block before and during a program pulse according to an exemplary embodiment of the present disclosure; Fig. 43 is a table identifying which data states are verified in which program loops according to another exemplary embodiment of a programming process; Fig. 44 is a flowchart including the steps of performing an SLC programming operation that includes an analog bit sampling operation according to an exemplary embodiment of the present disclosure; Fig. 45 is a flowchart including the steps of performing an intelligent verification operation including an analog bit sampling operation according to another exemplary embodiment of the present disclosure; Fig. 46 is a flowchart including the steps of performing a STPFINE operation including an analog bit sampling operation according to an exemplary embodiment of the present disclosure; Fig. 47 is a flowchart including the steps of performing a STPFINE operation including an analog bit sampling operation according to another exemplary embodiment of the present disclosure; Fig. 48 is a flowchart including the steps of performing an intelligent verification operation including an analog bit sampling operation according to another exemplary embodiment of the present disclosure; and Fig. 49 is a flowchart including the steps of performing an intelligent verification operation including an analog bit sampling operation according to yet another exemplary embodiment of the present disclosure. DESCRIPTION OF THE SUPPORTING EMBODIMENTS

[0026] Programming and erasing typically both occur in a plurality of loops, each of which includes a program or erase pulse and a verify operation. In the verify operation, the threshold voltages Vt of the memory cells being programmed or erased are checked to determine whether they have completed the programming or erasing. After the verify operation, a bit scan operation may be performed to count how many memory cells have completed or failed the program or erase operation. The present disclosure generally refers to a so-called "analog bit scan" operation, where the bit scan operation may produce more than two possible outputs, i.e., more than just "pass" and "fail."By creating additional output options (e.g., strong pass, minor pass, minor fail, and strong fail), certain parameters of the program or erase operation can be optimized to improve the performance, reliability, and / or durability of the memory device. These analog bit sampling techniques and corresponding program and erase operations using analog bit sampling are discussed in more detail below.

[0027] Fig. 1A is a block diagram of an exemplary memory device 100 configured to operate according to the analog bit sensing techniques of the present disclosure. The memory chip 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and read / write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuits 128 include multiple sense blocks SB1, SB2, ... SBp (sense circuitry) and enable parallel reading or programming of a page of memory cells. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108.Commands and data are transferred between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 118.

[0028] The memory structure 126 may be two-dimensional or three-dimensional. The memory structure 126 may include one or more arrays of memory cells, including a three-dimensional array. The memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory levels are formed above (rather than within) a single substrate, such as a wafer, with no intervening substrates. The memory structure 126 may include any type of non-volatile memory monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The memory structure 126 may be located in a non-volatile memory device that includes circuitry associated with the operation of the memory cells, whether the associated circuitry is located above or within the substrate.

[0029] The control logic 110 cooperates with the read / write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations.

[0030] For example, a storage region 113 may be provided for programming parameters. The programming parameters may include a program voltage, a bias voltage for the program voltage, position parameters specifying the positions of the memory cells, parameters for the thickness of the contact line connectors, a verification voltage, and / or the like. The position parameters may specify a position of a memory cell within the entire array of NAND strings, a position of a memory cell within a particular NAND string group, a position of a memory cell in a particular level, and / or the like. The parameters for the thickness of the contact line connector may specify the thickness of the contact line connector, the substrate or the material from which the contact line connector is made, and / or the like.

[0031] The on-chip address decoder 114 provides an address interface between that used by the host or a memory controller and the hardware address used by decoders 124 and 132. The power control module 116 controls the power and voltages supplied to the wordlines and bitlines during memory operations. It may include drivers for wordlines, SGS and SGD transistors, and source lines. The sense blocks may include bitline drivers in one approach. An SGS transistor is a select gate transistor at a source end of a NAND string, and an SGD transistor is a select gate transistor at a drain end of a NAND string.

[0032] In some embodiments, some of the components may be combined. In various implementations, one or more of the components (alone or in combination) other than memory structure 126 may be considered to be at least one control circuit configured to perform the operations described herein. A control circuit may include, for example, any one or a combination of control circuitry 110, state machine 112, decoders 114 / 132, power control module 116, sense blocks SBb, SB2 ... SBp, read / write circuits 128, controller 122, and the like.

[0033] The control circuits 150 may include a programming circuit 151 configured to perform a program and test operation for a set of memory cells, wherein the one set of memory cells comprises memory cells assigned to represent one data state from a plurality of data states and memory cells assigned to represent a different data state from the plurality of data states; wherein the program and test operation comprises a plurality of program and test iterations; and wherein, in each program and test iteration, the programming circuit performs programming for the one selected word line, after which the programming circuit applies a test signal to the one word line.The control circuits 150 may also include a counting circuit 152 configured to obtain a number of memory cells that have passed a verification test for the one data state. The control circuits 150 may also include a determination circuit 153 configured to determine whether a programming operation is complete based on the amount by which the count exceeds a threshold.

[0034] Fig. For example, Figure 1B is a block diagram of an exemplary control circuit 150 including programming circuit 151, counting circuit 152, and determining circuit 153.

[0035] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct a number of read errors caused when the upper tail of a Vth distribution becomes too high. However, in some cases, uncorrectable errors may be present. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0036] The storage device(s) 122a, 122b include code, such as a set of instructions, and the processor 122c is operable to execute the set of instructions and provide the functionality described herein. Alternatively or additionally, the processor 122c may access code from a storage device 126a of the memory structure 126, such as a reserved area of ​​memory cells in one or more wordlines. Code may be used, for example, by the controller 122 to access the memory structure 126, such as for program, read, and erase operations. The code may include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the controller 122 during a boot or startup operation and enables the controller 122 to access the memory structure 126.The code can be used by controller 122 to control one or more memory structures 126. During bootup, processor 122c retrieves the boot code from ROM 122a or storage device 126a for execution, and the boot code initializes the system components and loads the control code into RAM 122b. Once the control code is loaded into RAM 122b, it is executed by processor 122c. The control code includes drivers for performing basic tasks, such as controlling and allocating memory, prioritizing command processing, and controlling input and output ports.

[0037] In general, the control code may include instructions to perform the functions described herein, including the flowchart steps explained below, and to provide the voltage waveforms, including those explained below. For example, as shown in Fig. 1C illustrates that control circuitry 110, controller 122, and / or control circuitry 150 are configured to program and / or erase the memory cells of a selected word line WLn according to the unique techniques discussed herein, including an analog bit sensing operation. At step 160, the circuitry begins the program or erase operation. At step 161, the circuitry performs an analog bit sensing operation that produces one of more than two possible outputs. At step 162, the circuitry adjusts at least one parameter of the program or erase operation based on the output of the analog bit sensing operation. At step 163, the circuitry continues the program or erase operation using the at least one adjusted parameter.

[0038] In one embodiment, the host is a computing device (e.g., a laptop, a desktop, a smartphone, a tablet, a digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices in communication with the one or more processors.

[0039] Other types of non-volatile memory in addition to NAND flash memory can also be used.

[0040] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices; non-volatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"); and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in a NAND or NOR configuration.

[0041] The memory devices may be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching storage element such as an anti-fuse or phase-change material, and optionally a steering element such as a diode or transistor. Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and Flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0042] Multiple storage elements can be configured to be connected in series, or such that each element is individually accessible. As a non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically include storage elements connected in series. A NAND chain is an example of a set of series-connected transistors comprising memory cells and SG transistors.

[0043] A NAND memory array can be configured such that the array consists of multiple memory chains, where each chain consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured otherwise. The semiconductor memory elements, arranged in and / or above a substrate, can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0044] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., a plane in the xy direction) that extends substantially parallel to a major surface of a substrate supporting the memory elements. The substrate may be a wafer over or in which the layer of memory elements is formed, or it may be a carrier substrate that is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0045] The memory elements may be arranged in an ordered array at the individual memory device level, such as in a plurality of rows and / or columns. However, the memory elements may be arranged in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

[0046] A three-dimensional memory array is arranged so that memory elements occupy multiple levels or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, with the z direction being substantially perpendicular and the x and y directions being substantially parallel to the main surface of the substrate).

[0047] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As a further non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), each column having multiple memory elements. The columns may be arranged in a two-dimensional configuration, e.g., in an xy-plane, resulting in a three-dimensional array of memory elements with elements on multiple vertically stacked memory levels. Other configurations of memory elements in three dimensions may also form a three-dimensional memory array.

[0048] As a non-limiting example, in a three-dimensional array of NAND chains, the storage elements may be interconnected to form a NAND chain within a single horizontal (e.g., xy) memory device plane. Alternatively, the storage elements may be coupled together to form a vertical NAND chain spanning multiple horizontal memory device planes. Other three-dimensional configurations may be contemplated, with some NAND chains including storage elements in a single memory plane, while other chains including storage elements spanning multiple memory planes. Three-dimensional memory arrays may also be configured in a NOR configuration and a ReRAM configuration.

[0049] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also include one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers forming the individual memory device levels of the array are typically formed on top of the layers of the underlying memory device levels of the array. However, layers may be shared by adjacent memory device levels of a monolithic three-dimensional memory array or may include intermediate layers between memory device levels.

[0050] Again, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, non-monolithic stacked memories can be constructed by forming memory planes on separate substrates and then stacking the memory planes on top of each other. The substrates can be thinned or removed from the memory device planes before stacking, but because the memory device planes are initially formed over separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0051] Fig. 2 illustrates memory blocks 200, 210 of memory cells in an exemplary two-dimensional configuration of the memory array 126 of Fig. 1. The memory array 126 may include many such memory blocks 200, 210. Each example block 200, 210 includes a number of NAND strings and corresponding bit lines, e.g., BL0, BL1, .., shared by the blocks. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gates of the drain-side select gates are connected via a common SGD line. The NAND strings are connected at their other end to a source-side select gate (SGS), which in turn is connected to a common source line 220. One hundred and twelve word lines, e.g., WL0-WL111, extend between the SGSs and the SGDs. In some embodiments, the memory block may include more or fewer than one hundred and twelve word lines. In some embodiments, a memory block includes one hundred sixty-four word lines.In some cases, dummy word lines that do not contain user data can also be used in the memory array next to the select gate transistors or between certain data word lines. Such dummy word lines can shield the edge data word line from certain edge effects.

[0052] One type of non-volatile memory that can be provided in the memory array is a floating-gate memory such as the type used in Fig. 3A and Fig. 3B. However, other types of non-volatile memory may also be used. As discussed in more detail below, in another example shown in Fig. 4A and Fig. As shown in Figure 4B, a charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to non-volatilely store charge. A three-layer dielectric of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and a surface of a semiconducting substrate over the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a confined area. This stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride.A similar cell can be provided in a split-gate configuration, in which a doped polysilicon gate extends over a portion of the memory cell channel, thereby forming a separate selection transistor.

[0053] Another approach uses NROM cells. Two bits, for example, are stored in each NROM cell, where an ONO dielectric layer extends across the channel between the source and drain diffusion. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is achieved by separately reading binary states of the physically separate charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0054] Fig. Figure 3A illustrates a cross-section of exemplary floating-gate memory cells 300, 310, 320 in NAND strings. In this figure, the direction of a bit line or NAND string is inward into the page, and the direction of a word line is from left to right. As an example, word line 324 extends across NAND strings that enclose the respective channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and the channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and the channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and the channel region 326. Each memory cell 300, 310, 320 is located in a different respective NAND chain. An interpolar dielectric (IPD) layer 328 is also illustrated.The control gates 302, 312, 322 are sections of the word line. A cross-sectional view along the contact line connector 329 is shown in FIG. Fig. 3B provided.

[0055] The control gate 302, 312, 322 surrounds the floating gate 304, 314, 321, thereby increasing the surface contact area between the control gate 302, 312, 322 and the floating gate 304, 314, 321. This results in a higher IPD capacitance, which leads to a higher coupling ratio, facilitating programming and erasing. However, as NAND memory devices become smaller, the distance between adjacent cells 300, 310, 320 becomes smaller, so that there is almost no space left for the control gates 302, 312, 322 and the IPD layer 328 between two adjacent floating gates 302, 312, 322.

[0056] As an alternative, as in Fig. 4A and Fig. 4B, the flat or planar memory cell 400, 410, 420 is developed in which the control gate 402, 412, 422 is flat or planar; that is, it does not enclose the floating gate and only has contact with the charge storage layer 428 from above. In this case, a tall floating gate is not advantageous. Instead, the floating gate is made significantly thinner. Furthermore, the floating gate can be used for charge storage, or a thin charge trap layer can be used to capture charge. This approach can avoid the problem of ballistic electron transport, in which an electron can migrate through the floating gate during programming after tunneling through the tunnel oxide.

[0057] Fig. 4A illustrates a cross-sectional view of exemplary charge trapping memory cells 400, 410, 420 in NAND chains. The view is in a word line direction of the memory cells 400, 410, 420 having a flat control gate and charge trapping regions as a two-dimensional example of the memory cells 400, 410, 420 in the memory cell array 126 of Fig. 1. The charge-trapping memory can be used in a NOR and NAND flash memory device. This technology uses an insulator such as a SiN film to store electrons, unlike floating-gate MOSFET technology, which uses a conductor such as doped polycrystalline silicon to store electrons. For example, a wordline 424 extends across NAND strings that include respective channel regions 406, 416, 426. Portions of the wordline provide control gates 402, 412, 422. Below the word line are an IPD layer 428, charge trapping layers 404, 414, 421, polysilicon layers 405, 415, 425, and tunneling layers 409, 407, 408. Each charge trapping layer 404, 414, 421 extends continuously in a respective NAND chain. The flat configuration of the control gate can be made thinner than a floating gate.In addition, the memory cells can be placed closer together.

[0058] Fig. Figure 4B illustrates a cross-section of the structure of Fig. 4A along the contact line connector 429. The NAND chain 430 includes an SGS transistor 431, exemplary memory cells 400, 433, ... 435, and an SGD transistor 436. Vias in the IPD layer 428 in the SGS and SGD transistors 431, 436 enable communication between the control gate layers 402 and the floating gate layers. The control gate 402 layers and floating gate layers may be made of polysilicon, and the tunnel oxide layer may be made of silicon oxide, for example. The IPD layer 428 may be a stack of nitrides (N) and oxides (O), such as in a NONON configuration.

[0059] The NAND string can be formed on a substrate having a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage, Vch, can be applied directly to the channel region of the substrate.

[0060] Fig. Figure 5 illustrates an exemplary block diagram of the detection block SB1 of Fig. 1. In one approach, a sense block includes multiple sense circuits. Data latches are associated with each sense circuit. For example, sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different subgroups of bit lines may be sensed using different respective sense blocks. This allows the processor load associated with the sense circuits to be divided and handled by a respective processor in each sense block. For example, sense circuit controller 560 in SB1 may communicate with the set of sense circuits and latches. Sensing circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sense circuit for setting a precharge voltage.In one possible approach, the voltage is provided to each detection circuit independently, e.g., via the data bus and a local bus. In another possible approach, a common voltage is provided to each detection circuit simultaneously. The detection circuit controller 560 may also include a precharge circuit 561, a memory 562, and a processor 563. The memory 562 may store code executable by the processor to perform the functions described herein. These functions may include reading the latches 550b, 551b, 552b, 553b associated with the detection circuits 550a, 551a, 552a, 553a, setting bit values ​​in the latches, and providing voltages to set precharge levels in the detection nodes of the detection circuits 550a, 551a, 552a, 553a.Further example details regarding the control of the detection circuit 560 and the detection circuits 550a, 551a, 552a, 553a are provided below.

[0061] In some embodiments, a memory cell may include a flag register that includes a set of latches for storing flag bits. In some embodiments, a set of flag registers may correspond to a set of data states. In some embodiments, one or more flag registers may be used to control some type of verification technique in verifying memory cells. In some embodiments, asserting a flag bit may modify the associated logic of the device, e.g., address decoding circuitry, to select a particular block of cells. A bulk operation (e.g., an erase operation, etc.) may be performed using the flags set in the flag register or a combination of the flag register with the address register, as in implicit addressing, or alternatively, by direct addressing with the address register alone.

[0062] Fig. 6A is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of Fig. 1. On the substrate are exemplary blocks BLK0, BLK1, BLK2, BLK3 of memory cells (memory elements) and a peripheral region 604 with circuit logic for use by the blocks BLK0, BLK1, BLK2, BLK3. For example, the circuits may include voltage drivers 605, which may be connected to control gate layers of the blocks BLK0, BLK1, BLK2, BLK3. In one approach, control gate layers at a common height in the blocks BLK0, BLK1, BLK2, BLK3 are driven together. The substrate 601 may also carry circuit logic beneath the blocks BLK0, BLK1, BLK2, BLK3, along with one or more lower metal layers patterned into conductive traces to transmit signals of the circuit logic. The blocks BLK0, BLK1, BLK2, BLK3 are formed in an intermediate region 602 of the memory device.In an upper region 603 of the memory device, one or more upper metal layers are patterned into conductive traces to carry logic signals. Each block BLK0, BLK1, BLK2, BLK3 comprises a stacked memory cell area, with alternating levels of the stack representing word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposite stepped sides from which vertical contacts extend upward to an upper metal layer to establish connections to conductive traces. While four blocks BLK0, BLK1, BLK2, BLK3 are illustrated by way of example, two or more blocks extending in the x- and / or y-direction may be used.

[0063] In one possible approach, the x-direction length of the plane represents a direction in which signal paths extend to word lines in the one or more upper metal layers (a word line or SGD line direction), and the y-direction width of the plane represents a direction in which signal paths extend to bit lines in the one or more upper metal layers (a bit line direction). The z-direction represents a height of the memory device.

[0064] Fig. 6B illustrates an exemplary cross-section of a portion of one of the blocks BLK0, BLK1, BLK2, BLK3 Fig. 6A. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers comprise two SGD layers, two SGS layers, and four dummy wordline layers DWLD0, DWLD1, DWLS0, and DWLS1, in addition to the data wordline layers (wordlines) WL0-WL111. The dielectric layers are designated DL0-DL116. Also illustrated are regions of the stack 610 comprising the NAND strings NS1 and NS2. Each NAND string includes a storage hole 618, 619 filled with materials that form memory cells adjacent to the word rows. A region 622 of the stack 610 is shown in Fig. 6D and is discussed in more detail below. The dielectric layers can have variable thicknesses, so some of the conductive layers can be closer or farther from neighboring conductive layers. The thicknesses of the dielectric layers affect the "ON slope," which is a factor in memory density. In particular, a smaller ON slope allows for more memory cells in a given area, but may compromise reliability.

[0065] The 610 stack includes a substrate 611, an insulating layer 612 on the substrate 611, and a portion of a source line SL. NS1 has a source end 613 at a bottom 614 of the stack and a drain end 615 at a top 616 of the stack 610. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 may be provided periodically throughout the stack 610 as connections extending through the stack 610, such as to connect the source line to a specific contact line above the stack 610. The contact line connectors 617, 620 may be used in the formation of the word lines and subsequently filled with metal. A portion of a bit line BL0 is also illustrated. A conductive via 621 connects the drain end 615 to BL0.

[0066] Fig. Figure 6C illustrates a graphical representation of the storage hole diameter in the stack of Fig. 6B. The vertical axis is aligned to the stack of Fig. 6B and illustrates a width (wMH), e.g., the diameter of the memory holes 618 and 619. The word line layers WL0-WL111 of Fig. 6A are repeated as an example and are located at the respective heights z0-z111 in the stack. In such a memory device, the memory holes etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of about 25 to 30 is common. The memory holes may have a circular cross-section. Due to the etching process, the memory hole width may vary along the length of the hole. Typically, the diameter becomes progressively smaller from top to bottom of the memory hole. That is, the memory holes taper, narrowing at the bottom of the stack. In some cases, there is a slight narrowing at the top of the hole near the select gate, so the diameter becomes slightly wider before becoming progressively smaller from the top to the bottom of the memory hole.

[0067] Due to the uneven width of the memory hole, the programming speed, including the program edge and the erase speed of the memory cells, can vary depending on their position along the memory hole, e.g., depending on their height in the stack. For a smaller memory hole diameter, the electric field above the tunnel oxide is relatively stronger, so the programming and erase speeds are relatively higher. One approach is to define groups of adjacent wordlines for which the memory hole diameter is similar, e.g., within a defined diameter range, and apply an optimized verification scheme for each wordline in a group. Different groups may have differently optimized verification schemes.

[0068] Fig. Figure 6D illustrates a close-up of region 622 of stack 610 of Fig. 6B. Memory cells are formed at the various levels of the stack at the intersection of a wordline layer and a memory hole. In this example, the SGD transistors 680, 681 are provided above the dummy memory cells 682, 683 and a data memory cell MC. A series of layers may be deposited along the sidewall (SW) of the memory hole 630 and / or within each wordline layer, e.g., using atomic layer deposition. For example, each pillar (e.g., the pillar formed by the materials within a memory hole 630) may include a charge-trapping layer or film 663 such as SiN or another nitride, a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. A wordline layer may include a blocking oxide / block high-k material 660, a metal barrier 661, and a conductive metal 662 such as tungsten as a control gate.For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided in storage hole 630. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in the various storage holes. A pillar may form a columnar active area (AA) of a NAND chain.

[0069] When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are drawn into the charge-trapping layer from the channel and through the tunnel layer. The Vth of a memory cell increases proportionally to the amount of stored charge. During an erase operation, the electrons return to the channel.

[0070] Each of the storage holes 630 may be filled with a plurality of annular layers including a blocking oxide layer, a charge trapping layer 663, a tunneling layer 664, and a channel layer. A core region of each of the storage holes 630 is filled with a body material, and the plurality of annular layers are located between the core region and the word line in each of the storage holes 630.

[0071] The NAND chain can be considered to have a floating-body channel, since the entire length of the channel is not formed on a substrate. Furthermore, the NAND chain is formed by a plurality of wordline layers arranged one above the other in a stack and separated by dielectric layers.

[0072] Fig. 7A illustrates a top view of an exemplary wordline layer WL0 of the stack 610 of Fig. 6B. As mentioned above, a three-dimensional memory device may include a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates of the SG transistors and memory cells. The layers used for the SG transistors are SG layers, and the layers used for the memory cells are wordline layers. Furthermore, storage holes are formed in the stack and filled with a charge-trapping material and a channel material. This forms a vertical NAND string. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0073] A BLK block in a three-dimensional memory device may be divided into sub-blocks, each sub-block comprising a NAND chain sharing a common SGD control line. See, for example, the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBa, SBb, SBc, and SBd, respectively. Furthermore, a wordline layer in a block may be divided into regions. Each region is located in a respective sub-block and may extend between contact line connectors (e.g., slots) that are periodically formed in the stack to process the wordline layers during the memory device manufacturing process. This processing may include replacing a sacrificial material of the wordline layers with metal.In general, the spacing between contact line connectors should be relatively small to account for limiting the distance an etchant can travel laterally to remove the sacrificial material and the distance that the metal can travel to fill a void created by the removal of the sacrificial material. The spacing between contact line connectors may, for example, allow for several rows of memory holes between adjacent contact line connectors. The layout of the memory holes and contact line connectors should also account for limiting the number of bit lines that can span the region while each bit line connects to a different memory cell. After processing the word line layers, the contact line connectors can optionally be filed with metal to provide a connection through the stack.

[0074] In this example, four rows of storage holes are located between adjacent contact line connectors. A row here is a group of storage holes aligned in the x-direction. Furthermore, the rows of storage holes are located in a staggered pattern to increase the density of the storage holes. The wordline layer or wordline is divided into regions WL0a, WL0b, WL0c, and WL0d, each connected by an interconnect line 713. In one approach, the last region of a wordline layer in one block may be connected to a first region of a wordline layer in a next block. The contact line 713, in turn, is connected to a voltage driver for the wordline layer. The region WL0a has example storage holes 710, 711 along a contact line 712. The region WL0b has example storage holes 714, 715. The region WL0c has example storage holes 716, 717.The region WL0d has exemplary memory holes 718, 719. The memory holes are also shown in . Fig. 7B. Each memory hole may be part of a corresponding NAND chain. For example, memory holes 710, 714, 716, and 718 may be part of NAND chains NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe.

[0075] Each circle represents the cross-section of a memory hole at a wordline layer or SG layer. Each circle, shown with dashed lines, represents memory cells provided by the materials in the memory hole and by the adjacent wordline layer. For example, memory cells 720, 721 are in WL0a, memory cells 724, 725 are in WL0b, memory cells 726, 727 are in WL0c, and memory cells 728, 729 are in WL0d. These memory cells are located at a common height in the stack.

[0076] Contact line connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 may be located between and adjacent to the edges of the regions WL0a-WL0d. The contact line connectors 701, 702, 703, 704 provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, where the conductive line is connected to a voltage driver in a peripheral region of the memory device.

[0077] Fig. Figure 7B illustrates a top view of an exemplary top dielectric layer DL116 of the stack of Fig. 6B. The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to a respective voltage driver. This allows a set of memory cells in a region of a wordline layer to be programmed simultaneously, with each memory cell being in a respective NAND chain connected to a respective bitline. A voltage can be set on each bitline to enable or disable programming during each programming voltage.

[0078] The region DL116a has the exemplary storage holes 710, 711 along a contact line 712 that coincides with a bit line BL0. A number of bit lines extend over the storage holes and are connected to the storage holes, as indicated by the "X" symbols. BL0 is connected to a set of storage holes that includes the storage holes 711, 715, 717, 719. Another exemplary bit line BL1 is connected to a set of storage holes that includes the storage holes 710, 714, 716, 718. The contact line connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 of Fig. 7A are also illustrated as they extend vertically through the stack. The bitlines may be numbered in a sequence BL0-BL23 across the DL116 layer in the x-direction.

[0079] Different subsets of bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, BL20 are connected to memory cells in a first row of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, BL22 are connected to memory cells in an adjacent row of cells that borders the first row at the right edge. BL3, BL7, BL11, BL15, BL19, BL23 are connected to memory cells in a first row of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, BL21 are connected to memory cells in an adjacent row of memory cells that borders the first row at the left edge.

[0080] The memory cells of the memory blocks can be programmed to store one or more data bits in multiple data states, each of which is associated with a respective threshold voltage Vt. For example, Fig. Figure 8 illustrates a threshold voltage Vt distribution of a group of memory cells programmed according to a one-bit-per-memory-cell (SLC) memory scheme. In the SLC memory scheme, there are two overall data states, including the erased state (Er) and a single programmed data state (S1). Fig. Figure 9 illustrates the threshold voltage Vt distribution of a three-bit per cell (TLC) memory scheme that includes eight total data states, namely the erased state (Er) and seven programmed data states (S1, S2, S3, S4, S5, S6, and S7). Each programmed data state (S1-S7) is associated with a respective verify voltage (Vv1-Vv7) used during a verify portion of a programming operation. Other storage schemes are also available, such as two-bit per cell (MLC) with four data states, four-bit per cell (QLC) with sixteen data states, or five-bit per cell (PLC) with thirty-two data states.

[0081] Programming the memory cells of a memory block is performed on a word line by word line basis from one side of the memory block to an opposite side. The programming direction can start from a drain side of a memory block (or a sub-block in some cases) and continue to the source side, or vice versa. For example, with reference to Fig. 6B, in a normal order programming (NOP) direction, the first word line to be programmed may be WL0. The next word line to be programmed may be WL1, then WL2, and so on. In a reverse order programming (ROP) operation, the first word line to be programmed may be the physical WLN (where N is the highest data word line in the memory block or sub-block, e.g., WL111), and then programming continues with the physical WLN-1 (e.g., WL110), then the physical WLN-2 (e.g., WL109), and so on.

[0082] Programming the memory cells of one of the word lines to multiple bits per memory cell (for example, MLC, TLC, or QLC) typically begins with the memory cells in the erased state and includes a plurality of program loops. Fig. 10 illustrates a waveform 1000 of the voltages applied to a selected wordline during an exemplary memory cell programming operation for programming the memory cells of the selected wordline with a larger number of bits per memory cell (e.g., TLC). As illustrated, each programming loop includes a programming pulse VPGM and one or more verify pulses, depending on which data states are being programmed in a particular programming loop. For simplicity, a square waveform is illustrated for each pulse; however, other shapes are possible, such as a multi-level shape or a ramp shape.

[0083] Furthermore, this example pulse sequence uses Incremental Step Pulse Programming (ISPP), which means that the Vpgm pulse amplitude increases, or increases, in each subsequent program loop. In other words, the pulse sequence includes VPGM pulses whose amplitude increases incrementally by a fixed step size (dVPGM) with each subsequent program loop. A new pulse sequence begins at an initial VPGM pulse level VPGMU and ends at a final VPGM pulse level that does not exceed a maximum allowed level. The example pulse sequence 1000 includes a series of VPGM pulses 1001-1009 applied to a selected word line including a set of non-volatile memory cells. One or more test voltage pulses 1010-1019 are provided, for example, after each VPGM pulse based on the target data states being tested in the program loop.The test voltages correspond to the voltages Vv1-Vv7 given in . Fig. 9. Simultaneously with the application of the test voltages, a sensing operation may determine whether a particular memory cell in the selected word line has a threshold voltage Vt above the test voltage associated with its intended data state by detecting a current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state, so its threshold voltage Vth is less than the test voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state, so the threshold voltage Vth is above the test voltage.If the memory cell passes the test, programming of that memory cell is complete, and further programming of that memory cell is inhibited for all remaining program loops by applying a reverse voltage to a bit line coupled to the memory cell simultaneously with the VPGM pulse. Programming continues until all memory cells are tested for their intended data states, in which case the programming passes fail, or until a predetermined maximum number of program loops is exceeded, and programming fails. In some embodiments, the memory cells of a word line may be divided into a series of chain groups or simply chains that can be programmed independently, and programming may begin from one chain to another across the word line before continuing to the next word line in the memory block.

[0084] In addition to the verification operations described above, a bit scan operation may also be performed to determine when programming is complete for a group of memory cells, e.g., a plurality of memory cells in a selected word line that are being programmed to a given data state or that are being erased. As used herein, a "bit scan" is an operation that counts a number of memory cells whose programming characteristic has not been shifted above or below a particular verify voltage level for a particular data state, or has been shifted above the verify voltage, depending on a particular application. In some embodiments, a bit scan may include a bit counting operation that counts a number of memory cells whose threshold voltages Vt have not been shifted above a particular verify voltage level Vv for a particular data state.For example, a bit sample of the data state Sn is a count of a number of memory cells of the data state Sn that fail verification, i.e., whose threshold voltages Vt have not shifted above a verification voltage level Vvn for the data state Sn. Similarly, a bit sample of the state Sn+1 is a count of a number of memory cells of the state n+1 whose threshold voltages Vt have not shifted above a verification voltage level Vvn+1 for the data state Sn+1, and so on. In some other embodiments, a bit sample may be a count of the number of memory cells that pass verification, i.e., whose threshold voltages Vt have shifted above a verification voltage level Vvn.

[0085] The programming of memory cells for a particular memory state Sn may be considered complete when the bit scan count for a particular state is less than a predetermined bit scan failure pass (BSPF) threshold. In some embodiments, the BSPF threshold is less than a number of read errors that can be corrected by the ECC engine of the memory device. In other words, the programming of memory cells for a particular memory state Sn may be considered complete even though all memory cells to be programmed to the particular memory state Sn do not have threshold voltages that have shifted above a verify voltage level Vvn for the data state Wn, as long as the number of "failing" memory cells is less than a number of read errors that can be corrected by the ECC engine.

[0086] Bit scan operations are typically performed based on the results of verification operations for a given program verification iteration. In particular, the results of the verification operations can be used to calculate the bit scan for a given memory state.

[0087] Bit sampling may also be performed after erase verify in an erase operation to count the number of memory cells whose threshold voltages Vt are greater than an erase verify voltage, as discussed in more detail below.

[0088] Traditionally, the result of a bit scan operation is binary. That is, the bit scan passes (e.g., if the number of failing memory cells is less than the BSPF threshold) or fails (e.g., if the number of failing memory cells is greater than the BSPF threshold). The present disclosure improves on these techniques by enabling the bit scan operation to produce additional (non-binary) results. A bit scan operation that produces non-binary results (greater than two possible options) is referred to below as an "analog bit scan."For example, if a bit scan operation passes, several analog bit scan operations can determine whether the pass was a clear pass (where the number of failed memory cells is significantly less than the BSPF threshold) or a marginal pass (where the number of failed memory cells is equal to or barely less than the BSPF threshold). Similarly, if the bit scan operation fails, several analog bit scan operations can determine whether the fail was a clear fail (where the number of failed memory cells is significantly higher than the BSPF threshold) or a marginal fail (where the number of failed bits is barely above the BSPF threshold).

[0089] In some embodiments discussed below, an analog bit scan operation may even produce more than four possible outputs or bins. By extending the bit scan results to provide additional information beyond just the binary pass / fail of conventional bit scan operations, program and erase algorithms and modes can be optimized with dynamic control to improve performance, reliability, and / or endurance. For example, in some embodiments, program verification may be skipped in certain program loops to improve performance. In some other embodiments, different dVPGM voltages or dVERA voltages may be dynamically applied to improve performance and / or endurance. In still other embodiments, additional verification operations may be triggered to improve reliability.These and other features and benefits are explained in more detail below.

[0090] A first example of an analog bit scan operation uses a occupancy time detector to determine the output (e.g., "significant fail," "minor fail," "minor pass," or "significant pass"). If a bit scan operation fails, it stops immediately after the number of failed bits exceeds the BSPF threshold. Thus, a word line that fails the bit scan with a large number of failed bits (a significant fail) will fail the bit scan more quickly than a word line that fails a bit scan with a comparatively smaller number of failed bits (a minor fail). Similarly, counting failed bits during the bit scan operation takes some time.Therefore, a wordline with a relatively low number of failed bits (clear pass) will pass the bit scan faster than a wordline with a relatively higher (but still passing) number of failed bits (marginal pass). In this exemplary embodiment, the degree of bit scan pass (clear pass / marginal pass) or bit scan fail (clear fail / marginal fail) is determined primarily based on the time or occupancy time of the bit scan operation.

[0091] The analog bit scan process begins by determining whether the bit scan passed or failed by comparing the number of failed bits (memory cells) to the BSPF threshold. A occupancy time detector then determines whether a bit scan pass or fail was a significant or marginal pass. The time required to complete the bit scan process is proportional to the occupancy time, which can be determined using a mathematical formula such as: BusyTime = 1 + (DBUS_Precharge_Cyle​ + 1)+ (DBUS_Discharge_Cycle+1) +(Detection_Time_1_Tier_No_Error)∗(#_of_Tiers_Executed) + #_of_Fail_Bits / 8

[0092] DBUS is an internal bus that connects the user cache to internal data latches. DBUS_Precharge_Cycle is thus a count of clock cycles required to precharge the DBUS, and DBUS_Discharge_Cycle is a count of clock cycles required to discharge the DBUS. Both DBUS_Precharge_Cycle and DBUS_Discharge_Cycle are thus preset parameters. In an exemplary embodiment, both are set to five (5) cycles. Detection_Time_for_1_Tier_No_Error is also a parameter and is set to thirty-one (31) cycles in one exemplary embodiment, but can be set to different levels in other embodiments. The variable #_of_Tiers_Executed contains the number of layers in a page. In an exemplary embodiment, the number of layers is sixteen (16).The variable #_of_Fail_Bits increases the occupancy time with each failed bit (memory cell) that is detected.

[0093] A sample table illustrating an example of how the occupancy time can be used to determine the extent of a bit scan pass or fail is shown in Fig. 11. In this example, the BSPF threshold is set to one hundred and twenty (120) bits, and the bit scan is a four-layer bit scan. There are four possible outputs for this exemplary analog bit scan operation: significant fail, minor fail, minor pass, and significant pass. In some embodiments, more bins could be added, such as a medium fail and a medium pass. The bit scan pass / fail status is first determined by comparing the number of failed bits to the BSPF threshold.

[0094] Once the bit scan status is determined, the occupancy time can be calculated using a formula such as the one presented above. If the occupancy time is less than a occupancy time threshold (for example, one hundred and fifty

[150] cycles), then if the bit scan status is passed, the output is a major pass, and if the bit scan status is failed, the output is a major fail. On the other hand, if an occupancy time is greater than or equal to the occupancy time threshold, then if the bit scan status is passed, the output is a minor pass, and if the bit scan status is failed, the output is a minor fail.

[0095] For example, if the analog bit sampling operation fails (failed bits have exceeded the BSPF threshold) while sampling the first layer, then the occupancy time will naturally be below the occupancy time threshold, and the output will be a significant failure. On the other hand, if the bit sampling operation fails during the last layer sampling, the occupancy time will be equal to or above the occupancy time threshold, and the output will be a minor failure. In other words, if the bit sampling operation completed relatively quickly, the output will be a significant failure, and if the bit sampling operation completed relatively slowly, the output will be a minor failure.

[0096] According to the above formula, in the case where the bit scan status is passed, when there are very few failed bits, the occupancy time is lower compared to a case where there are many failed bits because the variable (#_of_Fail_Bits) is low. Therefore, if the bit scan status is pass and the occupancy time is less than the occupancy time threshold, the output is a significant pass. In other words, if the bit scan operation was completed relatively quickly, then the output is a significant pass, and if the bit scan operation was completed relatively slowly, then the output is a marginal pass. The occupancy time threshold for a pass can be the same as or different from the occupancy time threshold for a fail.

[0097] With reference to Fig. 18, a flowchart 1800 is provided illustrating an exemplary embodiment of the present disclosure. These steps could be performed by the controller, a processor or processing device, or any other circuitry executing instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0098] At step 1802, an analog bit sampling operation is performed to count the failed bits and compare the number of failed bits to the BSPF threshold. At step 1804, the occupancy time is determined, for example, using the occupancy time formula set forth above.

[0099] At decision step 1806, it is determined whether the analog bit scan operation passed. If the answer to decision step 1806 is "yes," at decision step 1808, it is determined whether the occupancy time is less than the occupancy time threshold. If the answer to decision step 1808 is "no," at step 1810, the output of the analog bit scan operation is a marginal pass. If the answer to decision step 1808 is "yes," at step 1812, the output of the analog bit scan operation is a significant pass.

[0100] If the answer to decision step 1806 is "no," then in decision step 1814, it is determined whether the occupancy time is less than the occupancy time threshold. If the answer to decision step 1814 is "no," the output of the analog bit scan operation is a minor failure. If the answer to decision step 1814 is "yes," the output of the analog bit scan operation is a major failure.

[0101] In the Fig. 11, Fig. 12 and Fig. In the example illustrated in Figure 18, the bit scan operation scans four layers of the page. In some embodiments, only a single layer may be scanned during the bit scan operation. In some embodiments where multiple layers are scanned, whether a bit scan miss is a hard miss or a minor miss may be determined based on which layer was scanned when the bit scan operation completed. For example, if four layers are scanned and the bit scan operation failed while scanning one of the first three layers, then the miss layer information is introduced into the occupancy time formula, increasing the occupancy time and likely resulting in a hard miss output. However, if the bit scan operation failed while scanning the fourth layer, the output may be a minor fail.If only one layer is sampled, a number of clock cycles can be used to determine whether the output is a clear fail or a weak fail.

[0102] With reference to Fig. 12 and Fig. 13, shown in this figure, are a occupancy control signal YBUSYn that remains active during the bit scan operation, an oscillator TMOSC_SMB, and a clock CLK counter that counts the oscillator cycles during the bit scan operation. Based on the clock count, parameters are set that determine whether a bit scan fail is a significant fail or a minor fail, and a bit scan pass is a significant pass or a minor pass during an analog bit scan operation involving only a single-layer scan.

[0103] Specifically, the CLK counter is compared to a counter threshold. If the CLK counter is less than the counter threshold at the end of the scan, the output is a clear fail, and if the CLK counter is equal to or greater than the counter threshold, the output is a minor fail. The counter threshold can be set at any suitable level to separate a clear fail from a minor fail condition.

[0104] As with determining whether a pass was a major pass or a minor pass, separate parameters BSPF_ABSCAN_WP and BSPF_ABSCAN_SP are provided to change the occupancy time that separates a major pass from a minor pass. Specifically, when determining whether a pass is a minor pass, the difference between BSPF and BSPF_ABSCAN_WP (BSPF - BSPF_ABSCAN_WP) is input into the above occupancy time formula instead of (#_of_Fail_Bits / 8) to establish a minor pass occupancy time threshold. The number of clock cycles during the bit scan operation is then compared to the occupancy time threshold. If the number of clock cycles is greater than the minor pass occupancy time threshold, the output is a minor pass.Similarly, the difference between BSPF and BSPF_ABSCAN_SP can be calculated and substituted into the above formula to establish a clear pass occupancy time threshold. The number of clock cycles required to complete the bit scan operation is then compared to the clear pass occupancy time threshold. If the number of clock cycles is less than the clear pass occupancy time threshold, then the output is a clear pass. Conversely, if the number of clock cycles required to complete the bit scan operation is greater than the clear pass occupancy time threshold, then the output is a marginal pass.

[0105] According to another exemplary embodiment, the determination of whether a bit scan miss is significant or minor is based on which layer was being scanned at the time of the bit scan miss. As discussed above, a page may be divided into a plurality of layers, e.g., sixteen (16) layers (layers 0-15) in one exemplary embodiment. The bit scan operation may scan all sixteen layers or only some of these layers, e.g., every other layer, every fourth layer, or only two layers. Fig. Figure 14 is a table illustrating various layer scanning options, the layer scanning order, and the outputs based on which layer is being scanned at the time of the bit scan failure. For example, with a scan of sixteen layers, if the failure occurs during the scan from layer 0 to layer 3, the output is a significant failure. If the failure occurs during the scan from layer 12 to layer 15, the output is a minor failure. If the failure occurs during any of the other layers, the output is a regular failure or a "medium failure." Additional bins may be possible depending on how many layers are being scanned. Furthermore, the barriers between these bins can be adjusted as appropriate for a given memory device or operation.In a two-layer scan, only two miss bins (significant miss, minor miss) are possible according to the techniques of this embodiment.

[0106] Fig. 19 illustrates a flowchart 1900 illustrating an exemplary embodiment of the present disclosure. These steps could be performed by the controller, a processor or processing device, or any other circuitry that executes instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0107] At step 1902, a multi-layer analog bit scan operation is performed on a page, e.g., a selected word line being programmed. At decision step 1904, it is determined whether the analog bit scan operation has completed a scan of all layers and the number of failed bits is also less than or equal to the BSPF threshold. If the answer at decision step 1904 is "yes," then at step 1906, the output of the analog bit scan operation is "pass."

[0108] If the answer in decision step 1904 is "no," then the method continues with decision step 1908. At decision step 1908, it is determined whether the analog bit scan operation failed during an early slice scan, e.g., one of the first four slices scanned in a sixteen-slice scan. If the answer in decision step 1908 is "yes," the output of the analog bit scan operation in step 1910 is a clear failure.

[0109] If the answer in decision step 1908 is "no," then the method continues with decision step 1912. At decision step 1912, it is determined whether the analog bit scan operation failed during a late slice scan, e.g., one of the last four slices scanned in a sixteen-slice scan. If the answer in decision step 1912 is "yes," then at step 1914, the output of the analog bit scan operation is a minor fail. If the answer in decision step 1912 is "no," then at step 1916, the output of the analog bit scan operation is a medium fail.

[0110] In the exemplary embodiment of Fig. 14, the layers are scanned sequentially in the order from layer 0 to layer 15. However, in some embodiments, other orders may be used. The outputs are adjusted accordingly so that the output is a significant failure if a failure occurs during the scanning of any of the first layers (regardless of the layer number thereof), and the output is a minor failure if a failure occurs during the scanning of any of the last layers (regardless of the layer number thereof).

[0111] A disadvantage of the exemplary embodiment of Fig. 14 is that this embodiment does not allow the analog bit scan operation to differentiate between a slight pass and a significant pass, that is, the output for each completion of the bit scan operation is only a pass. Referring to Fig. 15, according to another exemplary embodiment, a marginal pass can be detected by adjusting (reducing) the BSPF threshold downward from a base so that BSPF_adj is at a lower amount than the ECC engine can easily correct. Specifically, the BSPF threshold is set to an adjusted (reduced) level BSPF_adj before the bit scan. Then, if the bit scan operation fails during the scanning of the last layer or any of the last layers, the output is a marginal pass. If the bit scan also passes at the higher BSPF_adj level, the output is a significant pass, since the number of failed bits must actually be less than the base BSPF threshold.In other words, in this embodiment, the layers are binned and a failure during each bin can be either a significant failure, a minor failure, or a minor pass, and any pass at the adjusted BSPF is a significant pass.

[0112] In some embodiments, the layers are selected to cover memory hole variations, so that each layer is associated with memory holes originating from a particular row (e.g., see the rows in Fig. 7B). Selecting the layers in this way ensures that each layer includes memory cells that exhibit a range of different behaviors (fast to program and slow to program), and thus each layer represents a cross-section of similar cell behaviors.

[0113] According to another embodiment, multiple BSPF windows or ranges are established, and the fact which option (for example, a clear fail, a minor fail, a minor pass, or a clear pass) is output depends on which BSPF window the failure bit count (FBC) falls into. The BSPF windows are defined by predetermined BSPF criteria. For example, in the table of Fig. 16, the base BSPF is one criterion. The other exemplary criteria are BSPF_ABSCAN_F, which is greater than BSPF, and BSPF_ABSCAN_P, which is less than BSPF. These three criteria define four total windows: a first window that includes the FBC greater than BSPF_ABSCAN_F; a second window that includes the FBC between BSPF_ABSCAN_F and BSPF; a third window that includes the FBC between BSPF and BSPF_ABSCAN_P; and a fourth window that includes the FBC below BSPF_ABSCAN_P.

[0114] In this example, the analog bit scan operation is performed to determine the FBC. If the FBC is in the first window (FBC > BSPF_ABSCAN_F), then the output is a major fail. If the FBC is in the second window (BSPF < FBC ≤ BSPF_ABSCAN_F), then the output is a minor fail. If the FBC is in the third window (BSPF_ABSCAN_P < FBC ≤ BSPF), then the output is a minor pass. If the FBC is less than the fourth window (FBC ≤ BSPF_ABSCAN_P), then the output is a major pass.

[0115] With reference now to Fig. 17 illustrates a flowchart 1700 including the steps of performing an analog bit sampling operation according to an embodiment of the present disclosure. These steps could be performed by the controller, a processor or processing device, or any other circuitry executing instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0116] In step 1702, the variable n is set to zero so that the first layer to be sampled is layer 0. This numbering format is intended to be exemplary in nature, and in some embodiments, the numbering may be different and the first layer to be sampled could be a layer other than layer 0.

[0117] In step 1704, the bit scan operation on Tier_n is performed, and the failed bits are counted and included in the FBC. At decision step 1706, it is determined whether Tier_n is the last layer to be scanned. If the answer at decision step 1706 is "no," the next layer to be scanned is incremented in step 1708. In the exemplary embodiment, this involves incrementing the variable n, i.e., n = n + 1. In some embodiments, every other layer or every fourth layer may be scanned, at which point n may be incremented by two or four. In some other embodiments, the layers may be scanned in a very different order, and in those embodiments, the scanned layers may be incremented in a different way. The process then returns to step 1704.

[0118] If the answer to decision step 1706 is "yes," it is determined at decision step 1710 whether the FBC is greater than BSPF_ABSCAN_F. If the answer to decision step 1710 is "yes," the output at step 1712 is a clear failure, and the process ends.

[0119] If the answer to decision step 1710 is "yes," then decision step 1714 determines whether the FBC is between BSPF_ABSCAN_F and BSPF. If the answer to decision step 1714 is "yes," the output at step 1716 is a minor failure, and the process ends.

[0120] If the answer to decision step 1714 is "no," then decision step 1718 determines whether the FBC is between BSPF and BSPF_ABSCAN_P. If the answer to decision step 1718 is "yes," then the output at step 1720 is a marginal pass, and the process ends. If the answer to decision step 1718 is "no," the output at step 1722 is a significant pass, and the process ends.

[0121] According to this embodiment, the scan must be completed for all layers to be scanned, i.e., the failed bits must be counted up to the last layer. In other words, the bit scanning process cannot stop when the FBC exceeds the BSPF threshold, as is the case in the embodiments described above. However, in an alternative embodiment, an additional decision step may be introduced between steps 1704 and 1706 to determine whether the FBC is greater than BSPF_ABSCAN_F. This additional decision step determines whether a clear fail condition has already been reached. If the answer to this additional decision step is "yes," the process proceeds directly to step 1712, and the process ends with the clear fail output.

[0122] The fail bit count detector that performs or contributes to the performance of these steps can be integrated into a number of different circuits within a memory device.

[0123] Another aspect of the present disclosure relates to the use of an analog bit sampling process, such as any of the techniques and embodiments discussed above, to improve erase efficiency and improve the operating life or lifetime of the memory device.

[0124] An erase operation involves transitioning the memory cells from their respective programmed data states (e.g. data states S1-S7 in Fig. 9) into the erased state Er so that they can be reprogrammed to contain new data. During the erase operation, it is desirable to lower the threshold voltages Vt of the memory cells below an erase-verify level, which represents an upper limit of the erased data state Er. An erase operation often includes a number of erase loops, each including an erase section followed by an erase-verify operation. The erase operation is typically performed at a memory block or sub-block level rather than a wordline level. In other words, one memory block or sub-block, including many wordlines, is erased at a time.

[0125] In the erase section of an erase loop, the circuitry in the memory device applies an erase voltage VERA to the strings of the memory block via the bit lines and / or the source line, while applying a very low voltage (e.g., zero volts) to the word lines of the memory block to provide a positive channel-to-gate voltage difference for the memory cells of the memory block to tunnel holes from the channel to the charge storage materials of the memory cells, thereby reducing the threshold voltages Vt of the memory cells. In the verify section, a verification voltage is applied to the word lines, and detection circuitry is used to detect currents in the NAND strings to determine whether the memory cells have been sufficiently erased.If an insufficient number of memory cells have been sufficiently erased, this process is repeated in one or more subsequent erase loops until the erase verification procedure is passed. Between erase loops, the erase voltage can be increased by an increment dVERA, similar to how the programming voltage VPGM increases by dVPGM between programming loops.

[0126] An unnecessarily deep erase, in which the threshold voltages Vt of the memory cells are significantly lower than the erase verification voltage, can reduce the lifetime of the memory device and / or lead to data retention degradation. It is also known that with increased program and erase cycles, the memory cells are erased more slowly and additional erase pulses may be required to bring their threshold voltages Vt below the erase verification voltage, compared to when the memory device is at the beginning of its lifetime. Each time the number of erase loops to pass erase verification increases with the program erase cycle, the erase depth is reduced by approximately the same voltage as the step size dVERA. For example, Fig. 20 is a graphical representation of the top of the erase versus program erase (PE) cycles in an exemplary memory device, and Fig. Figure 21 is a diagram of erase loops to complete erase cycles versus program erase cycles. The erase verify level is illustrated, and an "overerase" voltage region is highlighted. As illustrated, the top of the erase increases with the program erase cycle because the erase rates of the memory cells are slowed until the top reaches the erase verify level, at which point an additional erase loop is initiated and added to each subsequent erase operation. When this occurs, the top of the erase falls into the "overerase" zone by approximately the step size dVERA, thereby increasing the degradation in the memory cells. One approach to avoiding overerase is to use a small step size dVERA, but this may come at the expense of erase time (performance), as it will require additional erase loops to complete the erase operation.

[0127] According to one aspect of the present disclosure, the analog bit sensing operation is used in each erase loop to enable finely controlled erase depth with minimal performance degradation. According to these techniques, the erase voltage step size dVERA by which the erase voltage VERA is increased between erase loops is set as a function of the output of the analog bit sensing operation. In some embodiments, if the output of the analog bit sensing operation is a marginal pass (i.e., the threshold voltages Vt of the memory cells are just above the erase verify voltage), the erase voltage VERA can be increased by a reduced step size (e.g., dVERA / 2), and the erase verify operation can be skipped in a final erase loop. This also enables improved erase accuracy and a reduction in the threshold voltages Vt of the memory cells reaching the over-erased zone.

[0128] Fig. Figure 22 is a flowchart 2200 illustrating the steps of erasing a memory block or sub-block according to one embodiment of these techniques. These steps could be performed by the controller, a processor or processing device, or any other circuitry that executes instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0129] At step 2202, an erase pulse at an erase voltage VERA is applied to the NAND chains of a memory block that is itself to be fully erased or contains a sub-block that is to be erased. The VERA voltage may be applied to a drain side of the NAND chains; to a source side of the NAND chains; or to both the source and drain sides. At step 2204, an erase verify operation is performed on the memory block or sub-block to determine whether a sufficient number of memory cells in the memory block or sub-block have threshold voltages Vt that are below the erase verify voltage. Also in this step, the analog bit sampling operation is performed to determine whether an erase verification has significantly failed, slightly failed, or passed.

[0130] At decision step 2206, it is determined whether the analog bit scan operation passed. If the response or output at decision step 2206 is a clear fail, the process proceeds to step 2208. An exemplary threshold voltage distribution that would produce a clear fail result is shown in Fig. 23A illustrates this because a large number of memory cells have threshold voltages Vt higher than the erase verification voltage. At step 2208, the erase voltage VERA is increased by a first increment dVERA. The process then returns to step 2202 to begin another erase loop.

[0131] If the output at decision step 2206 is a significant failure, the process proceeds to step 2210. An exemplary distribution of the threshold voltage Vt that would produce a minor failure output is shown in Fig. 23B illustrates that an average set of memory cells has threshold voltages Vt higher than the erase verify voltage. At step 2210, the erase voltage VERA is increased by a second step size that is smaller than the first step size, e.g., dVERA / 2. In other embodiments, the second step size may be any suitable voltage that is smaller than the first step size dVERA. At step 2212, an erase pulse at the erase voltage VERA is applied to the memory block without a subsequent erase verify operation. The erase operation then ends.

[0132] If the output at decision step 2206 is a pass (either a major pass or a minor pass), the erase process ends right there without any further erase loops. An example distribution of the threshold voltage Vt that would produce a pass output is shown in Fig. 23C illustrates that a high number of memory cells have threshold voltages Vt that are below the erase verification voltage, meaning that very few memory cells failed the erase verification.

[0133] Now referring to the flowchart 2400 of Fig. 24, the steps of erasing the memory cells of a memory block or sub-block are shown with like digits, separated by a prefix of “24” instead of “22”, which represents corresponding steps with the embodiment of Fig. 22. This embodiment differs from the embodiment of Fig. 22 in that if the output at 2406 is a marginal pass, the process proceeds to step 2410 instead of ending. Also, after the erase pulse at step 2412, an erase verify operation is performed at step 2414, followed by an analog bit scan operation. At step 2416, it is determined whether the analog bit scan passed. The process ends only if the output at step 2416 is a significant pass. If the output in step 2416 is a fail or marginal pass, the process returns to step 2410 to begin another erase verify loop with the reduced erase voltage step size (dVERA / 2). In this embodiment, the applied erase pulse is always verified with an erase verify VERA pulse before the end of the process.In some alternative embodiments, if the output at decision step 2406 is either a major pass or a minor pass, the process ends, and only a minor fail output causes the process to proceed to step 2410.

[0134] In some alternative embodiments, more than two step size voltages dVERA may be used, with the step size selected based on how clearly the bit scan operation passes or fails. In other embodiments, the erase strength may be adjusted by changing the erase duration or the bias voltage of the BL, the source voltage, or other nodes.

[0135] By reducing the step size voltage when bit sampling is close to failing, as in Fig. As illustrated in Figure 25, over-erasure is avoided, thereby protecting the memory cells from damage. Thus, the overall endurance and performance of the memory device are both improved. Fig. 25 is the Fig. 20, but applying the techniques of those exemplary embodiments. As illustrated, over-erasure is substantially eliminated.

[0136] Another aspect of the present disclosure relates to the use of analog bit sampling to enhance the implementation of smart PCV during a programming operation. When programming to many data bits per memory cell (e.g., TLC or QLC), not all data states are verified in every program loop. Rather, only the early data states are verified in the early program loops (e.g., S1 or S2), and only the later data states are verified in the later program loops (e.g., S6 or S7). Smart PCV is a programming technique in which the memory device dynamically decides when to verify each of the data states being programmed during a programming operation, i.e., which program loop begins the verification.For example, in some implementations, the smart PCV specifies that the verification for the S2 data state should start in the program loop after passing the verification of some memory cells in the S1 data state.

[0137] With reference now to Fig. 26 illustrates the threshold voltage Vt distributions of a plurality of memory cells after a first program loop 2600, a second program loop 2602, a third program loop 2604, a fourth program loop 2606, and a fifth program loop 2608. According to an intelligent PCV implementation in which verification of the data state Sn begins when some memory cells begin to pass verification in the data state Sn-1, verification of the data state S2 begins after the second program loop 2602, and verification of the data state S3 begins after the third program loop 2604. However, in this exemplary intelligent PCV technique, some overprogramming of memory cells being programmed to the S3 data state could occur in the fourth program loop 2606.In other words, some memory cells intended for the S3 data state were inadvertently programmed into the voltage range associated with the S4 data state. This is also shown in the table of . Fig. 27, which shows that overprogramming occurred in the fourth pulse. One solution to this is to perform additional verification operations, e.g., automatically starting a verification for each data state earlier. However, this more cautious approach reduces performance by requiring unnecessary verification pulses in cases where overprogramming would not have occurred.

[0138] According to some embodiments of the present disclosure, an intelligent PCV technique is provided that more effectively prevents overprogramming while avoiding unnecessary verification operations. Specifically, after each verification operation, an analog bit scan operation is performed to determine whether the verification was a significant pass (zero or very few memory cells passed the verification), a marginal pass (many memory cells passed the verification, but fewer than the threshold), a marginal fail (the number of memory cells that passed the verification is barely above the threshold), or a significant fail (the number of memory cells that passed the verification is significantly above the threshold).The output of the analog bit scan operation dictates which data states are verified during the subsequent program loop. In this embodiment, it is the number of memory cells that passed (rather than failed) the verification that is compared to the threshold.

[0139] Fig. 28 is a flowchart 2800 including the steps of programming the memory cells of a selected wordline WLn according to an exemplary embodiment of the present disclosure, using an analog bit sampling operation to determine when verification begins for certain data states. These steps could be performed by the controller, a processor or processing device, or any other circuitry executing instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0140] In step 2802, the programming voltage VPGM is set to an initial level VPGMU, and verification is set to begin for the first programmed data state S1. In step 2804, the VPGM pulse is applied to the selected word line Wln. In step 2806, the verification process is performed for all data states currently being verified. In the first case, only the data state S1 is verified. However, in later cases, additional data states are verified, and some data states that have completed programming are not verified. For example, if the programming of the data state S1 is completed, then the verification of the data state S1 is not performed in step 2806.

[0141] Additionally, in step 2806, an analog bit scan is performed to determine how many memory cells have passed verification for a highest data state SN being verified in this program loop. For this analog bit scan, a "pass" occurs when fewer memory cells than a threshold pass verification, and a "fail" occurs when more memory cells than a threshold pass verification. The more memory cells pass verification, the less pass or the more significant the fail. Conversely, the fewer memory cells pass verification, the more significant the pass or the less significant the fail. Additionally, the analog bit scan is only performed on the highest data state being verified in a given program loop; that is, no analog bit scan is performed for data state SN-1.

[0142] At decision step 2808, it is determined whether the analog bit scan operation for the highest data state being verified, i.e., SN, passed. If the output at decision step 2808 is a clear pass, then at step 2814, the programming voltage VPGM is incremented, i.e., VPGM = VPGM + dVPGM. The process then returns to step 2804 to begin the next program loop without adding any new data states to be verified.

[0143] If the output at decision step 2808 is a minor fail or a minor pass, then in step 2812 the highest data state SN being verified is incremented by one, ie, SN = SN + 1. The process then proceeds to step 2814 to increment the programming voltage VPGM and then to step 2804 to begin a next program loop.

[0144] If the output at decision step 2808 is a clear fail, in step 2810, the highest data state SN being verified is incremented by two, i.e., SN = SN + 2. Thus, verification for two additional data states begins in this state. The process then proceeds to state 2814 to increment the programming voltage VPGM and then to step 2804 to begin the next program loop.

[0145] These steps continue until verification begins for a final data state, e.g., S7 in the case of TLC or S15 in the case of QLC.

[0146] In some programming operations, an intelligent verification operation is performed during the first pair of program loops to improve programming performance, i.e., to reduce verification time. During intelligent verification program loops, only a portion of the selected wordline (for example, a chain) is selected to capture an appropriate SV_VPGM voltage, which is then used as the initial SV_VPGM programming voltage during programming of other wordlines or chains within the same memory block. Intelligent verification improves performance by optimizing the initial VPGM voltage during programming of these other wordlines, rather than setting the initial VPGM voltage at an overly conservative level that would require unnecessary program loops, or an overly aggressive level that could lead to overprogramming.During intelligent verification, the programming voltage VPGM starts with a pre-truncated and conservative initial voltage VPGMU, and the verification begins with an intelligent verification voltage Vsv that is either equal to or lower than a verification voltage for a first programmed data state, e.g., S1. Referring to . Fig. 29, during an exemplary triple-level cell (TLC) program operation, an intelligent verification operation is performed on the selected word line WLn up to a predetermined threshold of memory cells having threshold voltages Vt that exceed the verification level V SVexceed, as determined by a bit scan operation. After the predetermined threshold is exceeded, the programming voltage in this program loop is stored in latches as SV_VPGM for later use as the initial programming voltage VPGM for other programming operations on other chains and / or word lines in the memory block. In all subsequent program loops, the verify voltages applied during the verify section are the verify voltages Vv1-Vv7 (or Vv2-Vv7 if the smart verify voltage was Vv1) associated with the programmed data states, and the test for Vsv ends. In this example, smart verification fails after three program loops, and in the fourth program loop, the next data state Sn (for example, S1 or S2) is verified using the appropriate verify voltage Vvn.When programming for the next chain or wordline begins, the programming voltage applied during the first program loop is SV_VPGM. In some cases, two smart verification voltages (smart low verification level Vsvl and smart high verification level Vsvh) can be implemented to more accurately adjust SV_VPGM. However, this can add time to the process by requiring two verification pulses (one for Vsvl and one for Vsvh) instead of just one. Thus, the improved resolution for SV_VPGM may come at a performance penalty.

[0147] One aspect of the present disclosure relates to a smart verification technique that enables the smart verification programming voltage SV_VPGM to be more accurately adjusted using analog bit sampling without the performance penalty associated with verifying at both the smart low verification level Vsvl and the smart high verification level Vsvh. Fig. 30 is a flowchart 3000 illustrating the steps of programming a memory block or sub-block according to one embodiment of these intelligent verification techniques. These steps could be performed by the controller, a processor or processing device, or any other circuitry that executes instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0148] At step 3002, the smart verification process begins by setting the program voltage VPGM to a predetermined initial voltage VPGMU. At step 3004, a program loop including a program pulse followed by a verify pulse at a low smart verify voltage Vsvl is performed on the selected wordline. The number of bits that passed the verification is then counted and compared to a predetermined threshold in an analog bit scan process. In some embodiments, a loop count may be maintained to count the number of program loops to complete the analog bit scan process. At decision step 3006, it is determined whether the analog bit scan process passed, i.e., the number of memory cells that passed the verification was less than the predetermined threshold.

[0149] If the answer at decision step 3006 is "yes" (pass), the output of the analog bit scan process could be either a major pass or a minor pass. Fig. 31A illustrates an exemplary threshold voltage distribution of a marginal pass state where a small number of bits pass verification, but the number is less than the predetermined threshold. If the output of the analog bit scan operation is a marginal pass, in step 3008, the programming voltage VPGM is incrementally increased by a first increment dVPGM_SV1 (VPGM = VPGM + dVPGM_SV1), and the process then returns to step 3004 to begin another program loop.

[0150] Fig. 31B illustrates an exemplary threshold voltage distribution of a significant pass state where no or very few memory cells pass verification. If the output of the analog bit scan operation is a significant pass, in step 3007, the programming voltage VPGM is incrementally increased by a second step size dVPGM_SV2 (VPGM = VPGM + dVPGM_SV2), which is larger than the first step size dVPGM_SV1. The process then returns to step 3004 to begin another program loop. Thus, the selected word line WLn receives a stronger next VPGM pulse in response to a significant pass than in the case of a marginal pass.

[0151] If the answer at decision step 3006 is "no" (failed), the output of the analog bit scan operation could be either a minor fail or a major fail. Fig. Figure 31C illustrates the threshold distribution of a minor failure state where the number of existing bits barely exceeds the predetermined threshold. If the failure of the analog bit sampling operation is a minor failure, then in step 3010, the smart verification voltage SV_VPGM is set to the programming voltage VPGM.

[0152] Fig. Figure 31D illustrates the threshold voltage distribution of a clear fail condition where the number of existing bits greatly exceeds the predetermined threshold. If the output of the analog bit scan operation is a clear fail, in step 3012, the smart verify voltage SV_VPGM is set to a level lower than VPGM to avoid overprogramming in the other word lines. Specifically, the smart verify voltage SV_VPGM is set to VPGM - (1 / 2) * dVPGM. Since the step size dVPGM has been dynamically adjusted based on the output of the analog bit scan operation, in some embodiments, the SV_VPGM may be incremented by the result of dVPGM_SV * (Loops - 1).In one example, if an operation results in a significant pass for one loop, a marginal pass for two loops, and then a significant fail, SV_VPGM is set to VPGMU + 1 * dVPGM_SV2 + 2 * dVPGM_SV1 - (1 / 2) * dVPGM_SV1.

[0153] Following step 3010 or 3012, programming continues at step 3014 on the selected word line WLn until completed. Programming may then continue for the remaining chains of the selected word line WLn and / or additional word lines in the memory block while using SV_VPGM as the programming voltage in the first program loop.

[0154] As in Fig. As illustrated in Figures 31A-31D, according to these techniques, the smart verification programming voltage SV_VPGM is more accurately configured with only a single verification pulse at the low smart verification voltage Vsvl, meaning only one verification pulse is required in each of the smart verification loops. This improves performance by reducing programming time compared to using two verification pulses, one at a low smart verification voltage Vsvl and one at a high smart verification voltage Vsvh.

[0155] Furthermore, by increasing the programming voltage VPGM by a larger step size dVPGM_SV2 in response to the output of a significant pass, the smart verification voltage SV_VPGM can be obtained in fewer programming loops. In other words, the size of the step size dVPGM is dynamically adjusted based on the output of the analog bit sampling operation. However, in some embodiments, step 3007 may be skipped, and any pass (significant or marginal) at decision step 3006 may proceed to step 3008.

[0156] Fig. 32 is a flowchart 3200 illustrating the steps of programming a memory block or sub-block according to another embodiment of these intelligent verification techniques, using analog bit sampling and two intelligent verification voltages Vsvl, Vsvh to greatly improve SV_VPGM accuracy. These steps could be performed by the controller, a processor or processing device, or any other circuitry executing instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0157] At step 3202, the smart verification process begins by setting the program voltage VPGM to a predetermined initial voltage VPGMU. At step 3204, a program loop, including a program pulse followed by a verify process at a low smart verify voltage Vsvl, is performed on the selected word line WLn. The number of bits that passed the verification is then counted and compared to a predetermined threshold in an analog bit scan process. A loop count is also maintained at step 3204. At decision step 3206, it is determined whether the analog bit scan process passed, i.e., the number of passing bits was less than the predetermined threshold.

[0158] If the answer at decision step 3206 is "yes" (pass), the output of the analog bit scan operation could be either a major pass or a minor pass. If the output of the analog bit scan operation is a minor pass, in step 3208, the programming voltage VPGM is incrementally increased by a first increment dVPGM_SV1 (VPGM = VPGM + dVPGM_SV1), and the process then returns to step 3204 to begin another program loop.

[0159] If the output of the analog bit scan operation is a clear pass, in step 3207, the programming voltage VPGM is incremented by a second increment dVPGM_SV2 (VPGM = VPGM + dVPGM_SV2), which is greater than the first increment dVPGM_SV1. The process then returns to step 3204 to begin another program loop.

[0160] If the answer in decision step 3206 is "no" (failed), another program verification loop is performed in step 3210, but in this loop the verification voltage is the high smart verification voltage Vsvh.

[0161] At decision step 3212, it is determined whether the analog bit scan operation passed, i.e., the number of existing bits was less than the predetermined threshold. The output of this bit scan operation could be either a pass or a fail. If the output is a pass, then in step 3214, the smart verification voltage SV_VPGM is set to VPGM plus dVPGM_SV times Loops minus 1, i.e., SV_VPGM = VPGM + dVPGM_SV * (Loops - 1). Thus, in contrast to the embodiment of Fig. 30 the SV_VPGM in the embodiment of Fig. 32 to (Loops - 1). If the output fails, then in step 3216, the smart verification voltage SV_VPGM is set to the same value, but further reduced by half the step size, i.e., SV_VPGM = VPGM + dVPGM_SV * (Loops - 1) - (1 / 2) * dVPGM_SV. This minimizes the risk of overprogramming in the other chains and word lines of the memory block.

[0162] Following step 3214 or step 3216, programming of the memory cells of the selected word line WLn may continue in step 3218. Programming of the memory cells of other strings and / or word lines in the same memory block may use SV_VPGM as the programming voltage in the first program loop. In this embodiment, SV_VPGM is adjusted according to the number of marginal pass and major pass outputs at decision step 3206, and depending on whether the output during decision step 3212 is a pass or a fail.

[0163] This embodiment enables improved accuracy in setting SV_VPGM and improved performance by reducing the number of program loops required to complete the analog bit sampling for the low smart verify voltage Vsvl compared to other techniques using two smart verify voltages.

[0164] According to another embodiment shown in flowchart 3300 of Fig. As shown in Figure 33, the smart verification process includes verifying the low smart verification voltage Vsvl through a binary bit scan (the only output options are pass and fail), and then the analog bit scan process may be applied to verify at the high smart verification voltage Vsvh. These steps could be performed by the controller, a processor or processing device, or any other circuitry executing instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0165] In step 3302, the programming voltage VPGM is set to a predetermined initial programming voltage VPGMU. In step 3304, a program loop is performed on the selected word line WLn. During the verification portion of the program loop, the verification voltage is a low smart verification voltage Vsvl. In decision step 3306, it is determined whether the binary bit scan operation has passed, that is, the number of memory cells that have passed the verification is less than the predetermined threshold.

[0166] If the output in decision step 3306 is "pass," the programming voltage VPGM is incrementally increased in step 3308, i.e., VPGM = VPGM + dVPGM_SV. The process then returns to step 3304 to begin the next program loop. If the output in decision step 3306 is "fail," another program verification process is performed in step 3310, but this time the verification at Vsvl is skipped and the verification voltage is the high smart verification voltage Vsvh.

[0167] At decision step 3312, it is determined whether the analog bit scan operation passed. Four outputs are possible: major pass, marginal pass, marginal fail, and major fail. The output determines what voltage the intelligent verification programming voltage SV_VPGM is set to. If the output at decision step 3312 is a major pass, at step 3314 the intelligent verification programming voltage SV_VPGM is set to the programming voltage VPGM. If the output at decision step 3314 is a minor pass, at step 3316 the intelligent verification voltage SV_VPGM is set to VPGM reduced by one-quarter the step size dVPGM_SV, i.e., SV_VPGM = VPGM - (1 / 4)*dVPGM_SV.If the response in decision step 3312 is a minor failure, in step 3318, the smart verification voltage SV_VPGM is set to VPGM, reduced by one-half of the step size dVPGM_SV, i.e., SV_VPGM = VPGM - (1 / 2) * dVPGM_SV. If the response in decision step 3312 is a major failure, in step 3320, the smart verification voltage SV_VPGM is set to VPGM, reduced by three-quarters of the step size dVPGM_SV, i.e., SV_VPGM = VPGM - (3 / 4) * dVPGM_SV. In other embodiments, the specific voltage options could differ from those of the exemplary embodiment, with the size being decreased as the number of memory cells passing verification increases.

[0168] After step 3314, step 3316, step 3318, or step 3320, programming of the memory cells of the selected word line WLn may continue in step 3322. Programming of the memory cells of other chains and / or word lines in the same memory block may use SV_VPGM as the programming voltage in the first program loop.

[0169] According to another embodiment shown in flowchart 3400 of Fig. As shown in Figure 34, the resolution of the smart verification programming voltage SV_VPGM is further improved by performing analog bit sampling operations for both the low smart verification voltage Vsvl and the high smart verification voltage Vsvh. These steps could be performed by the controller, a processor or processing device, or any other circuitry that executes instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0170] In the embodiment of Fig. 34, steps 3402 to 3410 are respectively the same as steps 3302 to 3310, except that the analog bit sampling operation for the intelligent verification low voltage Vvsl is now an analog bit sampling operation instead of a binary bit sampling operation.

[0171] At decision step 3412, the analog bit scan operation has five possible outputs, enabling improved resolution of the intelligent verification voltage SV_VPGM. If the Vsvh analog bit scan operation of step 3412 produces a significant pass output and the Vsvl bit scan operation output at step 3406 was a minor fail, the intelligent verification programming voltage SV_VPGM is set to VPGM in step 3414. Fig. 35A illustrates a distribution of the threshold voltage Vt for an exemplary state with a significant pass output for Vsvh and a minor fail output for Vsvl.

[0172] If the Vsvh analog bit scan operation of step 3412 produces an output of a clear pass and the output of the Vsvl bit scan operation in step 3406 was a clear fail, the intelligent verify programming voltage SV_VPGM is set in step 3416 to VPGM reduced by one-quarter of the step size dVPGM_SV, ie, SV_VPGM = VPGM - 1 / 4 * dVPGM_SV. Fig. Figure 35B shows an example distribution of the threshold voltage Vt that could produce this result.

[0173] If the Vsvh analog bit scan operation of step 3412 produces a marginal pass output, then in step 3418 the smart verify programming voltage SV_VPGM is set to VPGM reduced by three-eighths of the step size dVPGM_SV, ie, SV_VPGM = VPGM - (3 / 8) * dVPGM_SV. Fig. Figure 35C shows an example distribution of the threshold voltage Vt that could produce this result.

[0174] If the analog bit sampling operation of step 3412 produces a minor fail output, then in step 3420 the intelligent verify programming voltage SV_VPGM is set to VPGM reduced by one-half the step size dVPGM_SV, ie, SV_VPGM = VPGM - 1 / 2 * dVPGM_SV. Fig. Figure 35D shows an example distribution of the threshold voltage Vt that could produce this result.

[0175] If the analog bit sampling operation of step 3412 produces a significant fail output, then in step 3422 the intelligent verify programming voltage SV_VPGM is set to VPGM reduced by three-quarters of the step size dVPGM_SV, ie, SV_VPGM = VPGM - ¾ * dVPGM_SV. Fig. Figure 35E shows an example distribution of the threshold voltage Vt that could produce this result.

[0176] In some embodiments, certain aspects of the embodiments of Fig. 30, Fig. 32, Fig. 33 and Fig. 34 into one process. For example, the dynamic step size dVPGM used in the embodiments of Fig. 30 and Fig. 32, either in the embodiment of the Fig. 33 or the embodiment of the Fig. 34 will be integrated.

[0177] Fig. 48 is a flowchart 4800 illustrating the steps of programming a memory block or sub-block according to another embodiment of these smart verification techniques, using analog bit sampling and two smart verification voltages Vsvl, Vsvh to prevent overprogramming during the smart verification process. These steps could be performed by the controller, a processor or processing device, or any other circuitry that executes instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0178] At step 4802, the program operation begins with the step of setting the program voltage VPGM to an initial level VPGMU to begin the intelligent verification operation. In step 4804, a program loop including both a VPGM pulse and a verification operation is performed on the selected word line WLn, and the number of memory cells passing the verification operation is counted and compared with a predetermined threshold in an analog bit scan operation. In this step, the verification operation is performed using the intelligent verification low voltage Vvsl. Furthermore, in step 4804, the number of program loops is counted.

[0179] At decision step 4806, it is determined whether the analog bit scan operation passed (the number of existing memory cells was less than the predetermined threshold). If the output at decision step 4806 is a pass, in step 4808, the programming voltage VPGM is incremented by an increment of dVPGM_SV, i.e., VPGM = VPGM + dVPGM_SV, and then the process returns to step 4804 to begin the next program loop.

[0180] If the output at decision step 4806 is "fail," then decision step 4810 determines whether the analog bit scan operation failure occurred during the first program loop. If the answer at decision step 4810 is "yes," and the analog bit scan operation output was a clear failure, the selected wordline WLn is at risk of overprogramming some of the memory cells that were intended for the first programmed data state, e.g., S1. In step 4812, the memory device logs the program operation as at risk of overprogramming. The remaining program operation for the selected wordline WLn is aborted, and programming continues with the next wordline to be programmed.

[0181] If the answer at decision step 4810 is "No" or "Yes" and the output of the analog bit scan operation was a minor failure, then the selected word line has a relatively lower risk of overprogramming and the process continues to step 4814. In step 4814, a verify operation is performed using the intelligent verify high voltage Vvsh.

[0182] At decision step 4816, it is determined whether the bit scan operation for the verify operation at the smart verify high voltage Vvsh passed (the number of existing memory cells was less than the predetermined threshold). If the output at decision step 4816 passed (the number of existing memory cells was less than the predetermined threshold), then in step 4818, the smart verify programming voltage SV_VPGM is set to VPGM. If the output at decision step 4816 fails, the smart verify programming voltage SV_VPGM is set to VPGM reduced by one-half the step size dVPGM_SV, i.e., SV_VPGM = VGPM - (1 / 2) * dVPGM_SV.

[0183] Following step 4818 or step 4820, the loop counter may be reset in step 4822, and then programming may continue to program the memory cells of the selected wordline WLn to their respective intended data states. The intelligent verification programming voltage SV_VPGM may then be used as the initial programming voltage when programming other strings of the selected wordline WLn and / or when programming other wordlines in the selected memory block.

[0184] This embodiment enables detection of overprogramming during programming so that the data intended for the selected word line WLn can be correctly programmed to another word line instead of being incorrectly programmed to the selected word line WLn.

[0185] Fig. 49 is a flowchart 4900 illustrating the steps of programming a memory block or sub-block according to yet another embodiment of these smart verification techniques, using analog bit sampling and two smart verification voltages Vsvl, Vsvh to prevent overprogramming during the smart verification process. These steps could be performed by the controller, a processor or processing device, or any other circuitry that executes instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0186] Steps 4902-4906 are similar to steps 4802-4808 of the previously described embodiment. However, if the output at decision step 4906 is a fail, the process proceeds to step 4910. At step 4910, the verification process is performed using the intelligent verification high voltage Vsvh, and the number of memory cells that pass the verification is counted in an analog bit scan process. Also at step 4910, the program loops are counted.

[0187] In decision step 4912, it is determined whether the analog bit scan operation passed, that is, the number of memory cells that passed the verification was less than a predetermined threshold. If the output in decision step 4912 is a pass (either a major pass or a minor pass), the intelligent verification programming voltage SV_VPGM is set to VPGM in step 4814.

[0188] If the output in decision step 4912 is a fail (either a major fail or a minor fail), then a determination is made at decision step 4916 as to whether the fail occurred in the first loop at decision step 4906. If the answer in decision step 4916 is "no" or "yes," and the output of the analog bit scan operation at decision step 4912 was also a minor fail, the risk of overprogramming is low, and the process continues to step 4918. In step 4918, the intelligent verification programming voltage SV_VPGM is set to VPGM - (1 / 2) * dVPGM_SV.

[0189] If the output in decision step 4916 is "Yes" and the output of the analog bit scan operation in decision step 4912 was also a clear failure, the risk of an overprogram is high. In step 4920, the intelligent verify program voltage SV_VPGM is set to VPGM - dVPGM_SV_OP, where dVPGM_SV_OP may be different from the step size dVPGM_SV. Also in step 4920, the overprogram status may be logged so that the memory device can take additional precautions before verifying the overprogram before completing the program operation.

[0190] After step 4914, 4918, or 4920, the loop counter is reset in step 4922 and the programming process continues to program all memory cells of the selected word line WLn to their respective intended data states.

[0191] As discussed above, in many program verification processes, the verification of each data state begins based on either a fixed program loop count or an intelligent PCV determination where fast-programming bits of a data state SN are detected to determine when to begin verification of the next data state or two data states, e.g., SN+1 and SN+2. Similarly, the verification of each data state can end when the number of slow bits is within a bit sampling criterion. The completion of each data state is detected sequentially. In other words, once verification for data state SN is complete, detection of data state SN+1 can begin, and so on. Fig. Figure 36 includes a table for an exemplary TLC programming operation, identifying which data states (S1-S7) are verified in which program loops (loops 1-12). In this table, a "0" indicates that verification is not performed for a given combination of program loop and data state, and a "1" indicates that verification is performed for a given combination of program loop and data state. In this example, a total of twenty-two (22) verification pulses are applied to the complete programming.

[0192] According to another aspect of the present disclosure, an analog bit scan operation is used to enable earlier completion of verification for each data state while still controlling slow bits to ensure they receive sufficient programming so that their threshold voltages Vt are above the respective verification voltages Vv. In other words, an early program verification completion parameter is set based on the output of an analog bit scan operation. By reducing the number of verification pulses performed, programming performance is improved with little or no loss of reliability.

[0193] The analog bit scan operation is performed after each verification pulse for one of the data states being verified in this loop. Depending on the results of the analog bit scan operation, programming to that particular data state may continue unchanged, programming to that data state may be terminated, or programming to that data state may continue for one or more program loops without verification. For example, the table illustrates Fig. 37 four options for a given data state SN based on the output of the analog bit scan operation. In this example, if the output of the analog bit scan operation for the data state SN is a clear failure (the failed bits significantly exceed the BSPF threshold), programming continues unchanged in the following program loop, i.e., the verification of the data state SN and all other data states being verified is performed. Fig. 39, curve 3900 illustrates the distribution of the threshold voltage Vt of a plurality of memory cells in a state of significant failure. If the output of the analog bit sampling operation for the data state SN is a minor failure (the failed bits barely exceed the BSPF threshold), then the verification of the data state SN ends. In the following two program loops, the unlocked memory cells are programmed to the data state SN, but there is no verification pulse of the data state SN after these programming pulses. These program loops with a programming pulse and no verification are hereinafter referred to as "dummy pulses." Fig. 39, curve 3902 illustrates the distribution of the threshold voltage Vt of a plurality of memory cells in a state of minor failure. If the output of the analog bit scan operation for the data state SN is a minor pass or a significant pass (the failed bits are less than the BSPF threshold), then the verification of the data state SN is terminated. In the following program loop, the unlocked memory cells that are programmed to the data state SN are programmed with a dummy pulse. Fig. 39, curve 3904 illustrates a distribution of the threshold voltage Vt of a plurality of memory cells in a pass state. As shown in the table of Fig. 38, in this example, by using the analog bit sampling process, one verification pulse is eliminated for each of the seven (7) data states, and a total of fifteen (15) verification pulses are performed. Thus, the performance is reduced compared to the twenty-two (22) verification pulses in the example of Fig. 36 significantly improved.

[0194] In some embodiments, the BSPF threshold can be adjusted to allow additional resolution (more possible outputs) for either a pass or a fail condition. For example, if the BSPF threshold is reduced to BSPF_Low, which is less than a base BSPF threshold, three possible failure options are available (minor failure, moderate failure, and significant failure) in addition to a single pass option. For example, Fig. Figure 40 illustrates a table of possible outputs for an analog bit scan operation where the BSPF threshold is set to a BSPF_Low level, and the associated action taken from each output option. In this example, in response to a significant fail output, programming continues unchanged in the following program loop. In response to a medium fail output, programming continues with three dummy pulses in the following three program loops to further program the slow bits, but by a lesser amount than the significant fail output. In response to a minor fail output, programming continues with two dummy pulses in the following two program loops to further program the slow bits, but by a lesser amount than the medium fail output.In response to a pass output, programming continues with a dummy pulse in the following program loop to further program the slow bits, but by a smaller amount than the minor fail output. In some embodiments, additional output options are possible. The lower BSPF threshold of this embodiment also enables improved performance by reducing bit scan operation time.

[0195] In the embodiment of Fig. 41, the BSPF threshold is set to BSPF_High, which is greater than the base BSPF threshold. In this embodiment, in addition to a single fail option, three possible pass options are available (minor pass, medium pass, and significant pass). In this example, programming continued unchanged in the following program loop in response to a fail output. In response to a minor pass output, programming then continues with three dummy pulses in the following three program loops to further program the slow bits. In response to a medium pass output, programming continues with two dummy pulses in the following two program loops to further program the slow bits, but by a lesser amount than the minor pass output.In response to a clear pass, programming continues with a dummy pulse in the following program loop to further program the slow bits, but by a smaller amount than the medium pass. In some embodiments, additional output options are possible.

[0196] The dummy pulses of the above exemplary embodiments may result in "Vt broadening," or a condition in which the threshold voltage Vt distributions for one or more of the data states are broadened. The threshold voltage Vt distributions can be fixed by verifying at two levels: a low verification level VL and a high verification level VH. When the threshold voltage Vt of a memory cell is detected as being between VL and VH, programming of that memory cell is nearly complete.Accordingly, on a subsequent programming pulse, a quick pass write (QPW) voltage is applied to a bit line coupled to that memory cell to slow down the programming of that memory cell so that it can be more accurately programmed to a threshold voltage Vt barely above the high verify level voltage VH, while other memory cells in the selected word line WLn can be programmed at high speed. Fig. Figure 42 illustrates the voltages applied to various components of a memory block during a programming pulse, where some of the memory cells have threshold voltages Vt between VL and VH and receive the QPW bias applied to their respective bit lines. The bit lines coupled to memory cells with threshold voltages Vt below VL receive a low VSS voltage.

[0197] According to an additional aspect of the present disclosure, an analog bit scan operation is performed after verification on the low verification level voltage VL and / or the high verification level voltage VH. The results of the analog bit scan operation(s) dictate whether programming occurs at full speed (no QPW bias) or at a reduced speed (with a QPW bias) in subsequent programming loops, as well as how many dummy pulses should follow.

[0198] In the table of Fig. 43, when the threshold voltage Vt of a memory cell is between the low verify level VL and the high verify level VH, the result of the analog bit scan operation determines how many dummy program pulses with the QPW bias should follow. For example, "Option 1" could be for a memory cell with a threshold voltage Vt much closer to the low verify level VL voltage than to the high verify level VH voltage, and requires four program pulses at the reduced speed to complete programming. "Option 4" could be for a memory cell with a threshold voltage Vt much closer to the high verify level VH voltage than to the low verify level VL voltage, and requires only a single program pulse at the reduced speed to complete programming.Options 2 and 3 can be between options 1 and 4.

[0199] Similarly, if the threshold voltage Vt of a memory cell is below the low verify level VL, the memory cell receives four dummy program pulses at appropriate programming speeds. For example, "Option 1" with four fast (VSS) dummy program pulses could be for a memory cell that has a threshold voltage Vt significantly below the low verify level voltage VL, and "Option 2" with one fast (VSS) and three slow (QPW) dummy pulses could be for a memory cell that has a threshold voltage Vt very close to the low verify level voltage VL.

[0200] Options 1-4 in the table of Fig. 43 may correspond to four possible options of the analog bit sampling operations discussed above. For example, option 1 may correspond to the output of a significant fail, option 2 may correspond to the output of a minor fail, option 3 may correspond to the output of a minor pass, and option 4 may correspond to the output of a significant pass. In some embodiments, there may be more or fewer than four options to correspond to more or fewer outputs of the analog bit sampling operation.

[0201] According to some additional embodiments, the output of the analog bit scan operation may be used to trigger an end of verification at the verify low VL voltage. If the output of the analog bit scan operation for the high verify level VH is a medium fail or a minor fail, performance gain may be achieved by ending verification at the low verify level VL voltage, i.e., by skipping the low verify level VL in subsequent program loops. If the output is a medium fail, then verification ends at the low verify level VL voltage only for the memory cells with threshold voltages Vt between the low verify level and high verify level voltages VL, VH.For memory cells with threshold voltages below the verify low voltage VL, the low VSS voltage is then applied to the bit lines coupled to those respective memory cells during subsequent VPGM pulses. Slow memory cells with threshold voltages Vt below the verify low voltage VL are still programmed in one or more subsequent program loops. The output of a minor fail can either produce the same output as the output of a medium fail, or verification can be set for both the low verify voltage and the high verify voltage VL, VH.

[0202] Another aspect of the present disclosure relates to an SLC programming technique in which an analog bit scan operation is implemented to improve performance. SLC programming is generally similar to TLC or QLC programming, as described above, in that programming occurs in one or more program loops, typically including a VPGM pulse and a verify operation. Timing-wise, the analog bit scan operation may occur as an independent operation; it may be partially or completely hidden at the end of the verify operation during discharge; or it may be partially or completely hidden at the beginning of a subsequent VPGM pulse means.

[0203] Fig. 44 includes a flowchart 4400 illustrating the steps of programming the memory cells of a selected word line WLn on SLC according to an exemplary embodiment of the present disclosure. These steps could be performed by the controller, a processor or processing device, or any other circuitry executing instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0204] In step 4402, the programming voltage VPGM is set to an initial voltage VPGMU. In step 4404, a VPGM pulse is applied to the selected word line WLn to program the non-locked memory cells of the selected word line WLn. After the VPGM pulse, a verify operation is performed to compare each memory cell being programmed to the verify voltage (there is only one verify voltage in SLC programming). In step 4406, an analog bit sampling operation is performed to compare the number of failed bits (memory cells that have not been verified) with a BSPF threshold.

[0205] At decision step 4408, it is determined whether the analog bit scan operation passed. If the output at decision step 4408 is a clear fail (the number of failed bits is significantly greater than the BSPF threshold), then in step 4410, the programming voltage VPGM is incrementally increased by an increment dVPGM, i.e., VPGM = VPGM + dVPGM. The process then returns to step 4404 to begin another program loop.

[0206] If the response in decision step 4408 is a minor failure (the number of failed bits is slightly greater than the BSPF threshold), then programming is almost complete. At step 4412, the programming voltage VPGM is incrementally increased (VPGM = VPGM + dVPGM), and a single VPGM pulse is applied to the selected word line WLn to continue programming the unlocked memory cells without a subsequent verify pulse.

[0207] After step 4412 or the output of a pass at decision step 4408, the programming operation is completed at step 4414. Programming may now move to a next word line in the memory block.

[0208] Fig. 45 includes a flowchart 4500 illustrating the steps of programming the memory cells of a selected word line WLn on SLC according to another exemplary embodiment of the present disclosure. These steps could be performed by the controller, a processor or processing device, or any other circuitry executing instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0209] In step 4502, the programming voltage VPGM is set to an initial voltage VPGMU. In step 4504, a VPGM pulse is applied to the selected word line WLn to program the non-locked memory cells of the selected word line WLn. After the VPGM pulse, a verify operation is performed to compare each memory cell being programmed to the verify voltage. In step 4506, an analog bit scan operation is performed to compare the number of failed bits (memory cells that have not been verified) with a BSPF threshold.

[0210] At decision step 4508, it is determined whether the analog bit scan operation passed. If the output at decision step 4508 is a significant fail (the number of failed bits is significantly greater than the BSPF threshold), then in step 4510, the programming voltage is increased by a first increment dVPGM_1, i.e., VPGM = VPGM + dVPGM_1. If the output at decision step 4508 is a minor fail (the number of failed bits is slightly greater than the BSPF threshold), then in step 4512, the programming voltage is increased by a second increment dVPGM_2, i.e., VPGM = VPGM + dVPGM_2. The second step size dVPGM_2 is smaller than the first step size dVPGM_1, so that the programming voltage VPGM increases by a smaller amount in response to the output of a minor failure of the analog bit sampling operation than in response to the output of a significant failure.

[0211] Following step 4510 or 4512, the process proceeds to step 4514 and a VPGM pulse is applied to the selected word line without subsequent verification operation.

[0212] After step 4514 or after a pass is issued at decision step 4508, the programming of the selected word line WLn is completed at step 4516.

[0213] In some embodiments, instead of adjusting the step size dVPGM, which depends on the output of the analog bit scan, another programming aspect may be adjusted. For example, in some embodiments, the programming clock (the time the VPGM pulse is held on the selected word line WLn) may be lengthened in response to the output of an analog bit scan with a significant miss and may be shortened in response to the output of an analog bit scan with a minor miss. In some other embodiments, the bit line voltage VBLC may also be adjusted to control the programming speed (e.g., see the discussion on QPW above) based on the output of the analog bit scan.

[0214] These SLC programming techniques can enable improved performance compared to conventional nPnV SLC programming operations, where each program loop includes both a VPGM pulse and a verify operation.

[0215] Another aspect of the present disclosure relates to the use of analog bit sampling in a programming technique sometimes known as STPFINE. In general, STPFINE involves automatically terminating the programming of a last data state (for example, data state S7 in the case of TLC, which is Fig. 9) after a predetermined number of program loops following completion of a previous data state (for example, data state S6) if verification fails before that point. That is, programming is complete even if data state S7 is not verified. As discussed in more detail below, the use of analog bit sampling allows certain variables to be dynamically optimized, for example, the number of program loops to perform after completion of the second to last data state and / or the programming voltage in these additional program loops. Dynamically optimizing these variables improved performance and / or reliability.

[0216] Fig. 46 includes a flowchart 4600 illustrating the steps of programming the memory cells of a selected word line WLn using an analog bit scan in a STPFINE operation. These steps could be performed by the controller, a processor or processing device, or any other circuitry that executes instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0217] At step 4602, the memory cells of the selected word line WLn are programmed to the data states S1 through SN-2 (where SN is the last data state to be programmed) in a plurality of program loops using an ISPP technique. In an exemplary embodiment in which the memory cells of the selected word line are programmed to TLC, the memory cells may be programmed to the data states S1-S5 in step 4602. Similarly, if the memory cells of the selected word line WLn are programmed to QLC, the memory cells are programmed to the data states S1-S13 in step 4602. In other words, the process moves to step 4604 only after passing the verification of the data state S5. At step 4604, another program loop is performed on the selected word line.The program loop includes a VPGM pulse, a verify operation, and an analog bit sampling operation for the data state SN-1 (e.g., S6 or S14) to compare a number of memory cells that fail verification to a BSPF threshold.

[0218] At decision step 4606, it is determined whether the analog bit scan operation passed. If the output at decision step 4606 is a fail, at step 4608 the programming voltage VPGM is incrementally increased by an increment dVPGM, i.e., VPGM = VPGM + dVPGM. The process then returns to step 4604 to begin another program loop. If the output at decision step 4606 is a marginal pass (the number of memory cells not verified is barely below the BSPF threshold), at step 4610, up to three additional program loops are performed on the selected word line WLn to further program the memory cells to the last data state SN (e.g., S7 or S15).If the output at decision step 4606 is a clear pass (the number of memory cells not verified is significantly below the BSPF threshold), then at step 4612, up to two additional program loops are performed on the selected word line WLn to further program the memory cells to the last data state SN (e.g., S7 or S15). The specific number of additional program loops for each of these outputs can be set to any suitable level.

[0219] In step 4610 or 4612, each program loop includes a VPGM pulse, a verify operation, and a bit scan operation for the data state SN. If verification occurs before the end of three program loops (in the case of step 4610) or two program loops (in the case of step 4612), programming completes early. However, after these additional program loops, programming is considered complete even if verification does not pass for the data state SN.

[0220] This embodiment allows the number of additional program loops to be performed after the program verification pass for state SN-1 to be dynamically determined based on how clearly the pass was. If the output of the analog bit scan operation was a marginal pass, the memory cells being programmed to the data state SN can receive more additional program loops to further program those memory cells than if the result was a clear pass.

[0221] In some embodiments, additional outputs or bins may be provided for the analog bit scan operation with different operations resulting from the different outputs. For example, in response to a significant pass output from the analog bit scan operation for data state SN-1, up to two additional program loops may be performed on the selected word line WLn; up to three additional program loops may be performed in response to a moderate pass output; and up to four additional program loops may be performed in response to a marginal pass output. One way to add bins to the analog bit scan operation is to tighten (or reduce) the BSPF threshold to add additional miss scenarios, as discussed above.

[0222] With reference to Fig.47, a flowchart 4700 is provided illustrating the steps of programming the memory cells of a selected wordline WLn using an analog bit scan in a STPFINE operation according to another embodiment of the present disclosure. These steps could be performed by the controller, a processor or processing device, or any other circuitry executing instructions stored in memory, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0223] In this embodiment, steps 4702-4708 are identical to steps 4602-4608 of the embodiment described above, but the analog bit sampling process is configured to provide four different output options (fail, marginal pass, moderate pass, and significant pass) instead of three output options as described above.

[0224] In response to a clear pass at decision step 4706, programming continues in step 4710 up to a predetermined number of program loops (e.g., up to three additional program loops), with the programming voltage VPGM increasing by a first increment dVPGM_1 between the additional program loops. In response to a medium pass at decision step 4706, programming continues in step 4712 up to a predetermined number of program loops, with the programming voltage VPGM increasing by a second increment dVPGM_2 between the additional program loops.In response to a marginal pass output at decision step 4706, at step 4714, programming continues up to a predetermined number of program loops, with the program voltage VPGM increasing by a third step size dVPGM_3 between the additional program loops.

[0225] In this embodiment, the third step size dVPGM_3 is larger than the second step size dVPGM_2, which is larger than the first step size dVPGM_1. Thus, the programming voltage VPGM increases more slowly for a significant pass because less additional programming is required, and increases more quickly for a marginal pass because more additional programming is required. In other words, the step size dVPGM is dynamically optimized during the additional program loops based on the results of the analog bit sampling operation for the data state SN-1.

[0226] In some embodiments, the step size dVPGM may be dynamically adjusted for only one or fewer than all additional program loops, rather than for all additional program loops, after verification of pass for data state SN-1.

[0227] In some further embodiments, certain aspects of both of these embodiments may be combined. For example, both the number of additional program loops performed after the pass verification for data state SN-1 and the step size dVPGM may be dynamically determined based on the results of the last bit scan operation for data state SN-1. In some embodiments, various programming parameters may be adjusted based on the results of the analog bit scan operation. For example, the program clock timing may be increased in response to the output of a marginal pass of the analog bit scan operation to further program the memory cells in subsequent additional program loops.In some other embodiments, the bias voltages applied to the unselected wordlines may be adjusted to increase or decrease the programming occurring in the additional program loops as desired. In some other embodiments, the bitline voltage VBLC may also be adjusted based on the output of the analog bit sensing operation to speed up or slow down the programming of a memory cell coupled to it.

[0228] Various terms are used to refer to particular system components. Different companies may refer to the same or similar component by different names, and this description does not intend to distinguish between components that differ in name but not in function. To the extent that various functional units described in the following disclosure are referred to as "modules," such characterization is not intended to unduly limit the range of possible implementation mechanisms. For example, a "module" could be implemented as a hardware circuit comprising custom-designed VLSI (Very Large Scale Integration) circuits or gate arrays, or off-the-shelf semiconductors incorporating logic chips, transistors, or other discrete components.In another example, a module may also be implemented in a programmable hardware device such as a field-programmable gate array (FPGA), programmable array logic, a programmable logic device, or the like. Furthermore, a module may also be implemented, at least in part, by software executed by various types of processors. For example, a module may comprise a segment of executable code containing one or more physical or logical blocks of computer instructions that translate into an object, process, or function. The executable portions of such a module are not required to be physically located together; they may comprise different instructions stored in different locations that, when executed together, comprise the identified module and fulfill the stated purpose of that module.The executable code may comprise a single instruction or a set of multiple instructions, but may also be distributed across different code segments or different programs, or across multiple storage devices, etc. In a software or partial software module implementation, the software sections may be stored on one or more computer-readable and / or executable storage media, including, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based system, device, or apparatus, or any suitable combination thereof.In general, for the purposes of the present disclosure, a computer-readable and / or executable storage medium may be any tangible and / or non-transitory storage medium capable of containing and / or storing a program for use by or in connection with an instruction execution system, device, processor, or apparatus.

[0229] Similarly, for the purposes of the present disclosure, the term "component" may include any tangible, physical, and non-transitory device. For example, a component may be in the form of a hardware logic circuit comprising custom VLSI circuits, gate arrays, or other integrated circuits, or it may be comprised of commercially available semiconductors including logic chips, transistors, or other discrete components, or other suitable mechanical and / or electronic devices. Furthermore, a component may also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc.Additionally, a component may include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices configured in an electrical communication configuration with one or more other components via electrical traces, e.g., on a printed circuit board (PCB) or the like. Accordingly, a module, as defined above, may be embodied by or implemented as a component in certain embodiments, and in some cases, the terms module and component may be used interchangeably.

[0230] When used herein, the term "circuit" includes one or more electrical and / or electronic components that form one or more conductive paths that allow electrical current to flow. A circuit can be configured as a closed-loop or open-loop configuration. In a closed-loop configuration, the circuit components can provide a return path for electrical current. In contrast, in an open-loop configuration, the circuit components can still be considered a circuit even if they do not include a return path for electrical current. For example, an integrated circuit can be referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return path for electrical current) or not.In certain example embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuits, gate arrays, logic circuits, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may include one or more silicon-based integrated circuit devices, such as chips, die, die planes, and packages, or other discrete electrical devices configured in an electrical communication configuration with one or more other components via electrical traces, for example, a printed circuit board (PCB).A circuit could also be implemented as a synthesized circuit with respect to a programmable hardware device such as a field-programmable gate array (FPGA), programmable array logic, and / or programmable logic devices, etc. In other exemplary embodiments, a circuit may comprise a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Accordingly, a module, as defined above, may be embodied by or implemented as a circuit in certain embodiments.

[0231] It should be understood that, in some examples, the embodiments disclosed herein may include one or more microprocessors and certain stored computer program instructions controlling the one or more microprocessors to, in conjunction with certain non-processor circuitry and other elements, implement some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions could be implemented by a state machine that does not have stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) in which each function, or some combination of certain functions, is implemented as custom logic. A combination of these approaches may also be used.Furthermore, subsequent references to a “controller” are defined to include individual circuit components, an application-specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a field-programmable gate array (FPGA), and / or a processor with control software, or combinations thereof.

[0232] Furthermore, the terms "couple," "coupled," or "couples," where used herein, are to be understood as either a direct or indirect connection. Thus, when a first device couples or is coupled to a second device, this connection may be through a direct connection or through an indirect connection via other devices (or components) and connections.

[0233] Regarding the use of phrases such as "one embodiment," "an embodiment," an "exemplary embodiment," "a particular embodiment," or similar terms, these terms are intended to indicate that a specific feature, structure, function, operation, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, phrases such as "in one embodiment," "in an embodiment," "in an exemplary embodiment," etc., may or may not refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless expressly stated otherwise.Furthermore, the terms "comprising," "having," "including," and variations thereof are used in an open-ended manner and should therefore be interpreted to mean "including, but not limited to," unless expressly stated otherwise. Furthermore, an element preceded by "comprises a" does not exclude, without further limitation, the existence of additional identical elements in the process, procedure, system, article, or facility in question that include the element.

[0234] The terms "a" and "the" also refer to "one or more" unless expressly stated otherwise. For example, "a processor" programmed to perform various functions refers to one processor programmed to perform each function individually, or more than one processor programmed together to perform each of the various functions. Furthermore, the phrase "at least one of A and B," as may be used herein and / or in the following claims, where A and B are variables indicating a particular object or attribute, indicates a selection of A or B, or both A and B, similar to the phrase "and / or."If there are more than two variables in such a formulation, that formulation is defined to include only one of the variables, any one of the variables, any combination (or subcombination) of any of the variables, and all of the variables.

[0235] Furthermore, the term "approximately" or "about" is applied herein to all numerical values, whether expressly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​(e.g., because they perform the same function or result). In certain cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0236] Furthermore, an enumeration of elements set forth herein does not imply that any or all of the listed elements are mutually exclusive and / or inclusive, unless expressly stated otherwise. Furthermore, the term "set," as used herein, shall be interpreted to mean "one or more," and in the case of "sets," it shall be interpreted to mean a multiple of (or a plurality of) "one or more" and / or "one or more" according to set theory, unless expressly stated otherwise.

[0237] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations are possible in light of the foregoing description. The described embodiments were chosen to best explain the principles of the technology and their practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the technology is defined by the claims appended hereto. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 524,015

[0001]

Claims

[1] A method for performing an erase operation in a memory device, comprising the steps of: Preparing a memory block including a plurality of memory cells arranged in a plurality of word lines, the plurality of word lines including a selected group of word lines to be erased; Erasing the memory cells of the selected group of word lines in at least one erase loop, wherein the at least one erase loop includes an erase pulse, an erase verify operation, and an analog bit scan operation; Determining an output of the analog bit sampling process, wherein the output is one of at least three options; and Setting at least one erase parameter based on the output of the analog bit sampling operation. [2] The method of claim 1, wherein the step of adjusting the at least one erasure parameter based on the output of the analog bit sampling operation includes: in response to the output of the analog bit scan operation being a first output option, increasing a voltage of the erase pulse by a first step size; and in response to the output of the analog bit sampling operation being a second output option, increasing the voltage of the erase pulse by a second step size different from the first step size. [3] The method of claim 2, wherein the step of adjusting the at least one erasure parameter based on the output of the analog bit sampling operation further includes: in response to the output of the analog bit scan operation being a third output option, terminating the erase operation. [4] The method of claim 3, wherein the first output option is a significant fail; the second output option is a minor fail or a minor pass; and the third output option is a significant pass. [5] The method of claim 4, wherein the second step size is approximately half of the first step size. [6] The method of claim 1, wherein the step of adjusting the at least one erasure parameter based on the output of the analog bit sampling operation includes: in response to the output of the analog bit scan operation being a first output option, increasing a voltage of the erase pulse by a first step size; and in response to the output of the analog bit scan operation being a second output option, increasing the voltage of the erase pulse by a second step size different from the first step size, and applying an additional erase pulse to the selected group of word lines. [7] The method of claim 6, wherein the step of adjusting the at least one erasure parameter based on the output of the analog bit sampling operation further includes: in response to the output of the analog bit scan operation being a third output option, terminating the erase operation. [8] The method of claim 6, wherein the first output option is a major failure, the second output option is a minor failure, and the third output option is a pass. [9] A storage device comprising: a memory block including a plurality of memory cells arranged in a plurality of word lines, the plurality of word lines including a selected group of word lines to be erased in the erase operation; Circuit logic configured to erase the memory cells of the selected group of word lines in at least one erase loop, the at least one erase loop including an erase pulse, an erase verify operation, and an analog bit sensing operation, the circuit logic configured to: Determining an output of the analog bit sampling process, wherein the output is one of at least three options, and Setting at least one erase parameter based on the output of the analog bit sampling operation. [10] The memory device of claim 9, wherein the circuit logic is further configured to: in response to the output of the analog bit scan operation being a first output option, increasing a voltage of the erase pulse by a first step size; and in response to the output of the analog bit sampling operation being a second output option, increasing the voltage of the erase pulse by a second step size different from the first step size. [11] The memory device of claim 10, wherein the circuit logic is further configured to: in response to the output of the analog bit scan operation being a third output option, terminating the erase operation. [12] The memory device of claim 11, wherein the first output option is a major fail; the second output option is a minor fail or a minor pass; and the third output option is a major pass. [13] The memory device of claim 12, wherein the second step size is approximately half the first step size. [14] The memory device of claim 9, wherein the circuit logic is further configured to: in response to the output of the analog bit scan operation being a first output option, increasing a voltage of the erase pulse by a first step size; and in response to the output of the analog bit scan operation being a second output option, increasing the voltage of the erase pulse by a second step size, which is different from the first step size, and applying an additional erase pulse to the selected group of word lines. [15] The memory device of claim 14, wherein the circuit logic is further configured to: in response to the output of the analog bit scan operation being a third output option, terminating the erase operation. [16] The memory device of claim 14, wherein the first output option is a major fail, the second output option is a minor fail, and the third output option is a pass. [17] Facility comprising: a memory block including a plurality of memory cells arranged in a plurality of word lines, the plurality of word lines including a selected group of word lines to be erased in the erase operation; an erase means for erasing the memory cells of the selected group of word lines in at least one erase loop, wherein the at least one erase loop includes an erase pulse, an erase verify operation and an analog bit scan operation, wherein the erase means is configured to: Determining an output of the analog bit sampling process, the output being one of at least three options comprising a significant fail, a minor fail, and a pass, Increasing a voltage of the erase pulse by a first step size in response to the output of the analog bit sampling operation being a clear failure, and Increasing the voltage of the erase pulse by a second step size in response to the output of the analog bit scan operation being a slight miss, wherein the second step size is different from the first step size. [18] The apparatus of claim 17, wherein the at least three options for outputting the analog bit sampling process further comprise a slight pass and a significant pass. [19] The apparatus of claim 18, wherein the erasing means is further configured to increase the voltage of the erasing pulse by the second step size in response to the output of the analog bit scan operation being a slight pass, and to terminate the erasing operation in response to the output of the analog bit scan operation being a clear pass. [20] The device of claim 17, wherein the erasing means is further arranged to apply an additional erase pulse to the selected group of word lines in response to the output of the analog bit scan operation being a minor failure.

Images