PIXEL STRUCTURES IN IMAGE SENSORS

Abstract

An optical device and a method for its fabrication are disclosed. The optical device comprises a first die layer and a second die layer. The first die layer comprises a first substrate with a first surface and a second surface opposite the first surface, a first and a second pixel structure, an interpixel insulating structure arranged in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region arranged in the first substrate and between the first and second pixel structures. The second die layer comprises a second substrate with a third surface and a fourth surface opposite the third surface, and a pixel transistor group arranged on the third surface of the second substrate and electrically connected to the first and second pixel structures.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 523,391, entitled "Layout for Multi-Layered Pixel Device," filed June 27, 2023, the disclosure of which is hereby incorporated by reference in its entirety. BACKGROUND

[0002] Image sensors are used to detect incoming visible or non-visible radiation, such as visible light and infrared light. Complementary metal-oxide-semiconductor image sensors (CMOS image sensors, CISs) and charge-coupled device (CCD) sensors are used in various applications, such as digital cameras, mobile phones, tablets, eyeglasses, and more. These image sensors use an array of pixel structures that absorb (i.e., detect) incoming radiation and convert it into electrical signals. One example of an image sensor is a back-illuminated image sensor (BSI) that detects radiation from the "back" of a BSI image sensor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. The Fig. 1A to 1G show different cross-sectional views of a BSI image sensor according to some embodiments. Fig. 2 is a flowchart of a method of manufacturing a BSI image sensor according to some embodiments. The Fig. 3 to 8 show cross-sectional views of a BSI image sensor at various stages of its manufacturing process according to some embodiments.

[0004] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate like, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the method of forming a first element over a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact. As used herein, forming a first element on a second element means forming the first element in direct contact with the second element.Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition does not, in itself, dictate any relationship between the various described embodiments and / or configurations.

[0006] Spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or section to one or more other elements or sections as shown in the figures. The spatially relative terms are intended to cover various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may be interpreted accordingly.

[0007] It should be noted that references in the specification to "a particular embodiment," "an embodiment," "an exemplary embodiment," "exemplary," etc., indicate that the described embodiment may include a particular element, structure, or characteristic, but not every embodiment necessarily includes that particular element, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, where a particular element, structure, or characteristic is described in connection with one embodiment, it is within the skill of those skilled in the art to make such an element, structure, or characteristic in connection with additional embodiments, whether expressly described or not.

[0008] It is to be understood that the phraseology or terminology used herein is for the purpose of description and not of limitation, insofar as the phraseology or terminology of the present application may be interpreted by one of ordinary skill in the relevant art(s) in light of the teachings herein.

[0009] In some embodiments, the terms "about" and "substantially" may refer to a value of a given quantity that varies within 5% of the value (e.g., +1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a range of percentage values ​​as interpreted by those skilled in the relevant art in light of the teachings contained herein.

[0010] A BSI image sensor includes an array of pixel structures (also referred to as "pixel units," "pixel cells," "pixel areas," and "pixels") on a first substrate of a first die layer. The pixel structures are configured to receive (or absorb) electromagnetic radiation (e.g., infrared radiation) projected onto a backside of the first substrate and to convert photons from the received radiation into electrical signals via pixel transistor groups on a second substrate of a second die layer bonded to the first die layer. Each pixel transistor group may include a source follower transistor, a row select transistor, and a reset transistor. The electrical signals are subsequently distributed to logic circuits on a third substrate of a third die layer bonded to the second die layer.

[0011] In the BSI image sensor, an interconnect layer is disposed on a front side of the first substrate, electrically connecting the pixel structures to the pixel transistor groups. Furthermore, color filters and microlenses are disposed on the back side of the first substrate to collect light with minimal or no obstruction by elements of the interconnect layer and / or the pixel structures. As a result, BSI image sensors exhibit improved low-light performance and higher quantum efficiency (QE) (e.g., the fraction of photons converted into electrons) than front-illuminated image sensors.

[0012] The present disclosure provides example structures of a BSI image sensor for improving sensor performance (e.g., increasing radiation sensitivity, increasing full well capacity, reducing capacitance, and / or reducing crosstalk between adjacent pixel structures) and reducing the manufacturing cost of the BSI image sensor. In some embodiments, the BSI image sensor may include dual radiation sensing device (RSD)-based pixel structures, each of which may include a first and a second RSD and may include no more than two RSDs. Both the first and second RSDs may have a rectangular radiation-sensing surface area.The rectangular radiation-sensing surface areas in each of the RSD-assisted dual-pixel structures can provide a larger radiation-sensing surface area than a similarly sized square RSD-assisted pixel structure with four RSDs with square radiation-sensing surface areas. As a result, the RSD-assisted dual-pixel structure can improve sensor performance (e.g., through increased radiation sensitivity and / or increased saturation charge) compared to the square RSD-assisted pixel structure.

[0013] In some embodiments, the BSI image sensor may further include interpixel isolation structures (also referred to as "interpixel deep trench isolation (DTI) structures") surrounding each pixel structure to reduce electrical and optical crosstalk between adjacent pixel structures. Furthermore, intrapixel isolation structures may be disposed between the first and second RSDs in each pixel structure to reduce electrical and optical crosstalk between the first and second RSDs of each pixel structure.

[0014] In some embodiments, each pair of adjacent pixel structures of the BSI image sensor may share a floating diffusion region and a pixel transistor group to reduce the manufacturing cost of the BSI image sensor compared to other BSI image sensors that have a separate floating diffusion region and pixel transistor group for each pixel structure. Furthermore, each floating diffusion region and each pair of adjacent pixel structures may be electrically connected to a corresponding pixel transistor group via a single metal conductive layer in the interconnect layer of the first die layer. Using a single metal conductive layer may further reduce the manufacturing cost of the BSI image sensor compared to other BSI image sensors that use multiple metal conductive layers to electrically connect the floating diffusion regions and pixel structures to corresponding pixel transistor groups.

[0015] Fig. 1A shows a vertical cross-sectional view of a BSI image sensor 100 (also referred to as “optical device 100”) along an XZ plane according to some embodiments. Fig. 1B and Fig. 1E show various horizontal cross-sectional views of the BSI image sensor 100 along the XY plane and along line AA of Fig. 1A. The Fig. 1C, Fig. 1D, Fig. 1F and Fig. 1G show various horizontal cross-sectional views of the BSI image sensor 100 along the XY plane and along line BB of Fig. 1A according to some embodiments. In some embodiments, Fig. 1A is a vertical cross-sectional view of the BSI image sensor 100 along the line CC of the Fig. 1B, Fig. 1C, Fig. 1E and Fig. 1F. The Fig. 1B to 1G show horizontal cross-sectional views of the BSI image sensor 100 with additional structures shown in Fig. 1A are not visible or are not shown for the sake of simplicity. The description of the elements in the Fig. 1A to 1G with the same labels also apply to the others, unless otherwise stated.

[0016] With reference to Fig. 1A, in some embodiments, the BSI image sensor 100 may include (i) a first die layer 102A, (ii) a second die layer 102B bonded to the first die layer 102A, and (iii) a third die layer 102C bonded to the second die layer 102B. In some embodiments, the first die layer 102A may include (i) a device layer 104A, (ii) an interconnect layer 104B, and (iii) a bond layer 104C.

[0017] With reference to the Fig. 1A to 1C, in some embodiments, the device layer 104A may include (i) a substrate 106 having a back surface 106B and a front surface 106F, (ii) an anti-reflective coating layer 108 disposed on the back surface 106B of the substrate 106, (iii) a dielectric layer 110 disposed on the anti-reflective coating layer 108, (iv) an interlayer dielectric (ILD) layer 112 disposed on the front surface 106F of the substrate 106, (v) pixel structures 114A-114D, (vi) floating diffusion regions 116A and 116B, (vii) an interpixel isolation structure 118, and (viii) metal grid structures 120. The ILD layer 112 is shown for simplicity in the Fig. 1B and Fig. 1C. The pixel structures 114B and 114D as well as the floating diffusion regions 116A and 116B are shown in Fig. 1A is not visible. Although in the Fig. 1A to 1C show four pixel structures 114A-114D, the BSI image sensor 100 may have any number of pixel structures.

[0018] In some embodiments, substrate 106 may include a semiconductor material such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and a combination thereof. Furthermore, substrate 106 may be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic).

[0019] In some embodiments, the anti-reflective coating layer 108 may be disposed on the backside surface 106B of the substrate 106 to prevent incident radiation from being reflected from the pixel structures 114A-114D. In some embodiments, the anti-reflective coating layer 108 may include a high-k dielectric such as hafnium oxide (HfO2), tantalum pentoxide (Ta2O3), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), and any other suitable high-k dielectric. In some embodiments, the dielectric layer 110 and the ILD layer 112 may include a dielectric such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or any other suitable dielectric. In some embodiments, the dielectric layer 110 and the ILD layer 112 may include the same dielectric or a different dielectric.

[0020] In some embodiments, each of the pixel structures 114A-114D may include (i) RSDs 122A and 122B (also referred to as "radiation detection regions 122A and 122B"), (ii) transfer gate structures 124A and 124B, (iii) an intrapixel isolation structure 126, (iv) a color filter 128, and (v) a microlens 130. The RSDs 122A and 122B may be disposed in the substrate 106. In some embodiments, the RSDs 122A and 122B may include an epitaxial semiconductor layer comprising silicon, germanium, silicon germanium, or other III-V semiconductor materials such as gallium arsenide, gallium phosphide, indium phosphide, and gallium nitride, depending on the radiation wavelength in question. For example, an epitaxial silicon layer may be used for visible light applications (e.g., between about 380 nm and about 740 nm), and an epitaxial germanium layer may be used for infrared applications (e.g., for wavelengths between about 940 nm and about 1550 nm).For wavelengths between visible and infrared radiation, an epitaxial silicon germanium layer may be used. In some embodiments, each of the RSDs 122A and 122B may include a photodiode. Top surfaces 123 of the RSDs 122A and 122B may be substantially coplanar with the front surface 106F of the substrate 106. Radiation-detecting surfaces 125 of the RSDs 122A and 122B face the back surface 106B of the substrate 106 and detect radiation entering through the back surface 106B of the substrate 106. The photons of the detected radiation may generate electron-hole pairs, which may subsequently be converted into electrical signals, as described in detail below.

[0021] Each of the pixel structures 114A-114D includes two RSDs 122A and 122B and includes no more than two RSDs. Therefore, the pixel structures 114A-114D may be referred to as RSD-assisted dual pixel structures 114A-114D. Both the top surfaces 123 and the radiation sensing surfaces 125 of the RSDs 122A and 122B may include a rectangular surface area. In some embodiments, the rectangular surface area may have a width W1 and a length L1 that is greater than the width W1. In some embodiments, the width W1 may be about 0.15 µm to about 2 µm, and the length L1 may be about 0.4 µm to about 4 µm. In some embodiments, a ratio of length L1 to width W1 (L1:W1) may be about 1.5 to about 3.Within these dimensional ranges of length L1 and width W1, the radiation sensing areas 125 can provide a surface area sufficient to detect the radiation entering through the back surface 106B of the substrate 106. Furthermore, within these dimensional ranges of length L1 and width W1, the radiation sensing areas 125 can provide larger detection areas and higher radiation detection sensitivity, as well as a larger saturation charge, than other BSI image sensors with square RSD-based pixel structures.

[0022] In some embodiments, transfer gate structures 124A may be disposed on the top surfaces 123 of the RSDs 122A and in the ILD layer 112. Furthermore, transfer gate structures 124B may be disposed on the top surfaces 123 of the RSDs 122B and in the ILD layer 112. Each of the transfer gate structures 124A and 124B may include a gate dielectric layer (not shown) disposed on the top surfaces 123 and a gate metal layer (not shown) disposed on the gate dielectric layer. In some embodiments, the gate dielectric layer may include a high-k dielectric such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium aluminum oxide (ZrAlO), zirconium silicate (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium zinc oxide (HfZnO), and yttrium oxide (Y2O3).In some embodiments, the gate metal layer may include a conductive material such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), nickel (Ni), metal alloys, and a combination thereof.

[0023] The transfer gate structures 124A and 124B may control the transfer of electrons from the RSDs 122A and 122B, respectively, to other elements of the BSI image sensor 100, as described in detail below. In some embodiments, no transistors other than the transfer gate structures 124A and 124B need to be disposed directly on the top surfaces 123 of the RSDs 122A and 122B. In some embodiments, the first die layer 102A may be free of other logic devices (e.g., logic transistors) other than the first and second transfer gate transistors 124A and 124B. In some embodiments, the first die layer 102A may not include any peripheral circuitry for signal processing of the BSI image sensor 100. The signal processing elements of the BSI image sensor 100 may be located in the second and / or third die layers 102B and 102C, as described below.Gate spacers (not shown) may be arranged on sidewalls of the transfer gate structures and may comprise an insulating material such as SiO2, SiN, SiON, silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and SiGeO. x contain.

[0024] In some embodiments, the intrapixel isolation structure 126 may be disposed in the substrate 106 and between the RSDs 122A and 122B. The intrapixel isolation structure 126 may extend horizontally to a length L2 along the elongated sides of the RSDs 122A and 122B, as shown in FIGS. Fig. 1B and Fig. 1C. In some embodiments, the intrapixel isolation structure 126 may extend vertically along a Z-axis from the front surface 106F to the back surface 106B of the substrate 106, as shown in Fig. 1A. In some embodiments, a top surface of the intrapixel isolation structure 126 may be substantially coplanar with the front surface 106F of the substrate 106, and a bottom surface of the intrapixel isolation structure 126 may be substantially coplanar with the back surface 106B of the substrate 106. In some embodiments, the top surface of the intrapixel isolation structure 126 may contact the ILD layer 112, and the bottom surface of the intrapixel isolation structure 126 may contact the anti-reflective coating layer 108. In some embodiments, the intrapixel isolation structures 126 may be formed by extended portions of the interpixel isolation structure 118. In some embodiments, the intrapixel isolation structures 126 need not contact the interpixel isolation structure 118 (as shown in FIGS. Fig. 1B and Fig. 1C), but may be separated from the interpixel isolation structure 118 by a portion of the substrate 106 (not shown).

[0025] In some embodiments, the intrapixel isolation structure 126 may have a height H2 that is greater than the height H1 of each of the RSDs 122A and 122B. In some embodiments, the length L2 of the intrapixel isolation structure 126 may be less than or equal to the length L1 of each of the RSDs 122A and 122B. In some embodiments, a ratio between the lengths L1 and L2 (L1:L2) may be about 1:0.5 to about 1:1. Within this range of relative dimensions, the intrapixel isolation structure 126 may sufficiently prevent or minimize electrical and optical crosstalk between the RSDs 122A and 122B, thus improving the quantum efficiency of the pixel structures 114A-114D. In some embodiments, the intrapixel isolation structure 126 may include SiO2, SiN, SiON, HfO2, Al2O3, or any other suitable high-k dielectric.

[0026] In some embodiments, the color filter 128 may be disposed within the dielectric layer 110, and the top surface of the color filter 128 may be substantially coplanar with the top surface of the dielectric layer 110. In some embodiments, each color filter 128 may overlap the entire radiation-detecting areas 125 of the underlying RSD pair 122A and 122B in each of the pixel structures 114A-114D. In some embodiments, the color filter 128 may include a polymer material. In some embodiments, the microlens 130 may be disposed on the color filter 128, and each microlens may overlap the entire radiation-detecting areas 125 of the underlying RSD pair 122A and 122B in each of the pixel structures 114A-114D.

[0027] The floating diffusion regions 116A and 116B (also referred to as “floating diffusion nodes 116A and 116B”) may be arranged in the substrate 106 and need not overlap the RSDs 122A and 122B, as shown in the Fig. 1B and Fig. 1C. In some embodiments, floating diffusion regions 116A and 116B need not overlap intrapixel isolation structures 126 and interpixel isolation structures 118 in the XZ and YZ planes. In some embodiments, floating diffusion regions 116A and 116B may include doped regions disposed in substrate 106. In some embodiments, the doped regions may include n-type dopants when substrate 106 includes p-type dopants.

[0028] The floating diffusion region 116A may be arranged in a substrate region between the pixel structures 114A and 114B, and the floating diffusion region 116B may be arranged in a substrate region between the pixel structures 114C and 114D, as shown in the Fig. 1B and Fig. 1C. With such an arrangement of the floating diffusion regions 116A and 116B, the function of a floating diffusion region can be shared by two pixel structures of the BSI image sensor 100, rather than having a floating diffusion region for each pixel structure, as in other BSI image sensors. In other words, the floating diffusion region 116A can store charges (e.g., electrons) transferred through the transfer gate structures 124A and 124B from the RSDs 122A and 122B, respectively, of the pixel structures 114A and 114B. In addition, the floating diffusion region 116B can store charges (e.g., electrons) transferred through the transfer gate structures 124A and 124B from the RSDs 122A and 122B, respectively, of the pixel structures 114C and 114D. Thus, the total number of floating diffusion regions can be half the number of pixel structures in the BSI image sensor 100.By reducing the number of floating diffusion regions in the BSI image sensor 100, the floating diffusion capacitance in the BSI image sensor 100 can be reduced and consequently the conversion gain of the BSI image sensor 100 can be increased.

[0029] In some embodiments, the interpixel isolation structure 118 may be disposed in the substrate 106 and surround each pair of RSDs 122A and 122B. In some embodiments, portions of the interpixel isolation structure 118 may extend laterally between the pixel structures 114A and 114B and between the pixel structures 114C and 114D, as shown in FIGS. Fig. 1B and Fig. 1C. In some embodiments, the extended portions may have a length L3 that may be less than or equal to the width W1 of each of the RSDs 122A and 122B. In some embodiments, a ratio between the lengths W1 and L3 (W1:L3) may be about 1:0.5 to about 1:1. In some embodiments, a cross-section of the interpixel isolation structure 118 along an XY plane has a rectangular perimeter or ring around the pixel structures 114A and 114B and around the pixel structures 114C and 114D, as shown in FIGS. Fig. 1B and Fig. 1C. In some embodiments, a cross-section of the interpixel isolation structure 118 along an XY plane has a rectangular perimeter or ring around the pixel structures 114A, 114B, 114C, and 114D, as shown in FIGS. Fig. 1B and Fig. 1C. In some embodiments, a cross-section of the interpixel isolation structure 118 along an XZ plane includes a vertical structure separating the pixel structures 114A and 114C, as shown in Fig. 1A. The upper surface of the vertical structure may contact the ILD layer 112 and the lower surface of the vertical structure may contact the anti-reflective coating layer 108, as shown in Fig. 1A shown.

[0030] In some embodiments, the interpixel isolation structure 118 may extend vertically along a Z-axis from the front surface 106F to the back surface 106B of the substrate 106, as shown in Fig. 1A. In some embodiments, a top surface of the interpixel isolation structure 118 may be substantially coplanar with the front surface 106F of the substrate 106, and a bottom surface of the interpixel isolation structure 118 may be substantially coplanar with the back surface 106B of the substrate 106. In some embodiments, the top surface of the interpixel isolation structure 118 may contact the ILD layer 112, and the bottom surface of the interpixel isolation structure 118 may contact the anti-reflective coating layer 108. In some embodiments, the interpixel isolation structure 118 may have a height H3 that is greater than the height H1 of each of the RSDs 122A and 122B. Within these ranges of relative dimensions, the interpixel isolation structure 118 can sufficiently prevent or minimize electrical and optical crosstalk between the pixel structures 114A-114D, thus improving the quantum efficiency of the pixel structures 114A-114D.In some embodiments, the interpixel isolation structure 118 may include SiO2, SiN, SiON, HfO2, Al2O3, or any other suitable high-k dielectric.

[0031] In some embodiments, the metal grid structures 120 may be disposed in the dielectric layer 110, between adjacent color filters 128, and on the interpixel isolation structure 118. In some embodiments, for ease of manufacturing, the metal grid structures 120 may be separated from the interpixel isolation structure 118 by a distance of about 100 nm to about 300 nm along a Z-axis. The metal grid structures 120 may minimize or prevent crosstalk between the pixel structures 114A-114D.

[0032] With reference to the Fig. 1A and Fig. 1C, the interconnect layer 104B may be disposed on the front surface 106F of the substrate 106 and electrically connect elements of the device layer 104A to elements of the second die layer 102B. In some embodiments, the interconnect layer 104B may include a single metal line layer M1 and two via layers V1 and V2 disposed in an inter-metal dielectric (IMD) layer 136A (for simplicity, Fig. 1C not shown). By using a single metal conductive layer M1, the manufacturing cost of the BSI image sensor 100 can be reduced compared to other BSI image sensors with multiple metal conductive layers. In some embodiments, the metal conductive layer M1 can include metal lines 132A-132C, the via layer V1 can include conductive vias 134V1, and the via layer V2 can include conductive vias 134V2.

[0033] In some embodiments, the metal lines 132A may be electrically connected to the transfer gate structures 124A via the vias 134V1, the metal lines 132B may be electrically connected to the transfer gate structures 124B, and the metal lines 132C may be electrically connected to the floating diffusion regions 116A and 116B. The layout of the metal lines 132A-132C and the conductive vias 134V1 and 134V2 is exemplary and not limiting, and other layout variations of the metal lines 132A-132C and the conductive vias 134V1 and 134V2 are within the scope of this disclosure. In some embodiments, the metal lines 132A and 132B may extend over the RSDs 122A and 122B, respectively, as shown in Fig. 1C with solid lines, or they may extend over both the RSDs 122A and 122B and the intrapixel isolation structures 126, as in Fig. 1C with dashed lines. In some embodiments, the elongated sides of metal lines 132A and 132B may be perpendicular to the elongated sides of RSDs 122A and 122B.

[0034] With reference to Fig. 1A, the bond layer 104C may be disposed on the interconnect layer 104B and may include a dielectric layer 138A and metal pads 138B disposed within the dielectric layer 138A. The bond layer 104C may connect the first die layer 102A to the second die layer 102B and may establish electrical connections between elements of the first die layer 102A and elements of the second die layer 102B via the metal pads 138B. In some embodiments, the metal pads 138B may include copper, and the dielectric layer 138A may include SiO2, SiN, SiC, SiON, SiCN, or any other suitable dielectric.

[0035] With reference to Fig. 1A, in some embodiments, the second die layer 102B may include (i) a front-side bond layer 140A, (ii) a front-side interconnect layer 140B, (iii) a device layer 140C, (iv) a back-side interconnect layer 140D, and (v) a back-side bond layer 140E.

[0036] The front-side bonding layer 140A may be disposed on the front-side interconnect layer 140B and may include a dielectric layer 142A and metal pads 142B disposed in the dielectric layer 142A. In some embodiments, the metal pads 142B may include copper, and the dielectric layer 142A may include SiO2, SiN, SiC, SiON, SiCN, or any other suitable dielectric. The bonding layer 140A may be bonded to the bonding layer 104C, with dielectric-to-dielectric bonds formed between the dielectric layers 142A and 142A and metal-to-metal bonds formed between the metal pads 142B and 142B at the bonding interface 139, as shown in Fig. 1A. Electrical connections between elements of the first die layer 102A and elements of the second die layer 102B can be made via the metal pads 138B and 142B.

[0037] The front-side interconnect layer 140B may be disposed on the device layer 140C and electrically connect elements of the device layer 140C to elements of the first die layer 102A. In some embodiments, the interconnect layer 140B may include multiple metal line layers including metal lines 144M1 and 144M2 and multiple via layers including conductive vias 146V1-146V3 disposed within an IMD layer 136B. The layout and number of the metal lines 144M1 and 144M2 and the conductive vias 146V1-146V3 are exemplary and non-limiting, and other layout variations of the metal lines 144M1 and 144M2 and the conductive vias 146V1-146V3 are within the scope of this disclosure.

[0038] In some embodiments, device layer 140C may include (i) a substrate 148 having a back surface 148B and a front surface 148F, (ii) an ILD layer 150 disposed on the front surface 148F of substrate 148, (iii) silicon vias (TSVs) 152, and (iv) pixel transistor groups 154A and 154B disposed on the front surface 148F of substrate 148. In some embodiments, substrate 148 may include a semiconductor material similar to or different from that of substrate 106. In some embodiments, ILD layer 150 may include a dielectric similar to or different from that of ILD layer 112. In some embodiments, TSVs 152 may extend vertically through device layer 140C and electrically connect front-side interconnect layer 140B to back-side interconnect layer 140D.

[0039] In some embodiments, each of the pixel transistor groups 154A and 154B may include pixel transistors, for example, (i) a source follower transistor (SF transistor) 156A, (ii) a row select transistor (RS transistor) 156B, and (iii) a reset transistor (RST transistor) 156C. The pixel transistor group 154A may be electrically connected to the transfer gate structures 124A and 124B of the pixel structures 114A and 114B and the floating diffusion region 116A and configured to convert the detected photons from the pixel structures 114A and 114B into electrical signals. Similarly, the pixel transistor group 154B may be electrically connected to the transfer gate structures 124A and 124B of the pixel structures 114C and 114D and the floating diffusion region 116B and configured to convert the detected photons from the pixel structures 114C and 114D into electrical signals.With such an arrangement of pixel transistor groups 154A and 154B with pixel structures 114A-114D, the function of each pixel transistor group can be shared by two pixel structures of the BSI image sensor 100, rather than having one pixel transistor group for each pixel structure as in other BSI image sensors. Thus, the total number of pixel transistor groups can be half the number of pixel structures in the BSI image sensor 100. By reducing the number of pixel transistor groups in the BSI image sensor 100, the manufacturing cost of the BSI image sensor 100 can be reduced compared to other BSI image sensors.

[0040] During an example operation of the BSI image sensor 100, the transfer gate structures 124A and 124B of the pixel structure 114A may be selectively turned on to transfer photon-generated electrons from the RSDs 122A and 122B of the pixel structure 114A into the floating diffusion region 116A. The electrons in the floating diffusion region 116A may be converted into electrical signals by the SF transistor 156A of the pixel transistor group 154A, which is electrically connected to the floating diffusion region 116A via the metal lines 132C, 144M1, and 144M2, the conductive vias 134V2 and 146V1-146V3, and the metal pads 138B and 142B. The RS transistor 156B can select the electrical signals to be read by readout circuits in the third die layer 102C. The RST transistor 156C can be turned on to reset the floating diffusion region 116A by removing the transferred electrons.The reset operation may be followed by selectively turning on the transfer gate structures 124A and 124B of the pixel structure 114B to transfer electrons from the RSDs 122A and 122B of the pixel structure 114B into the previously emptied floating diffusion region 116A. Subsequent processing of the transferred electrons may be performed with the pixel transistor group 154A as described above. A similar example operation may be performed with the pixel transistor group 154B to convert the photon-generated electrons in the pixel structures 114C and 114D into electrical signals.

[0041] With reference to Fig. 1A, the backside interconnect layer 140D may be disposed on the backside surface 148B of the substrate 148 and may include conductive vias 146B disposed in a dielectric layer 136C. The conductive vias 146B may electrically connect the TSVs to elements of the third die layer 102C. In some embodiments, the backside bond layer 140E may be disposed on the backside interconnect layer 140D and may include a dielectric layer 158A and metal pads 158B disposed in the dielectric layer 158A. In some embodiments, the metal pads 158B may include copper, and the dielectric layer 158A may include SiO2, SiN, SiC, SiON, SiCN, or any other suitable dielectric.The bond layer 140E may bond the second die layer 102B to the third die layer 102C and may establish electrical connections between elements of the second die layer 102B and elements of the third die layer 102C via the metal pads 158B.

[0042] With reference to Fig. 1A, the third die layer 102C may, in some embodiments, include (i) a bond layer 160A, (ii) an interconnect layer 160B, and (iii) a device layer 160C. The bond layer 160A may be disposed on the interconnect layer 160B and may include a dielectric layer 162A and metal pads 162B disposed within the dielectric layer 162A. In some embodiments, the metal pads 162B may include copper, and the dielectric layer 162A may include SiO2, SiN, SiC, SiON, SiCN, or any other suitable dielectric. The bond layer 160A may be bonded to the bond layer 140E, with dielectric-dielectric bonds formed between the dielectric layers 162A and 158A and metal-metal bonds formed between the metal pads 162B and 158B at the bond interface 159, as shown in Fig. 1A. The electrical connections between elements of the second die layer 102B and elements of the third die layer 102C can be made via the metal pads 158B and 162B.

[0043] The interconnect layer 160B may be disposed on the device layer 160C and electrically connect elements of the device layer 160C to elements of the second die layer 102B. In some embodiments, the interconnect layer 160B may include multiple metal line layers including metal lines 164M1 and 164M2 and multiple via layers including conductive vias 166V1-166V3 disposed within an IMD layer 136D. The layout and number of the metal lines 164M1 and 164M2 and the conductive vias 166V1-166V3 are exemplary and non-limiting, and other layout variations of the metal lines 164M1 and 164M2 and the conductive vias 166V1-166V3 are within the scope of this disclosure.

[0044] In some embodiments, device layer 160C may include (i) a substrate 168 having a back surface 168B and a front surface 168F, (ii) an ILD layer 170 disposed on the front surface 168F of substrate 168, and (iii) devices 172 disposed on the front surface 168F of substrate 168. In some embodiments, substrate 168 may include a semiconductor material similar to or different from that of substrate 106. In some embodiments, ILD layer 170 may include a dielectric similar to or different from that of ILD layer 112.In some embodiments, devices 172 may include application-specific integrated circuits (ASICs) such as analog-to-digital converters (ADCs), counters, memory devices, and combinations thereof for processing electrical signals generated by pixel transistor groups 154A and 154B in second die layer 102B.

[0045] With reference to Fig. 1D, in some embodiments, the BSI image sensor 100 may include pixel structures 114E-114H (in Fig. 1A not shown). The BSI image sensor may include floating diffusion regions 116C and 116D in addition to floating diffusion regions 116A and 116B. The description of pixel structures 114A-114D applies to pixel structures 114E-114H, respectively, and the description of floating diffusion regions 116A and 116B applies to floating diffusion regions 116C and 116D, respectively, unless otherwise noted. In some embodiments, the directional arrangement of pixel structures 114E-114H may differ from the directional arrangement of pixel structures 114A-114D. For example, the elongated sides of the RSDs 122A and 122B and the intrapixel isolation structures 126 of the pixel structures 114E-114H may be perpendicular to the elongated sides of the RSDs 122A and 122B and the intrapixel isolation structures 126 of the pixel structures 114A-114D.In some embodiments, pixel structures 114E and 114F may share the functions of floating diffusion region 116C and a pixel transistor group (not shown), and pixel structures 114G and 114H may share the functions of floating diffusion region 116D and another pixel transistor group (not shown).

[0046] With reference to the Fig. 1E and Fig. 1F, in some embodiments, the BSI image sensor 100 may include floating diffusion regions 117A-117D instead of the floating diffusion regions 116A and 116B. The floating diffusion regions 117A-117D may be disposed in the substrate 106 and need not overlap the RSDs 122A and 122B. In some embodiments, the floating diffusion regions 117A-117D in the XZ and YZ planes need not overlap the intrapixel isolation structures 126 and the interpixel isolation structures 118. In some embodiments, the floating diffusion regions 117A-117D may include doped regions disposed in the substrate 106. In some embodiments, the doped regions may contain n-type dopants when the substrate 106 contains p-type dopants.

[0047] The floating diffusion region 117A may be arranged in a substrate region between the RSDs 122A and 122B of the pixel structure 114A, the floating diffusion region 117B may be arranged in a substrate region between the RSDs 122A and 122B of the pixel structure 114B, the floating diffusion region 117C may be arranged in a substrate region between the RSDs 122A and 122B of the pixel structure 114C, and the floating diffusion region 117D may be arranged in a substrate region between the RSDs 122A and 122B of the pixel structure 114D. With such an arrangement of the floating diffusion regions 117A-117D, the floating diffusion regions 117A-117D can each store electrons transferred from the pixel structures 114A-114D. In some embodiments, the floating diffusion regions 117A and 117B can be electrically connected to a common metal line 132C (in Fig. 1F), which in turn may be electrically connected to the SF transistor 156A of the pixel transistor group 154A as described above. Similarly, the floating diffusion regions 117C and 117D may be electrically connected to a common metal line 132C (see Fig. 1F), which in turn may be electrically connected to the SF transistor 156A of the pixel transistor group 154B.

[0048] With reference to Fig. 1G, in some embodiments, the BSI image sensor 100 may include, in addition to the pixel structures 114A-114D of Fig. 1F pixel structures 114E-114H (in Fig. 1A not shown). The BSI image sensor 100 may, in addition to the floating diffusion regions 117A-117D of Fig. 1F may have further floating diffusion regions 117E-117H. The description of pixel structures 114A-114D applies to pixel structures 114E-114H, respectively, and the description of floating diffusion regions 117A-117D applies to floating diffusion regions 117E-117H, respectively, unless otherwise stated. In some embodiments, the directional arrangement of pixel structures 114E-114H may differ from the directional arrangement of pixel structures 114A-114D. For example, the elongated sides of the RSDs 122A and 122B and the intrapixel isolation structures 126 of the pixel structures 114E-114H may be perpendicular to the elongated sides of the RSDs 122A and 122B and the intrapixel isolation structures 126 of the pixel structures 114A-114D.In some embodiments, floating diffusion regions 117E and 117F may be electrically connected to a common metal line 132C, which in turn may be electrically connected to an SF transistor of a pixel transistor group (not shown). Similarly, floating diffusion regions 117G and 117H may be electrically connected to a common metal line 132C, which in turn may be electrically connected to another SF transistor of another pixel transistor group (not shown).

[0049] Fig. 2 is a flowchart of an example method 200 for manufacturing a BSI image sensor 100 according to some embodiments. For description purposes, the Fig. 2 will be described with reference to the exemplary manufacturing method for manufacturing the BSI image sensor 100 as shown in the Fig. 3 to 8. The Fig. 3 to 8 are vertical cross-sectional views of the BSI image sensor 100 at various stages of fabrication according to some embodiments. The operations may be performed in a different order or omitted depending on the application. It should be noted that method 200 does not require the fabrication of a complete BSI image sensor 100. Accordingly, it should be understood that additional processes may be provided before, during, and after method 200, and that some further processes may only be briefly described here. The description of elements in the Fig. 1A to 1G and 3 to 8 with the same reference numerals also apply to the others, unless otherwise stated.

[0050] With reference to Fig. 2, at operation 205, a first die layer is formed including RSDs, transfer gate structures, a first interconnect layer, and a first bond layer. As described with reference to Fig. 3, for example, the first die layer 102A is formed with the RSDs 122A and 122B, the transfer gate structures 124A and 124B, the interconnect layer 104B and the bond layer 104C. In some embodiments, the formation of the first die layer 102A may include the sequential operations of: (i) forming the RSDs in the substrate 106, (ii) forming the transfer gate structures 124A and 124B on the front surface 106F of the substrate 106, (iii) depositing the ILD layer 112 on the front surface 106F of the substrate 106, (iv) forming the conductive vias 134V1 of the interconnect layer 104B, (v) forming the metal lines 132A-132C of the interconnect layer 104B, (vi) forming the conductive vias 134V2 of the interconnect layer 104B, (vii) depositing the dielectric layer 138A of the bond layer 104C on the interconnect layer 104B, and (viii) forming the metal pads 138B in the dielectric layer 138A.

[0051] With reference to Fig. 2, at operation 210, a second die layer is formed with pixel transistor groups, a second interconnect layer, and a second bond layer. As described with reference to Fig. 4, for example, the second die layer 102B is formed with the pixel transistor groups 154A and 154B, the interconnect layer 140B and the bond layer 140A.In some embodiments, the formation of the second die layer 102B may include the sequential operations of: (i) forming the pixel transistor groups 154A and 154B on the front surface 148F of the substrate 148, (ii) depositing the ILD layer 150 on the front surface 148F of the substrate 148, (iii) forming the conductive vias 146V1 of the interconnect layer 140B, (iv) forming the metal lines 144M1 of the interconnect layer 140B, (v) forming the conductive vias 146V2 of the interconnect layer 140B, (vi) forming the metal lines 144M2 of the interconnect layer 140B, (vii) forming the conductive vias 146V3 of the interconnect layer 140B, (viii) depositing the dielectric layer 142A of the bonding layer 140A on the interconnect layer 140B; and (ix) forming the metal pads 142B in the dielectric layer 142A.

[0052] With reference to Fig. 2, at operation 215, a bonding process is performed between the first and second die layers. As described with reference to Fig. 5, for example, a bonding process is performed between the first and second die layers 102A and 102B. In some embodiments, performing the bonding process may include the sequential operations of: (i) performing an activation process with a plasma (e.g., hydrogen plasma) on the upper surfaces of the bonding layers 104C and 140A, (ii) bringing together the metal pads 138B of the bonding layer 104C and the corresponding metal pads 142B of the bonding layer 140A, and (iii) performing an annealing process at a melting temperature of the material of the metal pads 138B and 142B such that the structure of Fig. 5 is trained.

[0053] With reference to Fig. 2, process 220 forms TSVs, a third interconnect layer, and a third bond layer of the second die layer. As described with reference to Fig. 6, for example, the TSVs 152, the interconnect layer 140D, and the bond layer 140E of the second die layer are formed. In some embodiments, the TSVs 152 may be formed extending vertically through the substrate 148 and the ILD layer 150, followed by the formation of the conductive vias 146B on the TSVs 152. The formation of the conductive vias 146B may be followed by the formation of the bond layer 140E, which may include the sequential operations of: (i) depositing the dielectric layer 158A on the interconnect layer 140D and (ii) forming the metal pads 158B in the dielectric layer 158A.

[0054] With reference to Fig. 2, at operation 225, a third die layer is formed with devices, a fourth interconnect layer, and a fourth bond layer. As described with reference to Fig. 7, for example, the third die layer 102C is formed with the devices 172, the interconnect layer 160B and the bond layer 160A.In some embodiments, the formation of the third die layer 102C may include the sequential operations of: (i) forming the devices 172 on the front surface 168F of the substrate 168, (ii) depositing the ILD layer 170 on the front surface 168F of the substrate 168, (iii) forming the conductive vias 166V1 of the interconnect layer 160B, (iv) forming the metal lines 164M1 of the interconnect layer 160B, (v) forming the conductive vias 166V2 of the interconnect layer 160B, (vi) forming the metal lines 164M2 of the interconnect layer 160B, (vii) forming the conductive vias 166V3 of the interconnect layer 160B, (viii) depositing the dielectric layer 162A of the bond layer 160A on the interconnect layer 160B and (ix) forming the metal pads 162B in the dielectric layer 162A.

[0055] With reference to Fig. 2, at operation 230, a bonding process is performed between the second and third die layers. As described with reference to Fig. 7, for example, a bonding process is performed between the die layers 102B and 102C. In some embodiments, performing the bonding process may include the sequential operations of: (i) performing an activation process with a plasma (e.g., hydrogen plasma) on the upper surfaces of the bonding layers 140E and 160A, (ii) bringing together the metal pads 158B of the bonding layer 140E and the corresponding metal pads 162B of the bonding layer 160A, and (iii) performing an annealing process at a melting temperature of the material of the metal pads 158B and 162B such that the structure of Fig. 7 is trained.

[0056] With reference to Fig. 2, in process 235, insulating structures, color filters, grating structures, and microlenses of the first die layer are formed. As with reference to Fig. For example, as described in Figure 8, the interpixel isolation structures 118, the intrapixel isolation structures 126, the color filters 128, the metal grid structures 120, and the microlenses 130 of the first die layer 102A are formed. In some embodiments, the interpixel isolation structures 118 and the intrapixel isolation structures 126 may be formed simultaneously through the backside surface 106B of the substrate 106.In some embodiments, the formation of the interpixel isolation structures 118 and the intrapixel isolation structures 126 may comprise the sequential operations of: (i) performing a thinning process on the backside surface 106B of the substrate 106, (ii) etching the substrate 106 through the backside surface 106B to form trenches (not shown) in the substrate 106, (iii) depositing a dielectric layer (not shown) in the trenches, and (iv) performing a chemical mechanical polishing (CMP) process on the deposited dielectric layer such that the interpixel isolation structures 118 and the intrapixel isolation structures 126 are formed as shown in FIG. Fig. 8 are shown.

[0057] The formation of the interpixel isolation structures 118 and the intrapixel isolation structures 126 may be followed by deposition of the anti-reflective coating layer 108 on the backside surface 106B of the substrate 106, which may be followed by deposition of a dielectric layer 110 on the anti-reflective coating layer 108. The metal grid structures 120 and the color filters 128 may be formed in the dielectric layer 110, which may be followed by formation of the microlenses 130 on the color filters 128.

[0058] The present disclosure provides example structures of a BSI image sensor (e.g., BSI image sensor 100) for improving sensor performance (e.g., increasing radiation sensitivity, increasing saturation charge, reducing capacitance, and / or reducing crosstalk between adjacent pixel structures) and reducing the manufacturing cost of the BSI image sensor. In some embodiments, the BSI image sensor may include dual pixel structures based on radiation sensing devices (RSDs) (e.g., pixel structures 114A-114H), each of which may include a first and a second RSD (e.g., RSDs 122A and 122B) and may include no more than two RSDs. Both the first and second RSDs may include a rectangular radiation-sensing surface area (e.g., radiation sensing areas 125).The rectangular radiation-sensing surface areas in each of the RSD-assisted dual-pixel structures can provide a larger radiation-sensing surface area than a similarly sized square RSD-assisted pixel structure with four RSDs with square radiation-sensing surface areas. As a result, the RSD-assisted dual-pixel structure can improve sensor performance (e.g., through increased radiation sensitivity and / or increased saturation charge) compared to the square RSD-assisted pixel structure.

[0059] In some embodiments, the BSI image sensor may further include interpixel isolation structures (e.g., interpixel isolation structures 118) surrounding each pixel structure to reduce electrical and optical crosstalk between adjacent pixel structures. Furthermore, intrapixel isolation structures (e.g., intrapixel isolation structures 126) may be disposed between the first and second RSDs within each pixel structure to reduce electrical and optical crosstalk between the first and second RSDs of each pixel structure.

[0060] In some embodiments, each pair of adjacent pixel structures of the BSI image sensor may share a floating diffusion region (e.g., floating diffusion regions 116A and 116B) and a pixel transistor group (e.g., pixel transistor groups 154A and 154B) to reduce the manufacturing cost of the BSI image sensor compared to other BSI image sensors that have a separate floating diffusion region and pixel transistor group for each pixel structure. Furthermore, each floating diffusion region and each pair of adjacent pixel structures may be electrically connected to a corresponding pixel transistor group via a single metal conductive layer (e.g., metal conductive layer M1 of interconnect layer 104B) in an interconnect layer.By using a single metal conductive layer, the manufacturing cost of the BSI image sensor can be further reduced compared to other BSI image sensors that use multiple metal conductive layers to electrically connect the floating diffusion regions and pixel structures to corresponding pixel transistor groups.

[0061] In some embodiments, an optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite the first surface, first and second pixel structures, an interpixel isolation structure disposed in the first substrate, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. A first cross-section of the interpixel isolation structure along a first plane includes a rectangular perimeter around the first and second pixel structures, and a second cross-section of the interpixel isolation structure along a second plane includes a vertical structure separating the first and second pixel structures.The second die layer comprises a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.

[0062] In some embodiments, an optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite the first surface, a first pixel structure including first and second radiation sensing devices, a first floating diffusion region disposed in the first substrate and between the first and second radiation sensing devices, a second pixel structure including third and fourth radiation sensing devices, a second floating diffusion region disposed in the first substrate and between the third and fourth radiation sensing devices, and an interconnect layer including a first metal line disposed on the second surface of the first substrate.The first metal line is electrically connected to the first and second floating diffusion regions. The second die layer includes a second substrate having a third surface and a fourth surface opposite the third surface, and a pixel transistor array disposed on the substrate and electrically connected to the first metal line.

[0063] In some embodiments, a method comprises forming a first die layer with radiation sensing devices in a first substrate, a first interconnect layer on the radiation sensing devices, and a first bond layer on the first interconnect layer. Each of the radiation sensing devices has a rectangular cross-sectional profile along a horizontal plane. The method further comprises forming a second die layer with pixel transistors on a second substrate, a second interconnect layer on the pixel transistors, and a second bond layer on the second interconnect layer, performing a bonding process between the first and second die layers, and forming an isolation structure surrounding the radiation sensing devices.

[0064] The above disclosure describes features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should recognize that they can readily use the present disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 523 391

[0001]

Claims

[1] Optical device comprising: a first die layer comprising: a first substrate having a first surface and a second surface opposite to the first surface; a first and a second pixel structure; an interpixel isolation structure disposed in the first substrate, wherein: a first cross-section of the interpixel isolation structure along a first plane has a rectangular perimeter around the first and second pixel structures, and a second cross-section of the interpixel isolation structure along a second plane has a vertical structure separating the first and second pixel structures; and a floating diffusion region disposed in the first substrate and between the first and second pixel structures; and a second die layer comprising: a second substrate having a third surface and a fourth surface opposite to the third surface; and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures. [2] The optical device according to claim 1, wherein the first pixel structure comprises: a first and a second radiation detection device in the first substrate; and an intrapixel isolation structure disposed in the first substrate and between the first and second radiation detection devices. [3] The optical device according to claim 2, wherein the intrapixel isolation structure extends vertically from the first surface of the first substrate to the second surface of the first substrate. [4] The optical device according to claim 2 or 3, wherein a height of the intrapixel isolation structure is greater than a height of the first radiation detection device. [5] An optical device according to any preceding claim, wherein the first pixel structure comprises first and second radiation detection devices in the first substrate; and wherein each of the first and second radiation detection devices has a rectangular cross-sectional profile along a horizontal plane. [6] An optical device according to any preceding claim, wherein the first and second pixel structures comprise transfer gate structures electrically connected to a transistor in the pixel transistor group. [7] An optical device according to any preceding claim, wherein the floating diffusion region is electrically connected to a transistor in the pixel transistor group. [8] An optical device according to any preceding claim, wherein the floating diffusion region is configured to store charges transferred from the first and second pixel structures. [9] An optical device according to any preceding claim, wherein the interpixel isolation structure extends vertically from the first surface of the first substrate to the second surface of the first substrate. [10] Optical device according to one of the preceding claims, further comprising: a first bonding layer disposed on the second surface of the first substrate; a second bonding layer disposed on the third surface of the second substrate; and a third bonding layer disposed on the fourth surface of the second substrate. [11] Optical device comprising: a first die layer comprising: a first substrate having a first surface and a second surface opposite to the first surface; a first pixel structure having first and second radiation detection devices; a first floating diffusion region disposed in the first substrate and between the first and second radiation detection devices; a second pixel structure having third and fourth radiation detection devices; a second floating diffusion region disposed in the first substrate and between the third and fourth radiation detection devices; and an interconnect layer having a first metal line disposed on the second surface of the first substrate, the first metal line being electrically connected to the first and second floating diffusion regions; and a second die layer comprising: a second substrate having a third surface and a fourth surface opposite to the third surface; and a pixel transistor group arranged on the substrate and electrically connected to the first metal line. [12] The optical device of claim 11, further comprising an insulating structure disposed in the first substrate, wherein a top surface of the insulating structure is substantially coplanar with the first surface of the first substrate and a bottom surface of the insulating structure is substantially coplanar with the second surface of the first substrate. [13] An optical device according to claim 11 or 12, wherein each of the first and second radiation detecting devices has a rectangular cross-sectional profile along a horizontal plane. [14] An optical device according to any one of claims 11 to 13, wherein the pixel transistor group comprises a source follower transistor, a reset transistor and a row select transistor. [15] The optical device of any one of claims 11 to 14, wherein the interconnect layer further comprises second and third metal lines; and wherein the second metal line is electrically connected to the first pixel structure and the third metal line is electrically connected to the second pixel structure. [16] The optical device of claim 15, wherein the second and third metal lines are electrically connected to another pixel transistor in the second die layer. [17] Method comprising: Forming a first die layer having radiation detection devices in a first substrate, a first interconnect layer on the radiation detection devices, and a first bond layer on the first interconnect layer, each of the radiation detection devices having a rectangular cross-sectional profile along a horizontal plane; Forming a second die layer having pixel transistors on a second substrate, a second interconnect layer on the pixel transistors, and a second bond layer on the second interconnect layer; Performing a bonding process between the first and second die layers; and Forming an insulating structure surrounding the radiation detection devices. [18] The method of claim 17, wherein forming the insulating structure comprises forming the insulating structure with upper and lower surfaces that are substantially coplanar with the first and second surfaces of the first substrate, respectively. [19] The method of claim 17 or 18, wherein forming the first die layer further comprises forming a further isolation structure in the first substrate and between the radiation detection devices. [20] The method of claim 17, 18 or 19, wherein forming the first die layer further comprises forming a floating diffusion region between the radiation sensing devices.

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