Packages with various power switches and power consumer circuits separated into these.

Abstract

A method comprises forming a first device die and a second device die. The first device die has a first integrated circuit and a first bond pad on a first surface of the first device die. The first integrated circuit is electrically connected to the first bond pad. The second device die has a power switch comprising a first source / drain region, a second source / drain region, a second bond pad that makes an electrical connection to the first source / drain region, and a third bond pad that makes an electrical connection to the second source / drain region. The method further comprises bonding the first device die to the second device die to form a package, wherein the first bond pad is bonded to the third bond pad, and bonding the package to a package component.

Description

PRIORITY CLAIM AND CROSS REFERENCEThis application claims priority to the following filed U.S. Provisional Patent Application: Application No. 63 / 517,381, filed August 3, 2023, entitled "CHIPLET POWER SWITCHES," which is incorporated herein by reference.BACKGROUNDHeader cells (power switches) are used in integrated circuits for "power gating" the power supplied to particular circuits. A header cell may include a transistor whose source may be connected to a power node such as VDD. The drain may be used as another power node whose voltage is determined by whether the transistor is on or off. When the header cell is on, the drain receives the power and the circuit is thus powered. When the header cell is off, no power is supplied to the circuit.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIGS. 1-5 show the cross-sectional views of intermediate stages in the formation of a package including a power switch and a power consumer circuit separated into different dies, in accordance with some embodiments. FIGS. 6-11 show the cross-sectional views of intermediate stages in the formation of a package including a power switch and a power consumer circuit separated into different dies, in accordance with some embodiments. FIGS. 12 and 13 show the cross-sectional views of packages including power switches and corresponding power consumer circuits separated into different dies, in accordance with some embodiments. FIG. 14 illustrates a process flow for forming a package including a power switch and a power consumer circuit separated into different dies, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Concrete examples of components and arrangements will be described below in order to simplify the present disclosure. These are, of course, merely examples and should not be understood as limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not automatically prescribe a relationship between the various embodiments and / or configurations discussed.Further, for convenience of description, spatially relative terms such as "underlying", "below", "lower / r / s", "overlying", "upper / r / s", and the like may be used in this document to describe the relationship of one element or feature to (another) element(s) or feature(s) as depicted in the figures. The spatially relative terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used in this document may likewise be interpreted accordingly.Provided are a package having a power switch and a power consumer circuit separated into different dies and the method of forming the same. According to some embodiments of the present disclosure, a first device die is configured to include a power switch and a second device die is configured to include a power consumer circuit. The first device die is bonded to the second device die such that the power switch in the first device die supplies power to the power consumer circuit and controls that power. By arranging the power switch in the first device die and not in the second device die that includes the power consumer circuit of the power, the chip area of the second device die that includes sophisticated circuits and is thus greatly used is saved. Embodiments discussed in this document are intended to provide examples to enable the manufacture or use of the subject matter of this disclosure, and modifications that can be made without departing from the intended scope of protection of various embodiments will readily occur to one of ordinary skill in the art. Throughout the several views and illustrative embodiments, like reference numerals are used to identify like elements. Although embodiments of methods may have been discussed as being performed in a particular order, other embodiments of methods may be performed in any logical order.FIGS. 1-5 show the cross-sectional views of intermediate stages in the formation of a package including a power switch and a power consumer circuit, in accordance with some embodiments of the present disclosure. The corresponding processes are also schematically illustrated in the process flow 200 illustrated in FIG. 14.FIG. 1 illustrates the formation of a device wafer 20 in accordance with some embodiments. The corresponding process is depicted as process 201 in process flow 200 depicted in FIG. 14. The device wafer 120 is also formed. The corresponding process is depicted as process 202 in process flow 200 depicted in FIG. 14. The wafer 20 may have multiple device dies 20' therein. The wafer 120 may have multiple device dies 120' therein. According to some embodiments, wafer 120 has circuits and a different configuration from those of wafer 20. In some embodiments, wafer 20 includes input / output (I / O) circuits, memory circuits (such as dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, or the like. The wafer 120 may include logic circuits such as a central processing unit (CPU), a graphics processing unit (GPU), or the like.In some embodiments, wafer 120 is manufactured using a more sophisticated technology (which may be newer) than wafer 20. For example, wafer 20 may be an undeveloped wafer that may be formed from 10 nm technology or an older technology, while wafer 120 may be an sophisticated wafer that may be fabricated using 7 nm technology or a newer technology. The critical dimensions (the widths of the gates) of the transistors in wafer 120 are thus less than the critical dimensions of the transistors in wafer 20.According to some embodiments, the wafer 20 includes a semiconductor substrate 24 and the elements formed on the upper surface of the semiconductor substrate 24. The semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon doped silicon, a III-V compound semiconductor, or the like. The semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.In accordance with some embodiments, wafer 20 includes IC devices 26 formed on the top surface of semiconductor substrate 24. In some embodiments, the IC devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and / or the like. The details of the IC devices 26 are not illustrated in this document.An interlayer dielectric (ILD) 28 is formed over the semiconductor substrate 24 and fills the spaces between the gate stacks of transistors (not shown) in the IC devices 26. According to some embodiments, the ILD 28 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), fluorine doped silicate glass (FSG), silicon oxide, silicon oxynitride, silicon nitride, or the like. The ILD 28 may be formed by spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), or the like.Contact plugs 30 are formed in the ILD 28 to electrically connect IC devices 26 to overlying metal lines 44 and vias 46. According to some embodiments, contact plugs 30 are formed from or include: a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.FIG. 1 further illustrates a header cell 32 (alternatively referred to as a power switch), in accordance with some embodiments. The power switch 32 may include a transistor, which may include a source region 34, a drain region 36, and a gate 38. The source region 34 and the drain region 36 are collectively referred to as source / drain regions. The power switch 32 has the function of receiving power (referred to as true VDD (TVDD)) at the source region 34, which is alternatively referred to as TVDD node. The drain region 36 is referred to as a virtual VDD (VVDD) node that receives the power when the power switch 32 is turned on and is disconnected from the power when the power switch 32 is turned off. The power at the VVDD node 36 is provided to a power consumer circuit in the device die 120', as discussed in subsequent paragraphs.An interconnect structure 42 is formed over the ILD 28 and the contact plug 30. The interconnect structure 42 may include metal lines 44 and vias 46 formed in dielectric layers 48 (also referred to as inter-metal dielectrics (IMDs)). The metal lines 44 at a same level will hereinafter be collectively referred to as a metal layer. In some embodiments, the interconnect structure 42 includes a plurality of metal layers interconnected by vias 46. The metal lines 44 and the vias 46 may be formed from copper, a copper alloy, and / or another metal. In accordance with some embodiments, the dielectric layers 48 are formed of low-k dielectrics. The dielectric constants (k-values) of the low-k dielectrics may be, for example, less than about 3.5 or less than about 3.0. The dielectric layers 48 may include a low-k carbonaceous dielectric.In some embodiments, the formation of metal lines 44 and vias 46 may include single damascene or dual damascene techniques. According to some embodiments, the formation of a bottom metal layer (including the metal lines 44) may be performed by a single damascene process including depositing a dielectric layer 48, etching the dielectric layer 48 to form trenches, filling the trenches with conductive materials, and thereafter performing a planarization process, such as a CMP process, to remove excess portions of the conductive materials. The overlying metal lines and vias may be formed using dual damascene techniques including forming dielectric layers, forming via openings and trenches in the dielectric layers, filling the via openings and trenches with conductive materials, and performing planarization processes.Over the interconnect structure 42 may be / may be provided (a) passivation layer(s) (not specifically shown) that may be / may be formed of a non-low-k dielectric over the low-k dielectric layers. The passivation layer may be formed of or include: undoped silicate glass (USG), silicon nitride, silicon oxide or the like, or multilayers thereof. Metal pads (e.g., aluminum copper pads), post passivation interconnect (PPI), or the like may also be present.A bond film 54 is deposited over the interconnect structure 42. The upper surface of the bonding film 54 is coplanar. According to some embodiments, the bond film 54 may be formed of a silicon-based dielectric material, which may be formed of or include: SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like.Bond pads 56 are formed in the bond film 54 to provide electrical connection to the power switch 32 and the integrated circuits 26. The bond pads 56 may have top surfaces that are coplanar with the top surface of the bond film 54, which may be achieved by a planarization process. According to some embodiments, the bond pads 56 are formed in a damascene process, including etching the bond film 54 to form openings, filling the openings with (a) conductive material(s), and performing the planarization process.FIG. 1 also shows the formation of the wafer 120. According to some embodiments, wafer 120 has layers similar to those of wafer 20. The structures and materials of the elements in wafer 120 can be found by reference to the similar elements in wafer 20, with the similar elements in wafer 120 being identified by adding the numeral "1" prior to the reference numerals of the corresponding elements in wafer 20. For example, the substrate in wafer 20 is identified by reference numeral 24, and accordingly, the substrate in wafer 120 is identified by reference numeral 124. Wafer 120 may include IC devices 126, an ILD 128, contact plugs 130, an interconnect structure 142, dielectric layers 148, metal lines 144, and vias 146. Further, the wafer 120 includes a bonding film 154 and bonding pads 156 in the bonding film 154. The details of these elements may be similar to the corresponding elements in wafer 20 and will not be described again herein.In some embodiments, wafer 120 includes integrated circuits 126 further including active devices and passive devices therein to form the functional circuits. The integrated circuits 126 may include integrated circuits 126A, integrated circuits 126B, and integrated circuits 126C. In some embodiments, integrated circuits 126A continuously receive power (e.g., TVDD) during operation thereof. Integrated circuits 126C, on the other hand, are the power consumer circuits that receive as consumers of power the "gated" ("gated") voltage VVDDfrom device die 20'. Accordingly, depending on whether the power switch 32 is turned on or off, the integrated circuits 126C may be powered or not powered. The integrated circuits 126B may be a control circuit that provides a control signal to control whether the power switch 32 is turned on or off and provides control signals to control whether the power consumer circuits 126C receive the power or not.According to some embodiments, vias 127 (alternatively, silicon vias (TSVs) or semiconductor vias (also referred to as TSVs)) are formed in the wafer 120. The vias 127 extend from the top surface to an intermediate level between the top surface and the bottom surface of the semiconductor substrate 124. The top ends of the vias 127 may extend to the top surface of the ILD 128. Alternatively, the top ends of the vias 127 may be at any available level, such as the level of the top surface of the semiconductor substrate or a level of the top surface of any of the dielectric layers 148.In accordance with some embodiments, such as those illustrated in FIGS. 1-4, the packaging process is a through via first process in which the vias 127 are formed prior to bonding the wafer 20 to the wafer 120. According to alternative embodiments, a through via load process may be applied to form the vias 127 such that the vias are formed after the wafer bonding process. An example through via load process according to some embodiments is illustrated in FIGS. 8 and 9.Referring to FIG. 2, therein the wafer 20 is upside down and bonded to the wafer 120 to form the composite wafer 68. The corresponding process is depicted as process 204 in the process flow 200 depicted in FIG. 14. Bonding may be implemented by hybrid bonding, which includes direct metal-to-metal bonding of the bond pads 56 to the bond pads 156 and fusion bonding (e.g., with Si-O-Si bonds formed) of the bond film 54 to the bond film 154. According to alternative embodiments, wafers 20 and 120 may be bonded by solder bonding, direct metal-to-metal (metal) bonding, or the like. In the illustrated example, bonding is face-to-face ("face-to-face") bonding in which the front side (the end face) of the wafer 20 is bonded to the front side of the wafer 120. Arrows 33 on the right side of FIG. 2 are shown facing each other to illustrate face-to-face bonding. The front side is that side of the respective semiconductor substrate which has integrated circuits formed.According to some embodiments, wafer-to-wafer bonding is performed to bond wafer 20 to wafer 120 and, consequently, device die 20' to device die 120'. According to alternative embodiments, bonding may be through die wafer bonding, where single dies 20' are bonded to a wafer 120, or die bonding, where a single die 20' is bonded to a single die 120'.FIG. 3 shows a back side thinning process for thinning the semiconductor substrate 124 from the back side thereof. The corresponding process is depicted as process 206 in process flow 200 depicted in FIG. 14. The back side thinning process may be performed by a chemical mechanical polishing (CMP) process or a mechanical grinding process. According to some embodiments, the back side thinning process is stopped after the vias 127 are exposed from the back side of the semiconductor substrate 124.Next, the semiconductor substrate 124 may be recessed from the back side so that, as illustrated in FIG. 4, some end portions of the vias 127 protrude from the semiconductor substrate 124. Then, a dielectric layer 160 is formed to surround and contact the protruding portions of the vias 127, as also shown in FIG. 4. According to some embodiments, the formation of the dielectric layer 160 includes depositing a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like to embed the protruding portions of the vias 127 therein. A slight planarization process is then performed to remove excess portions of the dielectric layer and revisibly visualize the vias 127. Thus, the remaining portions of the dielectric material form the dielectric layer 160.Next, a back side interconnect structure including a dielectric layer 162 and metal pads 164 is formed. The corresponding process is depicted as process 208 in process flow 200 depicted in FIG. 14. The formation process may include depositing a metallic layer, for example, an aluminum layer, an aluminum-copper layer, a nickel layer, a titanium layer, and / or the like, and then patterning the metallic layer to form the metal pads 164. Then, the dielectric layer 162 is deposited. Alternatively, the dielectric layer 162 may be deposited first, followed by forming the metal pads 164 in the dielectric layer 162 by a damascene process. It will be appreciated that although a metal layer (the layer of metal pads 164) is illustrated, the back side interconnect structure may include multiple metal layers for back side routing of electrical signals / voltages.Electrical connectors 166 are then formed. In some embodiments, electrical connectors 166 include metal flakes, solder regions, and / or the like. The electrical connectors 166 may include electrical connectors (power bumps) 166A and 166B discussed in subsequent paragraphs.In a subsequent process, the composite wafer 68 illustrated in FIG. 4 may be singulated, for example, in a die-saw process, such that multiple identical packages 68' are formed as individual packages. The corresponding process is depicted as process 210 in process flow 200 depicted in FIG. 14. The wafers 20 and 120 in the composite wafer 68 are also singulated into device dies 20' and device dies 120', respectively.Referring to FIG. 5, in accordance with some embodiments, one of the individual packages 68' is bonded to a package component 70 to form a package 74. The corresponding process is depicted as process 212 in the process flow 200 depicted in FIG. 14. The package component 70 may be a package substrate, a silicon interposer, an organic interposer, a package having device die(s) therein (or the like). The bonding may be realized by solder bonding, direct metal-metal bonding, or the like. Thereafter, an underfill 72 may be introduced between the package 68' and the package component 70.In the package 74, the electrical connector 166A may be used as a first power bump, and power is supplied from the package component 70 to the electrical connector 166A. Power is then supplied through electrical path 76 which includes via 127A, metal lines 144, and vias 146 of device die 120', and metal lines 44 and vias 46 of device die 20'. Thus, the power (also referred to as "ungated" ("ungated") voltage TVDD) is supplied to the TVDD node 34.When the power switch 32 is turned on, the power is supplied to the VVDD node 36, and the corresponding voltage at the VVDD node 36 (also referred to as gated voltage / power VVDD) is transferred back into the device dies 120' through the electrical path 78 that includes the metal lines 44 and vias 46 of the device die 20' and the metal lines 144 and vias 146 of the device die 120'. The integrated circuits 126C, also referred to as gated voltage power consumer circuits VVDD, may thus receive the gated voltage VVDD when the power switch 32 is turned on. When the power switch 32 is off, the integrated circuits 126C are disconnected from the power.According to some embodiments, by forming the power switch 32 in the device die 20' rather than in the device die 120' in which the power consumer circuits 126C are disposed, the chip area of the device die 120' is saved. For example, the device die 120' may be a CPU die or a GPU die that places high demands on chip area due to its high circuit density. Further, the power switch 32 may occupy a large chip area, for example, up to 10 percent of the chip area of the device die 120'. Accordingly, by routing the power switches to the less die area intensive device die 20', the die areas are used more efficiently. Further, since the device density of the device die 20' is lower, the metal lines in the device die 20' can be made wider and thicker, and the voltage drop of the power transmission paths in the device die 20' is low.In some embodiments, the power switch 32 is controlled by the control circuit 35, which may provide control signals to the gate 38 of the power switch 32 to control the on / off state of the power switch 32. According to some embodiments, the control circuit 35 may be disposed outside the device die 20'. For example, the control circuit 35 may include the integrated circuits 126B physically located in the device die 120'. Accordingly, the control circuit 35 is shown in phantom to indicate that it may not physically be located in the device die 20'. When the control circuit 35 includes the integrated circuit 126B, an additional signal path (not shown) including the metal lines 44 and vias 46 in the device dies 20', the metal lines 44 and vias 146 in the device dies 120', and bond pads 56 and 156 may electrically connect the integrated circuit 126B to the gate 38 of the power switch 32.According to some embodiments, a second power bump 166B is used to supply power to integrated circuits 126A through electrical path 80 including via 127B, metal lines 144, and contact plugs 130. Accordingly, the device die 120' includes the integrated circuits 126A driven by ungate power (which may or may not include the ungate voltage TVDD) and the integrated circuits 126C driven by the gated voltage VVDD. In addition, the integrated circuits 126B (the control circuit) may also be connected to the ungate power, for example, by connecting to the power bump 166B, such that the integrated circuits 126B may be capable of generating the control signals for controlling the power switch 32 even when the power switch 32 is turned off.FIGS. 6 through 11 show the cross-sectional views of intermediate stages in the formation of the package according to alternative embodiments of the present disclosure. These embodiments are similar to the embodiments shown in FIGS. 1-5, except that device die 120' (which includes the power consumer circuits) is an upper die and device die 20' having a power switch therein is a lower die. The bonding of the device dies 20' and 120' is also done by face-to-face bonding. Unless otherwise indicated, the materials, structures, and formation processes of the components in these embodiments are substantially the same as the same components denoted by the same reference numerals in the foregoing embodiments. The details regarding the materials, the structures, and the formation processes provided in each of the embodiments throughout the specification may be applied to any other embodiment as appropriate.In a first process, the wafers 20 and 120 are formed as shown in FIG. 6. The materials, structures, and formation processes of wafer 20 and wafer 120 can be seen from the discussion of the previous embodiments. However, according to these embodiments, unlike the previous embodiments, the wafer 20 is bottom and the wafer 120 is top. According to some embodiments, vias may be formed using a through via load process, and at this time, no vias are formed. According to alternative embodiments, vias may also be formed by a through via first process, and at this time, vias may be formed in wafer 20. The corresponding formation process of vias in wafer 120 via a through via first process may be similar to that illustrated in FIGS. 2-4.Referring next to FIG. 7, wafer 120 is bonded to wafer 20, for example, by hybrid bonding, while other applicable bonding methods may also be used. In this manner, the composite wafer 68 is formed.Referring to FIG. 8, a back side thinning process is performed so that the semiconductor substrate 24 is thinned. Next, as shown in FIG. 9, a dielectric layer 60 is formed on the back surface of the semiconductor substrate 24, and vias 27 are formed to pass through the dielectric layer 60 and the semiconductor substrate 24.According to some embodiments, the formation of the vias 27 includes depositing the dielectric layer 60 on the back side of the semiconductor substrate 24 and etching the dielectric layer 60 and the semiconductor substrate 24 to form deep openings. Metal lines 44 (metal pads) are exposed to the deep openings. Next, in a conformal deposition process, a dielectric liner (not shown) is deposited extending into the openings, followed by an anisotropic etch process such that the horizontal portions of the dielectric liner are removed and vertical portions remain as the dielectric liner. The metal pads of the metal lines 44 are again visible. Then, the deep openings are filled with conductive materials to form the vias 27.According to alternative embodiments, the formation of the vias 27 includes etching the semiconductor substrate 24 to form deep openings, forming dielectric liners lining the deep openings, and forming the vias 27 in the openings and surrounded by the dielectric liners. The semiconductor substrate 24 may then be recessed such that some end portions of the vias 27 protrude from the recessed semiconductor substrate 24. Then, the dielectric layer 60 is formed. The dielectric layer 60 may also be formed of silicon oxide, silicon nitride, silicon oxynitride, and the like.Next, a back side interconnect structure including metal pads 64 and a dielectric layer 62 is formed, where the metal pads 64 are connected to the vias 27. The materials and the formation processes of the metal pads 64 and the dielectric layer 62 may be substantially the same as for the metal pads 164 and the dielectric layer 162 of FIG. 4, respectively. The details are not repeated here. Electrical connectors 166 are then formed. The electrical connectors 166 may be substantially the same as the previous embodiments.In a subsequent process, as shown in FIG. 10, the composite wafer 68 may be singulated, for example, in a dicing process, such that multiple individual packages 68' are formed. Wafers 20 and 120 are also singulated into device dies 20' and 120', respectively.Referring to FIG. 11, one of the individual packages 68' is bonded to a package component 70, which may be a package substrate, an interposer (e.g., a silicon interposer or an organic interposer), a package having device die(s) therein(s), or the like. In this way, the package 74 is formed. The bonding may be realized by solder bonding, direct metal-metal bonding, or the like. Thereafter, an underfill 72 may be introduced between the package 68' and the package component 70.In the package 74, the electrical connector 166A may be used as a first power bump, and power is supplied from the package component 70 to the electrical connector 166A. Power is then supplied through electrical path 84 comprising via 27A, metal line(s) 44, and contact plugs 30. The non-gated voltage TVDD is thus supplied to the TVDD node 34, which may be the source region of the power switch 32. When the power switch 32 is turned on, the power is supplied to the VVDD node 36 and the gated voltage VVDD is supplied through the electrical path 86 to the integrated circuits 126C. Electrical path 86 includes metal lines 44 and vias 46 of device die 20' and metal lines 144 and vias 146 of device die 120'. Integrated circuits 126C, also referred to as power consumer circuits, that are powered by gated voltage VVDD may thus receive gated voltage VVDD when power switch 32 is turned on and are disconnected from power when power switch 32 is turned off.According to some embodiments, by forming the power switch 32 in the device die 20' rather than in the device die 120' in which the power consumer circuits 126C are disposed, the chip area of the device die 120' is saved.According to some embodiments, the power switch 32 is disposed in the device die 20' and is controlled by the control circuit 35, which may provide control signals to the gate 38 of the power switch 32 to control the on / off state of the power switch 32. According to some embodiments, the control circuit 35 may be disposed outside the device die 20'. For example, the control circuit 35 may include the integrated circuits 126B physically located in the device die 120'. Accordingly, the control circuit 35 is shown in phantom to indicate that it may not be physically (or already) located in the device die 20'. When the control circuit 35 includes the integrated circuit 126B, an additional signal path (not shown) may electrically connect the integrated circuit 126B to the gate 38 of the power switch 32.In some embodiments, a second power bump 166B is used to supply power to integrated circuits 26 through electrical path 88 having via 27B. Further, device die 120' includes integrated circuits 126A that receive ungate power through electrical path 90 including via 27B, metal lines 44 and vias 46 of device die 20' and metal lines 144 and vias 146 of device die 120'. Integrated circuits 126A are driven by ungated power. In addition, integrated circuits 126B (control circuit) may also be connected to the ungated power, for example, by connecting to power bump 166B, such that integrated circuits 126B may be capable of generating the signals for controlling power switch 32 when power switch 32 is off.FIG. 12 illustrates a package 74 formed in accordance with other alternative embodiments. FIG. 12 shows a package formed by a face-to-back ("face-to-back") bonding process, wherein the front side of the device die 120' faces the back side of the device die 20'. The arrows 33 on the right side of FIG. 12 represent the alignment directions of the wafers 20 (and the device dies 20') and 120 (and the device dies 120'). In addition, in the package 74, the device die 20' in which the power switch 32 is disposed is disposed below, while the device die 120' having the gated power consumer circuits is above. The formation of the package 74 in FIG. 12 may be implemented in accordance with the description of the formation processes illustrated in FIGS. 1-11.In the package 74, the electrical connector 166A may be used as a first power bump, and power is supplied from the package component 70 to the electrical connector 166A. The power is then supplied through the electrical path 94 that includes the metal lines 44 and vias 46 in the device die 20' and the contact plug 30. The power is supplied to the TVDD node 34, which may be the source region of the power switch 32. When the power switch 32 is turned on, the gated power is supplied to the VVDD node 36. The gated voltage VVDD may be supplied to the device die 120' through the electrical path 96. Electrical path 96 includes metal lines 44 and vias 46 of device die 20', via 27A, bond pads, and metal lines 144 and vias 146 of device die 120'. The integrated circuits 126C, which are also the power consumer circuits of the gated voltage VVDD, may thus receive the gated voltage VVDD when the power switch 32 is turned on and are disconnected from the power when the power switch 32 is turned off.According to some embodiments, the power switch 32 is disposed in the device die 20' and may be controlled by the control circuit 35 (e.g., integrated circuits 126B), which may provide control signals to the gate 38 of the power switch 32 to control the on / off state of the power switch 32. According to some embodiments, the control circuit 35 may be disposed outside the device die 20'. For example, the control circuit 35 may include the integrated circuits 126B physically located in the device die 120'. Accordingly, the control circuit 35 is shown in phantom to indicate that it may not be physically (or already) located in the device die 20'. When the control circuit 35 includes the integrated circuit 126B, an additional signal path may electrically connect the integrated circuit 126B to the gate 38 of the power switch 32.According to some embodiments, a second power bump 166B is used to supply power to integrated circuits 26 through electrical path 98 that includes metal lines 44 and vias 46 of device die 20' and contact plugs 30. Further, the device die 120' includes the integrated circuits 126A that receive power through the electrical path 112 including the via 27B, the metal lines 144, and vias 146 of the device die 120', the metal lines 44, and vias 46 of the device die 20', and bond pads 56 and 156. Integrated circuits 126A are driven by ungated power. In addition, the integrated circuits 126B (the control circuit) may be connected to the ungate voltage, for example, by connecting to the power bump 166B, such that the integrated circuits 126B may be capable of generating the signals for controlling the power switch 32 when the power switch 32 is turned off.FIG. 13 illustrates package 74 formed in accordance with alternative embodiments. FIG. 13 also shows a package formed by a face-to-back bonding process, wherein the front side of the device die 20' faces the back side of the device die 120'. The arrows 33 on the right side of FIG. 13 represent the alignment directions of the wafers 20 (and the device dies 20') and 120 (and the device dies 120'). In addition, in the package 74, the device die 20' in which the power switch 32 is disposed is top, while the device die 120' having the power consumer circuits 126C of the gated voltage VVDD is bottom. The formation of the package 74 in FIG. 13 may be implemented in accordance with the description of the formation processes illustrated in FIGS. 1-11.In the package 74, an electrical connector 166A may be used as the first power bump, and power is supplied from the package component 70 to the electrical connector 166A. Power is then supplied through electrical path 114 which includes metal lines 144 and vias 146 in device die 120', via 127A1, and metal lines 44 and vias 46 in device die 20'. The power is supplied to the TVDD node 34, which may be the source region of the power switch 32. When the power switch 32 is turned on, the gated power is supplied to the VVDD node 36.The gated voltage VVDD may be supplied to the device die 120' through the electrical path 116. Electrical path 116 includes metal line 134 and vias 146 of device die 20', via 127A2, and bond pads 56 and 156. Thus, in accordance with these embodiments, power has been passed through two vias 127A1 and 127A2 before the gated power is provided to integrated circuits 126C.According to some embodiments, a second power bump 166B is used to supply power to integrated circuits 126A and 126B through electrical path 118 that includes metal lines 144 and vias 146 of device die 120' and metal lines 44 and vias 46 in device die 20'. The device die 20' includes integrated circuits 26 that receive power through the electrical path 122 including the metal lines 144 and vias 146 of the device die 12o', the via 127B, and the metal lines 44 and vias 46 of the device die 20'. The integrated circuits 26 are driven by the non-gated power. In addition, the integrated circuits 126B (the control circuit) may be connected to the ungate power, for example, by connecting to the power bump 166B, such that the integrated circuits 126B may be capable of generating the signal for controlling the power switch 32 when the power switch 32 is turned off.In the embodiments depicted above, some processes and features are discussed to form a three-dimensional (3D) package, in accordance with some embodiments of the present disclosure. Other features and processes may also be incorporated. For example, test structures may be incorporated to support verification tests of 3D packaging or 3DIC components. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which enables testing of 3D packaging or 3Cs, use of probes and / or probe cards, and the like. The verification tests may be performed on intermediate structures as well as on the final structure. Additionally, the structures and methods disclosed herein may be used in connection with test methods that include intermediate verification of well-established dies ("Known Good Dies") to increase yield and decrease cost.The embodiments of the present disclosure have some advantageous features. By forming power switches outside the sophisticated device die that includes the power consumer circuits that use the gated power, the chip area otherwise occupied by the chip area intensive power switches is saved. The circuit breaker is routed to a less sophisticated device die, which has more space for accommodating the circuit breaker. In addition, since the metal lines in the less sophisticated device die may be thick and wide, the voltage drop in the less sophisticated device die is low.According to some embodiments of the present disclosure, a method includes forming a first device die including: a first integrated circuit; a first bond pad on a first surface of the first device die, the first integrated circuit electrically connected to the first bond pad; forming a second device die including: a power switch including: a first source / drain region; a second source / drain region; a second bond pad electrically connecting to the first source / drain region; and a third bond pad electrically connecting to the second source / drain region; bonding the first device die to the second device die to form a first package, the first bonding pad being bonded to the third bonding pad; and bonding the first package to a package component.In an embodiment, forming the first device die further includes forming a via that passes through a semiconductor substrate of the first device die, wherein after the first device die is bonded to the second device die, the via is electrically coupled to the first source / drain region. In an embodiment, the via is formed before the first device die is bonded to the second device die. In an embodiment, the via is formed after the first device die is bonded to the second device die. In an embodiment, the first device die is bonded between the second device die and the package component.In an embodiment, the first device die is bonded to the package component by a power bump receiving a non-gated voltage from the package component and connected to the first integrated circuit by an electrical path, the electrical path including: a first portion from the power bump to the power switch; and a second portion from the power switch to the first integrated circuit. In an embodiment, the first device die is face-to-face bonded to the second device die.In an embodiment, the first device die is bonded to the second device die by face-to-back bonding. In an embodiment, the second device die is bonded between the first device die and the package component. In an embodiment, the first device die further includes a second integrated circuit, wherein the second integrated circuit is configured to receive power when the first integrated circuit is disconnected from the power by the power switch.According to some embodiments of the present disclosure, a structure includes: a first device die including a first integrated circuit; and a second device die including a power switch that electrically connects to the first integrated circuit, the power switch configured to disconnect power to the first integrated circuit in response to a first control signal; and supply power to the first integrated circuit in response to a second control signal. In an embodiment, the first device die includes a logic die and the second device die includes an input / output die or a memory die. In an embodiment, the structure further comprises a control circuit configured to provide the first control signal and the second control signal, wherein the control circuit is disposed outside the first device die.In an embodiment, the control circuit is in the second device die. In an embodiment, the first device die is face-to-face bonded to the second device die. In an embodiment, the first device die is face-to-back bonded to the second device die. In an embodiment, a power supply path for supplying power to the first integrated circuit includes a first portion that passes through the first device die to reach the power switch; and a second portion that includes a first portion in the first device die and a second portion in the second device die. In an embodiment, the first device die further includes a second integrated circuit, wherein a power supply path for supplying power to the second integrated circuit is decoupled from the power switch.According to some embodiments of the present disclosure, a structure includes: a package substrate; a first device die over and bonded to the package substrate, the first device die including: a semiconductor substrate; an integrated circuit on the semiconductor substrate; a via passing through the semiconductor substrate; and a second device die over and bonded to the first device die, the second device die including a power switch, and the power switch including: a first source / drain region that electrically connects to the via in the first device die; and a second source / drain region that connects to the integrated circuit in the first device die. In one embodiment, the power switch is configured to disconnect or supply power to the integrated circuit in response to various control signals that control switching operations of the power switch.The foregoing description outlines features of several embodiments in order that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures to realize the same purposes and / or achieving the same advantages of the embodiments presented herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedUS 63 / 517,381

[0001]

Claims

A method comprising: forming a first device die comprising: a first integrated circuit; a first bond pad on a first surface of the first device die, the first integrated circuit being electrically connected to the first bond pad; forming a second device die comprising: a power switch comprising: a first source / drain region; a second source / drain region; a second bond pad electrically connected to the first source / drain region; and a third bond pad electrically connected to the second source / drain region; bonding the first device die to the second device die to form a first package, the first bond pad being bonded to the third bond pad; and bonding the first package to a package component.The method of claim 1, wherein forming the first device die further comprises: forming a via that passes through a semiconductor substrate of the first device die, wherein, after bonding the first device die to the second device die, the via is electrically coupled to the first source / drain region.The method of claim 2, wherein the via is formed before the first device die is bonded to the second device die.The method of claim 2, wherein the via is formed after the first device die is bonded to the second device die.The method of any of claims 1 to 4, wherein the first device die is bonded between the second device die and the package component.The method of claim 5, wherein the first device die is bonded to the package component by a power bump receiving a non-gated voltage from the package component and connected to the first integrated circuit by an electrical path, and wherein the electrical path comprises: a first portion of the power bump to the power switch; and a second portion of the power switch to the first integrated circuit.The method of any of claims 1 to 6, wherein the first device die is face-to-face bonded to the second device die.The method of any of claims 1 to 6, wherein the first device die is bonded to the second device die by face-to-back bonding.The method of any of claims 1 to 4, wherein the second device die is bonded between the first device die and the package component.The method of any of claims 1 to 9, wherein the first device die further comprises a second integrated circuit, wherein the second integrated circuit is configured to receive power when the first integrated circuit is disconnected from the power by the power switch.A structure comprising: a first device die comprising: a first integrated circuit; and a second device die comprising a power switch that electrically connects to the first integrated circuit, wherein the power switch is configured to: - disconnect power to the first integrated circuit in response to a first control signal; and - supply power to the first integrated circuit in response to a second control signal.The structure of claim 11, wherein the first device die comprises a logic die and the second device die comprises an input / output die or a memory die.The structure of claim 11 or 12, further comprising a control circuit configured to provide the first control signal and the second control signal, wherein the control circuit is disposed outside the first device die.The structure of claim 13, wherein the control circuit is in the second device die.The structure of any of claims 11 to 14, wherein the first device die is face-to-face bonded to the second device die.The structure of any of claims 11 to 14, wherein the first device die is face-to-back bonded to the second device die.The structure of any of claims 11 to 16, wherein a power supply path for supplying power to the first integrated circuit comprises: a first part that passes through the first device die to reach the power switch; and a second part that comprises a first portion in the first device die and a second portion in the second device die.The structure of any of claims 11 to 17, wherein the first device die further comprises a second integrated circuit, wherein a power supply path for supplying power to the second integrated circuit is decoupled from the power switch.A structure comprising: a package substrate; a first device die over and bonded to the package substrate, wherein the first device die comprises: a semiconductor substrate; an integrated circuit on the semiconductor substrate; a via that passes through the semiconductor substrate; and a second device die over and bonded to the first device die, wherein the second device die comprises a power switch, and wherein the power switch comprises: a first source / drain region that electrically connects to the via in the first device die; and a second source / drain region that connects to the integrated circuit in the first device die.The structure of claim 19, wherein the power switch is configured to disconnect or supply power to the integrated circuit in response to various control signals that control switching actions of the power switch.

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