STRUCTURE AND TRAINING METHOD OF SEMICONDUCTOR DEVICE WITH REAR CONDUCTIVE CONTACT

Abstract

A method for forming a semiconductor device structure comprises forming a fin structure over a substrate. The fin structure includes a base layer, and the fin structure has multiple sacrificial layers and multiple semiconductor layers arranged alternately over the base layer. The method also includes partially removing the fin structure to form an opening that exposes the side faces of the semiconductor layers, the sacrificial layers, and the base layer. The method further includes partially or completely removing the base layer to form a depression, forming a protective structure in the depression, and forming an epitaxial structure that fills the opening.Furthermore, the method involves partially removing the substrate from a rear surface such that a contact opening is formed, exposing the protective structure and extending towards the epitaxial structure. The method includes forming a rear conductive contact within the contact opening.

Description

BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation features smaller and more complex circuits than the previous generation.

[0002] Over the course of IC evolution, feature density (i.e., the number of interconnected devices per chip area) has generally increased, while feature size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This downscaling process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] However, these advances have increased the complexity of IC processing and manufacturing. As component sizes become ever smaller, manufacturing processes become increasingly difficult to execute. Therefore, developing reliable semiconductor devices in ever smaller sizes is a challenge. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Indeed, the dimensions of various elements may be exaggerated or reduced as desired for clarity of description. The Fig. 1A to 1B are plan views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. The Fig. 2A to 2G are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. The Fig. 3A to 3T are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. Fig. 4 is a cross-sectional view of a stage of a process for forming a portion of a semiconductor device structure according to some embodiments. The Fig. 5A to 5E are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. The Fig. 6A to 6B are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. Fig. 7 is a cross-sectional view of a stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Fig. 8 is a cross-sectional view of a stage of a process for forming a portion of a semiconductor device structure according to some embodiments. The Fig. 9A to 9B are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. The Fig. 10A to 10B are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, in the following description, forming a first element over or on top of a second element may cover embodiments in which the first and second elements are formed in direct contact, and may also cover embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or section to one or more other elements or sections as shown in the figures. The spatially relative terms are intended to cover various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may be interpreted accordingly.

[0007] Embodiments of the disclosure may relate to a FinFET structure with fins. The fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, such as double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes so that structures may be created that have, for example, center-to-center pitches smaller than those otherwise obtainable with a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. However, the fins can be formed using another suitable process.

[0008] Embodiments of the disclosure may relate to gate-all-around (GAA) transistor structures. The GAA structure may be patterned using any suitable method. For example, the structures may be patterned using one or more photolithography processes, such as double-patterning or multi-patterning processes. In some embodiments, double-patterning or multi-patterning processes combine photolithography and self-aligned processes so that structures may be created that have, for example, center-to-center pitches smaller than those otherwise obtainable with a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process.Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0009] Some embodiments of the disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be substituted or omitted for various embodiments. Additional elements may be added to the semiconductor device structure. Some of the elements described below may be substituted or omitted for various embodiments. Although some embodiments are described with operations performed in a particular order, these operations may be performed in a different logical order.

[0010] The Fig. 2A to 2G are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. As in Fig. 2A, a semiconductor substrate 100 is received or provided. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate 100 may include silicon or other elemental semiconductor materials such as germanium. The semiconductor substrate 100 may be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, the semiconductor substrate 100 includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, another suitable material, or a combination thereof.

[0011] In some further embodiments, the semiconductor substrate 100 includes a compound semiconductor. For example, the compound semiconductor includes one or more III-V compound semiconductors having a composition represented by the formula Al X1 Ga X2 In X3 Ace Y1 P Y2 N Y3 Sb Y4 where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of them is greater than or equal to zero, and when added together, they equal 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination thereof. Other suitable substrates, such as II-VI compound semiconductors, may also be used.

[0012] In some embodiments, the semiconductor substrate 100 consists of an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another suitable method, or a combination thereof. In some further embodiments, the semiconductor substrate 100 has a multilayer structure. For example, the semiconductor substrate 100 includes a silicon germanium layer formed on a silicon layer.

[0013] In some embodiments, the semiconductor substrate 100 comprises a plurality of semiconductor layers 100a, 100b and 100c, as shown in Fig. 2A. In some embodiments, semiconductor layers 100a and 100c are made of a first semiconductor material, and semiconductor layer 100b is made of a second semiconductor material that is different from the first semiconductor material. In some embodiments, semiconductor layers 100a and 100c are made of silicon, and semiconductor layer 100b is made of silicon germanium.

[0014] As in Fig. 2A, according to some embodiments, a semiconductor stack having a plurality of semiconductor layers is formed over the semiconductor substrate 100. In some embodiments, the semiconductor stack includes a plurality of semiconductor layers 102a, 102b, 102c, and 102d. The semiconductor stack also includes a plurality of semiconductor layers 104a, 104b, 104c, and 104d. In some embodiments, the semiconductor layers 102a-102d and 104a-104d are arranged alternately, as shown in Fig. 2A. The semiconductor layers 102a-102d and 104a-104d together form a superlattice structure.

[0015] In some embodiments, semiconductor layer 102a acts as a base layer that is partially removed to form recesses used to accommodate protection structures. In some embodiments, semiconductor layers 102b-102d act as sacrificial layers that are removed in a subsequent process, exposing semiconductor layers 104b-104d. Exposed semiconductor layers 104b-104d may serve as channel structures of one or more transistors. In some embodiments, semiconductor layer 104a is thicker than each of semiconductor layers 104b-104d.

[0016] In some embodiments, the semiconductor layers 104b-104d used to form channel structures are made of a material different from that of the semiconductor layers 102a-102d. In some embodiments, the semiconductor layers 104a-104d are made of or include silicon, germanium, another suitable material, or a combination thereof. In some embodiments, the semiconductor layers 102a-102d are made of or include silicon germanium. In some further embodiments, the semiconductor layers 104a-104d are made of silicon germanium, and the semiconductor layers 102a-102d are made of silicon germanium with a different atomic fraction of germanium than the semiconductor layers 104a-104d.As a result, different etch selectivity and / or different oxidation rates of the semiconductor layers 102a-102d and the semiconductor layers 104a-104d may be achieved during subsequent processing.

[0017] The present disclosure contemplates that semiconductor layers 102a-102d and 104a-104d may include any combination of semiconductor materials that may provide the desired etch selectivity, desired oxidation rate differences, and / or desired performance characteristics.

[0018] In some embodiments, the composition of semiconductor layer 102a differs from that of semiconductor layers 102b-102d. In some embodiments, semiconductor layer 102a and semiconductor layers 102b-102d are made of silicon germanium with a different composition. In some embodiments, semiconductor layer 102a has a higher atomic fraction of germanium than semiconductor layers 102b-102d.

[0019] In some embodiments, the semiconductor layers 102a-102d and 104a-104d are formed using multiple epitaxial growth processes. Each of the semiconductor layers 102a-102d and 104a-104d may be formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor phase epitaxy (VPE) process), a low-pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum CVD (UHV) process, a molecular beam epitaxy process, another suitable process, or a combination thereof.

[0020] In some embodiments, semiconductor layers 102a-102d and 104a-104d are grown in situ in the same process chamber. In some embodiments, the growth of semiconductor layers 102a-102d and 104a-104d is performed alternately and sequentially in the same process chamber to achieve the formation of the semiconductor stack. In some embodiments, the vacuum of the process chamber is not broken until the epitaxial growth of semiconductor layers 102a-102d and 104a-104d is completed.

[0021] Subsequently, hard mask elements are formed over the semiconductor stack, which are used in subsequent patterning of the semiconductor stack. One or more photolithography processes and one or more etching processes are used, according to some embodiments, to pattern the semiconductor stack into a plurality of fin structures, including fin structures 106A and 106B, as shown in Fig. 2B shown.

[0022] The fin structures 106A and 106B may be patterned using any suitable method. For example, the fin structures 106A and 106B may be patterned using one or more photolithography processes, such as double patterning or multiple patterning processes. Double patterning or multiple patterning processes may combine photolithography and self-aligned processes, allowing the creation of structures having, for example, center-to-center pitches that are smaller than those otherwise obtainable using a single, direct photolithography process.

[0023] The semiconductor stack is partially removed so that several trenches 112 are formed, as in Fig. 2B. Each of the fin structures 106A and 106B may include portions of the semiconductor layers 102a-102d and 104a-104d and the semiconductor fins 101A and 101B. The semiconductor substrate 100 may also be partially removed during the etching process that forms the fin structures 106A and 106B. The remaining protruding portions of the semiconductor substrate 100 form the semiconductor fins 101A and 101B. Each of the semiconductor fins 101A and 101B may include portions of the semiconductor layers 100a-100c, as shown in Fig. 2B shown.

[0024] Each of the hard mask elements may include a first mask layer 108 and a second mask layer 110. The first mask layer 108 and the second mask layer 110 may be made of different materials. In some embodiments, the first mask layer 108 is made of a material that has good adhesion to the semiconductor layer 104d. The first mask layer 108 may be made of silicon oxide, germanium oxide, silicon germanium oxide, another suitable material, or a combination thereof. The second mask layer 110 may be made of silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof.

[0025] The Fig. 1A to 1B are top views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. In some embodiments, the fin structures 106A and 106B are longitudinally aligned. In some embodiments, the longitudinal directions of the fin structures 106A and 106B are substantially parallel to each other, as shown in Fig. 1A. In some embodiments, Fig. 2B is a cross-sectional view of the structure taken along line 2B-2B in Fig. 1A.

[0026] As in Fig. 2C, according to some embodiments, an isolation structure 115 is formed to laterally surround the lower portions of the fin structures 106A and 106B. In some embodiments, the isolation structure 115 includes a dielectric fill 114 and a liner layer 113 adjacent to the semiconductor fins 101A and 101B. In some embodiments, the semiconductor fins 101A and 101B protrude from the upper surface of the isolation structure 115.

[0027] In some embodiments, one or more dielectric layers are deposited over the fin structures 106A and 106B and the semiconductor layer 100A to overfill the trenches 112. The dielectric layers may be made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, a porous dielectric, another suitable material, or a combination thereof. The liner layer 113 may be made of or include silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and another suitable material, or a combination thereof.The liner layer 113 and the dielectric layers may be deposited sequentially using a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, another suitable process, or a combination thereof.

[0028] Subsequently, a planarization process is used to partially remove the dielectric layers and the liner layer 113. The hard mask elements (including the first mask layer 108 and the second mask layer 110) may also act as stop layers of the planarization process. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, a dry polishing process, an etching process, another suitable process, or a combination thereof.

[0029] Subsequently, one or more etching processes are used to partially remove the dielectric layers and the liner layer 113. As a result, the remaining portion of the dielectric layers forms the dielectric filling 114 of the insulating structure 115. Upper portions of the fin structures 106A and 106B protrude from the uppermost surface of the insulating structure 115, as shown in Fig. 2C shown.

[0030] In some embodiments, the etching process for forming the insulating structure 115 is carefully controlled to ensure that the top surface of the insulating structure 115 is at a suitable height. In some embodiments, the top surface of the insulating structure 115 is at a higher level than the top surface of the semiconductor layer 102a, which functions as a base layer. The top surface of the semiconductor layer 102a is closer to the semiconductor layer 100a than the top surface of the insulating structure 115, as shown in Fig. 2C. The semiconductor layer 102a is covered and protected by the insulating structure 115 and the semiconductor layer 104a.

[0031] Subsequently, the remaining portions of the hard mask elements (including the first mask layer 108 and the second mask layer 110) are removed. Alternatively, in some further embodiments, the hard mask elements are removed or consumed during the planarization process and / or the etch-back process for forming the isolation structure 115.

[0032] Thereafter, according to some embodiments, dummy gate stacks 120 are formed extending over the fin structures 106A and 106B, as shown in Fig. 1B shown. Fig. Figure 2D is a cross-sectional view of the structure in some embodiments taken along line 2D-2D in Fig. 1B. The Fig. 3A to 3T are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. In some embodiments, Fig. Figure 3A is a cross-sectional view of the structure taken along line 3A-3A in Fig. 1B.

[0033] As in the Fig. 1B, Fig. 2D and Fig. 3A, according to some embodiments, the dummy gate stacks 120 are formed to partially cover and extend over the fin structures 106A and 106B. In some embodiments, the dummy gate stacks 120 enclose portions of the fin structures 106A and 106B. As shown in Fig. 1B, other portions of the fin structures 106A and 106B are exposed without being covered by the dummy gate stacks 120. In Fig. 3A, upper portions of the dummy gate stacks 120 are not shown.

[0034] As in the Fig. 2D and Fig. As shown in Figure 3A, each of the dummy gate stacks 120 includes a dummy gate dielectric layer 116 and a dummy gate electrode 118. The dummy gate dielectric layers 116 may be made of or include silicon oxide or another suitable material. The dummy gate electrodes 118 may be made of or include polysilicon or another suitable material.

[0035] In some embodiments, a dummy gate dielectric layer and a dummy gate electrode layer are sequentially deposited over the isolation structure 115 and the fin structures 106A and 106B. The dummy gate dielectric layer may be deposited using an ALD process, a CVD process, another suitable process, or a combination thereof. The dummy gate electrode layer may be deposited using a CVD process. Subsequently, the dummy gate dielectric layer and the dummy gate electrode layer are patterned to form the dummy gate stacks 120.

[0036] In some embodiments, hard mask elements such as mask layers 122 and 124 are used to assist the patterning process for forming dummy gate stacks 120. With the hard mask elements as an etch mask, one or more etch processes are used to partially remove the dummy gate dielectric layer and the dummy gate electrode layer. As a result, remaining portions of the dummy gate dielectric layer and the dummy gate electrode layer form dummy gate stacks 120.

[0037] As in Fig. 3B, according to some embodiments, a spacer layer 128 is subsequently deposited over the dummy gate stacks 120 and the fin structure 106B. The spacer layer 128 extends along the top and sidewalls of the dummy gate stacks 120, as shown in Fig. 3B. The spacer layer 128 also extends along the top of the fin structure 106B, as shown in Fig. 3B shown.

[0038] The spacer layer 128 may be made of or include silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, silicon oxycarbide, carbonaceous silicon oxynitride, carbonaceous silicon nitride, another suitable material, or a combination thereof. The spacer layer 128 may be deposited sequentially using a CVD process, an ALD process, a physical vapor deposition (PVD) process, another suitable process, or a combination thereof.

[0039] In some embodiments, the spacer layer 128 forms a single layer. In some further embodiments, the spacer layer 128 comprises multiple sublayers. Some of the sublayers may be made of the same material. Some of the sublayers may be made of different materials. Some of the sublayers may be made of similar materials with different compositions. For example, one of the sublayers may have a higher atomic fraction of carbon than other sublayers.

[0040] As in Fig. 3C, the spacer layer 128 is partially removed according to some embodiments. One or more anisotropic etch processes may be used to partially remove the spacer layer 128. As a result, remaining portions of the spacer layer 128 form gate spacers 128'. The gate spacers 128' extend along the sidewalls of the dummy gate stacks 120, as shown in Fig. 3C shown.

[0041] Subsequently, the fin structure 106B is partially removed to form a plurality of openings 130 that are used to accommodate subsequently formed epitaxial structures. As shown in Fig. 3C, according to some embodiments, the fin structure 106B is partially removed to form the openings 130. In Fig. 3C shows one of the openings 130. As in Fig. As shown in Figure 3C, the opening 130 exposes the side surfaces of the semiconductor layers 104a-104d, on which epitaxial structures (such as source / drain structures) are later formed. Source / drain structures may refer to a source structure or drain structure, individually or collectively, depending on the context. The opening 130 also exposes the side surfaces of the semiconductor layers 102a-102d, as shown in Fig. 3C shown.

[0042] One or more etching processes may be used to form the opening 130. In some embodiments, a dry etching process is used to form the opening 130. Alternatively, a wet etching process may be used to form the opening 130. In some embodiments, the opening 130 extends into the fin structure 106B. In some embodiments, the opening 130 further extends into the semiconductor fin 101B, as shown in Fig. 3C. In some embodiments, the gate spacers 128' and the opening 130 are formed simultaneously using the same etch process.

[0043] In some embodiments, opening 130 has sidewalls that are substantially vertical. In these cases, due to the profile of opening 130, an upper semiconductor layer (such as semiconductor layer 104d) is substantially the same width as a lower semiconductor layer (such as semiconductor layer 104b).

[0044] However, embodiments of the disclosure may have many variations. In some further embodiments, the opening 130 has sloped sidewalls. The upper portion of the opening 130 is larger (or wider) than the lower portion of the opening 130. In these cases, due to the profile of the opening 130, an upper semiconductor layer (such as semiconductor layer 104d) is narrower than a lower semiconductor layer (such as semiconductor layer 104b).

[0045] As in Fig. 3D, the semiconductor layers 102a-102d are laterally etched according to some embodiments. As a result, the edges of the semiconductor layers 102a-102d are recessed from the edges of the semiconductor layers 104a-104d. As shown in Fig. As shown in Figure 3D, recesses 132 and 132' may be simultaneously formed by the lateral etching of semiconductor layers 102a-102d, according to some embodiments. Recesses 132 may be used to receive internal spacers that will be formed later. Recesses 132' may be used to receive protection structures that will be formed later.

[0046] The semiconductor layers 102a-102d may be laterally etched using a wet etching process, a dry etching process, or a combination thereof. In some further embodiments, the semiconductor layers 102a-102d are partially oxidized before being laterally etched.

[0047] In some embodiments, each of the recesses 132' is deeper than each of the recesses 132. As described above, in some embodiments, the semiconductor layer 102a has a higher atomic fraction of germanium than the semiconductor layers 102b-102d. Therefore, during the laterally etching of the semiconductor layers 102a-102d, the semiconductor layer 102a is laterally etched at a higher etch rate than the semiconductor layers 102b-102d. This forms recesses 132' that are deeper than the recesses 132.

[0048] In some embodiments, during the lateral etching of the semiconductor layers 102a-102d, the semiconductor layers 104a-104d may also be slightly etched. As a result, edge regions of the semiconductor layers 104a-104d are partially etched and thus shrink.

[0049] As in Fig. 3E, according to some embodiments, an insulating layer 134 is formed over the Fig. 3D. The insulating layer 134 covers the dummy gate stacks 120 and fills the recesses 132 and 132'. The insulating layer 134 may be made of or include carbonaceous silicon nitride (SiCN), carbonaceous silicon oxynitride (SiOCN), carbonaceous silicon oxide (SiOC), silicon oxide, silicon nitride, another suitable material, or a combination thereof. In some embodiments, the insulating layer 134 forms a single layer. In some further embodiments, the insulating layer 134 comprises multiple sublayers. Some of the sublayers may be made of different materials and / or have different compositions. The insulating layer 134 may be deposited using a CVD process, an ALD process, another suitable process, or a combination thereof.

[0050] As in Fig. As shown in Figure 3F, according to some embodiments, an etching process is used to partially remove the insulating layer 134. The portions of the insulating layer 134 outside the recesses 132 may be removed. The remaining portions of the insulating layer 134 in the recesses 132 form internal spacers 136. The remaining portions of the insulating layer 134 in the recesses 132' form protective structures 302. The etching process may include a dry etching process, a wet etching process, or a combination thereof.

[0051] In some embodiments, each of the protective structures 302 is wider than each of the inner spacers 136, as shown in Fig. 3F. Since, in some embodiments, the protective structures 302 and the inner spacers 136 are portions of the same material layer (i.e., the insulating layer 134), the protective structures 302 and the inner spacers 136 have the same composition.

[0052] In some embodiments, each of the protection structures 302 is in direct contact with or adjacent to the semiconductor layer 102a, which functions as a base layer. However, embodiments of the disclosure are not limited thereto. Many variations and / or modifications may be made for embodiments of the disclosure. Since the recesses 132' are deeper, the insulating layer 134 may not completely fill the recesses 132' in some further embodiments. In these cases, a cavity may be formed between the insulating layer 134 and the semiconductor layer 102a. Thus, one or more cavities may be formed between the protection structure 302 and the semiconductor layer 102a. In these cases, the protection structure 302 does not need to be in direct contact with the semiconductor layer 102a.

[0053] As in Fig. 3F, the inner spacers 136 cover the edges of the semiconductor layers 102b-102d. The inner spacers 136 may be used to prevent later-formed epitaxial structures (functioning, for example, as source / drain structures) from being damaged during a subsequent process for removing the semiconductor layers 102b-102d. In some embodiments, the inner spacers 136 are made of a low-k material having a lower dielectric constant than that of silicon oxide. In these cases, the inner spacers 136 may also be used to reduce the parasitic capacitance between the subsequently formed source / drain structures and the gate stacks. This may improve the operating speed of the semiconductor device structure.

[0054] In some embodiments, after the etching process to form the inner spacers 136, a portion of the semiconductor fin 101B that was originally covered by the insulating layer 134 is exposed through the opening 130, as shown in Fig. 3F. The edges of the semiconductor layers 104a-104d are also exposed through the opening 130, as shown in Fig. 3F shown.

[0055] As in Fig. 3G, according to some embodiments, an epitaxial structure comprising an undoped epitaxial portion 304 and a doped epitaxial portion 138 is formed to fill the opening 130. In some embodiments, the undoped epitaxial portion 304 is adjacent to the semiconductor layer 104a. The undoped epitaxial portion 304 is formed over the bottom surface of the opening 130. In some embodiments, the undoped epitaxial portion 304 is substantially free of n-type dopants or p-type dopants. The undoped epitaxial portion 304 may provide a relatively flat surface that facilitates the subsequent formation of the epitaxial structure.

[0056] The undoped epitaxial portion 304 may be made of or include silicon, silicon germanium, another suitable material, or a combination thereof. The undoped epitaxial portion 304 may be formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a VPE process, a low-pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum CVD (UHV) process), a molecular beam epitaxial growth process, another suitable process, or a combination thereof. In some embodiments, forming the undoped epitaxial portion 304 includes one or more etch processes used to fine-tune the profiles of the undoped epitaxial portion 304.

[0057] Subsequently, according to some embodiments, a lower isolation element 306 is selectively formed on the undoped epitaxial portion 304, as shown in Fig. 3G. The lower insulating element 306 may act as a stop layer during a subsequent process for forming a backside conductive contact.

[0058] In some embodiments, the lower insulating member 306 is made of or includes a dielectric. The dielectric may include silicon oxide, silicon nitride, carbonaceous silicon nitride, carbonaceous silicon oxynitride, carbonaceous silicon oxide, aluminum oxide, hafnium oxide, another suitable material, or a combination thereof. Forming the lower insulating member 306 may include one or more deposition processes and one or more patterning processes.

[0059] However, embodiments of the disclosure are not limited thereto. Many variations and / or modifications may be made to embodiments of the disclosure. In some further embodiments, the lower insulating member 306 is not formed.

[0060] As in Fig. As shown in Figure 3G, according to some embodiments, a doped epitaxial section 138 is formed on the lower insulating element 306 and the side surfaces of the semiconductor layers 104b-104d. In some embodiments, the doped epitaxial section 138 is substantially level with the top surfaces of the semiconductor layer 104d. In some further embodiments, the top surfaces of the doped epitaxial section 138 are higher than the top surface of the dummy gate dielectric layer 116.

[0061] In some embodiments, the doped epitaxial section 138 abuts the semiconductor layers 104b-104d. In some embodiments, the doped epitaxial section 138 includes lightly doped sections 308 adjacent to the semiconductor layers 104b-104d. The dopant concentration of the lightly doped sections 308 is lower than that of the other portions of the doped epitaxial section 138.

[0062] In some embodiments, the doped epitaxial sections 138 form p-doped regions. The doped epitaxial section 138 may include epitaxially grown silicon germanium (SiGe), epitaxially grown silicon, or another suitable epitaxially grown semiconductor material. The p-dopants may include boron, another suitable element, or a combination thereof.

[0063] However, embodiments of the disclosure are not limited thereto. In some further embodiments, the doped epitaxial sections 138 are n-doped regions. The doped epitaxial section 138 may include epitaxially grown silicon, epitaxially grown silicon carbide (SiC), epitaxially grown germanium, or another suitable epitaxially grown semiconductor material. The n-type dopants may include phosphorus, arsenic, another suitable element, or a combination thereof.

[0064] In some embodiments, the doped epitaxial sections 138 are doped in-situ during their epitaxial growth. The starting reaction gas mixture for forming the doped epitaxial section 138 contains dopants. In some further embodiments, the doped epitaxial section 138 is not doped during the growth of the doped epitaxial section 138. Instead, after the formation of the doped epitaxial section 138, the doped epitaxial section 138 is doped in a subsequent process. In some embodiments, the doping is achieved using an ion implantation process, a plasma immersion ion implantation process, a gas and / or solid diffusion process, another suitable process, or a combination thereof.In some embodiments, the doped epitaxial sections 138 are further subjected to one or more annealing processes to activate the dopants. For example, a rapid thermal anneal is used.

[0065] As in Fig. 3H, according to some embodiments, a contact etch stop layer 139 and a dielectric layer 140 are formed over the Fig. 3G. The contact etch stop layer 139 may be made of or include silicon nitride, silicon oxynitride, silicon carbide, carbonaceous silicon nitride or carbonaceous silicon oxynitride, carbonaceous silicon oxide, aluminum oxide, another suitable material, or a combination thereof. The dielectric layer 140 may be made of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, a porous dielectric, another suitable material, or a combination thereof.

[0066] In some embodiments, an etch stop material layer and a dielectric layer are sequentially deposited over the Fig. 3G. The etch stop material layer may be deposited using a CVD process, an ALD process, a PVD process, another suitable process, or a combination thereof. The dielectric layer may be deposited using an FCVD process, a CVD process, an ALD process, another suitable process, or a combination thereof.

[0067] Subsequently, a planarization process is used to partially remove the etch stop material layer and the dielectric layer. As a result, the remaining portions of the etch stop material layer and the dielectric layer form the contact etch stop layer 139 and the dielectric layer 140, as shown in Fig. 3H. The planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, another suitable process, or a combination thereof. In some embodiments, the mask layers 122 and 124 over the dummy gate stacks 120 are removed during the planarization process.

[0068] Subsequently, a gate replacement process is performed to replace the dummy gate stack 120 with a metal gate stack. As shown in the Fig. 2E and Fig. As shown in Figure 3I, according to some embodiments, the dummy gate electrodes 118 are removed using one or more etch processes to form trenches 142. The trenches 142 expose the dummy gate dielectric layer 116 and the inner sidewalls of the gate spacers 128'.

[0069] As in the Fig. 2F and Fig. 3J, according to some embodiments, the dummy gate dielectric layer 116 and the semiconductor layers 102b-102d (which function as sacrificial layers) are removed. In some embodiments, one or more etch processes are used to remove the dummy gate dielectric layer 116 and the semiconductor layers 102b-102d. This forms recesses 144, as shown in FIGS. Fig. 2F and Fig. 3J shown.

[0070] Due to the high etch selectivity, the semiconductor layers 104a-104d are lightly (or substantially not) etched. The remaining portions of the semiconductor layers 104a-104d form a plurality of semiconductor nanostructures 104a'-104d'. The semiconductor nanostructures 104a'-104d' are fabricated from or consist of the remaining portions of the semiconductor layers 104a-104d. The semiconductor nanostructures 104b'-104d' may serve as channel structures of the transistors. The semiconductor nanostructures 104a' may be used as base semiconductor nanostructures. In some embodiments, the semiconductor nanostructures 104a' are separated from the epitaxial structures 138. In some embodiments, the semiconductor nanostructures 104a' are electrically insulated from the epitaxial structures 138.

[0071] In some embodiments, the etchant used to remove the semiconductor layers 102b-102d also slightly removes the semiconductor layers 104a-104d that form the semiconductor nanostructures 104a'-104d'. As a result, the resulting semiconductor nanostructures 104a'-104d' become thinner after removing the semiconductor layers 102b-102d.

[0072] After removing the semiconductor layers 102b-102d (which act as sacrificial layers), the recesses 144 are formed. The recesses 144 surround each of the semiconductor nanostructures 104a'-104d'. Even if the recesses 144 are formed between the semiconductor nanostructures 104a'-104d', the semiconductor nanostructures 104a'-104d' are still held by the epitaxial structure with the undoped epitaxial section 304 and the doped epitaxial section 138. Thus, after removing the semiconductor layers 102b-102d (which act as sacrificial layers), the exposed semiconductor nanostructures 104a'-104d' are prevented from collapsing.

[0073] When removing the semiconductor layers 102b-102d (which act as sacrificial layers), the inner spacers 136 protect the doped epitaxial section 138 from etching or damage. The quality and reliability of the semiconductor device structure are ensured.

[0074] As in Fig. As shown in Figure 2F, according to some embodiments, during the removal of the semiconductor layers 102b-102d, the semiconductor layer 102a (acting as a base layer) is protected by the insulating structure 115 and the semiconductor nanostructure 104a'. Thus, the semiconductor layer 102a is prevented from being reached and removed by the etch used to remove the semiconductor layers 102b-102d.

[0075] As in the Fig. 2G and Fig. 3K, according to some embodiments, metal gate stacks 156 are formed filling the trenches 142. The metal gate stacks 156 further extend into the recesses 144 to enclose each of the semiconductor nanostructures 104a'-104d'. Each of the metal gate stacks 156 includes a plurality of metal gate stack layers. Each of the metal gate stacks 156 may include a gate dielectric layer 150, a work function layer 152, and a conductive fill 154.

[0076] In some embodiments, forming the metal gate stacks 156 includes depositing a plurality of metal gate stack layers over the dielectric layer 140, filling the trenches 142 and the recesses 144. The metal gate stack layers extend into the recesses 144 to enclose each of the semiconductor nanostructures 104a'-104d'.

[0077] In some embodiments, the gate dielectric layer 150 is made of or includes a high-k dielectric. The gate dielectric layer 150 may be made of or include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-k materials, or a combination thereof. The gate dielectric layer 150 may be deposited using an ALD process, a CVD process, another suitable process, or a combination thereof.

[0078] In some embodiments, prior to the formation of the gate dielectric layer 150, interface features are formed on the surfaces of the semiconductor nanostructures 104a'-104d'. The interface features are very thin and are made, for example, from silicon oxide or germanium oxide. In some embodiments, the interface features are formed by applying an oxidizing agent to the surfaces of the semiconductor nanostructures 104a'-104d'. For example, a hydrogen peroxide-containing liquid may be applied or dispensed onto the surfaces of the semiconductor nanostructures 104a'-104d' to form the interface features.

[0079] The work function layer 152 can be used to provide the desired work function for transistors to enhance device performance, such as through improved threshold voltage. In some embodiments, the work function layer is used to form a PMOS device. The work function layer forms a p-type work function layer. The p-type work function layer can provide a work function value suitable for the device, for example, greater than or equal to 4.8 eV.

[0080] The p-type work function layer may contain metal, metal carbide, metal nitride, another suitable material, or a combination thereof. For example, the p-type metal includes tantalum nitride, tungsten nitride, titanium, titanium nitride, another suitable material, or a combination thereof.

[0081] In some further embodiments, the work function layer is used to form an NMOS device. The work function layer forms an n-type work function layer. The n-type work function layer can provide a work function value suitable for the device, for example, less than or equal to 4.5 eV.

[0082] The n-type work function layer may contain metal, metal carbide, metal nitride, or a combination thereof. For example, the n-type work function layer contains titanium nitride, tantalum, tantalum nitride, another suitable material, or a combination thereof. In some embodiments, the n-type work function layer is an aluminum-containing layer. The aluminum-containing layer may be made of or contain TiAlC, TiAlO, TiAlN, another suitable material, or a combination thereof.

[0083] The work function layer may also be made of or contain hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminum, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. The thickness and / or composition of the work function layer can be fine-tuned to adjust the work function level.

[0084] The work function layer may be deposited over the gate dielectric layer 150 using an ALD process, a CVD process, a PVD process, an electroplating process, an electrochemical plating process, another suitable process, or a combination thereof.

[0085] In some embodiments, a barrier layer is formed prior to the work function layer and disposed between the gate dielectric layer 150 and the subsequently formed work function layer 152. The barrier layer may also be used to prevent diffusion between the gate dielectric layer 150 and the subsequently formed work function layer 152. The barrier layer may be made of or include a metal-containing material. The metal-containing material may include titanium nitride, tantalum nitride, another suitable material, or a combination thereof. The barrier layer may be deposited using an ALD process, a CVD process, a PVD process, an electroplating process, an electrochemical plating process, another suitable process, or a combination thereof.

[0086] In some embodiments, different portions of the metal gate stacks 156 enclose the semiconductor nanostructures 104a'-104d' of different devices, such as PMOS devices and NMOS devices. Different portions of the metal gate stacks 156 thus have different work function layer types or different combinations of work function layers. Multiple deposition processes and multiple patterning processes may be used to selectively form different work function layers 152 at different portions of the metal gate stacks 156.

[0087] In some embodiments, the conductive fills 154 are made of or include a metal material. The metal material may include tungsten, ruthenium, aluminum, copper, cobalt, another suitable material, or a combination thereof. A conductive layer used to form the conductive fill may be deposited over the work function layer using a CVD process, an ALD process, a PVD process, an electroplating process, an electrochemical plating process, a spin-on coating process, another suitable process, or a combination thereof.

[0088] In some embodiments, a barrier layer is formed over the work function layer prior to the formation of the conductive layer used to form the conductive fill. The barrier layer may be used to prevent the subsequently formed conductive layer from diffusing or penetrating into the work function layer. The barrier layer may be made of or include tantalum nitride, titanium nitride, another suitable material, or a combination thereof. The barrier layer may be deposited using an ALD process, a PVD process, an electroplating process, an electrochemical plating process, another suitable process, or a combination thereof.

[0089] Subsequently, according to some embodiments, a planarization process is performed to remove the portions of the metal gate stack layers outside the trenches 142. Thus, the remaining portions of the metal gate stack layers form the metal gate stacks 156, as shown in the Fig. 2G and Fig. 3K shown.

[0090] Subsequently, an interconnect structure is formed over the metal gate stacks 156 and the dielectric layer 140. The interconnect structure includes multiple dielectric layers and multiple conductive elements. The conductive elements may include conductive contacts, conductive vias, and conductive traces. The interconnect structure may be used to establish electrical connection between various devices formed below or within the interconnect structure. Formation of the interconnect structure may include multiple deposition processes, multiple patterning processes, and multiple planarization processes.

[0091] As in Fig. 3L, according to some embodiments, after the formation of the interconnect structure, the structure is flipped. For simplicity, the interconnect structure, the dielectric layer 140, and the upper portions of the metal gate stacks 156 are shown in Fig. 3L not shown.

[0092] As in Fig. As shown in Figure 3M, according to some embodiments, the semiconductor layers 100a and 100b of the semiconductor substrate 100 are removed. This exposes the semiconductor fin 101B laterally surrounded by the insulation structure 115. The semiconductor layers 100a and 100b may be removed using planarization processes. The planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, another suitable process, or a combination thereof.

[0093] As in Fig. As shown in Figure 3N, according to some embodiments, mask layers 310 and 312 are formed sequentially over semiconductor fin 101B. Mask layer 310 may be made of or include silicon nitride, silicon oxynitride, another suitable material, or a combination thereof. Mask layer 312 may be made of or include silicon oxide or another suitable material.

[0094] As in Fig. 30, according to some embodiments, one or more photolithography processes and one or more etching processes are used to pattern the mask layers 310 and 312. With the mask layers 310 and 312 as an etch mask, one or more etching processes are used to partially remove the semiconductor layer 100c of the semiconductor substrate 100 from the back surface. As a result, a contact opening 314 is formed, exposing the protection structures 302 and the sidewalls of the semiconductor nanostructures 104a', as shown in Fig. 30. Due to the protection structures 302, the contact opening 314 may be self-aligned with the doped epitaxial section 138. In some embodiments, the contact opening 314 is wider than the doped epitaxial section 138.

[0095] In some embodiments, the undoped epitaxial portion 304 is also removed during the etching process to form the contact opening 314. As a result, the lower insulating element 306, which may act as a stop layer, is also exposed through the contact opening 314.

[0096] As in Fig. 3P, according to some embodiments, a dielectric layer 316 is deposited over the Fig. 30. The dielectric layer 316 extends along the sidewalls and the bottom of the contact opening 314. In some embodiments, the dielectric layer 316 is in direct contact with the semiconductor fin 101B, the protection structures 302, and the semiconductor nanostructures 104a'.

[0097] In some embodiments, the dielectric layer 316 is substantially oxygen-free. The dielectric layer 316 may be made of or include silicon nitride, carbonaceous silicon nitride, another suitable material, or a combination thereof. However, embodiments of the disclosure have many variations. In some further embodiments, the dielectric layer 316 includes oxygen. For example, the dielectric layer 316 is made of or includes silicon oxynitride, carbonaceous silicon oxynitride, another suitable material, or a combination thereof. The dielectric layer 316 may be deposited using a CVD process, an ALD process, another suitable process, or a combination thereof.

[0098] As in Fig. As shown in Figure 3Q, according to some embodiments, the dielectric layer 316, the lower insulating element 306, and the doped epitaxial section 138 are partially removed. This deepens the contact opening 314. One or more etch processes may be used to deepen the contact opening 314.

[0099] Subsequently, a cleaning process is performed to clean the exposed surface of the doped epitaxial section 138 prior to subsequent formation of metal-semiconductor interconnect elements on the doped epitaxial section 138.

[0100] As in Fig. 3R, according to some embodiments, a metal-semiconductor interconnect element 318 is formed on the exposed surface of the doped epitaxial portion 138. In some embodiments, prior to forming the metal-semiconductor interconnect element 318, the exposed doped epitaxial portion 138 is altered to assist in the subsequent formation of the metal-semiconductor interconnect element 318. In some embodiments, one or more ion implantation processes are used to reduce the crystallinity of the surface portion of the doped epitaxial portion 138, thereby allowing a subsequently deposited metal material to more easily react with the altered surface portions. The formation of the metal-semiconductor interconnect element 318 may thus be facilitated.

[0101] In some embodiments, the implantation process consists of a plasma doping process. Plasma may be introduced into the contact opening 314 to modify the exposed surface portion of the doped epitaxial section 138. In some embodiments, the reaction gas used in the implantation process includes a silicon-containing gas, a germanium-containing gas, an argon-containing gas, a helium-containing gas, another suitable gas, or a combination thereof.

[0102] In some embodiments, a heat treatment is performed after a metal-containing material is deposited onto the doped epitaxial section 138. In some further embodiments, a metal-containing material is deposited onto the doped epitaxial section 138 while the doped epitaxial section 138 is heated. In some embodiments, the metal-containing material is deposited using a CVD process, an ALD process, or a combination thereof.

[0103] With the heat treatment, the thermal energy can help trigger a chemical reaction between the surface portion of the doped epitaxial section 138 and the metal-containing material. Thus, the surface portion of the doped epitaxial section 138 reacts with the metal-containing material, and they are converted into the metal-semiconductor interconnect element 318.

[0104] The metal-semiconductor interconnect element 318 may be made of or include a metal silicide material, a metal-containing silicon germanium material, a metal-containing germanium material, another suitable material, or a combination thereof. For example, the metal-semiconductor interconnect element 318 includes TiSi, MoSi, RuSi, ZrSi, another suitable material, or a combination thereof.

[0105] In some embodiments, during the heat treatment, the doped epitaxial section 138 is heated to a temperature ranging from about 390°C to about 440°C. In some further embodiments, the doped epitaxial section 138 is heated to an elevated temperature before the metal-containing material is dispensed (or deposited) onto the doped epitaxial section 138. Subsequently, the doped epitaxial section 138 is maintained at the elevated temperature while the metal-containing material is dispensed (or deposited). The elevated temperature may be between about 390°C and about 440°C.

[0106] In some embodiments, when depositing the metal-containing material to form the metal-semiconductor interconnect 318, the metal-containing material is also deposited to form a metal layer on sidewalls of the contact opening 314. The metal layers may be made of or include titanium, cobalt, ruthenium, molybdenum, nickel, tantalum, tungsten, platinum, another suitable material, or a combination thereof. In some embodiments, after the formation of the metal-semiconductor interconnect 318, the portions of the metal layers that have not reacted with the doped epitaxial portion 138 are removed. One or more etching processes may be used to remove the metal layer.

[0107] However, embodiments of the disclosure are not limited thereto. Many variations and / or modifications may be made to embodiments of the disclosure. In some further embodiments, the metal-semiconductor interconnect element 318 is not formed.

[0108] Subsequently, according to some embodiments, a conductive layer 320 is deposited over the metal-semiconductor interconnect element 318, overfilling the contact opening 314, as shown in Fig. 3R. The conductive layer 320 may be made of or include tungsten, ruthenium, molybdenum, cobalt, titanium, tantalum, tungsten, another suitable material, or a combination thereof. The conductive layer 320 may be deposited using an ALD process, a CVD process, a PVD process, an electroplating process, an electrochemical plating process, another suitable process, or a combination thereof.

[0109] As in Fig. 3S, according to some embodiments, a planarization process is used to remove the conductive layer 320 outside the contact opening 314. As a result, the remaining portions of the conductive layer 320 in the contact opening 314 form a backside conductive contact 322, as shown in Fig. 3S. In some embodiments, mask layers 310 and 312 are also removed during the planarization process. The above-mentioned planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, another suitable process, or a combination thereof.

[0110] In some embodiments, the backside conductive contact 322 is electrically connected to the doped epitaxial section 138. In some embodiments, the backside conductive contact 322 extends across the opposing surfaces of the protection structures 302 and the opposing surfaces of the semiconductor nanostructures 104a', as shown in Fig. 3S shown.

[0111] As in Fig. 3T, according to some embodiments, a backside interconnect structure 324 is formed over the semiconductor fin 101B and the backside conductive contact 322. The backside interconnect structure 324 includes a plurality of dielectric layers and a plurality of conductive elements. The conductive elements may include conductive vias and traces. The backside interconnect structure 324 may be used to establish electrical connection between various backside conductive contacts and various devices. Formation of the interconnect structure may include a plurality of deposition processes, a plurality of patterning processes, and a plurality of planarization processes.

[0112] Fig. 4 is a cross-sectional view of a stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Fig. 4 shows a semiconductor device structure similar to that shown in Fig. 3T. The upper portions of the metal gate stacks 156 and a front-side interconnect structure 402 are shown in Fig. 4. In some embodiments, a front-side conductive contact 408 is formed. The front-side conductive contact 408 may be electrically connected to the epitaxial structure 138. In some embodiments, a metal-semiconductor interconnect element 406 is formed between the front-side conductive contact 408 and the epitaxial structure 138. A dielectric layer 404 may be formed between the front-side conductive contact 408 and the gate spacer 128'.

[0113] The front-side interconnect structure 402 includes multiple dielectric layers and multiple conductive elements. The conductive elements may include conductive vias and traces. The front-side interconnect structure 402 may be used to establish electrical connection between various back-side conductive contacts and various devices. Formation of the interconnect structure may include multiple deposition processes, multiple patterning processes, and multiple planarization processes. In some embodiments, the average line width of the conductive elements in the back-side interconnect structure 324 is larger than the average line width of the conductive elements in the front-side interconnect structure 402.

[0114] As in the Fig. 3T and Fig. 4, in some embodiments, the backside conductive contact 322 is separated from the metal gate stacks 156 by the protection structures 302. Short circuits between the backside conductive contact 322 and the metal gate stacks 156 are significantly reduced. Due to the protection structures 302, it is not necessary to form a narrow backside conductive contact to prevent a short circuit between the backside conductive contact 322 and the metal gate stacks 156. As shown in the Fig. 3T and Fig. As shown in Figure 4, the backside conductive contact 322 is wider than the doped epitaxial section 138. The wider backside conductive contact 322 thus has better conductivity. The performance and reliability of the semiconductor device structure have been significantly improved.

[0115] Many variations and / or modifications may be made to embodiments of the disclosure. Fig. 5A to 5E are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. As in Fig. 5A, a structure is formed which is similar to that shown in Fig. 3C. Processes similar to those shown in Fig. 3A to 3C can be used to identify the Fig. 5A. In some embodiments, the semiconductor layer 102a' has a higher atomic fraction of germanium than the structure shown in Fig. 3C shown semiconductor layer 102a.

[0116] As in Fig. 5B, according to some embodiments, the semiconductor layers 102a' and 102b-102d are laterally etched. As a result, the edges of the semiconductor layers 102b-102d are recessed from the edges of the semiconductor layers 104a-104d. In some embodiments, the semiconductor layer 102a' is completely removed. As shown in Fig. As shown in Figure 5B, according to some embodiments, recesses 132 and 532' are formed simultaneously by lateral etching of semiconductor layers 102a' and 102b-102d. Recesses 132 may be used to receive internal spacers that will be formed later. Recesses 532' may be used to receive protection structures that will be formed later.

[0117] In some embodiments, each of the recesses 532' is deeper than each of the recesses 132. In some embodiments, the semiconductor layer 102a' has a higher atomic fraction of germanium than the semiconductor layers 102b-102d. Therefore, during the laterally etching of the semiconductor layers 102a' and 102b-102d, the semiconductor layer 102a' is laterally etched at a higher etch rate than the semiconductor layers 102b-102d. This forms recesses 532' that are deeper than the recesses 132.

[0118] As in Fig. 5C, according to some embodiments, is similar to the Fig. 3E, the insulating layer 134 is deposited. The insulating layer 134 overfills the recesses 132 and 532'. In some embodiments, the insulating layer 134 completely fills the recesses 532'.

[0119] As in Fig. As shown in Figure 5D, according to some embodiments, an etching process is used to partially remove the insulating layer 134. The portions of the insulating layer 134 outside the recesses 132 may be removed. The remaining portions of the insulating layer 134 in the recesses 132 form internal spacers 136. The remaining portions of the insulating layer 134 in the recesses 532' form protective structures 502. The etching process may include a dry etching process, a wet etching process, or a combination thereof.

[0120] In some embodiments, each of the protective structures 502 is wider than each of the inner spacers 136, as shown in Fig. 5D. Since, in some embodiments, the protective structures 502 and the inner spacers 136 are portions of the same material layer (i.e., the insulating layer 134), the protective structures 502 and the inner spacers 136 have the same composition.

[0121] Subsequently, processes can be carried out that meet the requirements set out in the Fig. 3G to 3T. This, according to some embodiments, Fig. The structure shown in Figure 5E is formed.

[0122] Many variations and / or modifications may be made to embodiments of the disclosure. Fig. 6A to 6B are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. As in Fig. 6A, a structure is formed which is similar to that shown in Fig. 5C. In some embodiments, the insulating layer 134 does not completely fill the recesses formed between the semiconductor fin 101B and the semiconductor layer 104a. In some embodiments, one or more cavities 602 are formed in the insulating layer 134, as shown in Fig. 6A shown.

[0123] Subsequently, processes can be carried out that meet the requirements Fig. 5D to 5E. This, according to some embodiments, Fig. 6B. In some embodiments, one or more cavities 602 are formed in the protective structures 502.

[0124] Many variations and / or modifications may be made to embodiments of the disclosure. Fig. 7 is a cross-sectional view of a stage of a process for forming a portion of a semiconductor device structure according to some embodiments. As shown in Fig. 7, a structure is formed which is similar to that shown in Fig. 3T. In some embodiments, the insulating layer used to form the protective structure 302 does not completely fill the recesses used to receive the protective structures 32. In some embodiments, one or more cavities 602 are formed in the protective structure 302, as shown in Fig. 7 shown.

[0125] In some embodiments, each of the protective structures is wider than each of the inner spacers. However, embodiments of the disclosure are not so limited. In some further embodiments, each of the protective structures is substantially as wide as each of the inner spacers.

[0126] Fig. 8 is a cross-sectional view of a stage of a process for forming a portion of a semiconductor device structure according to some embodiments. In some embodiments, the atomic fraction of germanium of semiconductor layer 102a is substantially equal to that of semiconductor layers 102b-102d. Therefore, the recesses used to receive protection devices 802 are substantially as deep as the recesses used to receive internal spacers 136. In some embodiments, each of protection structures 802 is substantially as wide as each of internal spacers 136.

[0127] In some embodiments, the protective structures and the inner spacers are formed from the same insulating layer. Therefore, the protective structures and the inner spacers are made of the same material. However, embodiments of the disclosure are not limited thereto. Many variations and / or modifications may be made for embodiments of the disclosure. In some further embodiments, the protective structures and the inner spacers are made of different materials.

[0128] The Fig. 9A to 9B are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. As in Fig. As shown in Figure 9A, a structure is formed which is similar to that shown in Fig. 3E is similar to or identical to that shown.

[0129] As in Fig. As shown in Figure 9B, according to some embodiments, an etching process is used to partially remove the insulating layer 134. The remaining portions of the insulating layer 134 form the protection structures 302. The portions of the insulating layer 134 that originally fill the recesses 132 may be partially or completely removed. In some embodiments, the semiconductor layers 102b-102d are exposed after the partial removal of the insulating layer 134.

[0130] As in Fig. As shown in Figure 9C, according to some embodiments, inner spacers 902 are formed in the recesses 132. In some embodiments, the inner spacers 902 and the protection structures 302 are made of different materials. In some embodiments, the inner spacers 902 have a lower dielectric constant than the protection device 302. In some embodiments, the inner spacers 902 have a higher atomic fraction of carbon than the protection structures 302.

[0131] Similar to the Fig. In the embodiments shown in Figure 3E, in some embodiments, a second insulating layer is deposited overfilling the recesses 132. The second insulating layer and the insulating layer 134 are made of different materials. In some embodiments, the second insulating layer has a lower dielectric constant than the insulating layer 134. Subsequently, an etching process may be used to remove the portion of the second insulating layer that lies outside the recesses 132. As a result, the remaining portions of the second insulating layer form the inner spacers 902.

[0132] Subsequently, processes can be carried out that meet the requirements Fig. 3G to 3T. This, according to some embodiments, Fig. The structure shown in Figure 9D is formed.

[0133] Many variations and / or modifications may be made to embodiments of the disclosure. In some further embodiments, the semiconductor fins are replaced by dielectric structures or thermally conductive structures. In some embodiments, the dielectric structures or thermally conductive structures have high thermal conductivity.

[0134] The Fig. 10A to 10B are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure according to some embodiments. As in Fig. 10A, a structure is formed which is similar to that shown in Fig. 3M. With reference to Fig. 2G, the semiconductor fin 101B is laterally surrounded by the insulating structure 115.

[0135] Subsequently, according to some embodiments, the semiconductor fin 101B is removed, as shown in Fig. 10B. This forms a trench 1002. In some embodiments, the trench 1002 is laterally surrounded by the isolation structure 115.

[0136] As in Fig. 10C, according to some embodiments, a dielectric structure (or a thermally conductive structure) 1004 may be formed to fill the trench 1002. In some embodiments, the dielectric structure 1004 may be laterally surrounded by the isolation structure 115. In some embodiments, a dielectric layer (or a layer of thermally conductive material) may be deposited to overfill the trench 1002. Subsequently, a planarization process may be used to remove the portion of the dielectric layer (or the layer of thermally conductive material) that lies outside the trench 1002. As a result, the remaining portion of the dielectric layer (or the layer of thermally conductive material) may form the dielectric structure (or the thermally conductive structure, respectively) 1004.

[0137] The dielectric layer (or the layer of thermally conductive material) may be made of or contain aluminum oxide, aluminum nitride, titanium oxide, zinc oxide, silicon carbide, silicon oxide, another suitable material, or a combination thereof. The dielectric layer (or the layer of thermally conductive material) may be deposited using a CVD process, an ALD process, another suitable process, or a combination thereof.

[0138] Subsequently, processes can be carried out that meet the requirements Fig. 3N to 3T. This, according to some embodiments, Fig. 10D is formed. The dielectric structure (or thermally conductive structure) 1004 can contribute to improving the heat dissipation of the semiconductor device structure. The performance and reliability of the semiconductor device structure can be improved.

[0139] Many variations may be made and / or modifications may be made for embodiments of the disclosure. In some embodiments, there are three channel structures (such as semiconductor nanostructures 104b'-104d') formed adjacent to the nearby doped epitaxial section 138. However, embodiments of the disclosure are not so limited. Many variations may be made and / or modifications may be made for embodiments of the disclosure. In some embodiments, the total number of channel structures formed adjacent to the nearby doped epitaxial section 138 is greater than three. In some further embodiments, the total number of channel structures formed adjacent to the nearby doped epitaxial section 138 is less than three.The total number of channel structures formed adjacent to the nearby doped epitaxial section 138 can be tailored to requirements. For example, the total number of channel structures formed adjacent to the nearby doped epitaxial section 138 can be between 2 and 10. The channel structures can have many applicable profiles. The channel structures can include nanosheets, nanowires, or other suitable nanostructures.

[0140] In embodiments of the disclosure, a semiconductor device structure is formed with a backside conductive contact electrically connected to an epitaxial structure. A lower inner spacer may act as a protection structure to enable self-alignment between the backside conductive contact and the epitaxial structure. With the protection structure, the backside conductive contact can be made wider to achieve better conductivity. Short circuits between the backside conductive contact and the gate stack are also prevented by the protection structure. The performance and reliability of the semiconductor device structure are thereby improved.

[0141] According to some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a base layer, and the fin structure includes a plurality of sacrificial layers and a plurality of semiconductor layers alternately disposed over the base layer. The method also includes partially removing the fin structure to form an opening exposing side surfaces of the semiconductor layers, the sacrificial layers, and the base layer. The method further includes partially or completely removing the base layer from the side surface of the base layer to form a recess, forming a protective structure in the recess, and forming an epitaxial structure filling the opening.Furthermore, the method comprises partially removing the substrate from a back surface of the substrate such that a contact opening is formed that exposes the protective structure and extends toward the epitaxial structure. The method comprises forming a back conductive contact in the contact opening.

[0142] According to some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a fin structure over a substrate, and the fin structure has a plurality of sacrificial layers and a plurality of semiconductor layers arranged alternately. The method also includes partially removing the fin structure to form an opening exposing side surfaces of the semiconductor layers and the sacrificial layers, and partially removing the sacrificial layers from the side surfaces of the sacrificial layers to form recesses and a bottom recess. The method further includes forming internal spacers in the recesses, forming a protective structure in the bottom recess, and forming an epitaxial structure filling the opening.Furthermore, the method comprises partially removing the substrate from a back surface of the substrate such that a contact opening is formed exposing the protective structure, and forming a back conductive contact in the contact opening. The back conductive contact is electrically connected to the epitaxial structure.

[0143] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a base semiconductor nanostructure and a plurality of semiconductor nanostructures over the base semiconductor nanostructure. The semiconductor device structure also includes a gate stack enclosing each of the semiconductor nanostructures and an epitaxial structure connecting the semiconductor nanostructures. The semiconductor device structure further includes an internal spacer between the epitaxial structure and the gate stack and a backside conductive contact electrically connected to the epitaxial structure. The backside conductive contact extends through opposing surfaces of the base semiconductor nanostructure. Furthermore, the semiconductor device structure includes a protection structure, and the base semiconductor nanostructure is located between the protection structure and the semiconductor nanostructures.

[0144] The foregoing describes features of various embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should recognize that they can readily use the present disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

[1] A method of forming a semiconductor device structure, comprising: Forming a fin structure over a substrate, the fin structure comprising a base layer, and the fin structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers alternately disposed over the base layer; partially removing the fin structure so as to form an opening exposing side surfaces of the semiconductor layers, the sacrificial layers and the base layer; partially or completely removing the base layer from the side surface of the base layer so as to form a recess; Formation of a protective structure in the depression; Forming an epitaxial structure that fills the opening; partially removing the substrate from a back surface of the substrate such that a contact opening is formed which exposes the protective structure and extends towards the epitaxial structure; and Forming a rear conductive contact in the contact opening. [2] A method of forming a semiconductor device structure according to claim 1, further comprising: partially removing the sacrificial layers from the side surfaces of the sacrificial layers so that second depressions are formed, and Forming internal spacers in the second recesses. [3] A method of forming a semiconductor device structure according to claim 2, wherein the recess and the second recesses are formed simultaneously. [4] A method of forming a semiconductor device structure according to claim 2 or 3, wherein the sacrificial layers and the base layer contain silicon and germanium, and the base layer has a higher atomic fraction of germanium than the sacrificial layers. [5] A method of forming a semiconductor device structure according to any one of claims 2 to 4, further comprising: Forming an insulating layer in the opening that overfills the recess and the second recesses; and partially removing the insulating layer, wherein a first remaining portion of the insulating layer in the recess forms the protective structure, and second remaining portions of the insulating layer in the second recesses form the inner spacers. [6] A method of forming a semiconductor device structure according to any one of claims 2 to 5, wherein the recess is deeper than each of the second recesses. [7] A method of forming a semiconductor device structure according to any one of claims 2 to 6, wherein the protective structure is wider than each of the inner spacers. [8] A method of forming a semiconductor device structure according to any one of the preceding claims, further comprising: Forming a dummy gate stack over the fin structure before forming the opening, wherein the base layer is completely removed after the dummy gate stack is formed and before the protection structure is formed; Removing the dummy gate stack and the sacrificial layers after forming the epitaxial structure, wherein remaining portions of the semiconductor layers form a plurality of semiconductor nanostructures; and Forming a metal gate stack that encloses the semiconductor nanostructures. [9] A method of forming a semiconductor device structure according to any one of the preceding claims, further comprising: Forming a dielectric layer along sidewalls of the contact opening before forming the back conductive contact. [10] A method of forming a semiconductor device structure according to any one of the preceding claims, further comprising: Forming an insulating structure laterally surrounding a lower portion of the fin structure before forming the opening, wherein a top surface of the base layer is closer to the substrate than a top surface of the insulating structure. [11] A method of forming a semiconductor device structure, comprising: Forming a fin structure over a substrate, the fin structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers arranged alternately; partially removing the fin structure so as to form an opening exposing side surfaces of the semiconductor layers and the sacrificial layers; partially removing the sacrificial layers from the side surfaces of the sacrificial layers so that recesses and a lower recess are formed; Forming internal spacers in the recesses; Formation of a protective structure in the lower depression; Forming an epitaxial structure that fills the opening; partially removing the substrate from a back surface of the substrate such that a contact opening is formed exposing the protective structure; and Forming a back-side conductive contact in the contact opening, wherein the back-side conductive contact is electrically connected to the epitaxial structure. [12] A method of forming a semiconductor device structure according to claim 11, wherein forming the epitaxial structure comprises: Forming an undoped epitaxial portion over a bottom surface of the opening, wherein the protective structure is lower than a top surface of the undoped epitaxial portion and higher than a bottom surface of the undoped epitaxial portion; Forming a stop layer over the undoped epitaxial section; and Forming a doped epitaxial section over the stop layer. [13] A method of forming a semiconductor device structure according to claim 12, further comprising: Removing the undoped epitaxial section so that the contact opening exposes the protective structure and the stop layer; and Forming a dielectric layer over sidewalls and the bottom of the contact opening. [14] A method of forming a semiconductor device structure according to claim 13, further comprising: Partial removal of the dielectric layer, the stop layer and the doped epitaxial section to deepen the contact opening before forming the backside conductive contact. [15] A method of forming a semiconductor device structure according to claim 14, further comprising: Forming a metal-semiconductor interconnect element on the doped epitaxial portion exposed from the contact opening after the contact opening has been recessed and before the backside conductive contact is formed. [16] A semiconductor device structure comprising: a basic semiconductor nanostructure; multiple semiconductor nanostructures over the base semiconductor nanostructure; a gate stack enclosing each of the semiconductor nanostructures; an epitaxial structure connecting the semiconductor nanostructures; an inner spacer between the epitaxial structure and the gate stack; a backside conductive contact electrically connected to the epitaxial structure, the backside conductive contact extending through opposite surfaces of the base semiconductor nanostructure; and a protective structure, wherein the base semiconductor nanostructure lies between the protective structure and the semiconductor nanostructures. [17] The semiconductor device structure of claim 16, wherein the protective structure and the inner spacer are made of a same material. [18] A semiconductor device structure according to claim 16 or 17, further comprising: a dielectric layer extending along a sidewall of the rear conductive contact. [19] The semiconductor device structure of claim 18, wherein the dielectric layer is in direct contact with the protective structure and the base semiconductor nanostructure. [20] A semiconductor device structure according to any one of claims 16 to 19, further comprising: a semiconductor layer, wherein the base semiconductor nanostructure is located between the semiconductor layer and the semiconductor nanostructures, and wherein the semiconductor layer is adjacent to the protective structure.

Images