DIE-BOND STRUCTURE AND METHOD FOR MAKING THE SAME

Abstract

The Bond structure (100), comprising: a carrier substrate (110); a sintered layer (108) on the support substrate (110); a nano-twin layer (106) on the sintered layer (108), wherein a surface of the nano-twin layer (106) has a [111] crystal orientation with a density of more than 80%, wherein the nano-twin layer (106) comprises parallel twin boundaries, the parallel twin boundaries have more than 40% [111] crystal orientation and the distance between the parallel twin boundaries is 10 to 100 nm; an adhesion layer (104) on the nano-twin layer (106) and a chip (102) on the adhesion layer (104).

Description

TECHNICAL AREA

[0001] The disclosure relates to die-bond technology, in particular to die-bond structures with nano-twin layers and to a method for their production. BACKGROUND DESCRIPTION OF THE STATE OF THE TECHNOLOGY

[0002] The packaging of integrated circuits (ICs) and high-power LEDs (light-emitting diodes) involves a die-bonding step between the chip and the ceramic substrate. Current die-bonding technologies include eutectic bonding, gluing, soldering, and similar processes, which cannot withstand the high temperatures encountered during chip processing and exhibit low reliability. Therefore, silver sintering and copper sintering are becoming increasingly popular die-bonding technologies, particularly for packaging power modules for electric vehicles. However, the thermal stresses generated by the high temperatures during die bonding in silver and copper sintering cause extremely severe damage, so the bond strength is generally below 20 MPa.

[0003] The back of the chip must be coated with a metal layer before bonding, regardless of whether it is a power IC module or a high-power LED package. The traditional structure of the backside metal layer is Ti / Ni / Ag, with the outermost silver layer consisting of equiaxial coarse grains and grain boundaries exhibiting chaotic lattice orientations.

[0004] Taiwanese patent no. I432613 discloses a method for electroplating copper nanotwins. Taiwanese patent no. I703226 also discloses a method for sputtering silver nanotwins. Furthermore, Taiwanese patent no. I810631 discloses a method for vapor deposition of silver nanotwins by ion beam bombardment. These techniques have confirmed that a high-density (111) crystal orientation of the nanotwin layers can be achieved and that the atomic diffusion rate of the (111) crystal orientation is 3 to 5 orders of magnitude higher than that of the (100) and (110) crystal orientations.

[0005] Taiwanese patent no. 1686518 discloses a method for direct, low-temperature bonding using copper nanotwins, applying the aforementioned method. Taiwanese patent no. I432613 further discloses a method for direct, low-temperature bonding between a chip and a ceramic substrate using silver nanotwins. However, the bond interface of existing direct stack bonding technology using nanotwins has a thin-film structure of less than 10 mm, and the bond strength is generally only 20 to 40 MPa, raising significant concerns regarding reliability.In the existing direct stacking process using nanotwins, die bonding between the chip and ceramic substrate involves inserting the nanotwin film directly between the chip and the ceramic substrate. However, this method is prone to cracking at the bond interface and is not yet widely used, especially in high-performance automotive modules with extremely demanding requirements. US 2022 / 0 336 407 A1 proposes a die bonding structure using a silver nanotwined thin film. However, US 2022 / 0 336 407 A1 does not include a sintered layer on the substrate. SUMMARY

[0006] One embodiment of the present disclosure provides a die-bond structure. The die-bond structure comprises a support substrate, a sintered layer, a nano-twin layer, an adhesion layer, and a chip. The sintered layer is arranged on the support substrate. The nano-twin layer is located on the sintered layer, wherein the surface of the nano-twin layer has a

[111] crystal orientation with a density of more than 80%, wherein the nano-twin layer comprises parallel twin boundaries, the parallel twin boundaries having a

[111] crystal orientation of more than 40%, and the distance between the parallel twin boundaries is 10 to 100 nm. The adhesion layer is located on the nano-twin layer. The chip is located on the adhesion layer.

[0007] One embodiment of the present disclosure provides a method for producing a die-bonded structure. The method comprises providing a chip, forming an adhesion layer on the nano-twin layer, forming a nano-twin layer on the sintered layer, and performing a bonding process to connect the nano-twin layer to a support substrate via a sintered layer. The surface of the nano-twin layer has a

[111] crystal orientation with a density of more than 80%. The nano-twin layer comprises parallel twin boundaries. The parallel twin boundaries constitute more than 40% of the

[111] crystal orientation. The spacing between the parallel twin boundaries is 10 to 100 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure will be better understood from the following detailed description when read together with the accompanying figures. It should be noted that some features are not drawn to scale, as is common practice in the industry. Indeed, the dimensions of the various features may be arbitrarily enlarged or reduced to clarify their discussion. It is also emphasized that the accompanying drawings show only typical embodiments of this disclosure and are therefore not to be considered limiting, as the disclosure may equally apply to other embodiments. Fig. Figures 1-4 are cross-sectional views of different stages of the fabrication of a die-bond structure according to some embodiments. Fig. Figure 5 is a cross-sectional view of a die-bond structure according to a comparative example. Fig.Figure 6 is a focused ion beam (FIB) image showing a cross-sectional view of a SiC / Cr / Ni / Ag structure. Fig. Figure 7 is an FIB image showing a cross-sectional view of a SiC / Cr / nt-Ag structure according to some embodiments. Fig. Figures 8-9 are diagrams showing the bonding temperature in relation to the porosity of Ag sintered compounds according to some embodiments. Fig. Figures 10-11 are diagrams showing the bond temperature as a function of the bond strength in accordance with some embodiments. Fig. Figure 12 is an FIB image showing a cross-sectional view of a SiC / Ti / Ni / Ag structure. Fig. Figure 13 is an FIB image showing a cross-sectional view of a SiC / Ti / nt-Ag structure according to other embodiments. Fig.Figure 14 is a diagram showing the bonding temperature as a function of the porosity of sintered Ag compounds according to other embodiments. Fig. Figure 15 is a diagram showing the bond temperature in relation to the bond strength, in accordance with other embodiments. Fig. Figures 16-17 are diagrams showing the bonding temperature in relation to the bond strength according to further embodiments. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not to be understood as limitations. For example, the formation of a first feature over or on top of a second feature, which follows in the description, may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features do not have to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples of the present disclosure.This repetition serves for simplicity and clarity and does not in itself establish a relationship between the various designs and / or configurations discussed.

[0010] Several variations of the embodiments are described. In the different views and embodiments, identical elements are designated with the same numbers. However, it should be understood that additional steps may be provided before, during, and after the method, and that some of the described steps may be replaced or eliminated in other embodiments of the method.

[0011] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like can be used here for easier description to describe the relationship of one element or feature to another, as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented (rotated by 90 degrees or otherwise), and the spatially relative descriptors used here may be interpreted accordingly. When a spatially relative term, such as those listed above, is used to describe a first element in relation to a second element, the first element may lie directly on top of the other, or there may be intervening elements or layers.When an element or layer is described as lying “on” another element or layer, it is located directly on and in contact with the other element or layer.

[0012] The terms used in this description serve only to describe certain embodiments and are not intended to limit the inventive concept. A singular expression includes the plural expression unless it has a clearly different meaning in context. In this specification, terms such as "including," "with," or "comprising," etc., are to be understood as indicating the presence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the specification and are not intended to preclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or be added.

[0013] This disclosure provides a die-bond structure with a nano-twin layer that enables the chip to be bonded to the substrate at a low temperature of approximately 150°C to 350°C, ensuring process yield and the desired bond strength (e.g., higher than 20 MPa) of the power module package. The presence of a sintered layer avoids the problem of interface cracking associated with direct bonding of nano-twin layers (direct insertion of the nano-twin layer between the chip and the ceramic substrate), thus effectively improving the reliability of the packaged product. Furthermore, the adhesive layer can provide enhanced bond strength to prevent the nano-twin layer from detaching from the chip and has a lattice buffering effect to reduce the impact of the chip's lattice on the growth of the silver nano-twin structure.Furthermore, unwanted diffusion due to high temperatures can be avoided, so that the diffusion barrier layer between the adhesion layer and the nano-twin layer can be omitted, while at the same time preventing the possibility of a weak bond force between the nano-twin layer and the diffusion barrier layer.

[0014] Fig. Figures 1-4 are cross-sectional views of different stages of the manufacture of a die-bond structure 100 according to some embodiments.

[0015] As in Fig. Figure 1 shows that in one embodiment a chip 102 is provided. In one embodiment, the chip 102 can comprise an integrated power circuit (IC) or a light-emitting diode (LED). In one embodiment, the chip 102 can contain a single crystal: silicon (Si), germanium (Ge), silicon carbide (SiC), sapphire, gallium arsenide (GaAs), or gallium nitride (GaN).

[0016] As in Fig.In one embodiment, an adhesion layer 104 is formed on the chip 102, as shown in Figure 2.

[0017] In some embodiments, the adhesion layer 104 can provide a better bond strength between the chip 102 and the nano-twin layer 106 (as in Fig.(Figure 3) offer. The die bond structure 100 between the chip 102 and the nano-twin layer 106 is easily fractured due to insufficient bond strength between the nano-twin layer 106 and the chip 102. If the thickness of the nano-twin layer 106 is greater than 2 µm, the bond strength between the nano-twin layer 106 and the chip 102 decreases significantly in practice, and the nano-twin layer 106 can be easily detached. To address this problem, the present disclosure incorporates the formation of an adhesion layer 104 on the chip 102 before the nano-twin layer 106 is formed, ensuring that the nano-twin layer 106 and the wafer 102 remain in contact even when the nano-twin layer 106 is greater than 10 µm.

[0018] In some embodiments, the adhesion layer 104 has a lattice-buffering effect. If the nano-twin layer 106 is formed directly on the chip 102, the crystal orientation of the nano-twin layer 106 is influenced by the crystal orientation of the chip 102. For example, it is unlikely that a film formed on the chip with a (100) orientation will have a (111) crystal orientation. Therefore, the nano-twin layer 106 can be formed with a high twin density on the chip 102 with the (111) orientation, and the nano-twin structure formed on the chip 102 with the (110) orientation has an extremely low twin density. However, due to the lattice-buffering effect, the adhesion layer 104 of the present disclosure enables the formation of nano-twin structures with different crystal orientations on the chip 102.Regardless of whether the crystal orientation of chip 102 is (100), (110), or (111), the formed nano-twin layer 106 exhibits a

[111] crystal orientation to more than 40%. It should be clear that the presence of the adhesion layer 104 not only enables the formation of the nano-twin layer 106 with the (111) crystal orientation on the chip 102 with the aforementioned (100), (110), or (111) orientation, but also reduces the influence of the crystal orientation of other chip types (such as SiC, GaAs, etc.) on the crystal orientation of the subsequently deposited nano-twin layer structure.

[0019] In one embodiment, the adhesion layer 104 can contain titanium (Ti), aluminum-titanium (TiAl), chromium (Cr), or titanium-tungsten (TiW). In one embodiment, the thickness of the adhesion layer 104 is 0.01 µm to 10 µm (e.g., 0.02 µm to 0.2 µm). It is understood that the thickness of the adhesion layer 104 can be adjusted as appropriate depending on the practical application, but the disclosure is not limited thereto.

[0020] In some embodiments, the adhesion layer 104 can be formed by sputtering, evaporation, or electroplating. According to some embodiments, the adhesion layer 104 can be formed on the chip 102 by sputtering. In some embodiments, sputtering can be performed with a single sputtering gun or with multiple sputtering guns. The energy source for sputtering can be direct current (DC), DC pulse, RF, high-intensity pulsed magnetron sputtering (HIPIMS), or similar. The power can be, for example, about 100 W to about 200 W. The processing temperature is room temperature, but during the sputtering process it increases by about 50 °C to about 200 °C. The background pressure of the sputtering process is less than 1.33 × 10⁻⁶ -3 Pa. The working pressure can be, for example, approximately 1.33×10 -1The pressure can range from Pa to approximately 1.33 Pa. The argon flux can be, for example, approximately 10 sccm to approximately 20 sccm. The chuck rotational speed can be, for example, between 5 and 20 revolutions per minute. The bias voltage applied to the substrate during the sputtering process is approximately -100 V to approximately -200 V. The deposition rate of the adhesion layer 104 can be, for example, approximately 0.5 nm / s to approximately 3 nm / s. It should be understood that the sputtering process parameters described above can be adjusted accordingly depending on the practical application, and the disclosure is not limited thereto.

[0021] In other embodiments, the adhesion layer 104 can be formed on the chip 102 by vapor deposition. The background pressure of the vapor deposition process is below 1.33 × 10⁻⁶. -3 Pa, and the working pressure of the process can be, for example, about 1.33×10 -2 Pa up to about 6.7×10 -2The pressure may be Pa. The argon flow rate can be approximately 2 sccm to approximately 10 sccm. The chuck rotational speed can be, for example, between 5 and 20 revolutions per minute. The deposition rate of the adhesion layer 104 can be, for example, approximately 1 nm / s to approximately 5 nm / s. It should be understood that the parameters of the vapor deposition process described above can be adjusted accordingly depending on the practical application, and the disclosure is not limited thereto.

[0022] As in Fig.As shown in Figure 3, in one embodiment a nano-twin layer 106 is formed on the adhesion layer 104. The surface of the nano-twin layer 106 has a

[111] crystal orientation with a density of more than 80% (e.g., more than 85% or more than 90%). The nano-twin layer 106 contains parallel twin boundaries that have more than 40% (e.g., more than 50% or more than 60%)

[111] crystal orientation, and the distance between the parallel twin boundaries is 10 nm to 100 nm (e.g., 20 nm to 30 nm).

[0023] The formation of a twin structure is due to the accumulated strain energy within a material. This strain energy leads to a uniform shearing of the atoms in certain regions within the grain, resulting in lattice positions that are mirror images of each other. These twins can be recrystallization twins or strain twins. The mutually symmetrical interface is the twin boundary.

[0024] Twins are primarily formed in face-centered cubic (FCC) or hexagonal close-packed (HCP) crystalline materials with the densest lattice arrangement. In addition to the densest lattice structure, twins are more likely to form in materials with low stacking fault energy.

[0025] Twin boundaries are coherent crystal structures and are classified as special Σ3 and Σ9 grain boundaries with low interfacial energy. The crystal orientations are all {111}. Compared to high-angle grain boundaries formed by general annealing and recrystallization, the interfacial energy of twin boundaries is about 5% of that of high-angle grain boundaries (George E. Dieter, Mechanical Metallurgy, McGraw-Hill Book Company, 1976, pp. 135–141).

[0026] Due to the low interfacial energy of the twin boundaries, oxidation, sulfurization, and chloride ion corrosion can be avoided. Therefore, the thin silver nano-twin layer exhibits improved oxidation and corrosion resistance. Furthermore, the symmetrical lattice arrangement of the twins is less likely to impede electron transport. Consequently, the silver nano-twin layer exhibits better electrical and thermal conductivity. Because the twin boundaries inhibit dislocation movement, the materials can still exhibit high tensile strength. The properties of high tensile strength and electrical conductivity have been demonstrated in the copper thin film. (See Ultrahigh Strength and High Electrical Conductivity in Copper, Science, Vol. 304, 2004, pp. 422–426, by L. Lu, Y. Shen, X. Chen, L. Qian, and K. Lu).

[0027] Regarding high-temperature stability, twin boundaries are more stable than high-angle grain boundaries due to their lower interfacial energy. Twin boundaries are less prone to displacement at high temperatures. They can even block the movement of surrounding high-angle grain boundaries, preventing their movement. Consequently, grain growth is significantly reduced at high temperatures, thus maintaining the material's tensile strength even at elevated temperatures.

[0028] Regarding current reliability, because atoms exhibit a low diffusion rate when passing through twin boundaries with low interfacial energy, it is difficult to move atoms within the wire at high current density during the operation of electronic devices. This prevents electromigration, which commonly occurs when current flows through a wire. Twins have been shown to inhibit electromigration in thin copper films. (See Observation of Atomic Diffusion at Twin-Modified Grain Boundaries in Copper, Science, Vol. 321, 2008, pp. 1066–1069, by K.C. Chen, W.W. Wu, C.N. Liao, L.J. Chen, and K.N. Tu).

[0029] In one embodiment, the nano-twin layer 106 can contain silver, copper, or a silver-copper alloy. In one embodiment, the thickness of the nano-twin layer 106 is 0.1 µm to 100 µm (e.g., 0.5 µm to 10 µm). If the thickness of the nano-twin layer 106 is less than 0.1 µm, the nano-twin layer 106 can react rapidly with the bonding material and be completely consumed during the subsequent bonding process. An intermetallic compound formed in this way cannot be bonded to the chip 102, leading to interface detachment and rendering it unusable for applications. If, however, the thickness of the nano-twin layer 106 is greater than 100 µm, the nano-twin layer 106 can be easily detached from the adhesion layer 104 located on the chip 102.

[0030] In some embodiments, the nano-twin layer 106 can be formed by sputtering, evaporation, or electroplating. In some embodiments, sputtering can be performed with a single sputtering gun or with multiple sputtering guns. The energy source for sputtering can be direct current (DC), DC pulse, RF, or high-intensity pulsed magnetron sputtering (HIPIMS). The power used for sputtering the nano-twin layer 106 can range from approximately 100 W to approximately 500 W. The process temperature is room temperature, but increases by approximately 50 °C to approximately 200 °C during the sputtering process. The deposition rate of the nano-twin layer 106 can range from approximately 0.5 nm / s to approximately 3 nm / s. The background pressure of the sputtering process is less than 1.33 × 10⁻⁶ -3 Pa. The working pressure can be, for example, approximately 1m33×10 -1The pressure can range from Pa to approximately 1.33 Pa. The argon flux can be, for example, approximately 10 sccm to approximately 20 sccm. The chuck rotational speed can be, for example, between 5 and 20 rpm. The bias voltage applied to the substrate during the sputtering process is approximately -100 V to approximately -200 V. It should be understood that the sputtering process parameters described above can be adjusted according to practical application, and the disclosure is not limited thereto.

[0031] According to other embodiments, the nano-twin layer 106 can be formed on the adhesion layer 104 by vapor deposition. In some embodiments, the background pressure of the vapor deposition process is less than 1.33 × 10⁻⁶. -3 Pa, and the working pressure of the process can be, for example, about 1.33×10 -2 Pa up to about 6.7×10 -2The pressure can be approximately Pa. The argon flux can range from approximately 2 sccm to approximately 10 sccm. The chuck rotational speed can be, for example, between 5 and 20 revolutions per minute. The deposition rate of the nano-twin layer 106 can be, for example, approximately 1 nm / s to approximately 5 nm / s. During the deposition process, the nano-twin layer 106 is bombarded with ions. The voltage is approximately 10 V to approximately 300 V and the current approximately 0.1 A to approximately 1.0 A. It should be understood that the parameters of the deposition process described above can be adjusted accordingly depending on the practical application, and the disclosure is not limited thereto.

[0032] As in Fig. As shown in Figure 4, in one embodiment a bonding process is carried out to connect the nano-twin layer 106 to a support substrate 110 via a sintered layer 108. As shown in the figure, the chip 102, the adhesion layer 104 and the nano-twin layer 106 (as shown in Figure 4) are bonded together. Fig. 3 shown) turned over and over the sintered layer 108 onto the support substrate 110 (as shown in Fig. (4 shown) are stacked, and then die bonding is performed. In one embodiment, the die-bond structure 100 comprises a support substrate 110, a sintered layer 108 located on the support substrate 110, a nano-twin layer 106 located on the sintered layer 108, an adhesion layer 104 located on the nano-twin layer 106, and the chip 102 located on the adhesion layer 104.

[0033] In one embodiment, the bonding process may initially comprise applying the sintered material to the support substrate 110, bonding the nano-twin layer 106 to the sintered material, and heating the sintered material to form the sintered layer 108, but the present disclosure is not limited thereto. In other embodiments, the bonding process may initially comprise applying the sintered material to the nano-twin layer 106, bonding the support substrate 110 to the sintered material, and heating the sintered material to form the sintered layer 108.

[0034] In some embodiments, the sintered layer 108 can be used as a buffer to prevent interfacial cracking caused by the direct bond between the nano-twin layer 106 and the support substrate 110, thereby effectively improving the reliability of the packaged product. In one embodiment, the sintering material can contain a silver paste, a copper paste, or a silver-coated copper paste, so that after heating and sintering, a sintered layer 108 is formed containing silver, copper, or a silver-copper composite, respectively.

[0035] In one embodiment, the support substrate 110 can include a metallic heat sink, and the metallic heat sink can contain aluminum or copper. In another embodiment, the support substrate 110 can be a printed circuit board (PCB) with a copper circuit layer and a protective layer thereon, or a ceramic substrate with the copper circuit layer and the protective layer thereon. In some embodiments, the protective layer is located on the copper circuit layer to prevent the copper circuit layer from corroding (sulfidation or oxidation) due to atmospheric exposure. In one embodiment, the protective layer can contain an organic surface protectant (OSP) or a metal film such as Ni, Ni / Pd, Ni / Au, Ni / Pd / Au, or the like. In one embodiment, the ceramic substrate can contain aluminum oxide (Al₂O₃), aluminum nitride (AlN), or silicon nitride (Si₃N₄).

[0036] The bonding process can be carried out under vacuum, in a protective atmosphere, or in an ambient atmosphere. In some embodiments, the bonding process is performed under a pressure of 5 MPa to 30 MPa (such as 10 MPa to 25 MPa or 15 MPa to 20 MPa) and at a temperature of 100°C to 350°C (such as 100°C to 250°C, 150°C to 200°C, or 120°C to 180°C). Such a pressure range can prevent damage to both the chip 102 and the nano-twin layer 106. Although existing techniques can perform the bonding process under low pressure from 0.8 MPa to 3 MPa, it is necessary to perform chemical-mechanical polishing (CMP) of the nano-twin thin film before bonding to reduce surface roughness, which not only complicates the process but also destroys the nano-twin thin film.Under the premise of not damaging the chip 102 and the nano-twin layer 106, the present disclosure applies a pressure of approximately 5 MPa to approximately 30 MPa (higher than in existing techniques) to subject the aforementioned surface structure of the nano-twin layer 106 to plastic deformation at the nanoscale in order to achieve tight contact. This not only solves the problem of the surface roughness of the nano-twin layer 106, but also eliminates the need for additional complicated chemical-mechanical polishing steps in existing processes, thus significantly improving throughput and yield, and the disclosure is not limited thereto. In other embodiments, the die-bond structure 100 can be bonded without applying pressure.

[0037] Fig. Figure 5 is a cross-sectional view of a die-bond structure 200 according to a comparative example. The die-bond structure 200 is similar to the die-bond structure 100 in [reference missing]. Fig. 4, except that the die-bond structure 200 has a diffusion barrier layer 202 and an equiaxial coarse-grained layer 204 instead of the nano-twin layer 106 between the adhesion layer 104 and the sintered layer 108. To prevent the equiaxial coarse-grained layer 204 from diffusing towards the chip 102 or the adhesion layer 104 from diffusing towards the equiaxial coarse-grained layer 204 during the high-temperature bonding process, the comparative embodiment requires the insertion of a diffusion barrier layer 202 between the adhesion layer 104 and the sintered layer 108. Furthermore, the equiaxial coarse-grain layer 204 (e.g. silver) does not react with the diffusion barrier layer 202 (e.g. nickel) at its interface and thus impairs the adhesive force between them.

[0038] Once again on Fig.4. Referring to: In one embodiment, the adhesion layer 104 is in direct contact with the nano-twin layer 106. In other words, there is no diffusion barrier layer 202 between the adhesion layer 104 and the nano-twin layer 106. If the nano-twin layer 106 is present between the chip 102 and the support substrate 110, a low-temperature bonding process can be carried out, avoiding unwanted diffusion due to high temperatures. Therefore, mutual diffusion without the diffusion barrier layer 202 between the adhesion layer 104 and the nano-twin layer 106 can be avoided, while at the same time weak bond forces between the nano-twin layer 106 and the diffusion barrier layer 202 are prevented, and the disclosure is not limited thereto. In other embodiments, the die-bond structure 100 can include the diffusion barrier layer 202 if required.

[0039] The following describes the test results of examples and comparison examples for the die-bond structures of the present disclosure. Comparison example 1: SiC / Cr / Ni / Ag structure

[0040] Fig. Figure 6 is a focused ion beam (FIB) image showing a cross-sectional view of a SiC / Cr / Ni / Ag structure. The SiC / Cr / Ni / Ag structure is an example of the die-bond structure 200 in Fig. 5, in which the chip 102 is made of silicon carbide (SiC), the adhesion layer 104 is made of chromium (Cr), the diffusion barrier layer 202 is made of nickel (Ni) and the equiaxial coarse grain layer 204 is made of silver (Ag). Example 1: SiC / Cr / nt-Ag structure

[0041] Fig. Figure 7 is an FIB image showing a cross-sectional view of a SiC / Cr / nt-Ag structure according to some embodiments. The SiC / Cr / nt-Ag structure is an example of the die-bond structure 100 in Fig.4, where the chip 102 is made of silicon carbide (SiC), the adhesion layer 104 is made of chromium (Cr), and the nano-twinned layer 106 is made of silver (Ag). The term "nt-Ag" used here refers to nano-twinned silver (nt).

[0042] The structures of comparison example 1 and example 1, as described above, were each bonded in a vacuum with the silver paste (as sintered layer 108) and the direct bonded copper (DBC) ceramic substrate, and the sintering was carried out under a pressure of 10 MPa or without pressure at various bonding temperatures (such as 150°C, 180°C and 225°C).

[0043] As in Fig. 8 (using a pressure of 10 MPa) and Fig.Figure 9 (without the application of pressure) shows that Example 1 evidently reduces the porosity of Ag-sintered joints compared to Reference Example 1. During die bonding at 225°C without external pressure, the porosity decreased from 8.6% to 6.5%. Surprisingly, the sintered Ag porosity can be reduced to an extremely low value of 7.8% after die bonding by using the nano-twin layer 106, even at a low temperature of 150°C and a pressure of 10 MPa. [Measurement of bond strength]

[0044] After the matrix was bonded, the bond strength was measured using a Nordson weld strength tester (DAGE 4000). The results at a pressure of 10 MPa are shown in Table 1 and Fig. 10 is shown, while the results without printing are shown in Table 2 and Fig. 11 will be shown. [Table 1] Bond strength (MPa) temperature 150°C 180°C 225°C Comparative example 1 10,50 21,67 31,07 Example 1 33,10 38,60 45,20 [Table 2] Bond strength (MPa) temperature 150°C 180°C 225°C 300°C Comparative example 1 10,17 19,67 26,07 12,80 Example 1 12,57 21,60 28,20 16,00

[0045] According to Table 1, Table 2, Fig. 10 and Fig. Example 1 (SiC / Cr / nt-Ag) exhibited better bond strength after sintering at various bonding temperatures (such as 150°C, 180°C, 225°C, and 300°C) in a vacuum than comparison example 1 (SiC / Cr / Ni / Ag), regardless of whether a pressure of 10 MPa was applied or not. In other words, the die-bond structure 100 with the nano-twin layer 106 exhibits better bond strength under various bonding temperatures and conditions than the die-bond structure 200 with the equiaxial coarse-grained layer 204. Comparison example 2: SiC / Ti / Ni / Ag structure

[0046] Fig.Figure 12 is an FIB image showing a cross-sectional view of a SiC / Ti / Ni / Ag structure after die bonding. The SiC / Ti / Ni / Ag structure was bonded to the silver paste (as sintered layer 108) and the DBC ceramic substrate (as support substrate 110) in a vacuum, and sintering was carried out at a pressure of 10 MPa and a bonding temperature of 250°C. The SiC / Ti / Ni / Ag structure is another example of the die-bond structure 200 in Fig. 5, where the chip 102 is made of silicon carbide (SiC), the adhesion layer 104 is made of titanium (Ti), the diffusion barrier layer 202 is made of nickel (Ni), and the equiaxial coarse-grained layer 204 is made of silver (Ag). It should be noted that due to the absence of nanocrystalline silver in comparative example 2 (e.g., the nano-twin layer 106 in Fig.4) the silver in the equiaxial coarse-grain layer 204 did not diffuse into the sintered layer 108 during matrix bonding (as shown in Block 302), so that the bond strength between the equiaxial coarse-grain layer 204 and the sintered layer 108 was poor. Example 2: SiC / Ti / nt-Ag structure

[0047] Fig. Figure 13 is an FIB image showing a cross-sectional view of a SiC / Ti / nt-Ag structure after die bonding according to some embodiments. The SiC / Ti / nt-Ag structure was bonded to the silver paste (as sintered layer 108) and the DBC ceramic substrate (as support substrate 110) in a vacuum, and sintering was carried out at a pressure of 10 MPa and a bonding temperature of 250°C. The SiC / Ti / nt-Ag structure is another example of the die-bond structure 100 in Fig.4, where the chip 102 is made of silicon carbide (SiC), the adhesion layer 104 is made of titanium (Ti), and the nano-twin layer 106 is made of silver (Ag). It should be noted that due to the high diffusion rate properties of the silver nano-twin layer in Example 2 (e.g., the nano-twin layer 106 in Fig. 4) the nano-twin layer 106 diffused into the sintered layer 108 to promote the sintering reaction at the interface (as shown in Block 402) during die bonding, thus improving the bond strength between the nano-twin layer 106 and the sintered layer 108.

[0048] As in Fig.As shown in Figure 14, Example 2 exhibited a significant reduction in the porosity of the Ag sintered compounds compared to Reference Example 2. During low-temperature die bonding at 150°C, the porosity decreased from 18.4% to 10.9%. Surprisingly, the Ag sintered porosity can be reduced to an extremely low value of 1.2% after die bonding at 250°C by using the nano-twin layer 106. [Measurement of bond strength]

[0049] The structures of Comparative Example 2 and Example 2, as described above, were used to measure the bond strength using a Nordson weld strength tester (DAGE 4000). The results are shown in Table 3 and Fig. 15 shown. [Table 3] Bond strength (MPa) temperature 150°C 200°C 250°C Comparative example 2 11,0 15,3 19,9 Example 2 18,9 20,5 38,8

[0050] According to Table 3 and Fig.Example 2 (SiC / Ti / nt-Ag) exhibits better bond strength after sintering at various bonding temperatures (such as 150°C, 200°C, and 250°C) than comparison example 2 (SiC / Ti / Ni / Ag). In other words, the die-bond structure 100 with the nano-twin layer 106 shows better bond strength at various bonding temperatures than the die-bond structure 200 with the equiaxial coarse-grained layer 204.

[0051] It should be noted that after sintering the structure of Comparison Example 2 at a bonding temperature of 150°C, the bond strength was too low for practical application; the structure of Example 2, on the other hand, reached almost 20 MPa. Furthermore, after sintering the structures of Comparison Example 2 and Example 2 at a bonding temperature of 250°C, the bond strength of Example 2 was almost twice that of Comparison Example 2. Comparison example 3: Si / Ti / Ni / Cu structure

[0052] The Si / Ti / Ni / Cu structure is another example of the die-bond structure 200 in Fig. 5, in which the chip 102 is made of silicon (SiC), the adhesion layer 104 is made of titanium (Ti), the diffusion barrier layer 202 is made of nickel (Ni) and the axially aligned coarse grain layer 204 is made of copper (Cu). Example 3: Si / Ti / nt-Cu structure

[0053] The Si / Ti / nt-Cu structure is another example of the die-bond structure 100 in Fig. 4, in which the chip 102 is made of silicon (SiC), the adhesion layer 104 is made of titanium (Ti) and the nano-twin layer 106 is made of copper (Cu). [Measurement of bond strength]

[0054] The structures of Comparison Example 3 and Example 3, as described above, were bonded in a vacuum using the silver paste (as sintered layer 108) and the direct bonded copper (DBC) ceramic substrate. Sintering was performed under 15 MPa pressure and at various bonding temperatures (such as 150°C, 200°C, and 250°C). After matrix bonding, the bond strength was measured using a Nordson weld strength tester (DAGE 4000). The results obtained at 15 MPa pressure are shown in Table 4. Fig. 16 is shown, while the results without printing are shown in Table 5 and Fig. 17 will be shown. [Table 4] Bond strength (MPa) temperature 150°C 200°C 250°C Comparative example 3 15,88 28,67 32,33 Example 3 17,02 31,79 39,84 [Table 5] Bond strength (MPa) temperature 150°C 200°C 250°C Comparative example 3 10,00 18,16 20,22 Example 3 10,74 18,62 21,70

[0055] According to Table 4, Table 5, Fig. 16 and Fig.Example 17 shows that after sintering at various bonding temperatures (such as 150°C, 200°C, and 250°C) in a vacuum, Example 3 (Si / Ti / Ni / Cu) exhibits better bond strength than comparison example 3 (Si / Ti / Ni / Cu), regardless of whether a pressure of 15 MPa is applied or not. In other words, the die-bond structure 100 with the nano-twin layer 106 exhibits better bond strength at various bonding temperatures than the die-bond structure 200 with the equiaxial coarse-grained layer 204.

[0056] The embodiments of the present disclosure have several advantageous properties. The adhesion layer located between the chip and the nano-twin layer provides improved bond strength to prevent the nano-twin layer from detaching from the chip and has a lattice buffering effect to mitigate the impact of the chip's lattice on the growth of the silver nano-twin structure. The present disclosure provides a die-bond structure with a nano-twin layer that utilizes the high diffusion rate of the (111) crystal orientation of the nano-twin layer to indirectly promote the progress of the interfacial sintering reaction, thereby supporting the silver- or copper-sintered die-bond structure for packaging power IC modules and high-power LEDs. Not only can the bonding temperature be reduced, as with direct nano-twining, but the bond strength can also be increased.At the same time, the sintered layer avoids the problem of cracking at the interface in direct nano-twin bonding. Furthermore, unwanted diffusion due to high temperatures can be prevented, thus eliminating the need for a diffusion barrier layer between the adhesion layer and the nano-twin layer, while simultaneously preventing the possibility of weak bond strength between the nano-twin layer and the diffusion barrier layer.

[0057] Although the present disclosure has been described with reference to examples and preferred embodiments, it is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as will be apparent to the person skilled in the art).

Claims

[1] The Bond structure (100), comprising: a carrier substrate (110); a sintered layer (108) on the support substrate (110); a nano-twin layer (106) on the sintered layer (108), wherein a surface of the nano-twin layer (106) has a [111] crystal orientation with a density of more than 80%, wherein the nano-twin layer (106) comprises parallel twin boundaries, the parallel twin boundaries have a [111] crystal orientation of more than 40% and the distance between the parallel twin boundaries is 10 to 100 nm; an adhesion layer (104) on the nano-twin layer (106) and a chip (102) on the adhesion layer (104). [2] Die-bond structure (100) according to claim 1, wherein the support substrate (110) comprises a metallic heat sink, a printed circuit board with a copper circuit layer and a protective layer thereon, or a ceramic substrate with the copper circuit layer and the protective layer thereon. [3] Die-bond structure (100) according to claim 2, wherein the protective layer comprises an organic surface protection or a metal film. [4] Die-bond structure (100) according to claim 3, wherein the metal film contains Ni, Ni / Pd, Ni / Au or Ni / Pd / Au. [5] Die-bond structure (100) according to any one of claims 2 to 4, wherein the ceramic substrate contains aluminium oxide, aluminium nitride or silicon nitride. [6] Die-bond structure (100) according to any one of claims 2 to 5, wherein the metallic heat sink contains aluminium or copper. [7] Die-bond structure (100) according to any one of claims 1 to 6, wherein the sintered layer (108) contains silver, copper or a silver-copper composite. [8] Die-bond structure (100) according to any one of claims 1 to 7, wherein the nano-twin layer (106) contains silver, copper or a silver-copper alloy. [9] Die-bond structure (100) according to any one of claims 1 to 8, wherein the thickness of the nano-twin layer is 0.1 µm to 100 µm. [10] Die-bond structure (100) according to any one of claims 1 to 9, wherein the adhesion layer (104) contains titanium, aluminum-titanium, chromium or titanium-tungsten. [11] Die-bond structure (100) according to any one of claims 1 to 10, wherein the thickness of the adhesion layer (104) is 0.01 µm to 0.5 µm. [12] Die-bond structure (100) according to any one of claims 1 to 11, wherein the chip (102) comprises an integrated circuit or a light-emitting diode chip. [13] Die-bond structure (100) according to any one of claims 1 to 12, wherein the chip (102) comprises a single crystal of: silicon, germanium, silicon carbide, sapphire, gallium arsenide or gallium nitride. [14] Die-bond structure (100) according to one of claims 1 to 13, wherein the adhesion layer (104) is in direct contact with the nano-twin layer (106). [15] Method for producing a die-bond structure (100), comprising: Providing a chip (102); Formation of an adhesion layer (104) on the nano-twin layer (102); Forming a nano-twin layer (106) on the adhesion layer (104), wherein a surface of the nano-twin layer (106) has a [111] crystal orientation with a density of more than 80%, wherein the nano-twin layer (106) comprises parallel twin boundaries, the parallel twin boundaries have a [111] crystal orientation of more than 40%, and the distance between the parallel twin boundaries is 10 to 100 nm; and Performing a bonding process to connect the nano-twin layer (106) to a support substrate (110) via a sintered layer (108). [16] Method according to claim 15, wherein the execution of the bonding process comprises: Application of a sintered material to the support substrate (110); and Applying the nano-twin layer (106) to the sintered material and heating the sintered material to form the sintered layer (108). [17] Method according to claim 15, wherein the execution of the bonding process comprises: Application of a sintered material to the nano-twin layer (106); and Applying the support substrate (110) to the sintering material and heating the sintering material to form the sintered layer (108). [18] Method according to claim 16, wherein the sintering material is a silver paste, a copper paste or a copper paste covered with silver. [19] Method according to any one of claims 15 to 18, wherein the bonding process is carried out under a pressure of 5 MPa to 30 MPa and at a temperature of 100°C to 350°C. [20] Method according to any one of claims 15 to 19, wherein the adhesion layer (104) and the nano-twin layer (106) are each formed by sputtering, vapor deposition or electroplating. [21] Method according to any one of claims 15 to 20, wherein the bonding process is carried out under vacuum, a protective atmosphere or an ambient atmosphere.

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