DC converter, control method and control program

Abstract

DC converter (1) comprising: a smoothing filter containing an inductor (L1) and a first capacitive element (C1) configured to smooth an output voltage (VO) of an external output terminal (OUT); a first switching element (MP1) provided between an external input terminal (IN), to which an input voltage (VI) is applied, and the inductor (L1); a second switching element (MN1) provided between the inductor (L1) and a reference voltage terminal, to which a reference voltage (VSS) is applied; a lower limit detection circuit (13) configured to detect that the output voltage (VO) decreases such that it is equal to or less than a lower limit; a voltage detection circuit (20) comprising an upper limit detection circuit and an upper limit detection circuit, configured to detect a voltagewhich corresponds to an upper limit of the output voltage (VO), wherein the upper limit detection circuit comprises a reverse flow detection circuit (14) configured to detect a reverse flow of current flowing in the inductor (L1), and wherein the upper limit detection circuit is configured to detect the voltage corresponding to the upper limit of the output voltage (VO) at a time when the reverse flow detection circuit (14) detects a reverse flow of current in the inductor (L1); a control circuit (11) configured to supply a current from the external input terminal (IN) to the external output terminal (OUT) by means of the first switching element (MP1) and the inductor (L1) by performing a control to ensure that, at a time when the lower limit detection circuit (13) detects that the output voltage (VO) is decreasing such that it is equal to or less than the lower limit,for a predetermined period (TO) to switch on the first switching element (MP1) and switch off the second switching element (MN1), to supply a current from the reference voltage terminal to the external output terminal (OUT) via the second switching element (MN1) and the inductor (L1) by performing a control to switch off the first switching element (MP1) and switch on the second switching element (MN1) after the predetermined period (TO) has elapsed, and to perform a control to switch off both the first switching element (MP1) and the second switching element (MN1) at a time when the reverse current detection circuit (14) detects a reverse current in the inductor (L1); and a period determination circuit (16) configured to determine the predetermined period (TO) based on the voltage corresponding to the upper limit of the output voltage (VO) detected by the voltage detection circuit (20).

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS The disclosure of Japanese patent application No. 2023-036241, filed on March 9, 2023, including the application text, drawings and abstract, is incorporated herein in full by reference. BACKGROUND The present invention relates to a DC converter, a control method therefor and a control program therefor, e.g. a DC converter suitable for improving energy efficiency while generating a stable output voltage, a control method therefor and a control program therefor. A technique is revealed, which is described below. [Non-Patent Document 1] Jong-Seok Kim, Jin-O Yoon and Byong-Deok Choi, “A High-Light-Load-Efficiency Low-Ripple-Voltage PFM Buck Converter for IoT Applications,” IEEE TRANSACTIONS ON POWER ELECTRONICS, BD. 37, NO. 5, MAY 2022, pp. 5763-5772 Non-patent document 1 discloses a DC-DC converter that detects the start of charging an inductor using a dynamic comparator. Here, the DC-DC converter disclosed in non-patent document 1 reduces power consumption by lowering the frequency of a clock signal supplied to the dynamic comparator during a low load. In DE 10 2009 024 159 A1, an electronic device and method for DC-DC conversion using a comparator to generate an output signal for controlling a power switch of a switching mode DC-DC converter is described. SUMMARY The present solution is defined by the attached claims. In the following, parts of the description and the drawings relating to earlier embodiments and not necessarily including all features for implementing embodiments of the claimed solution are to be understood as not representing embodiments of the solution, but serving as examples to facilitate understanding of the embodiments of the invention. In recent years, further improvements in the energy efficiency of a DC-DC converter at low load have been necessary. However, when attempts are made to reduce the power consumption of the DC-DC converter during low load, ripple occurs in the output voltage, and it is difficult to generate a stable output voltage. Further problems and novel features will become apparent from the description of this application and the accompanying drawings. A DC-DC converter according to this disclosure comprises the following: a smoothing filter containing an inductor and a first capacitive element, configured to smooth an output voltage of an external output terminal; a first switching element provided between an external input terminal, to which an input voltage is applied, and the inductor; a second switching element provided between the inductor and a reference voltage terminal, to which a reference voltage is applied; a lower-limit detection circuit configured to detect that the output voltage is decreasing such that it is equal to or less than a lower limit; a voltage detection circuit configured to detect a voltage corresponding to an upper limit of the output voltage; and a control circuit configured toto supply a current from the external input terminal to the external output terminal by means of the first switching element and the inductor, by performing a control to switch on the first switching element and switch off the second switching element for a predetermined period at a time when the lower limit detection circuit detects that the output voltage is decreasing such that it is equal to or less than the lower limit; to supply a current from the reference voltage terminal to the external output terminal by means of the second switching element and the inductor, by performing a control to switch off the first switching element and switch on the second switching element after the predetermined period has elapsed; and by performing a control to switch off both the first switching element and the second switching element at a time when the voltage detection circuit detects the voltagewhich corresponds to the upper limit of the output voltage, and a period determination circuit configured to determine the predetermined period based on the voltage corresponding to the upper limit of the output voltage and detected by the voltage detection circuit. A control method of a DC-DC converter according to this disclosure is a control method of a DC-DC converter comprising at least a smoothing filter containing an inductor and a first capacitive element and configured to smooth an output voltage of an external output terminal, a first switching element provided between an external input terminal to which an input voltage is supplied and the inductor, a second switching element provided between the inductor and a reference voltage terminal to which a reference voltage is supplied, a lower limit detection circuit configured to detect that the output voltage decreases such that it is equal to or less than a lower limit, and a voltage detection circuit configured to detect a voltage corresponding to an upper limit of the output voltage.and the method comprises the following: supplying a current from the external input terminal to the external output terminal by means of the first switching element and the inductor, by performing a control operation to turn on the first switching element and turn off the second switching element for a predetermined period at a time when the lower limit detection circuit detects that the output voltage is decreasing such that it is equal to or less than the lower limit; supplying a current from the reference voltage terminal to the external output terminal by means of the second switching element and the inductor, by performing a control operation to turn off the first switching element and turn on the second switching element after the predetermined period has elapsed; performing a control operation to turn off both the first switching element and the second switching element at a time whenthe voltage detection circuit detects the voltage corresponding to the upper limit of the output voltage; determining the predetermined time period based on the voltage corresponding to the upper limit of the output voltage detected by the voltage detection circuit; and supplying a current from the external input terminal to the external output terminal by means of the first switching element and the inductor, by performing a control operation to switch on the first switching element and switch off the second switching element for a newly determined predetermined time period at the time when the lower limit detection circuit next detects that the output voltage is decreasing such that it is equal to or less than the lower limit. A control program according to this disclosure is a control program for causing a computer to perform control processing of a DC-DC converter, which includes at least one smoothing filter comprising an inductor and a first capacitive element and configured to smooth an output voltage of an external output terminal; a first switching element provided between an external input terminal to which an input voltage is supplied and the inductor; a second switching element provided between the inductor and a reference voltage terminal to which a reference voltage is supplied; a lower limit detection circuit configured to detect that the output voltage decreases such that it is equal to or less than a lower limit; and a voltage detection circuit configured to detect a voltage corresponding to an upper limit of the output voltage.and the control program causes the computer to perform processing that includes: supplying a current from the external input terminal to the external output terminal by means of the first switching element and the inductor, by performing a control to turn on the first switching element and turn off the second switching element for a predetermined period at a time when the lower limit detection circuit detects that the output voltage is decreasing such that it is equal to or less than the lower limit; supplying a current from the reference voltage terminal to the external output terminal by means of the second switching element and the inductor, by performing a control to turn off the first switching element and turn on the second switching element after the predetermined period has elapsed; performing a control,to switch off both the first switching element and the second switching element at a time when the voltage detection circuit detects the voltage corresponding to the upper limit of the output voltage; determining the predetermined period based on the voltage corresponding to the upper limit of the output voltage detected by the voltage detection circuit; and supplying a current from the external input terminal to the external output terminal by means of the first switching element and the inductor by performing a control operation to switch on the first switching element and switch off the second switching element for a newly determined predetermined period at a time when the lower limit detection circuit next detects that the output voltage is decreasing such that it is equal to or less than the lower limit. According to the present disclosure, it is possible to create a DC converter suitable for improving energy efficiency while generating a stable output voltage, a control method for it, and a control program for it. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram illustrating a configuration example of a DC-DC converter according to a first example. Fig. 2 is a timing diagram illustrating the operation of the DC-DC converter illustrated in Fig. 1. Fig. 3 is a diagram illustrating the relationship between a current to be supplied to a load and the ripple of an output voltage. Fig. 4 is a diagram illustrating a first specific configuration example of a voltage comparison circuit provided in the DC-DC converter illustrated in Fig. 1. Fig. 5 is a diagram illustrating a first specific configuration example of a one-period determination circuit provided in the DC-DC converter illustrated in Fig. 1.Figure 6 is a diagram illustrating a second specific configuration example of the voltage comparison circuit provided in the DC-DC converter illustrated in Figure 1. Figure 7 is a diagram illustrating a second specific configuration example of the one-period determination circuit provided in the DC-DC converter illustrated in Figure 1. Figure 8 is a diagram used to describe a problem. Figure 9 is a diagram used to describe a problem. DETAILED DESCRIPTION Examples not covered by the claims, but which contribute to understanding the present solution, are described in detail below with reference to the drawings. It should be noted that, since the drawings are simplified, the technical scope of the examples should not be interpreted restrictively based on the illustrations in the drawings. It should also be noted that the same component is designated with the same reference numeral, and redundant descriptions are avoided. In the following description, the invention is described in several sections or examples where this is necessary for simplification. However, these sections or examples are not irrelevant to one another unless otherwise stated, and one refers to the complete or a part of the further as a modification, detail, or supplementary explanation thereof. Furthermore, in the examples described below, when the number of elements (which includes the quantity, values, amount, range, and the like) is mentioned, the number of elements is not limited to a specific number unless otherwise stated, except in cases where the number is obviously limited to a specific number in principle, and a number greater or less than the specified number is also applicable. Furthermore, in the examples described below, the components (containing element steps) are not always indispensable unless otherwise stated, or except where the components are obviously indispensable in principle. Similarly, in the examples described below, when the form of the components, their positional relationship, and the like are mentioned, substantially similar and related forms and the like are included unless otherwise stated, or except where it is conceivable that they are obviously excluded in principle. The same applies to the quantity and the like (including a number, a value, an amount, a scope, and the like) described above. <Erstes Beispiel > Fig. 1 is a diagram illustrating a configuration example of a DC converter 1 according to a first example. As illustrated in Fig. 1, the DC converter 1 includes a control circuit 11, a drive circuit 12, a lower limit detection circuit 13, a reverse flow detection circuit 14, a voltage comparison circuit 15, a single-period determination circuit 16, a transistor (a first switching element) MP1, a transistor (a second switching element) MN1, an inductor L1, a capacitive element C1, and a resistive element R1. The reverse flow detection circuit 14 and the voltage comparison circuit 15 form a voltage detection circuit 20. It should be noted that a load Ld is also illustrated in Fig. 1. Transistor MP1 is a P-channel MOS transistor and switches on / off via a pulse signal P1 output by the driver circuit 12. Specifically, in transistor MP1, a source is connected to an input terminal IN, to which an input voltage VI is applied. A drain is connected to a terminal (a node N1) of inductor L1, and the pulse signal P1 is applied to a gate. Transistor MP1 is switched on when the pulse signal P1 is at a low level and switched off when the pulse signal P1 is at a high level. Transistor MN1 is an N-channel MOS transistor and switches on / off via a pulse signal P2 output by the driver circuit 12. Specifically, in transistor MN1, a source is connected to a reference voltage terminal (hereinafter referred to as reference voltage terminal VSS), to which a reference voltage VSS is applied. A drain is connected to one terminal (node ​​N1) of inductor L1, and the pulse signal P2 is applied to a gate. Transistor MN1 is switched on when the pulse signal P2 is at a high level and switched off when the pulse signal P2 is at a low level. The inductor L1 is connected between node N1, between transistors MP1 and MN1, and an output terminal OUT. The capacitive element C1 is connected between the output terminal OUT and the reference voltage terminal VSS. The inductor L1 and the capacitive element C1 form a smoothing filter that smooths an output voltage VO. Hereafter, the voltage at the output terminal OUT is referred to as the output voltage VO. In the example shown in Fig. 1, the output voltage VO is applied to the load Ld. The control circuit 11 controls the switching on / off of transistors MP1 and MN1 by pulse frequency modulation (PFM) using the drive circuit 12. Specifically, the control circuit 11 sets a duty cycle of the pulse signal P1 by changing a period of only one of the high level and the low level (the low level in this example) of the pulse signal P1 and accordingly stabilizes the output voltage VO to a desired level. The lower limit detection circuit 13 is a comparator and detects when the output voltage VO decreases to the point where it is equal to or less than a lower limit. Specifically, the lower limit detection circuit 13 compares a voltage obtained by dividing the output voltage VO by a portion of the resistive element R1 (i.e., a voltage equal to the output voltage VO) with a reference voltage VREF1 and outputs a detection result LL indicating whether the output voltage VO is equal to or less than the lower limit. Since the rate of decrease of the output voltage VO is generally slow, the response speed of the lower limit detection circuit 13 does not need to be high. Therefore, the lower limit detection circuit 13 can be configured to reduce power consumption in exchange for a reduced response speed. For example, when the output voltage VO decreases to the point where it is equal to or less than the lower limit, the lower limit detection circuit 13 switches the detection result LL from a high level to a low level. Furthermore, when the output voltage VO increases and becomes greater than the lower limit, the lower limit detection circuit 13 switches the detection result LL from a low level to a high level. When the lower limit detection circuit 13 detects that the output voltage VO is decreasing to the point where it is equal to or less than the lower limit, the control circuit 11, using the drive circuit 12, begins charging the inductor L1 by switching transistor MP1 on and switching transistor MN1 off. At this point, as a current flows from the input terminal IN to the output terminal OUT via transistor MP1 and inductor L1, the output voltage VO gradually increases. Then, after a set time period TO has elapsed, the control circuit 11 stops charging the inductor L1 by switching transistor MP1 from on to off using the drive circuit 12.At present, since a current flows from the reference voltage terminal VSS to the output terminal OUT via the transistor MN1 and the inductor L1 due to a counter-electromotive force of the inductor L1, the output voltage VO increases continuously. The voltage detection circuit 20 detects a voltage corresponding to an upper limit of the output voltage VO. Within the voltage detection circuit 20, the reverse current detection circuit 14 is an upper limit detection circuit that detects when the output voltage VO has reached the voltage corresponding to the upper limit. Furthermore, within the voltage detection circuit 20, the voltage comparison circuit 15 is an upper limit detection circuit that detects the voltage corresponding to the upper limit of the output voltage VO. The reverse current detection circuit 14 and the voltage comparison circuit 15 are described in detail below. The reverse flow detection circuit 14 is a comparator and detects that a current IL, which flows from transistor MN1 to load Ld via inductor L1 in a forward direction, begins to flow in the opposite direction from load Ld to transistor MN1 via inductor L1. Specifically, the reverse flow detection circuit 14 compares a voltage LX of node N1 between transistors MP1 and MN1 (a drain voltage of transistor MN1) with a source voltage of transistor MN1 and switches a detection result BS from a low level to a high level if the drain voltage of transistor MN1 is equal to or greater than the source voltage. In a case where the reverse flow of current IL into inductor L1 is detected by the reverse flow detection circuit 14, the control circuit 11 prevents the reverse flow of current IL into inductor L1 by switching off both transistors MP1 and MN1 using the drive circuit 12. At this point, since the current flow from inductor L1 to the output terminal OUT stops, the output voltage VO gradually decreases. It should be noted that when the reverse flow of current IL into inductor L1 is stopped by switching off transistors MP1 and MN1, the reverse flow detection circuit 14 switches the detection result BS from a high level to a low level. By repeatedly switching transistors MP1 and MN1 on and off, as described above, by control circuit 11, the output voltage VO is stabilized at a desired level. The voltage comparison circuit 15 compares a feedback voltage FBIN to the output voltage VO with a reference voltage VREF2 at a time when the reverse flow of the current IL flowing into the inductor L1 is detected by the reverse flow detection circuit 14 (i.e., a time when the detection result BS of the reverse flow detection circuit 14 switches from the L level to the H level) and outputs a comparison result AJ. It should be noted that the feedback voltage FBIN is a voltage obtained by dividing the output voltage VO by a portion of the resistive element R1. The one-period determination circuit 16 determines the set period TO, which is set by the control circuit 11. The set period TO is an on-period of transistor MP1. In other words, the set period TO is a period (one pulse width) of the low level of the pulse signal P1. Specifically, the one-period determination circuit 16 receives a rise in a signal DI output by the control circuit 11 at the time when the reverse flow of current IL flowing into inductor L1 is detected by the reverse flow detection circuit 14. The one-period determination circuit 16 then adds a delay of a specific amount, determined by the comparison result AJ of the voltage comparison circuit 15, to the signal DI and outputs the signal DI as a signal DO to the control circuit 11. That is, the one-period determination circuit 16 determines the time period from the rise of signal DI to the rise of signal DO as the set period TO. For example, if the feedback voltage FBIN (the voltage corresponding to an output voltage VO) is equal to or greater than the reference voltage VREF2, the output voltage VO will be greater than expected. Therefore, the one-period determination circuit 16 decreases the delay amount to be added to the signal DI. That is, the one-period determination circuit 16 shortens the set period TO by one step. Conversely, if the feedback voltage FBIN (the voltage corresponding to an output voltage VO) is less than the reference voltage VREF2, the output voltage VO will be less than expected. Therefore, the one-period determination circuit 16 increases the delay amount to be added to the signal DI. That is, the one-period determination circuit 16 increases the set period TO by one step.Then, when transistor MP1 is switched on again, the control circuit 11 switches transistor MP1 on only for a length of the set period TO, which was determined by the one-period determination circuit 16. In this manner, according to the present example, the DC-DC converter 1 samples the output voltage VO (the upper limit of the output voltage VO) at the moment when the reverse flow of current IL into inductor L1 is detected, and determines a charging period for inductor L1 (a one-time period for transistor MP1) in the next cycle based on the sampled output voltage VO. Here, since the DC-DC converter 1, according to the present example, detects the upper limit of the output voltage VO only at the moment when the reverse flow of current IL into inductor L1 is detected, without using a high-speed clock signal, it is possible to reduce power consumption.Furthermore, since the DC-DC converter 1, according to the present example, can adjust the charging period of inductor L1 so that it is no longer than necessary, compared to a case where the charging period of inductor L1 is fixed, it is possible to prevent ripple in the output voltage. Additionally, since the DC-DC converter 1, according to the present example, performs feedback control to determine the charging period of inductor L1 in the next cycle based on the sampled output voltage VO, it is possible to ensure sufficient time for the feedback control. That is to say, the DC-DC converter 1, according to the present example, can improve energy efficiency during low load operation while generating a stable output voltage. (Operation of DC converter 1) The operation of the DC converter 1 is then described with reference to Fig. 2 in addition to Fig. 1. In the DC converter 1, when the output voltage VO decreases to the point where it is equal to or less than the lower limit, the lower limit detection circuit 13 switches the detection result LL from a high level to a low level (time t11). When the lower limit detection circuit 13 detects that the output voltage VO is decreasing to the point where it is equal to or less than the lower limit, the control circuit 11 starts charging the inductor L1 by using the drive circuit 12 to switch on transistor MP1 and switch off transistor MN1 (time t11). At this point, as a current flows from the input terminal IN to the output terminal OUT via transistor MP1 and inductor L1, the output voltage VO gradually increases (times t11 and t12). Then, when the set time period TO has elapsed, the control circuit 11 stops the charging of the inductor L1 by switching transistor MP1 from on to off using the drive circuit 12 (time t12). At this point, current flows from the reference voltage terminal VSS to the output terminal OUT via transistor MN1 and the inductor L1 due to the opposing electromotive force of the inductor L1. As a result, the output voltage VO increases continuously (times t12 and t13). Subsequently, if the reverse flow of current IL into inductor L1 is detected by the reverse flow detection circuit 14, the control circuit 11 prevents the reverse flow of current IL into inductor L1 by switching off both transistors MP1 and MN1 using the drive circuit 12 (time t13). At this point, since the current flow from inductor L1 to the output terminal OUT has stopped, the output voltage VO gradually decreases (times t13 and t14). By repeatedly switching transistors MP1 and MN1 on and off at times t11 to t14, the DC converter 1 stabilizes the output voltage VO at the desired level (times t11 to t14). It should be noted that the output voltage VO is smoothed by the capacitive element C1. Here, in the DC converter 1, the voltage comparison circuit 15 compares the feedback voltage FBIN of the output voltage VO with the reference voltage VREF2 at the time when the reverse flow of the current IL flowing into the inductor L1 is detected by the reverse flow detection circuit 14, and outputs the comparison result AJ (time t13). Furthermore, the one-period determination circuit 16 receives the rise of the signal DI, output by the control circuit 11, at the time when the reverse flow of the current IL flowing into the inductor L1 is detected by the reverse flow detection circuit 14. The one-period determination circuit 16 then adds a delay of a delay amount, according to the comparison result AJ of the voltage comparison circuit 15, to the signal DI and outputs the signal DI as a signal DO to the control circuit 11. That is, the one-period determination circuit 16 determines a period from the rise of the signal DI to the rise of the signal DO as the set period TO. In the example in Fig. 5, because the feedback voltage FBIN (the voltage corresponding to an output voltage VO) is equal to or greater than the reference voltage VREF2, and the output voltage VO is greater than the expected value, the one-period determination circuit 16 reduces the amount of delay to be added to the signal DI. That is, the one-period determination circuit 16 shortens the set period TO by one step. Then, the next time transistor MP1 is turned on, the control circuit 11 turns transistor MP1 on only for the length of the set period TO determined by the one-period determination circuit 16 (times t14 and t15). In this manner, according to the present example, the DC-DC converter 1 samples the output voltage VO (upper limit of an output voltage VO) at the moment when the reverse flow of current IL into inductor L1 is detected, and determines the charging period of inductor L1 (the on-period of transistor MP1) in the next cycle based on the sampled output voltage VO. Here, since the DC-DC converter 1, according to the present example, detects the upper limit of the output voltage VO only at the moment when the reverse flow of current IL into inductor L1 is detected, without using a high-speed clock signal, it is possible to reduce power consumption.Furthermore, since the DC-DC converter 1, according to the present example, can adjust the charging period of inductor L1 so that it is no longer than necessary, compared to a case where the charging period of inductor L1 is fixed, it is possible to prevent ripple in the output voltage. Additionally, since the DC-DC converter 1, according to the present example, performs feedback control to determine the charging period of inductor L1 in the next cycle based on the sampled output voltage VO, it is possible to ensure sufficient time for the feedback control. That is to say, the DC-DC converter 1, according to the present example, can improve energy efficiency during low load operation while generating a stable output voltage. Furthermore, since the DC converter 1, as shown in the present example, can improve energy efficiency during low load, it can be used instead of a low-power output (LDO) during low load, such as a standby mode. As a result, a device incorporating the DC converter 1 can reduce circuit size and shorten mode transition time. (Comparison between the DC converter 1 according to the present example and the related field) For example, since the first related area has a configuration in which transistor MP1 switches from ON to OFF at the time the upper limit of the output voltage VO is detected, requiring a high-speed response, it is difficult to reduce power consumption (see Fig. 8). Furthermore, with the second related area, which has a configuration in which the ON period of transistor MP1 is fixed, although power consumption can be reduced by adjusting the ON period to be long, ripple occurs in the output voltage (see Fig. 9). On the other hand, as described above, unlike the first and second related areas, the DC converter 1 according to the present example can improve energy efficiency while generating the stable output voltage. Fig. 3 is a diagram illustrating the relationship between the current supplied to the load Ld and the ripple of the output voltage VO. In the example in Fig. 3, a solid line indicates an experimental result of the DC-DC converter 1 according to the present example, and a dashed line indicates an experimental result of a DC-DC converter according to the first related area. As illustrated in Fig. 3, the DC-DC converter 1 according to the present example prevents the ripple generated in the output voltage VO, regardless of response capability (i.e., even in a case where response capability is low). <Zweites Beispiel> In the present example, a first specific configuration example of each of a voltage comparison circuit 15 and a one-period determination circuit 16, provided in a DC converter 1, is described. Fig. 4 is a diagram illustrating the first specific configuration example of the voltage comparison circuit 15 as a voltage comparison circuit 15a. Fig. 5 is a diagram illustrating the first specific configuration example of the one-period determination circuit 16 as a one-period determination circuit 16a. First, the voltage comparator circuit 15a is described with reference to Fig. 4. As illustrated in Fig. 4, the voltage comparator circuit 15a is a so-called dynamic comparator and contains transistors TR11 to TR15, TR21 to TR25, and TR31. In the present example, a case is described in which each of the transistors TR11, TR13, TR14, TR21, TR23, and TR24 is a P-channel MOS transistor, and each of the transistors TR12, TR15, TR22, TR25, and TR31 is an N-channel MOS transistor. In transistor TR11, a source is connected to a power supply voltage terminal (hereinafter referred to as power supply voltage terminal VDD), to which a power supply voltage VDD is applied, a drain is connected to node N11, and a gate is connected to node N21. In transistor TR12, a source is connected to node N12, a drain is connected to node N11, and a gate is connected to node N21. In transistor TR21, a source is connected to the power supply voltage terminal VDD, a drain is connected to node N21, and a gate is connected to node N11. In transistor TR22, a source is connected to node N22, a drain is connected to node N21, and a gate is connected to node N11.That is, a first inverter INV1, containing transistors TR11 and TR12, and a second inverter INV2, containing transistors TR21 and TR22, are connected in a loop form to configure a storage circuit. In transistor TR15, a source is connected to node N31, a drain is connected to node N12, and the reference voltage VREF2 is applied to a gate. In transistor TR25, a source is connected to node N31, a drain is connected to node N22, and a feedback voltage FBIN (a voltage corresponding to an output voltage VO) is applied to a gate. In transistor TR13, a source is connected to the power supply voltage terminal VDD, a drain is connected to node N11, and a detection result BS is fed to a gate of a reverse flow detection circuit 14. In transistor TR14, a source is connected to the power supply voltage terminal VDD, a drain is connected to node N12, and the detection result BS is fed to a gate of the reverse flow detection circuit 14. In transistor TR23, a source is connected to the power supply voltage terminal VDD, a drain is connected to node N21, and the detection result BS is fed to a gate of the reverse flow detection circuit 14. In transistor TR24, a source is connected to the power supply voltage terminal VDD, a drain is connected to node N22, and the detection result BS is fed to a gate of the reverse flow detection circuit 14.In transistor TR31, a source is connected to the reference voltage terminal VSS, a drain is connected to node N31, and the detection result BS of the backflow detection circuit 14 is fed to a gate. This means that during a period in which a reverse current IL flowing into inductor L1 is not detected by the reverse current detection circuit 14, transistors TR13, TR14, TR23, and TR24 are switched on, and transistor TR31 is switched off. Then, when the reverse current IL flowing into inductor L1 is detected by the reverse current detection circuit 14, transistors TR13, TR14, TR23, and TR24 are switched off, and transistor TR31 is switched on. Correspondingly, the voltage comparator circuit 15 temporarily performs a comparator operation. For example, in a case where the feedback voltage FBIN is equal to or greater than the reference voltage VREF2, the on-resistance of transistor TR25 is lower than the on-resistance of transistor TR15. Therefore, a charge accumulated in the drain (node ​​N22) of transistor TR25 is extracted earlier than a charge accumulated in the drain (node ​​N12) of transistor TR15. As a result, since transistor TR22 turns on earlier than transistor TR12, a voltage level at node N21 (an output from a second inverter INV2) indicates a low level, and a voltage level at node N11 (an output from a first inverter INV1 and a comparison result AJ) indicates a high level. That is, in a case where the feedback voltage FBIN is equal to or greater than the reference voltage VREF2, the voltage comparison circuit 15a outputs the comparison result AJ of the H level. On the other hand, in a case where the feedback voltage FBIN is smaller than the reference voltage VREF2, the on-resistance of transistor TR15 is smaller than the on-resistance of transistor TR25. Therefore, the charge accumulated in the drain (node ​​N12) of transistor TR15 is extracted earlier than the charge accumulated in the drain (node ​​N22) of transistor TR25. As a result, since transistor TR12 turns on earlier than transistor TR22, the voltage level of node N11 (the output of a first inverter INV1 and the comparison result AJ) indicates a low level, and the voltage level of node N21 (the output of a second inverter INV2) indicates a high level. That is, in a case where the feedback voltage FBIN is smaller than the reference voltage VREF2, the voltage comparison circuit 15a outputs the comparison result AJ of the L level. The single-period determination circuit 16a is then described with reference to Fig. 5. As illustrated in Fig. 5, the single-period determination circuit 16a includes an up / down counter 161, an inverter group 162, and a selection device 163. When an increase in a signal DI, output by a control circuit 11, is received at the time when the backflow of the current IL flowing into the inductor L1 is detected by the backflow detection circuit 14, the up / down counter 161 counts a preset count value (specifically the count value set at the previous time) up or down according to the comparison result AJ of the voltage comparison circuit 15a. For example, if the comparison result AJ indicates a high level (i.e., if the output voltage VO is greater than an expected value), the up / down counter 161 decrements the count by one and outputs the value as a selection signal S1. Conversely, if the comparison result AJ indicates a low level (i.e., if the output voltage VO is greater than an expected value), the up / down counter 161 increments the count by one and outputs the value as the selection signal S1. Inverter group 162 contains several inverters connected in series and delays the signal DI before outputting it. Selector device 163 selects the output of one of the inverters in inverter group 162 based on selection signal S1 and outputs the output as a signal DO. That is, selector device 163 adds a delay of a certain amount, according to selection signal S1, to signal DI and outputs signal DI as signal DO. For example, in a case where the count of the up / down counter 161 is counting down, the selector 163 selects a signal with a small delay added to signal DI and outputs the signal as signal DO. Conversely, in a case where the count of the up / down counter 161 is counting up, the selector 163 selects a signal with a large delay added to signal DI and outputs the signal as signal DO. In other words, in a case where the output voltage VO is greater than the expected value, the selector 163 shortens the set period TO by one step, and in a case where the output voltage VO is less than the expected value, the selector 163 increases the set period TO by one step.Then, when transistor MP1 is switched on the next time, the control circuit 11 switches transistor MP1 on only for a length of the set period TO, which is determined by the one-period determination circuit 16a. It should be noted that both the voltage comparison circuit 15a and the one-period determination circuit 16a can be suitably modified to a further configuration which has corresponding functions. <Drittes Beispiel> In the present example, a second specific configuration example of each of a voltage comparison circuit 15 and a one-period determination circuit 16, provided in a DC converter 1, is described. Fig. 6 is a diagram illustrating the second specific configuration example of the voltage comparison circuit 15 as a voltage comparison circuit 15b. Fig. 7 is a diagram illustrating the second specific configuration example of the one-period determination circuit 16 as a one-period determination circuit 16b. First, the voltage comparison circuit 15b is described with reference to Fig. 6. As illustrated in Fig. 6, the voltage comparison circuit 15b is a so-called integrator and contains an operational amplifier 151, a capacitive element 152, a capacitive element 153, a switching element 154 and a switching element 155. In operational amplifier 151, a reference voltage VREF2 is applied to an inverting input terminal, and a voltage from node N41 is applied to a non-inverting input terminal. Capacitive element 152 is connected between an output terminal and the non-inverting input terminal of operational amplifier 151. An output from operational amplifier 151 is used as a comparison result AJ of the voltage comparator circuit 15b. Switching elements 154 and 155 are connected in series between an input terminal of the voltage comparator circuit 15b, to which a feedback voltage FBIN is applied, and the non-inverting input terminal (node ​​N41) of operational amplifier 151. Capacitive element 153 is connected between node N42, between switching elements 154 and 155, and a reference voltage terminal VSS.The switching element 154 switches on / off based on a reversal signal of a detection result BS from a backflow detection circuit 14. The switching element 155 switches on / off based on the detection result BS from the backflow detection circuit 14. During a period in which a reverse current IL flowing into inductor L1 is not detected by the reverse current detection circuit 14, switching element 154 is turned on and switching element 155 is turned off. Therefore, charges of the feedback voltage FBIN accumulate in the capacitive element 153. Then, when the reverse current IL flowing into inductor L1 is detected by the reverse current detection circuit 14, switching element 154 is turned off and switching element 155 is turned on. A voltage (a voltage of node N42) corresponding to the charges accumulated in the capacitive element 153 is then applied to the non-inverting input terminal of operational amplifier 151.The integrator, which includes the operational amplifier 151 and the capacitive element 152, then outputs an integration result, known as the comparison result AJ, based on the feedback voltage FBIN and the reference voltage VREF2. It should be noted that the comparison result AJ is an analog voltage. For example, as the feedback voltage FBIN increases, the potential of the comparison result AJ decreases, and conversely, as the feedback voltage FBIN decreases, the potential of the comparison result AJ increases. The one-period determination circuit 16b is then described with reference to Fig. 7. As illustrated in Fig. 7, the one-period determination circuit 16b includes a constant current source 164, a capacitive element 165, a switching element 166, and a comparator 167. The constant current source 164 is connected between a power supply voltage terminal VDD and a node N51 and supplies a constant current to node N51. The capacitive element 165 is connected between node N51 and the reference voltage terminal VSS. The switching element 166 is connected in parallel to the capacitive element 165 and switches on / off based on a signal DI. The comparator 167 compares a potential of node N51 with the comparison result AJ of the voltage comparison circuit 15b and outputs a comparison result as a signal DO. When the rise of signal DI, output by a control circuit 11, is received at the same time as the backflow of current IL flowing into inductor L1 is detected by the backflow detection circuit 14, the switching element 166 is switched from ON to OFF. As a result, the potential of node N51 gradually increases. Then, when the potential of node N51 increases and reaches the potential of the comparison result AJ, the comparator 167 increases the signal DO. The one-period determination circuit 16 determines the time period from the rise of signal DI to the rise of signal DO as a set period TO. For example, if the potential of the comparison result AJ is smaller (i.e., if the output voltage VO is greater than an expected value), the potential of node N51 increases, and the time before its potential reaches the potential of the comparison result AJ is shortened. Therefore, the rise time of the signal DO is delayed. Conversely, if the potential of the comparison result AJ is larger (i.e., if the output voltage VO is less than an expected value), the potential of node N51 increases, and the time before its potential reaches the potential of the comparison result AJ is longer. Therefore, the rise time of the signal DO is earlier. In other words, the backflow detection circuit 14 shortens the set period TO when the output voltage VO is greater than the expected value and lengthens the set period TO when the output voltage VO is less than the expected value.Then, when transistor MP1 is switched on the next time, the control circuit 11 switches transistor MP1 on only for the length of the set period TO, which was determined by the one-period determination circuit 16b. It should be noted that both the voltage comparison circuit 15b and the one-period determination circuit 16b can be suitably modified to a further configuration that has corresponding functions. In this manner, according to the examples, the DC converter 1 samples the output voltage VO (the upper limit of an output voltage VO) at the moment when the reverse flow of current IL into inductor L1 is detected, and determines a charging period for inductor L1 (an on-period of transistor MP1) in the next cycle based on the sampled output voltage VO. Here, since the DC converter 1, according to the examples, detects the upper limit of the output voltage VO only at the moment when the reverse flow of current IL into inductor L1 is detected, without using a high-speed clock signal, it is possible to reduce power consumption.Furthermore, since the DC-DC converter 1, according to the present example, can adjust the charging period of inductor L1 so that it is no longer than necessary, compared to a case where the charging period of inductor L1 is fixed, it is possible to prevent ripple generated in the output voltage. Additionally, since the DC-DC converter 1, according to the examples, performs feedback control to determine the charging period of inductor L1 in the next cycle based on the sampled output voltage VO, it is possible to ensure sufficient time for the feedback control. That is to say, the DC-DC converter 1, according to the examples, can improve energy efficiency at low loads while generating a stable output voltage. Although the present invention, which was made by the inventors, has been specifically described on the basis of the examples above, the present invention is not limited to the examples described above and it is self-evident that various modifications can be made without deviating from its main content. Furthermore, the present disclosure can partially or completely implement the control processing of the DC converter by causing a CPU to execute a computer program. The program contains a set of instructions (or software code) to cause the computer to perform one or more functions described in the examples, if the computer reads the program. The program may be stored on non-transient computer-readable medium or physical storage medium. By way of example, not as a limitation, computer-readable medium or physical storage medium includes read / write memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other storage technologies, CD-ROM, versatile digital disc (DVD), Blu-ray disc (registered trademark) or other optical storage media, magnetic cartridge, magnetic tape, magnetic storage device, or other magnetic storage devices.The program can be transmitted in a transitory computer-readable medium or a communication medium. As an example, not a limitation, the transitory computer-readable medium or communication medium includes electrical, optical, acoustic, or other forms of propagating signals.

Claims

DC converter (1) comprising: a smoothing filter containing an inductor (L1) and a first capacitive element (C1) configured to smooth an output voltage (VO) of an external output terminal (OUT); a first switching element (MP1) provided between an external input terminal (IN), to which an input voltage (VI) is applied, and the inductor (L1); a second switching element (MN1) provided between the inductor (L1) and a reference voltage terminal, to which a reference voltage (VSS) is applied; a lower limit detection circuit (13) configured to detect that the output voltage (VO) decreases such that it is equal to or less than a lower limit; a voltage detection circuit (20) comprising an upper limit detection circuit and an upper limit detection circuit, configured to detect a voltagewhich corresponds to an upper limit of the output voltage (VO), wherein the upper limit detection circuit comprises a reverse flow detection circuit (14) configured to detect a reverse flow of current flowing in the inductor (L1), and wherein the upper limit detection circuit is configured to detect the voltage corresponding to the upper limit of the output voltage (VO) at a time when the reverse flow detection circuit (14) detects a reverse flow of current in the inductor (L1); a control circuit (11) configured to supply a current from the external input terminal (IN) to the external output terminal (OUT) by means of the first switching element (MP1) and the inductor (L1) by performing a control to ensure that, at a time when the lower limit detection circuit (13) detects that the output voltage (VO) is decreasing such that it is equal to or less than the lower limit,for a predetermined period (TO) to switch on the first switching element (MP1) and switch off the second switching element (MN1), to supply a current from the reference voltage terminal to the external output terminal (OUT) via the second switching element (MN1) and the inductor (L1) by performing a control to switch off the first switching element (MP1) and switch on the second switching element (MN1) after the predetermined period (TO) has elapsed, and to perform a control to switch off both the first switching element (MP1) and the second switching element (MN1) at a time when the reverse current detection circuit (14) detects a reverse current in the inductor (L1); and a period determination circuit (16) configured to determine the predetermined period (TO) based on the voltage corresponding to the upper limit of the output voltage (VO) detected by the voltage detection circuit (20). DC converter according to claim 1, wherein the reverse current detection circuit (14) is a first comparator configured to compare a voltage of a node between the first switching element (MP1) and the second switching element (MN1) with the reference voltage (VSS) of the reference voltage terminal and to output a comparison result indicating whether the current flowing in the inductor (L1) is reversed or not. DC converter (1) according to claim 1, wherein the upper limit detection circuit is a dynamic comparator configured to compare a feedback voltage (FBIN) of the output voltage (VO) with a reference voltage (VSS) at the time when the upper limit detection circuit detects that the output voltage (VO) has reached the voltage corresponding to the upper limit, and output a comparison result, and the period determination circuit (16) determines the predetermined period (TO) based on the comparison result output by the upper limit detection circuit. DC converter (1) according to claim 3, wherein the period determination circuit (16) shortens the predetermined period (TO) by one step if the comparison result indicating that the feedback voltage (FBIN) is equal to or greater than the reference voltage (VSS) is output by the upper limit detection circuit, and lengthens the predetermined period (TO) by one step if a comparison result indicating that the feedback voltage (FBIN) is less than the reference voltage (VSS) is output by the upper limit detection circuit. DC converter (1) according to claim 3, wherein the period determination circuit (16) comprises: an up / down counter (161) configured to count up or down a count value according to the comparison result output by the upper limit detection circuit; an inverter group (162) configured to add delays of several different delay amounts to a first signal and output the signal; and a selection device (163) configured to select the first signal to which the delay of the delay amount according to the count value of the up / down counter (161) has been added and output the selected signal as a second signal, and a delay difference between the first signal and the second signal is determined as the predetermined period (TO). DC converter (1) according to claim 1, wherein the upper limit detection circuit comprises: an integrator (15b) configured to output an integration result according to a feedback voltage (FBIN) of the output voltage (VO) and a reference voltage (VSS) at the time when the upper limit detection circuit detects that the output voltage (VO) has reached the voltage corresponding to the upper limit, and the period determination circuit (16) comprises: a constant current source (164); a second capacitive element (165) configured to convert a current supplied by the constant current source (164) into a voltage;and a second comparator (167) configured to compare the voltage converted by the second capacitive element (165) with the integration result output by the upper limit detection circuit and to output a comparison result indicating the specified time period (TO). Control method of a DC converter (1) comprising at least one smoothing filter containing an inductor (L1) and a first capacitive element (C1) and configured to smooth an output voltage (VO) of an external output terminal (OUT), a first switching element (MP1) provided between an external input terminal (IN) to which an input voltage (VI) is supplied and the inductor (L1), a second switching element (MN1) provided between the inductor (L1) and a reference voltage terminal to which a reference voltage (VSS) is supplied, a lower limit detection circuit (13) configured to detect that the output voltage (VO) decreases such that it is equal to or less than a lower limit, and a voltage detection circuit (20) comprising an upper limit detection circuit and an upper limit detection circuit, configured to detect a voltagewhich corresponds to an upper limit of the output voltage (VO), wherein the upper limit detection circuit comprises a reverse flow detection circuit (14) configured to detect a reverse flow of current flowing in the inductor (L1), and wherein the upper limit detection circuit is configured to detect the voltage corresponding to the upper limit of the output voltage (VO) at a time when the reverse flow detection circuit (14) detects a reverse flow of current in the inductor (L1), the method comprising: supplying a current from the external input terminal (IN) to the external output terminal (OUT) by means of the first switching element (MP1) and the inductor (L1), by performing a control to ensure that, at a time when the lower limit detection circuit (13) detects that the output voltage (VO) is decreasing such that it is equal to or less than the lower limit,to switch on the first switching element (MP1) and switch off the second switching element (MN1) for a predetermined period (TO); supplying a current from the reference voltage terminal to the external output terminal (OUT) via the second switching element (MN1) and the inductor (L1) by performing a control to switch off the first switching element (MP1) and switch on the second switching element (MN1) after the predetermined period (TO) has elapsed; performing a control to switch off both the first switching element (MP1) and the second switching element (MN1) at a time when the reverse current detection circuit (14) detects a reverse current in the inductor (L1); determining the predetermined period (TO) based on the voltage,which corresponds to the upper limit of the output voltage (VO) and was detected by the voltage detection circuit (20); and supplying a current from the external input terminal (IN) to the external output terminal (OUT) by means of the first switching element (MP1) and the inductor (L1), by performing a control operation to switch on the first switching element (MP1) and switch off the second switching element (MN1) for a newly determined predetermined period (TO) at a time when the lower limit detection circuit (13) next detects that the output voltage (VO) is decreasing such that it is equal to or less than the lower limit. Computer-readable storage medium storing a control program to cause a computer to perform control processing of a DC-DC converter (1) comprising at least one smoothing filter containing an inductor (L1) and a first capacitive element (C1) configured to smooth an output voltage (VO) of an external output terminal (OUT), a first switching element (MP1) provided between an external input terminal (IN) to which an input voltage (VI) is supplied and the inductor (L1), a second switching element (MN1) provided between the inductor (L1) and a reference voltage terminal to which a reference voltage (VSS) is supplied, a lower limit detection circuit (13) configured to detect that the output voltage (VO) decreases such that it is equal to or less than a lower limit, and a voltage detection circuit (20).comprising an upper limit detection circuit and an upper limit detection circuit, and configured to detect a voltage corresponding to an upper limit of the output voltage (VO), wherein the upper limit detection circuit comprises a reverse flow detection circuit (14) configured to detect a reverse flow of current flowing in the inductor (L1), and wherein the upper limit detection circuit is configured to detect the voltage corresponding to the upper limit of the output voltage (VO) at a time when the reverse flow detection circuit (14) detects a reverse flow of current in the inductor (L1), wherein the control program causes the computer to perform processing that includes: supplying a current from the external input terminal (IN) to the external output terminal (OUT) by means of the first switching element (MP1) and the inductor (L1),by performing a control operation to switch on the first switching element (MP1) and switch off the second switching element (MN1) for a predetermined period (TO) at a time when the lower limit detection circuit (13) detects that the output voltage (VO) is decreasing such that it is equal to or less than the lower limit; supplying a current from the reference voltage terminal to the external output terminal (OUT) by means of the second switching element (MN1) and the inductor (L1) by performing a control operation to switch off the first switching element (MP1) and switch on the second switching element (MN1) after the predetermined period (TO) has elapsed; performing a control operation to switch off both the first switching element (MP1) and the second switching element (MN1) at a timeat which the reverse current detection circuit (14) detects a reverse current in the inductor (L1); Determining the predetermined period (TO) based on the voltage corresponding to the upper limit of the output voltage (VO) detected by the voltage detection circuit (20); and Supplying a current from the external input terminal (IN) to the external output terminal (OUT) by means of the first switching element (MP1) and the inductor (L1) by performing a control operation to switch on the first switching element (MP1) and switch off the second switching element (MN1) for a newly determined predetermined period (TO) at a time when the lower limit detection circuit (13) next detects that the output voltage (VO) is decreasing such that it is equal to or less than the lower limit.

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