DIFFUSION BLOCKING LAYERS IN SEMICONDUCTOR COMPONENTS

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are disclosed. The semiconductor device comprises a substrate, a fin structure arranged on the substrate, and a gate structure. The gate structure comprises a high-k-gate oxide layer arranged on the fin structure, a diffusion barrier layer arranged on the high-k-gate oxide layer, and a metal layer arranged on the diffusion barrier layer. The semiconductor device further comprises a gate spacer arranged on the diffusion barrier layer and a source / drain (S / D) region arranged on the fin structure. A side wall of the S / D region is in contact with a side wall of the high-k-gate oxide layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 541,339, entitled "Semiconductor Device Structure and Method," filed September 29, 2023, which is incorporated by reference into the present application. BACKGROUND

[0002] Advances in semiconductor technology have led to a growing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry is continually reducing the dimensions of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (diffusion junction FinFETs), and gate-all-around field-effect transistors (GAA FETs). Such downsizing has increased the complexity of semiconductor manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure can best be understood from the following detailed description taken in conjunction with the accompanying figures. Fig. 1A illustrates an isometric view of a semiconductor device with diffusion barrier layers in accordance with some embodiments. Fig. 1B-1D illustrate various cross-sectional views of a semiconductor device having diffusion barrier layers in accordance with some embodiments. Fig. 2A and Fig. 2B illustrate various cross-sectional views of another semiconductor device having diffusion barrier layers in accordance with some embodiments. Fig. 3 is a flow diagram of a method of fabricating a semiconductor device with diffusion barrier layers in accordance with some embodiments. Fig. 4-16 illustrate isometric and cross-sectional views of a semiconductor device having diffusion barrier layers at various stages of its manufacturing process in accordance with some embodiments. Fig. 17 is a flow diagram of a method of fabricating a semiconductor device with diffusion barrier layers in accordance with some embodiments. Fig. 18-22 illustrate cross-sectional views of another semiconductor device having diffusion barrier layers at various stages of its manufacturing process in accordance with some embodiments.

[0004] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally designate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first structural element over or on a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements may not be in direct contact.As used herein, the formation of a first structural element in direct contact with a second structural element means that the first structural element is formed on the second structural element. Additionally, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, imply any relationship between the various embodiments and / or configurations discussed.

[0006] Spatially relative terms such as "underlying," "beneath," "under," "overlying," "upper," and the like may be used herein for ease of description to describe the relationship of one element or structural element to another element(s) or structural element(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0007] It is noted that references in the specification to "a single embodiment," "an embodiment," "an exemplary embodiment," "exemplary," etc., indicate that the described embodiment may include a particular structural element, structure, or feature, but not every embodiment necessarily includes the particular structural element, structure, or feature. Moreover, such phrases do not necessarily refer to the same embodiment. Further, if a particular structural element, structure, or feature is described in connection with one embodiment, one of ordinary skill in the art would know how to implement such structural element, structure, or feature in connection with other embodiments, whether explicitly described or not.

[0008] It is to be understood that the phraseology or terminology used herein is for the purpose of description and not of limitation, so that the terminology or phraseology of the present description will be interpreted by those skilled in the relevant arts in light of the present teachings.

[0009] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5-20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of the values, as interpreted by those skilled in the relevant arts in light of the present teachings.

[0010] The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multiple-patterning processes. Double-patterning or multiple-patterning processes may combine photolithography and self-aligning processes, thereby creating structures having, for example, pitches smaller than those otherwise obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligning process.The sacrificial layer is then removed and the remaining spacers can then be used to pattern the fin structures.

[0011] The present disclosure provides example gate structures with diffusion barrier layers in FETs (e.g., FinFETs and MOSFETs) and example methods for forming such FETs to improve threshold voltage control in the FETs. In some embodiments, the example gate structure of a FET may include a high-k gate oxide layer, first and second diffusion barrier layers disposed on the high-k gate oxide layer, and a gate metal fill layer disposed on the first and second diffusion barrier layers. In some embodiments, the first and second diffusion barrier layers may be disposed to prevent or minimize the diffusion of metal atoms from the gate metal fill layer to the high-k gate oxide layer. The presence of such diffused metal atoms in the high-k gate oxide layer may lead to threshold voltage variations in the FET and consequently degrade device performance.In some embodiments, the first diffusion barrier layer may be formed to have an amorphous structure and a feature density that can limit the concentration of metal atoms diffusing from the gate metal fill layer into the first diffusion barrier layer to about 10 atomic percent or less. Similarly, the second diffusion barrier layer may be formed to have an amorphous structure and a feature density that can limit the concentration of metal atoms diffusing from the gate metal fill layer into the second diffusion barrier layer to about 10 atomic percent to about 50 atomic percent. Within these concentration constraints, the diffusion of the metal atoms into the high-k gate oxide layer may be prevented or minimized.

[0012] Fig. 1A illustrates an isometric view of a semiconductor device 100 according to some embodiments. In some embodiments, semiconductor device 100 may represent a FinFET and may be referred to as "FinFET 100." Fig. 1B, Fig. 1C and Fig. 1D illustrate various cross-sectional views of semiconductor device 100, along line AA of Fig. 1A according to some embodiments. Fig. 1B, Fig. 1C and Fig. 1D illustrate cross-sectional views with additional structures that are omitted for simplicity in Fig. 1A are not shown. The discussion of elements in Fig. 1A-1D with the same designations apply reciprocally unless otherwise stated.

[0013] With reference to Fig. 1A and Fig. 1B, in some embodiments, semiconductor device 100 may include (i) a substrate 104, (ii) shallow trench isolation (STI) regions 106 disposed on substrate 104, (iii) fin structure 108 disposed on substrate 104, (iv) S / D regions 110 disposed on fin structure 108, (v) gate structures 112 surrounding portions of fin structure 108 that extend over STI regions 106, (vi) gate spacers 114 disposed along sidewalls of gate structures 112, (vii) etch stop layers (ESLs) 116 disposed directly on S / D regions 110, (viii) ILD layers 118 disposed directly on ESLs 116, (ix) S / D contact structures 120 arranged on S / D regions 110, and (x) gate contact structures 122 arranged on gate structures 112.

[0014] Semiconductor device 100 may be formed on a substrate 104. In some embodiments, substrate 104 may be a semiconductor material, such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, silicon-on-insulator, and a combination thereof. Further, substrate 104 may be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, STI regions 106 may comprise an insulating material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide (SiGeO x ) contain.

[0015] In some embodiments, fin structure 108 may include a material similar to substrate 104. Fin structure 108 may have elongated sides extending along an X-axis. S / D regions 110 may include an epitaxially grown semiconductor material, such as Si, and n-type dopants, such as phosphorus and other suitable n-type dopants for n-FinFET 100. S / D regions 110 may include an epitaxially grown semiconductor material, such as Si and SiGe, and p-type dopants, such as boron and other suitable p-type dopants for p-FinFET 100. S / D regions 110 may refer to a source or a drain, individually or jointly, depending on the context.

[0016] Gate structure 112 may be a multi-layer structure and may include (i) an interfacial oxide (IL) layer 112A, (ii) a high-k (HK) gate oxide layer 112B, (iii) a first diffusion barrier layer 112C, (iv) a second diffusion barrier layer 112D, (v) a work function metal (WFM) layer 112E, (vi) a gate metal fill layer 112F, (vii) a conductive cap layer 112G, and (viii) an insulating cap layer 112H.

[0017] In some embodiments, the IL layer 112A may be disposed directly on the portions of fin structure 108 that extend over STI regions 106, as described below with respect to Fig. 4-6. In some embodiments, IL layer 112A may be SiO2, SiGeO x or germanium oxide (GeO x) and may have a thickness T1 of about 1 nm to about 20 nm. In some embodiments, the HK gate oxide layer 112B may be disposed directly on IL layer 112A and overlies the portions of fin structure 108 that extend over STI regions 106, as described below with respect to Fig. 4-6. In some embodiments, HK gate oxide layer 112B may include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2), and may have a thickness T2 of about 1 nm to about 50 nm. In some embodiments, sidewalls of IL layer 112A and HK gate oxide layer 112B may be vertical, as shown by solid lines in Fig. 1B, or may be tapered, as shown by dashed lines in Fig. 1B. In some embodiments, the sidewalls of IL layer 112A and HK gate oxide layer 112B may be in contact with sidewalls of S / D regions 110.

[0018] In some embodiments, the first diffusion barrier layer 112C may be disposed directly on the HK gate oxide layer 112B and overlies the portions of fin structure 108 that extend over STI regions 106, as described below with respect to Fig. 4-6. In some embodiments, the first diffusion barrier layer 112C may include a metal nitride layer, such as a titanium nitride (TiN) layer, with metal atoms as dopants in the metal nitride layer. The metal atoms diffuse from the gate metal fill layer 112F into the first diffusion barrier layer 112C through the WFM layer 112E and the second diffusion barrier layer 112D. In some embodiments, the metal atoms may include aluminum atoms (Al atoms) if the gate metal fill layer 112F includes an Al layer.

[0019] In some embodiments, the first diffusion barrier layer 112C may be arranged to prevent or minimize the diffusion of these metal atoms from the gate metal fill layer 112F into the HK gate oxide layer 112B. The presence of such diffused metal atoms in the HK gate oxide layer 112B may cause threshold voltage variations in the semiconductor device 100 and consequently degrade the device's performance.To prevent or minimize such diffusion of metal atoms, the first diffusion barrier layer 112C may be formed in an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process (described below) to have an amorphous structure and a structure density that can limit the concentration of metal atoms diffusing from the gate metal fill layer 112F into the first diffusion barrier layer 112C to about 10 atomic % or less. By limiting the concentration of the diffused metal atoms to about 10 atomic % or less, the diffusion of the metal atoms into the HK gate oxide layer 112B can be prevented or minimized.In some embodiments, the first diffusion barrier layer 112C may include a conductive metal nitride, such as TiN, with a Ti concentration of about 30 at.% to about 70 at.% and an Al dopant concentration of about 1 at.% to about 10 at.%. In some embodiments, sidewalls of the first diffusion barrier layer 112C may be vertical, as shown by solid lines in FIG. Fig. 1B, or may be tapered, as shown by dashed lines in Fig. 1B. In some embodiments, the sidewalls of the first diffusion barrier layer 112C may be in contact with sidewalls of ESLs 116 and are not in contact with S / D regions 110.

[0020] In some embodiments, the second diffusion barrier layer 112D may be disposed directly on the first diffusion barrier layer 112C and may have a U-shaped cross-sectional profile. In some embodiments, the second diffusion barrier layer 112D may include a metal nitride layer, such as a tantalum nitride (TaN) layer, that is different from the metal nitride layer of the first diffusion barrier layer 112C. Similar to the first diffusion barrier layer 112C, the metal nitride layer of the second diffusion barrier layer 112D may include metal atoms as dopants diffused from the gate metal fill layer 112F through the WFM layer 112E. In some embodiments, the metal atoms may include Al atoms if the gate metal fill layer 112F includes an Al layer.

[0021] In some embodiments, the second diffusion barrier layer 112D may be disposed in addition to the first diffusion barrier layer 112C to prevent or minimize the diffusion of metal atoms from the gate metal fill layer 112F into the HK gate oxide layer 112B. Similar to the first diffusion barrier layer 112C, the second diffusion barrier layer 112D may be formed in an ALD process or a CVD process (described below) to have an amorphous structure and a structure density that may limit the concentration of metal atoms diffused from the gate metal fill layer 112F into the second diffusion barrier layer 112D to about 10 atomic percent to about 50 atomic percent.By limiting the concentration of diffused metal atoms to about 10 at.% to about 50 at.%, the concentration of diffused metal atoms in the first diffusion barrier layer 112C may be limited to 10 at.% or less, which in turn may prevent or minimize the diffusion of the metal atoms into the HK gate oxide layer 112B. In some embodiments, the second diffusion barrier layer 112D may have a thickness T4 that is greater than the thickness T3 of the first diffusion barrier layer 112C. In some embodiments, thicknesses T3 and T4 may be about 2 nm to about 10 nm. Within this thickness range, the diffusion of metal atoms into the HK gate oxide layer 112B may be adequately prevented or minimized without compromising device size and manufacturing costs.

[0022] In some embodiments, the WFM layer 112E may include Ti, titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), or tantalum aluminum carbide (TaAlC). In some embodiments, the WFM layer 112E may include an alloy of Ti and Al. In some embodiments, the gate metal fill layer 112F may include a suitable conductive material, such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and a combination thereof.

[0023] In some embodiments, the insulating cap layer 112H may be disposed directly on the conductive cap layer 112G. The insulating cap layer 112H may protect the underlying conductive cap layer 112G from structural and / or compositional degradation during subsequent processing of the semiconductor device 100. In some embodiments, the insulating cap layer 112H may include a nitride material, such as SiN, and may have a thickness of about 5 nm to about 10 nm for adequate protection of the underlying conductive cap layer 112G.

[0024] In some embodiments, the conductive cap layer 112G may be disposed directly on the second diffusion barrier layer 112D, the WFM layer 112E, and the gate metal fill layer 112F. The conductive cap layer 112G may provide a conductive interface between the gate metal fill layer 112F and the gate contact structure 122 to electrically connect the gate metal fill layer 112F to the gate contact structure 122 without forming the gate contact structure 122 directly on or in the gate metal fill layer 112F. The gate contact structure 122 is not formed directly on or in the gate metal fill layer 112F to prevent contamination by any of the processing materials used in the formation of the gate contact structure 122. Contamination of the gate metal fill layer 112F may lead to degradation of device performance.Therefore, by using the conductive cap layer 112G, the gate structure 112 may be electrically connected to the gate contact structure 122 without compromising the integrity of the gate structure 112. In some embodiments, the conductive cap layer 112G may include a metallic material, such as W, Ru, Mo, Co, other suitable metallic materials, and a combination thereof.

[0025] In some embodiments, the gate structure 112 may be electrically isolated from adjacent S / D regions 110 by gate spacers 114. In some embodiments, each gate spacer 114 may be disposed directly on the first diffusion barrier layer 112C and overlies portions of the HK gate oxide layer 112B and the IL layer 112A. In some embodiments, the gate spacer 114 may include a nitride spacer 114A and an oxide spacer 114B. In some embodiments, the nitride spacer 114A may have an L-shaped cross-sectional profile. In some embodiments, a horizontal portion of nitride spacer 114A may be disposed directly on the first diffusion barrier layer 112C and a vertical portion of nitride spacer 114A may be disposed directly along sidewalls of the second diffusion barrier layer 112D.In some embodiments, oxide spacer 114B may be disposed directly on nitride spacer 114A. In some embodiments, nitride spacer 114A may comprise silicon nitride (SiN. x ) and may not contain any oxide material. In some embodiments, the oxide spacer 114B may comprise silicon oxide (SiO x ) and cannot contain any nitride material.

[0026] In some embodiments, ESLs 116 may be directly located on S / D areas 110 (in Fig. 1A; in cross-sectional view of Fig. 1B not visible). In some embodiments, ESLs 116 may have a dielectric constant of about 4 to about 7 and may include a dielectric material such as lanthanum oxide (LaO), aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), TiO2, Ta2O3, ZrO2, HfO2, SiN, hafnium silicide (HfSi), aluminum oxynitride (AlON), SiO2, SiC, SiN, and zinc oxide (ZnO). In some embodiments, ILD layers 118 may be deposited directly on ILD layers 118 (in Fig. 1A; in cross-sectional view of Fig. 1B). In some embodiments, ILD layers 118 may include an insulating material, such as SiO2, SiN, SiON, SiCN, and SiOCN. In some embodiments, top surfaces of ILD layers 118, ESL 116, and the insulating cap layer 112H may be substantially coplanar with each other.

[0027] In some embodiments, the S / D contact structure 120 may include (i) silicide layers 120A disposed in S / D regions 110, and (ii) contact plugs 120B disposed on the silicide layers 120A. In some embodiments, the silicide layer 120A in the n-FinFET 100 may comprise titanium silicide (Ti x Si y ), tantalum silicide (Ta x Si y ), molybdenum (Mo x Si y ), zirconium silicide (Zr x Si y ), hafnium silicide (Hf x Si y ), scandium silicide (Sc x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), lutetium silicide (Lu x Si y ), erbium silicide (Er x Si y ), ybterbium silicide (Yb x Si y ), europium silicide (Eu x Si y ), thorium silicide (Th x Si y), other suitable metal silicide materials, or a combination thereof. In some embodiments, the silicide layer 120A in the p-FinFET 100 may comprise nickel silicide (Ni x Si y ), cobalt silicide (Co x Si y ), manganese silicide (Mn x Si y ), tungsten silicide (W x Si y ) Iron silicide (Fe x Si y ), rhodium silicide (Rh x Si y ), palladium silicide (Pd x Si y ), ruthenium silicide (Ru x Si y ), platinum silicide (Pt x Si y ), iridium silicide (Ir x Si y ), osmium silicide (Os x Si y), other suitable metal silicide materials, or a combination thereof. In some embodiments, contact plugs 120B may include low-resistivity conductive materials (e.g., resistivity of about 50 μΩ-cm, about 40 μΩ-cm, about 30 μΩ-cm, about 20 μΩ-cm, or about 10 μΩ-cm), such as Co, W, Ru, Al, Mo, iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), other suitable low-resistivity conductive materials, and a combination thereof. In some embodiments, gate contact structure 122 may include a conductive material similar to that of contact plug 120B.

[0028] With reference to Fig. 1C, in some embodiments, the semiconductor device 100 may include an HK gate oxide layer 112B*, first diffusion barrier layer 112C*, and second diffusion barrier layer 112D*, instead of the HK gate oxide layer 112B, first diffusion barrier layer 112C, and second diffusion barrier layer 112D of Fig. 1B. The discussion of HK gate oxide layer 112B, first diffusion barrier layer 112C, and second diffusion barrier layer 112D applies to HK gate oxide layer 112B*, first diffusion barrier layer 112C*, and second diffusion barrier layer 112D*, respectively, unless otherwise stated. In some embodiments, first diffusion barrier layer 112C* is sandwiched between spacers 114, as shown in Fig. 1C and not arranged under spacers 114, such as the first diffusion barrier layer 112C shown in Fig. 1B. Consequently, the horizontal portions of nitride spacers 114A are disposed directly on the HK gate oxide layer 112B*, and the vertical portions of nitride spacers 114A are disposed directly along sidewalls of the first diffusion barrier layer 112C*. In some embodiments, similar to the second diffusion barrier layer 112D*, the first diffusion barrier layer 112C* may have a U-shaped cross-sectional profile instead of the linear profile shown in Fig. 1B. The vertical portions of the second diffusion barrier layer 112D* are disposed directly on the vertical portions of the first diffusion barrier layer 112C*, and the horizontal portion of the second diffusion barrier layer 112D* is disposed directly on the horizontal portion of the first diffusion barrier layer 112C*.

[0029] With reference to Fig. 1D, in some embodiments, the semiconductor device 100 may include IL layer 112A*, HK gate oxide layer 112B*, and first diffusion barrier layer 112C*, instead of IL layer 112A, HK gate oxide layer 112B, and first diffusion barrier layer 112C of Fig. 1B. The discussion of IL layer 112A, HK gate oxide layer 112B, and first diffusion barrier layer 112C applies to IL layer 112A*, HK gate oxide layer 112B*, and first diffusion barrier layer 112C*, respectively, unless otherwise stated. In some embodiments, the stack of IL layer 112A*, HK gate oxide layer 112B*, and first diffusion barrier layer 112C* is disposed between spacers 114, as shown in Fig. 1D, and not arranged under spacers 114 like the stack of IL layer 112A, HK gate oxide layer 112B and first diffusion barrier layer 112C as in Fig. 1B. As a result, nitride spacers 114A are disposed directly on fin structure 108, and sidewalls of IL layer 112A*, HK gate oxide layer 112B*, and first diffusion barrier layer 112C* are in contact with sidewalls of nitride spacers 114A.

[0030] Fig. 2A and Fig. 2B illustrate various cross-sectional views of a semiconductor device 200 according to some embodiments. In some embodiments, semiconductor device 200 may represent a MOSFET and may be referred to as "MOSFET 200." The discussion of elements in Fig. 2A and Fig. 2B with the same designations applies to each other unless otherwise stated.

[0031] With reference to Fig. 2A, in some embodiments, semiconductor device 200 may include (i) a substrate 204, (ii) STI regions 206 disposed on substrate 204, (iii) S / D regions 210 disposed within substrate 204, (iv) gate structure 212 disposed on substrate 204, (v) gate spacers 214 disposed along sidewalls of gate structure 212, (vi) ILD layers 118 disposed directly on gate spacers 214 and STI regions 206. The discussion of substrate 104, STI regions 106, and ILD layers 118 applies to substrate 204, STI regions 206, and ILD layers 218 unless otherwise noted.

[0032] In some embodiments, S / D regions 210 may include doped regions in substrate 204. Doped regions may include n-type dopants, such as phosphorus and other suitable n-type dopants for n-MOSFET 200, or p-type dopants, such as boron and other suitable p-type dopants for p-MOSFET 200.

[0033] Gate structure 212 may be a multi-layer structure and may include (i) an IL layer 212A, (ii) an HK gate oxide layer 212B, (iii) a first diffusion barrier layer 212C, (iv) a second diffusion barrier layer 212D, (v) a WFM layer 212E, and (vi) a gate metal fill layer 212F. The discussion of IL layer 112A, HK gate oxide layer 112B, first diffusion barrier layer 112C, second diffusion barrier layer 112D, WFM layer 112E, and gate metal fill layer 112F applies to IL layer 212A, HK gate oxide layer 212B, first diffusion barrier layer 212C, second diffusion barrier layer 212D, WFM layer 212E, and gate metal fill layer 212F, respectively, unless otherwise stated.

[0034] With reference to Fig. 2B, in some embodiments, semiconductor device 200 may include an HK gate oxide layer 212B*, first diffusion barrier layer 212C*, and second diffusion barrier layer 212D* instead of HK gate oxide layer 212B, first diffusion barrier layer 212C, and second diffusion barrier layer 212D of Fig. 2A. The discussion of HK gate oxide layer 212B, first diffusion barrier layer 212C, and second diffusion barrier layer 212D applies to HK gate oxide layer 212B*, first diffusion barrier layer 212C*, and second diffusion barrier layer 212D*, respectively, unless otherwise stated. In some embodiments, first diffusion barrier layer 212C* is disposed between spacers 214, as shown in Fig. 2B, and not arranged under spacers 214, like the first diffusion barrier layer 212C, as in Fig. 2A. As a result, the bottom surfaces of gate spacers 214 are disposed directly on HK gate oxide layer 112B*, and the sidewalls of gate spacers 214 are disposed directly along sidewalls of the first diffusion barrier layer 212C*. In some embodiments, the first diffusion barrier layer 212C*, similar to the second diffusion barrier layer 212D*, may have a U-shaped cross-sectional profile instead of the linear profile shown in Fig. 2A. The vertical portions of the second diffusion barrier layer 212D* are disposed directly on the vertical portions of the first diffusion barrier layer 212C*, and the horizontal portion of the second diffusion barrier layer 212D* is disposed directly on the horizontal portion of the first diffusion barrier layer 212C*.

[0035] Fig. 3 is a flow diagram of an exemplary method 300 for manufacturing semiconductor device 100 with the cross-sectional view of Fig. 1B according to some embodiments. For illustration, the Fig. 3 illustrates operations with reference to the exemplary manufacturing process for manufacturing semiconductor device 100 as shown in Fig. 4-16 illustrates this. Fig. 4 is an isometric view of semiconductor device 100 and Fig. 5 is a cross-sectional view of semiconductor device 100 along line BB of Fig. 4 in a manufacturing stage of semiconductor device 100 according to some embodiments. Fig. 6 is an isometric view of semiconductor device 100 and Fig. 7 is a cross-sectional view of semiconductor device 100 along line CC of Fig. 6 in another manufacturing stage of semiconductor device 100 according to some embodiments. Fig. 8-16 are cross-sectional views of semiconductor device 100 along line AA of Fig. 1A in various manufacturing stages of semiconductor device 100 according to some embodiments. Operations may be performed in a different order or not performed depending on specific applications. It should be noted that method 300 may not produce a complete semiconductor device 100. Therefore, it is understood that additional processes may be provided before, during, and after method 300, and that some other processes may only be briefly described here. The discussion of elements in Fig. 1A-1D and 4-16 with the same designations apply to each other unless otherwise stated.

[0036] With reference to Fig. 3, a fin structure is formed on a substrate in operation 305. For example, as described with reference to Fig. 4 and Fig. 5, fin structure 108 is formed on substrate 104. In some embodiments, the formation of fin structure 108 may include patterning of substrate 104 using one or more photolithography processes, including double patterning or multiple patterning processes. The formation of fin structure 108 may be followed by the formation of STI regions 106, as shown in Fig. 4 shown.

[0037] With reference to Fig. 3, in operation 310, a first and second oxide layer are formed on the fin structure. For example, as described with reference to Fig. 4 and Fig. 5, IL layer 112A (also referred to as "first oxide layer 112A") and HK gate oxide layer 112B (also referred to as "second oxide layer 112B") are formed on fin structure 108. In some embodiments, the formation of IL layer 112A may include performing an oxidation process on the surfaces of fin structure 108 exposed above STI regions 106. In some embodiments, the oxidation process may be performed in an oxidizing ambient at a temperature of about 30°C to about 200°C or at other suitable oxidation temperatures. In some embodiments, the oxidizing ambient may include a combination of ozone (O3), a mixture of ammonia hydroxide, hydrogen peroxide, and water, and / or a mixture of hydrochloric acid, hydrogen peroxide, and water.In some embodiments, the oxidation process may be performed in an oxygen environment or in a steam and oxygen environment at a temperature of about 400°C to about 600°C.

[0038] In some embodiments, the formation of HK gate oxide layer 112B may include depositing an oxide layer comprising a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2), on IL layer 112A. In some embodiments, the portions of the oxide layer (not shown) on STI regions 106 that are not covered by first diffusion barrier layer 112C may be etched after formation of first diffusion barrier layer 112C in subsequent operation 315 to form HK gate oxide layer 112B, as shown in Fig. 4 and Fig. 5 shown.

[0039] With reference to Fig. 3, in operation 315, a first diffusion barrier layer is formed on the second oxide layer. As described, for example, with reference to Fig. 4 and Fig. 5, the first diffusion barrier layer 112C is formed on the HK gate oxide layer 112B. In some embodiments, the formation of the first diffusion barrier layer 112C may comprise depositing two or more monolayers of a metal nitride (not shown) on the HK gate oxide layer 112B. Each metal nitride monolayer may be deposited in one ALD cycle. In some embodiments, the total thickness of the metal nitride layer deposited on the HK gate oxide layer 112B may be measured after the deposition of each metal nitride monolayer. The ALD process may be terminated once the desired total thickness T3 of the metal nitride layer is reached.

[0040] The subsequent deposition of the metal nitride monolayers may form the first diffusion barrier layer 112C with higher conformality, higher thickness uniformity (e.g., about 10% to about 50% higher thickness uniformity), and higher density (e.g., about 10% to about 50% higher density) than similar metal nitride layers formed in physical vapor deposition (PVD) processes with a same thickness as the first diffusion barrier layer 112C. The higher density of the first diffusion barrier layer 112C may minimize diffusion of metal atoms (e.g., Al atoms) from the gate metal fill layer 112F into the first diffusion barrier layer 112C and maintain the concentration of metal atoms in the first diffusion barrier layer 112C at about 10 atomic % or less.Additionally, the higher thickness uniformity across the first diffusion barrier layer 112C can prevent or minimize structural weaknesses in the first diffusion barrier layer 112C through which the metal atoms can diffuse. The structural weaknesses may be present in relatively thinner regions if there is no uniform thickness across the first diffusion barrier layer 112C. Consequently, with such a high-density and highly uniform first diffusion barrier layer 112C, the concentration of metal atoms that diffuse into the HK gate oxide layer 112B from the gate metal fill layer 112F through the first diffusion barrier layer 112C can be prevented or minimized to improve device performance.

[0041] In some embodiments, the formation of the first diffusion barrier layer 112C may include the following operations: (i) performing an ALD cycle (e.g., one ALD cycle) to deposit the metal nitride monolayer (not shown) on the HK gate oxide layer 112B, (ii) performing another ALD cycle (e.g., one ALD cycle) to deposit another metal nitride monolayer (not shown) on the underlying metal nitride monolayer in an ALD process, (iii) measuring the total thickness of the metal nitride layer deposited on the HK gate oxide layer 112B, (iv) determining whether the measured total thickness is equal to thickness T3, (v) repeating steps (ii)-(iv) if the measured total thickness is less than thickness T3, (vi) terminating the ALD process once thickness T3 of the metal nitride layer is reached, and (vii) Etching the horizontal portions of the metal nitride layer on STI regions 106 to form the first diffusion barrier layer 112C, as shown in Fig. 4 and Fig. 5. In some embodiments, the metal nitride layer may be evaluated after deposition of each metal nitride monolayer to determine whether it is amorphous.

[0042] In some embodiments, performing the ALD cycle to form each monolayer of the metal nitride layer (e.g., TiN layer) may include the following operations: (i) flowing a metal precursor gas (e.g., titanium tetrachloride (TiCl4)) on the HK gate oxide layer 112B or on the metal nitride monolayer formed in a previous ALD cycle, (ii) purging to purge gas-phase reactants, (iii) flowing a nitrogen precursor gas (e.g., ammonia (NH3)) to react with the metal precursor chemisorbed on the HK gate oxide layer 112B or on the metal nitride monolayer (e.g., TiN monolayer) formed in the previous ALD cycle and to form a metal nitride monolayer, and (iv) purging byproducts (e.g., hydrogen chloride gas (HCl gas) and nitrogen gas (N gas)) formed during the reaction between the metal and nitrogen precursors.In some embodiments, the chemical reaction between the metal and nitrogen precursors can be represented by a chemical reaction formula: 6TiCl4 + 8NH3 → 6TiN + 24HCl + 4N2. In some embodiments, the first diffusion barrier layer 112C can be formed using a CVD process. The parameters (e.g., RF power, DC power, and / or argon and nitrogen flow ratio) of the CVD process can be modulated to obtain the first diffusion barrier layer 112C with a higher density than that achieved in PVD processes.

[0043] With reference to Fig. 3, in operation 320, a polysilicon structure is formed on the first diffusion barrier layer. For example, as described with reference to Fig. 6 and Fig. 7, polysilicon structure 612 is formed directly on the first diffusion barrier layer 112C. In some embodiments, the formation of polysilicon structure 612 may include the following operations: (i) depositing a polysilicon layer (not shown) on the structures of Fig. 4 and (ii) performing a patterning process (e.g., lithography process) on the polysilicon layer to form the polysilicon structure 612, as in Fig. 6 and Fig. 7. In some embodiments, a hard mask layer 624 may be formed during the formation of polysilicon structure 612.

[0044] With reference to Fig. 3, in operation 325, gate spacers are formed along sidewalls of the polysilicon structure and on the first diffusion barrier layer. As described, for example, with reference to Fig. 8 and Fig. 9, gate spacers 114 are formed with spacers 114A and 114B along sidewalls of polysilicon structure 612 and on the first diffusion barrier layer 112C. In some embodiments, the formation of gate spacers 114 may include the following operations: (i) depositing a nitride layer 814A directly on the structures of Fig. 6 and Fig. 7, as in Fig. 8, (ii) depositing an oxide layer 814B directly on nitride layer 814A to form the structure of Fig. 8, (iii) performing an annealing process on the structure of Fig. 8 to densify the nitride layer 814A, (iv) etching horizontal portions of oxide layer 814B to form spacers 114B, as in Fig. 9, and (v) etching portions of densified nitride layer 814A exposed after etching oxide layer 814B to form spacers 114A, as shown in Fig. 9 shown.

[0045] After the formation of gate spacers 114, the portions of IL layer 112A, HK gate oxide layer 112B, and first diffusion barrier layer 112C that do not underlie polysilicon structure 612 and spacers 114 may be removed, and surface portions of fin structure 108 may be exposed, as shown in Fig. 9. In some embodiments, the portions of IL layer 112A, HK gate oxide layer 112B, and first diffusion barrier layer 112C may be removed by a wet etching process or a dry etching process.

[0046] With reference to Fig. 3, S / D areas are formed on the fin structure in Operation 330. For example, with reference to Fig. 10 and Fig. 11, S / D regions 110 are formed on fin structure 108. In some embodiments, the formation of S / D regions 110 may include the following operations: (i) forming S / D openings 1010, as shown in Fig. 10, by etching through the exposed surface portions of fin structure 108 of Fig. 9 and (ii) epitaxial growth of a semiconductor material (e.g. Si or SiGe) with n- or p-dopants in S / D openings 1010, as in Fig. 11. The formation of S / D regions 110 may be followed by the formation of ESLs 116 and ILD layers 118, as shown in Fig. 11 shown.

[0047] With reference to Fig. 3, in operation 335, the polysilicon structure is replaced by a second diffusion barrier layer, a WFM layer, and a gate metal fill layer. As described, for example, with reference to Fig. 12 and Fig. 13, the polysilicon structure 612 is replaced by the second diffusion barrier layer 112D, WFM layer 112E, and gate metal fill layer 112F. In some embodiments, replacing the polysilicon structure 612 with the second diffusion barrier layer 112D, WFM layer 112E, and gate metal fill layer 112F may include the following operations: (i) etching the polysilicon structure 612 to form a gate opening 1212, as shown in Fig. 12, (ii) depositing the second diffusion barrier layer 112D in gate opening 1212, (iii) depositing the WFM layer 112E on the second diffusion barrier layer 112D, (iv) depositing the gate metal fill layer 112F on the WFM layer 112E, and (v) performing a chemical mechanical polishing (CMP) process to substantially coplanarize top surfaces of the second diffusion layer 112D, WFM layer 112E, and gate metal fill layer 112F with top surfaces of ILD layer 118, as shown in Fig. 13 shown.

[0048] The deposition of the second diffusion barrier layer 112D may include depositing another metal nitride layer (e.g., TaN) that is different from the metal nitride layer (e.g., TiN) of the first diffusion barrier layer 112C. Similar to the process for depositing the first diffusion barrier layer 112C, in some embodiments, the deposition of the second diffusion barrier layer 112D may include the following operations: (i) performing an ALD cycle (e.g., one ALD cycle) to deposit a monolayer of TaN (not shown) in gate opening 1212, (ii) performing another ALD cycle (e.g.,one ALD cycle) to deposit another TaN monolayer (not shown) on the underlying TaN monolayer, (iii) measuring the total thickness of the TaN layer deposited in gate opening 1212, (iv) determining whether the measured total thickness is equal to thickness T4, (v) repeating steps (ii)-(iv) to determine whether the measured total thickness is less than thickness T4, (vi) terminating the ALD process once thickness T4 of TaN layer is reached. In some embodiments, the TaN layer may be evaluated after deposition of each monolayer to determine whether it is amorphous. In some embodiments, the ALD cycle for depositing each TaN monolayer may be similar to depositing the TiN monolayer of the first diffusion barrier layer 112C in operation 315, except that a Ta precursor is used instead of Ti precursor (e.g., TiCl4).In some embodiments, the second diffusion barrier layer 112D may be formed using a CVD process.

[0049] Subsequent deposition of the monolayers may form the second diffusion barrier layer 112D with higher conformality and a higher density (e.g., about 10% to about 50% higher density) than similar metal nitride layers formed in PVD processes with the same thickness as the second diffusion barrier layer 112D. The higher density of the second diffusion barrier layer 112D may minimize diffusion of metal atoms (e.g., Al atoms) from the gate metal fill layer 112F into the second diffusion barrier layer 112D and maintain the concentration of metal atoms in the second diffusion barrier layer 112D at or below about 50 atomic %.As a result, the higher density of the second diffusion barrier layer 112D, in addition to the higher density of the first diffusion barrier layer 112C (discussed above), may minimize the concentration of metal atoms diffusing into the first diffusion barrier layer 112C from the gate metal fill layer 112F through the second diffusion barrier layer 112D to about 10 atomic % or less.

[0050] With reference to Fig. 3, in operation 340, gate cap layers are formed on the second diffusion barrier layer, the WFM layer, and the gate metal fill layer. As described, for example, with reference to Fig. 14 and Fig. 15, gate capping layers comprising conductive capping layer 112G and insulating capping layer 112H are formed on the second diffusion barrier layer 112D, the WFM layer 112E, and the gate metal fill layer 112F. In some embodiments, the formation of conductive capping layer 112G may include (i) etching the second diffusion barrier layer 112D, the WFM layer 112E, and the gate metal fill layer 112F to form opening 1412, as shown in Fig. 14, and (ii) depositing the conductive material of the conductive cap layer 112G in opening 1412, as shown in Fig. 15. In some embodiments, the formation of the insulating cap layer 112H may comprise (i) depositing the material of the insulating cap layer 112H on the conductive cap layer 112G to fill opening 1412, and (ii) performing a CMP process on the deposited material of the insulating cap layer 112H to substantially coplanarize the top surface of the insulating cap layer 112H with top surfaces of ILD layers 118, as shown in Fig. 15 shown.

[0051] With reference to Fig. 3, in operation 345, contact structures can be formed on S / D regions and in the gate cap layers. For example, as in Fig. 16, S / D contact structures 120 are formed on S / D regions 110 and the gate contact structure 122 is formed in the conductive cap layer 112G and insulating cap layer 112H.

[0052] In some embodiments, semiconductor device 100 may be illustrated with the cross-sectional view of Fig. 1C using method 300 as described above with reference to Fig. 3-16, except that (i) operation 310 may be followed by operation 320, (ii) polysilicon structure 612 may be formed directly on HK gate oxide layer 112B in operation 320 instead of being formed directly on first diffusion barrier layer 112C in operation 320, (iii) spacers 114A may be formed directly on HK gate oxide layer 112B in operation 325 instead of being formed directly on first diffusion barrier layer 112C in operation 325, (iv) first diffusion barrier layer 112C may be formed in gate opening 1212 after removal of polysilicon structure 612 and before formation of second diffusion barrier layer 112D in operation 335 instead of being formed in operation 315, and (v) the conductive cap layer 112G, in addition to being formed directly on the second diffusion barrier layer 112D, WFM layer 112E and gate metal fill layer 112F in operation 340,can be formed directly on the first diffusion barrier layer 112C.,

[0053] In some embodiments, semiconductor device 100 may be illustrated with the cross-sectional view of Fig. 1D using method 300 as described above with reference to Fig. 3-16, except that (i) the portions of IL layer 112A, HK gate oxide layer 112B, and first diffusion barrier layer 112C that do not underlie polysilicon structure 612 and spacers 114A and 114B may be removed after formation of polysilicon structure 612 in operation 320, rather than being removed after formation of spacers 114A and 114B in operation 325, and (ii) spacers 114A may be formed directly on fin structure 108 in operation 325, rather than being formed directly on first diffusion barrier layer 112C in operation 325.

[0054] Fig. 17 is a flow diagram of an exemplary method 1700 for manufacturing semiconductor device 200 with the cross-sectional view of Fig. 2A according to some embodiments. For illustrative purposes, the operations described in Fig. 17, with reference to the exemplary manufacturing process for manufacturing semiconductor device 200 as shown in Fig. 18-22 illustrates and describes. Fig. 18-22 are cross-sectional views of semiconductor device 200 at various stages of fabrication of semiconductor device 200 according to some embodiments. Operations may be performed in a different order or not at all depending on specific applications. It should be noted that method 1700 may not produce a complete semiconductor device 200. Therefore, it is understood that additional processes may be provided before, during, and after method 1700, and that some other processes may only be briefly described here. The discussion of elements in Fig. 2A, 2B and 18-22 with the same designations apply to each other unless otherwise stated.

[0055] With reference to Fig. 17, in operation 1705, a first and second oxide layer are formed on a substrate. As described, for example, with reference to Fig. 18, IL layer 212A (also referred to as "first oxide layer 212A") and HK gate oxide layer 212B (also referred to as "second oxide layer 212B") are formed on the substrate 204. In some embodiments, the process for forming IL layer 212A and HK gate oxide layer 212B may be the same as the process for forming IL layer 112A and HK gate oxide layer 112B, respectively, in operation 310, as described with reference to Fig. 3-5 described.

[0056] With reference to Fig. 17, in operation 1710, a first diffusion barrier layer is formed on the second oxide layer. For example, as described with reference to Fig. 18, the first diffusion barrier layer 212C is formed on the HK gate oxide layer 212B. In some embodiments, the process for forming the first diffusion barrier layer 212C may be the same as the process for forming the first diffusion barrier layer 112C in operation 315, as described with reference to Fig. 3-5. The formation of the first diffusion barrier layer 212C may be followed by the formation of STI regions 206, as shown in Fig. 19 shown.

[0057] With reference to Fig. 17, in operation 1715, a polysilicon structure is formed on the first diffusion barrier layer. For example, as in Fig. As shown in Figure 19, the polysilicon structure 1912 is formed directly on the first diffusion barrier layer 212C.

[0058] With reference to Fig. 17, S / D regions are formed in the substrate in operation 1720. As described, for example, with reference to Fig. 20, S / D regions 210 are formed in substrate 204. In some embodiments, the formation of S / D regions 110 may include forming doped regions in substrate 204 by performing doping processes in substrate 204 through first and second oxide layers 212A and 212B and first diffusion barrier layer 212C.

[0059] With reference to Fig. 17, in operation 1725, gate spacers are formed along sidewalls of the polysilicon structure and on the first diffusion barrier layer. For example, as in Fig. 20, gate spacers 214 are formed along sidewalls of polysilicon structure 1912 and on the first diffusion barrier layer 212C. The formation of gate spacers 214 may be followed by the formation of ILD layers 218, as shown in Fig. 20 shown.

[0060] With reference to Fig. 17, in operation 1730, the polysilicon structure is replaced by a second diffusion barrier layer, a WFM layer, and a gate metal fill layer. As described, for example, with reference to Fig. 21 and Fig. 22, the polysilicon structure 1912 is replaced by the second diffusion barrier layer 212D, WFM layer 212E, and gate metal fill layer 212F. In some embodiments, replacing the polysilicon structure 1912 with the second diffusion barrier layer 212D, WFM layer 212E, and gate metal fill layer 212F may include the following operations: (i) etching the polysilicon structure 1912 to form gate opening 2112, as shown in Fig. 21, (ii) depositing the second diffusion barrier layer 212D in gate opening 2112, (iii) depositing the WFM layer 212E on the second diffusion barrier layer 212D, (iv) depositing the gate metal fill layer 212F on the WFM layer 212E, and (v) performing a CMP process to substantially coplanarize top surfaces on the second diffusion layer 212D, WFM layer 212E, and gate metal fill layer 212F with top surfaces of ILD layer 218, as shown in Fig. 22 shown.

[0061] In some embodiments, the semiconductor device 200 may be illustrated in the cross-sectional view of Fig. 2B using method 1700 as described above with reference to Fig. 17-22, except that (i) operation 1705 may be followed by operation 1715, (ii) polysilicon structure 1912 may be formed directly on HK gate oxide layer 212B in operation 1715 instead of being formed directly on first diffusion barrier layer 212C in operation 1710, (iii) spacers 214 may be formed directly on HK gate oxide layer 212B in operation 1725 instead of being formed directly on first diffusion barrier layer 212C in operation 1725, and (iv) first diffusion barrier layer 212C may be formed in gate opening 2112 after removal of polysilicon structure 1912 and before formation of second diffusion barrier layer 212D in operation 1730, instead of in operation to be formed in 1710.

[0062] The present disclosure provides example gate structures (e.g., gate structures 112 and 212) with diffusion barrier layers (e.g., diffusion barrier layers 112C, 112D, 212C, and 212D) in FETs (e.g., FinFETs 100 and MOSFETs 200) and example methods (e.g., methods 300 and 1700) for forming such FETs to improve threshold voltage control in the FETs. In some embodiments, the example gate structure of a FET may include a high-k gate oxide layer (e.g., high-k gate oxide layer 112B or 212B), first and second diffusion barrier layers (e.g., first and second diffusion barrier layers 112C and 112D or 212C and 212D) disposed on the high-k gate oxide layer, and a gate metal fill layer (e.g., gate metal fill layer 112F or 212F) disposed on the first and second diffusion barrier layers. In some embodiments, the first and second diffusion barrier layers may be arranged to inhibit the diffusion of metal atoms (e.g.,B. Al atoms) from the gate metal fill layer to the high-k gate oxide layer. The presence of such diffused metal atoms in the high-k gate oxide layer can cause threshold voltage variations in the FET and consequently degrade device performance. In some embodiments, the first diffusion barrier layer can be formed to have an amorphous structure and a feature density that can limit the concentration of metal atoms diffusing from the gate metal fill layer into the first diffusion barrier layer to about 10 atomic % or less. Likewise, the second diffusion barrier layer can be formed to have an amorphous structure and a feature density that can limit the concentration of metal atoms diffusing from the gate metal fill layer into the second diffusion barrier layer to about 10 atomic % to about 50 atomic %.Within these concentration constraints, the diffusion of metal atoms into the high-k gate oxide layer can be prevented or minimized.

[0063] In some embodiments, a semiconductor device includes a substrate, a fin structure disposed on the substrate, and a gate structure. The gate structure includes a high-k gate oxide layer disposed on the fin structure, a diffusion barrier layer disposed on the high-k gate oxide layer, and a metal layer disposed on the diffusion barrier layer. The semiconductor device further includes a gate spacer disposed on the diffusion barrier layer and an S / D region disposed on the fin structure. A sidewall of the S / D region is in contact with a sidewall of the high-k gate oxide layer.

[0064] In some embodiments, a semiconductor device includes a substrate and a gate structure. The gate structure includes an oxide layer disposed on the substrate, a diffusion barrier layer disposed on the oxide layer, and a metal layer disposed on the diffusion barrier layer. The semiconductor device further includes a gate spacer disposed on the diffusion barrier layer and an S / D region disposed in the substrate. A top surface of the S / D region is in contact with a bottom surface of the oxide layer.

[0065] In some embodiments, a method includes forming first and second oxide layers on a substrate, forming a first diffusion barrier layer on the second oxide layer, forming a polysilicon structure on the first diffusion barrier layer, forming a gate spacer on the first diffusion barrier layer and on the polysilicon structure, and replacing the polysilicon structure with a second diffusion barrier layer and a metal layer.

[0066] The foregoing outlines features of some embodiments so that those skilled in the art will better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can already use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same benefits of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 541,339

[0001] Cited non-patent literature

[0000] Semiconductor Device Structure and Method”, filed on September 29, 2023

[0001]

Claims

[1] A semiconductor device comprising: a substrate; a fin structure arranged on the substrate; a gate structure comprising: a high-k gate oxide layer disposed on the fin structure, a first diffusion barrier layer disposed on the high-k gate oxide layer, and a metal layer disposed on the first diffusion barrier layer; a gate spacer disposed on the first diffusion barrier layer; and a source / drain (S / D) region disposed on the fin structure, wherein a sidewall of the S / D region is in contact with a sidewall of the high-k gate oxide layer. [2] The semiconductor device according to claim 1, wherein the gate spacer is disposed on a top surface of the first diffusion barrier layer. [3] The semiconductor device according to claim 1 or 2, wherein the gate spacer is disposed on a top surface of the high-k gate oxide layer and along a sidewall of the first diffusion barrier layer. [4] A semiconductor device according to any preceding claim, wherein the gate spacer is disposed on a first top surface portion of the first diffusion barrier layer, and wherein the metal layer is disposed on a second top surface portion of the first diffusion barrier layer. [5] A semiconductor device according to any preceding claim, wherein a horizontal portion of the gate spacer is disposed on the first diffusion barrier layer and wherein a vertical portion of the gate spacer is disposed on the metal layer. [6] A semiconductor device according to any preceding claim, wherein a horizontal portion of the gate spacer is disposed on the high-k gate oxide layer and wherein a vertical portion of the gate spacer is disposed on the first diffusion barrier layer. [7] A semiconductor device according to any preceding claim, further comprising a second diffusion barrier layer disposed on the first diffusion barrier layer, wherein: a horizontal portion of the gate spacer is disposed on the first diffusion barrier layer; and a vertical portion of the gate spacer is disposed on the second diffusion barrier layer. [8] A semiconductor device according to any preceding claim, wherein the first diffusion barrier layer has a U-shaped cross-sectional profile. [9] A semiconductor device according to any preceding claim, further comprising an etch stop layer disposed on the S / D region, wherein a sidewall of the etch stop layer is in contact with a sidewall of the first diffusion barrier layer. [10] A semiconductor device according to any preceding claim, wherein the first diffusion barrier layer comprises metal dopants at a concentration of about 1 atomic% to about 10 atomic%. [11] A semiconductor device comprising: a substrate; a gate structure comprising: an oxide layer arranged on the substrate, a first diffusion barrier layer disposed on the oxide layer, and a metal layer disposed on the first diffusion barrier layer; a gate spacer disposed on the first diffusion barrier layer; and a source / drain (S / D) region disposed in the substrate, wherein a top surface of the S / D region is disposed under the oxide layer. [12] The semiconductor device according to claim 11, further comprising a high-k oxide layer disposed between the oxide layer and the first diffusion barrier layer. [13] The semiconductor device according to claim 11 or 12, wherein the gate spacer is disposed on a top surface of the first diffusion barrier layer. [14] A semiconductor device according to any one of the preceding claims 11 to 13, wherein the gate spacer is arranged on a top surface of the oxide layer and along a sidewall of the first diffusion barrier layer. [15] A semiconductor device according to any one of the preceding claims 11 to 14, wherein the first diffusion barrier layer comprises a titanium nitride layer and aluminum dopants in the titanium nitride layer. [16] A semiconductor device according to any one of the preceding claims 11 to 15, further comprising a second diffusion barrier layer disposed on the first diffusion barrier layer, the second diffusion barrier layer comprising a tantalum nitride layer and aluminum dopants in the tantalum nitride layer. [17] Method comprising: Forming a first and second oxide layer on a substrate; Forming a first diffusion barrier layer on the second oxide layer; Forming a polysilicon structure on the first diffusion barrier layer; Forming a gate spacer on the first diffusion barrier layer and on the polysilicon structure; and Replacing the polysilicon structure with a second diffusion barrier layer and a metal layer. [18] The method of claim 17, wherein forming the first diffusion barrier layer comprises depositing a metal nitride monolayer on the second oxide layer. [19] The method of claim 17, wherein forming the first diffusion barrier layer comprises depositing an amorphous metal nitride layer on the second oxide layer. [20] The method of any one of claims 17 to 19, further comprising doping a region in the substrate through the first oxide layer, the second oxide layer and the first diffusion barrier layer to form a source / drain region.

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