SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

A semiconductor device (10) comprising a substrate (100), a fin (200), a gate structure (300), a single diffusion break structure (SDB) (400), and a capacitor gate structure (500). The substrate (100) has a first region (R1) and a second region (R2), the second region (R2) being located between the adjacent first regions (R1). The fin (200) is arranged on the substrate (100), the fin (200) located in the second region (R2) having a heavily doped region (HD). The gate structure (300) is arranged on the fin (200) and is located in the first region (R1). The SDB structure (400) is arranged on the fin (200) and is located in the second region (R2). The capacitor gate structure (500) is arranged on the fin (200) and is located in the second region (R2), wherein the capacitor gate structure (500) is arranged on the SDB structure (400).

Description

BACKGROUNDTechnical field

[0001] The disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a fin field effect transistor having a metal oxide semiconductor capacitor and a manufacturing method thereof. Description of the state of the art

[0002] In recent years, the size of semiconductor devices has gradually decreased, and technologies have been proposed to replace planar transistor devices with FinFET devices. To further increase the integration, density, and performance of semiconductor devices, the electrical performance and process yield of fin field-effect transistors need to be further improved through process and / or structural design.

[0003] For example, when a metal oxide semiconductor capacitor (MOSCAP) is deposited on the FinFET device structure, a heavily doped region should be doped in the fins of the FinFET device to achieve high conductivity. However, if an oxide layer is subsequently grown on the fins through a thermal oxidation process, the fins containing the heavily doped regions would consume too much power during oxide layer growth, resulting in the tip of the fins being tapered after the oxide layer growth. Therefore, the reliability of the fabricated semiconductor device is reduced.

[0004] In addition, the area in the FinFET device used for the transistor would be limited by the formation of the MOSCAP.

[0005] Patent Document 1 US 2011 / 0175152 A1 discloses an integrated circuit comprising a fully depleted semiconductor device and a capacitor provided on a semiconductor-on-insulator (SOI) substrate. The fully depleted semiconductor device may be a FinFET semiconductor device or a planar semiconductor device.

[0006] In one embodiment, the integrated circuit comprises a substrate having a first device region and a second device region. The first device region of the substrate comprises a first semiconductor layer present on a buried insulating layer. The buried insulating layer located in the first device region is present on a second semiconductor layer of the substrate. The second device region comprises the second semiconductor layer, but the first semiconductor layer and the buried insulating layer are not present in the second device region. The first device region comprises the fully depleted semiconductor device. A capacitor is present in the second device region. SUMMARY

[0007] The disclosure provides a semiconductor device having the effects of high integration, high density and high performance, and could have relatively good reliability.

[0008] According to some embodiments of the disclosure, a semiconductor device includes a substrate, a fin, a gate structure, a single diffusion break (SDB) structure, and a capacitor gate structure. The substrate has a first region and a second region, the second region being located between the adjacent first regions. The fin is disposed on the substrate, the fin located in the second region including a heavily doped region. The gate structure is disposed on the fin and located in the first region. The SDB structure is disposed on the fin and located in the second region. The capacitor gate structure is disposed on the fin and located in the second region, the capacitor gate structure being disposed on the SDB structure.

[0009] The disclosure also provides a manufacturing method for a semiconductor device. The manufactured semiconductor device exhibits the effects of high integration, high density, and high performance, and may exhibit relatively good reliability.

[0010] According to some embodiments of the disclosure, the semiconductor device manufacturing method includes the following steps. First, forming a fin on a substrate, the fin spanning a first region and a second region of the substrate, the second region being located between adjacent first regions. Next, forming a single diffusion disruption (SDB) structure in the second region of the substrate, an extension direction of the SDB structure being perpendicular to an extension direction of the fin, the SDB structure spanning the fin. Thereafter, forming a heavily doped region in the fin located in the second region. Then, forming a gate structure and a capacitor gate structure on each of the fin located in the first region and the second region of the substrate, the capacitor gate structure being arranged on the SDB structure.

[0011] Based on the above, in the semiconductor device and its manufacturing method provided by the disclosure, the area of ​​the first region for forming the gate structure cannot be reduced by forming the capacitor gate structure in the second region of the substrate, so that the semiconductor device provided by the disclosure can have better effects such as high integration, high density, and high performance. Moreover, the capacitor gate structure formed in the second region of the substrate is arranged on the SDB structure. Therefore, the phenomenon of taper on the top of the ridge in the second region due to the formation of the heavily doped region can be slowed down, so that the semiconductor device provided by the disclosure can have relatively good reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. Fig. 1A is a partial top plan view of a semiconductor device according to an embodiment of the disclosure. Fig. Figure 1B is a schematic partial sectional view along a cross-sectional line AA' of Fig. 1A. Fig. Figure 1C is a schematic partial sectional view along a cross-sectional line BB' of Fig. 1A. Fig. 2 is a schematic flow diagram of a manufacturing method for a semiconductor device according to an embodiment of the disclosure. DESCRIPTION OF THE EMBODIMENTS

[0013] The following examples are listed and described in detail with accompanying drawings, but the examples provided are not intended to limit the scope of the disclosure. Furthermore, the drawings are for illustrative purposes only and are not drawn at actual size. To facilitate understanding, the same elements are identified with the same symbols in the following description.

[0014] Fig. 1A is a partial plan view of a semiconductor device according to an embodiment of the disclosure, Fig. Figure 1B is a partial schematic cross-sectional view taken along a cross-sectional line AA' of Fig. 1A, and Fig. Figure 1C is a partial schematic cross-sectional view along a cross-section line BB' of Fig. 1A.

[0015] With reference to the Fig. 1A-1C, which illustrate a semiconductor device 10 provided by the present embodiment. In the present embodiment, the semiconductor device 10 includes a substrate 100, a fin 200, a gate structure 300, a single diffusion break structure (SDB) 400, and a capacitor gate structure 500.

[0016] A material of the substrate 100 includes elemental semiconductors, compound semiconductors, alloy semiconductors, or other suitable materials. The substrate 100 could be, for example, a silicon substrate or a silicon-on-insulator (SOI) substrate, but the disclosure is not limited thereto.

[0017] The substrate 100 includes a first region R1 and a second region R2, with the second region R2 located between the adjacent first regions R1. The first region R1 is a transistor region on which a FinFET (fin-field effect transistor) to be introduced later is arranged. The second region R2 is a capacitor region, which was originally a dummy region located between the adjacent transistor regions and on which a metal-oxide-semiconductor capacitor (MOSCAP) to be introduced later is arranged.

[0018] In the present embodiment, the second region R2 of the substrate 100 contains a heavily doped region HD. The doping ions in the heavily doped region HD could be N-type ions. The doping ions in the heavily doped region HD include, for example, phosphorus or arsenic ions, but the disclosure is not limited thereto. By forming the heavily doped region HD in the second region R2 of the substrate 100, the conductivity could be increased, so that the heavily doped region HD could be used as a terminal of the MOSCAP.

[0019] The rib 200 is arranged on the substrate 100. In some embodiments, the rib 200 extends along a direction X and spans the first region R1 and the second region R2 of the substrate 100. It is worth noting that the number of ribs 200 is not limited by the Fig. 1. Specifically, the semiconductor device 10 includes a plurality of fins 200, wherein the plurality of fins 200 are spaced apart from one another and extend along the direction X. The gate structure 300 is disposed on the fin 200. In some embodiments, the gate structure 300 extends along a direction Y that is perpendicular to the direction X. In the present embodiment, the gate structure 300 is located in the first region R1 of the substrate 100. Therefore, the gate structure 300 could span the fin 200 located in the first region R1 of the substrate 100.

[0020] In some embodiments, the gate structure 300 includes a gate dielectric layer 302 and a gate 304. The gate dielectric layer 302 is disposed on the fin 200. In some embodiments, the material of the gate dielectric layer 302 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but the disclosure is not limited thereto. In other embodiments, the material of the gate dielectric layer 302 includes a material with a high dielectric constant, which may include, for example, hafnium dioxide, zirconia, or other suitable materials. The gate 304 is disposed on the gate dielectric layer 302. In some embodiments, the material of the gate 304 includes polycrystalline silicon or amorphous silicon, but the disclosure is not limited thereto.

[0021] In some embodiments, a source / drain region 310 is disposed within the fin 200 on one side of the gate structure 300. The source / drain region 310 may include an epitaxial layer. In some embodiments, the epitaxial layer material includes silicon phosphide or silicon carbide, but the disclosure is not limited thereto. In other embodiments, the epitaxial layer material includes silicon germanium.

[0022] Based on the above, the semiconductor device 10 of the present embodiment includes a fin field effect transistor TFT including the above gate structure 300 and the source / drain region 310, wherein the fin 200 covered by the gate structure 300 serves as a channel region of the fin field effect transistor TFT.

[0023] Furthermore, in some embodiments, a contact plug 310P is disposed on the source / drain region 310 of the fin field effect transistor TFT and electrically connected to the fin field effect transistor TFT, wherein the contact plug 310P extends along a direction Z. The contact plug 310P may include a barrier layer (not shown) and a metal layer (not shown), wherein a material of the barrier layer includes titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof, and a material of the metal layer includes tungsten, copper, aluminum, a titanium-aluminum alloy, or a combination thereof, but the disclosure is not limited thereto.

[0024] The SDB structure 400 is arranged on the rib 200. In some embodiments, the SDB structure 400 extends along the Y direction and is located in the second region R2 of the substrate 100. The SDB structure 400 could separate the rib 200 into two parts. Specifically, the substrate 100 includes a groove 100Gr located in the second region R2 and extending along the Y direction, wherein the ribs 200 extending along the X direction are separated by the groove 100Gr and the SDB structure 400 is arranged in the groove 100Gr. In some embodiments, a material of the SDB structure 400 includes silicon oxide, but the disclosure is not limited thereto. In other embodiments, a material of the SDB structure 400 includes silicon nitride, silicon oxynitride, or a combination thereof.

[0025] The capacitor gate structure 500 is disposed on the fin 200. In some embodiments, the capacitor gate structure 500 extends along the Y direction. In the present embodiment, the capacitor gate structure 500 is located in the second region R2 of the substrate 100. Therefore, the capacitor gate structure 500 could extend over the fin 200, which is located in the second area R2 of the substrate 100.

[0026] In some embodiments, capacitor gate structure 500 includes a capacitor dielectric layer 502 and a capacitor gate 504. The capacitor dielectric layer 502 is disposed on the fin 200. In some embodiments, the material of the capacitor dielectric layer 502 could be the same or similar to that of the gate dielectric layer 302 and would be omitted here. The capacitor gate 504 is disposed on the capacitor dielectric layer 502. In some embodiments, a material of the capacitor gate 504 could be the same or similar to the material of the gate 304 and would be omitted here.

[0027] The capacitor gate structure 500 is disposed on the SDB structure 400. In the present embodiment, the capacitor gate structure 500 partially overlaps the SDB structure 400. Specifically, the capacitor gate structure 500 partially overlaps the SDB structure 400 in the Z direction, and a width of the capacitor gate structure 500 in the X direction is greater than a width of the SDB structure 400 in the X direction. Therefore, a portion of the capacitor gate structure 500 may be disposed between the segmented fins 200.

[0028] In some embodiments, a dummy source / drain region 510 is disposed in the fin 200 on both sides of the capacitor gate structure 500. The material of the dummy source / drain region 510 could be the same or similar to the material of the source / drain region 310 and would be omitted here.

[0029] Based on the above, the semiconductor device 10 of the present embodiment includes a capacitor CAP including the capacitor gate 504, the capacitor dielectric layer 502, the heavily doped region HD located in the fin 200, and the dummy source / drain region 510. The capacitor gate 504 serves as one terminal of the capacitor CAP, and the heavily doped region HD and the dummy source / drain region 510 serve as the other terminal of the capacitor CAP. In the present embodiment, the capacitor CAP is a MOSCAP.

[0030] Furthermore, in some embodiments, a contact plug 500P is disposed on the capacitor gate structure 500 of the capacitor CAP and electrically connected to the capacitor CAP, and a contact plug 510P is disposed on the dummy source / drain region 510 of the capacitor CAP and electrically connected to the capacitor CAP, wherein the contact plug 500P and the contact plug 510P extend along the direction Z. A material of the contact plug 500P and a material of the contact plug 510P could be the same or a similar material as the material of the contact plug 310P and would be omitted here.

[0031] By disposing the capacitor CAP in the second region R2 of the substrate 100, the second region R2, which was originally used as a dummy region, can be effectively utilized. Therefore, the capacitor CAP could be provided without reducing the number of components originally disposed in the first region R1 of the substrate 100, so that the semiconductor device 10 of the present embodiment could have high integration, high density, and high performance.

[0032] In addition, as in Fig. 1C, since the SDB structure 400 is located in the second region R2 of the substrate 100, the phenomenon of tapering at the top of the rib 200 in the second region R2 due to formation of the heavily doped region HD can be slowed down, so that the semiconductor device 10 of the present embodiment could have relatively good reliability.

[0033] Fig. 2 is a schematic flow diagram of a manufacturing method for a semiconductor device according to an embodiment of the disclosure. It should be noted that the embodiment of Fig. 2 the reference numerals and parts of the content of the above embodiments of the Fig. 1A-1C, wherein the same or similar reference numerals are used to represent the same or similar elements, and descriptions of the same technical content are omitted.

[0034] First, form a fin 200 on a substrate 100. The substrate 100 includes a first region R1 and a second region R2, where the first region R1 is defined as a transistor region and the second region R2 is defined as a capacitor region. It is worth noting that the remainder of the introduction relating to the substrate 100 could be related to the above embodiments and would be omitted here.

[0035] The rib 200 spans the first region R1 and the second region R2 of the substrate 100. In some embodiments, the rib 200 could be manufactured by a SIT (Sidewall Image Transfer) process and formed by the following method, but the disclosure is not limited thereto. Step (1): Providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Step (2): Performing a photolithography process and an etching process to form a plurality of patterned sacrificial layers (not shown) with equal pitch and width on the substrate 100, so that the appearance of the patterned sacrificial layers appears in a stripe shape. Step (3): Performing a deposition process and an etching process to form spacers (not shown) on each sidewall of the patterned sacrificial layers.Step (4): Removing the patterned sacrificial layers and performing an etching process through the spacers, so that a pattern formed by the spacers is transferred to the substrate 100. Step (5): Performing a cutting process on the substrate 100 to obtain the desired patterned structure, such as the one shown in FIG. Fig. 1A shown striped ribs 200.

[0036] In other embodiments, the fin 200 may be fabricated by the following process. Step (1): Form a patterned mask (not shown) on the substrate 100. Step (2): Use the patterned mask to perform an etching process on the substrate 100 to form the fin 200.

[0037] In some embodiments, the fin 200 could be formed by performing the following process. Step (1): Forming a patterned mask (not shown) on the substrate 100. Step (2): Using the patterned mask to perform an epitaxial process on the substrate 100 to grow a semiconductor layer (such as silicon germanium) on the substrate 100, wherein the semiconductor layer serves as the corresponding fin 200.

[0038] Next, a single diffusion disruption structure (SDB) 400 is formed in the second region R2 of the substrate 100, wherein an extension direction of the SDB structure 400 is perpendicular to an extension direction of the rib 200, and the SDB structure 400 spans the rib 200. Based on the above, the SDB structure 400 may separate the rib 200 into two parts.

[0039] The SDB structure 400 could be formed by performing the following method, but the disclosure is not limited thereto. Step (1): Form a patterned mask (not shown) on the substrate 100, wherein the patterned mask covers the first region R1 of the substrate 100. Step (2): Use the patterned mask to perform an etching process on the rib 200 and the substrate 100 to remove a portion of the rib 200 located in the second region R2 and to further remove a portion of the substrate 100 located below the original rib 200 to form a groove 100Gr separating the rib 200 into two parts. Step (3): Form a dielectric layer in the groove 100Gr to form the SDB structure 400, wherein an upper surface of the SDB structure 400 is lower than an upper surface of the rib 200.

[0040] The dielectric layer disposed in the groove 100Gr could be formed by performing the following process, but the disclosure is not limited thereto. Step (3-1): Fill the groove 100Gr with a dielectric layer. Step (3-2): Perform an etch-back process to remove a portion of the dielectric layer in the groove 100Gr so that the upper surface of the etched SDB structure 400 is lower than the upper surface of the ridge 200.

[0041] In some embodiments, prior to forming the SDB structure 400 in the second region R2 of the substrate 100, a shallow trench isolation structure (not shown) may be formed in the first region R1 of the substrate 100, wherein the shallow trench isolation structure surrounds the fin 200. A method for forming the shallow trench isolation structure includes performing a flowable chemical vapor deposition (FCVD) process to form a silicon oxide layer covering the fin 200 on the substrate 100, and then performing a chemical mechanical polishing (CMP) process and / or an etching process to remove a portion of the silicon oxide layer.

[0042] Then, a heavily doped region HD is formed in the second region R2 of the substrate 100. The heavily doped region HD can be formed by performing the following process, but the disclosure is not limited thereto. Step (1): Forming a patterned mask (not shown) on the substrate 100, the patterned mask covering the first region R1 of the substrate 100. Step (2): Performing an ion implantation process IMP using the patterned mask to ionize the second region R2 of the substrate 100. Step (3): Performing rapid thermal processing (RTP) on the substrate 100 to form the heavily doped region HD in the second region R2 of the substrate 100. In some embodiments, the implanted dopant ions in the ion implantation process IMP are N-type ions, which may include phosphorus or arsenic ions, but the disclosure is not limited thereto.By forming the heavily doped region HD in the second region R2 of the substrate 100, in which the conductivity could be increased, so that the heavily doped region HD could be used as a terminal of a capacitor.

[0043] It is worth noting that the fin 200 located in the second region R2 of the substrate 100 is more amorphous than the fin 200 located in the first region R1 of the substrate 100 because the heavily doped region HD is formed in the second region R2 of the substrate 100 to ensure that the second region R2 has a relatively high doping concentration. In this case, when the substrate 100 is subjected to the RTP process and / or a thermal oxidation process to form a dielectric layer IL, which will be introduced later, the fin 200 located in the second region R2 of the substrate 100 would be consumed at a faster rate than the fin 200 located in the first region R1 of the substrate 100.

[0044] Since the SDB structure 400 is formed in the second region R2 of the substrate 100, the phenomenon of tapering at the top of the rib 200 in the second region R2 due to the formation of the heavily doped region HD could be slowed down, so that the semiconductor device 10 could have relatively good reliability.

[0045] Thereafter, a gate structure 300 and a capacitor gate structure 500 are formed on the fin 200 in the first region R1 and in the second region R2, respectively. In some embodiments, the gate structure 300 and the capacitor gate structure 500 may be formed by performing a first gate process or a last gate process in accordance with the process requirements, but the disclosure is not limited thereto.

[0046] The gate structure 300 and the capacitor gate structure 500 could be formed by performing the following process, but the disclosure is not limited thereto. Step (1): Performing a thermal oxidation process or a deposition process to form the dielectric layer IL on the substrate 100. Step (2): Performing a deposition process to form a gate material layer (not shown) on the dielectric layer IL, wherein the deposition process could include chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).Step (3): Performing a patterning process on the substrate 100 to remove a portion of the dielectric layer IL and a portion of the gate material layer once or sequentially to form a gate dielectric layer 302 and a gate 304 in the first region R1, and to form a capacitor dielectric layer 502 and a capacitor gate 504 in the second region R2.

[0047] It is worth noting that the rest of the introduction relating to the gate structure 300 and the capacitor gate structure 500 could relate to the above embodiments and would be omitted here.

[0048] Next, a source / drain region 310 and a dummy source / drain region 510 are formed in the fin 200 located in the first region R1 and the second region R2. The source / drain region 310 and the dummy source / drain region 510 may be formed by performing the following process, but the disclosure is not limited thereto. Step (1): Performing an etching process on the fin 200 located in the first region R1 and the second region R2 of the substrate 100 to form a recess 200Gr by using the gate structure 300 and the capacitor gate structure 500 as masks, respectively. The additional mask may be used in the etching process, but the disclosure is not limited thereto.Step (2): Performing an epitaxial growth process to form an epitaxial layer in the recess 200Gr of the rib 200, wherein the epitaxial layer located in the first region R1 of the substrate 100 could be used as the source / drain region 310, and the epitaxial layer located in the second region R2 of the substrate 100 could be used as the dummy source / drain region 510.

[0049] After forming the source / drain region 310 and the dummy source / drain region 510, a fin field-effect transistor TFT and a capacitor CAP are formed, respectively. The fin field-effect transistor TFT includes the gate structure 300 and the source / drain region 310, with the fin 200 covered by the gate structure 300 serving as a channel region of the fin field-effect transistor TFT. The capacitor CAP includes the capacitor gate 504, the capacitor dielectric layer 502, the heavily doped region HD located in the fin 200, and the dummy source / drain region 510, with the capacitor gate 504 serving as one terminal of the capacitor CAP, and the heavily doped region HD and the dummy source / drain region 510 serving as the other terminal of the capacitor CAP. In the present embodiment, the capacitor CAP is a MOSCAP.

[0050] Thereafter, a contact plug 500P and a contact plug 510P are formed on the capacitor gate structure 500 and the dummy source / drain region 510 of the capacitor CAP. The remaining insertions regarding the contact plug 500P and the contact plug 510P could be related to the above embodiments and would be omitted here.

[0051] At this point, the manufacturing process for the semiconductor device 10 is completed. Although the manufacturing process of the semiconductor device 10 in the present embodiment is described using the above method as an example, the manufacturing process of the semiconductor device provided by the disclosure is not limited thereto. It is worth noting that the semiconductor device 10 of the present embodiment is a fin field effect transistor device including the MOSCAP, but the semiconductor device provided by the disclosure is not limited thereto.

[0052] In summary, in the semiconductor device and its manufacturing method provided by the disclosure, the area of ​​the first gate structure forming region cannot be reduced by forming the capacitor gate structure in the second region (the original dummy region) of the substrate, so that the semiconductor device provided by the disclosure can exhibit better effects such as high integration, high density, and high performance. Furthermore, the capacitor gate structure formed in the second region of the substrate is arranged on the SDB structure. Therefore, the taper phenomenon on the top surface of the ridge in the second region can be slowed down by forming the heavily doped region, so that the semiconductor device provided by the disclosure can exhibit relatively good reliability. List of reference symbols 10 semiconductor device 100 substrate R1 first area R2 second area 200 ribs HD highly endowed area 300 gate structure SDB Single Diffusion Interruption 400 SDB structure 500 capacitor gate structure 510 Dummy source / drain area Y extension direction X Extension direction 500 P first contact plug 510P second contact connector 100g groove IL dielectric layer 302 Gate dielectric layer 304 Gate 502 Capacitor dielectric layer 504 Capacitor Gate IMP ion implantation process

Claims

[1] A semiconductor device (10) comprising: a substrate (100) having adjacent first regions (R1) and a second region (R2), the second region (R2) being located between the adjacent first regions (R1); a rib (200) disposed on the substrate (100), the rib (200) located in the second region (R2) containing a heavily doped region (HD); a gate structure (300) arranged on the rib (200) and located in the first regions (R1); a single diffusion break (SDB) structure (400) disposed on the rib (200) and located in the second region (R2); and a capacitor gate structure (500) arranged on the rib (200) and located in the second region (R2), wherein the capacitor gate structure (500) is arranged on the SDB structure (400). [2] The semiconductor device (10) according to claim 1, wherein the capacitor gate structure (500) partially overlaps the SDB structure (400). [3] The semiconductor device (10) according to claim 1, wherein an upper surface of the SDB structure (400) is lower than an upper surface of the fin (200). [4] A semiconductor device (10) according to claim 1, further comprising: a dummy source / drain region (510) disposed in the fin (200) and located on both sides of the capacitor gate structure (500). [5] The semiconductor device (10) according to claim 4, wherein the dummy source / drain region (510) includes an epitaxial layer. [6] A manufacturing method for a semiconductor device (10) comprising: Forming a rib (200) on a substrate (100), the rib (200) spanning first regions (R1) and a second region (R2) of the substrate (100), the second region (R2) being located between the adjacent first regions (R1); Forming a single diffusion disruption (SDB) structure (400) in the second region (R2) of the substrate (100), wherein an extension direction (Y) of the SDB structure (400) is perpendicular to an extension direction (X) of the rib (200) and the SDB structure (400) spans the rib (200); Forming a heavily doped region (HD) in the rib located in the second region (R2); and Forming a gate structure (300) and a capacitor gate structure (500) on the rib (200) located in the first region (R1) and the second region (R2) of the substrate (100), wherein the capacitor gate structure (500) is arranged on the SDB structure (400). [7] A manufacturing method for the semiconductor device (10) according to claim 6, further comprising the following steps after forming the gate structure (300) and the capacitor gate structure (500): Forming a source / drain region (310) and a dummy source / drain region (510) in the rib (200) located in the first regions (R1) and the second region (R2) of the substrate (100); and Forming a first contact plug (500P) and a second contact plug (510P) on the capacitor gate structure (500) and the dummy source / drain region (510), respectively. [8] A manufacturing method for the semiconductor device (10) according to claim 6, wherein forming the SDB structure (400) includes: Performing an etching process on the rib (200) and the substrate (100) located in the second region (R2) to form a groove (100Gr) in the substrate (100); and Forming a dielectric layer in the groove (100Gr), wherein an upper surface of the SDB structure (400) is lower than an upper surface of the rib (200). [9] A manufacturing method for the semiconductor device (10) according to claim 6, wherein forming the gate structure (300) and the capacitor gate structure (500) includes: Forming a dielectric layer (IL) on the substrate (100); Forming a gate material layer on the dielectric layer (IL); and Removing a portion of the dielectric layer (IL) and a portion of the gate material layer to form the gate structure (300) including a gate dielectric layer (302) and a gate (304) in the first regions (R1) of the substrate (100) and the capacitor gate structure (500) including a capacitor dielectric layer (502) and a capacitor gate (504) in the second region (R2) of the substrate (100). [10] A manufacturing method for the semiconductor device (10) according to claim 6, wherein forming the heavily doped region (HD) in the fin (200) located in the second region (R2) includes performing an ion implantation process (IMP) and rapid thermal processing.

Images