Method for producing a semiconductor device comprising an ohmic contact and a gate dielectric

Abstract

A method for producing a semiconductor device (100) is proposed. The method comprises forming doped regions (1011, 1021, 1031) in a SiC semiconductor body (106) on a first surface (1061) of the SiC semiconductor body (106). The method further comprises forming an ohmic contact (108) to at least some of the doped regions (1011, 1021, 1031) on the first surface (1061) of the SiC semiconductor body (106). A gate dielectric (1101) is then formed on the SiC semiconductor body (106).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method of manufacturing a semiconductor device, in particular to a method of manufacturing a semiconductor device comprising an ohmic contact and a gate dielectric. BACKGROUND

[0002] The technological development of new generations of wide-bandgap semiconductor devices, such as SiC semiconductor devices, e.g., insulated-gate field-effect transistors (IGFETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs), aims to improve the properties of electrical devices and reduce costs by shrinking device geometries. For example, reference is made to the disclosure content of US 2022 / 0 278 205 A1. Although costs can be reduced by shrinking device geometries, a variety of compromises and challenges must be met when increasing device functionalities per unit area. For example, reducing the area-specific on-resistance, R onxA while maintaining device reliability can be challenging given process-related constraints when applying a thermal budget to a semiconductor substrate during device processing. Such process-related constraints can be caused, for example, by constraints on the thermal budget of structural elements. For example, thermal budget constraints can be applied to ohmic contacts and / or gate dielectrics to prevent damage to these structural elements.

[0003] There is a need to improve a method of manufacturing a semiconductor device. SUMMARY

[0004] The invention is defined in the independent patent claims. Further developments are the subject of the dependent patent claims.

[0005] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of semiconductor devices and methods of fabricating semiconductor devices and, together with the description, serve to explain principles of the embodiments. Further embodiments are described in the following detailed description and claims. Fig. 1 is an exemplary process illustration for manufacturing a semiconductor device. Fig. 2A to Fig. 2F, Fig. 3A to Fig. 3D, Fig. 4A to Fig. 4C, Fig. 5A to Fig. 5F, Fig. 6A to Fig. 6F, Fig. 7A to Fig. 7F, Fig. 8A to Fig. 8M, Fig. 9A to Fig. 9C are schematic cross-sectional views for illustrating process features of exemplary methods for manufacturing a semiconductor device based on the process of Fig. 1. Fig. 10 refers to another exemplary process illustration for manufacturing a semiconductor device. Fig. 11A to Fig. 11l are schematic cross-sectional views for illustrating process features of an exemplary method for manufacturing a semiconductor device based on the process of Fig. 10. DETAILED DESCRIPTION

[0007] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples in which semiconductor substrates may be processed. It should be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example may be used on or in conjunction with other examples to provide yet another example. It is intended that the present disclosure encompass such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for purposes of illustration only.Corresponding elements are designated by the same reference numerals in the various drawings unless otherwise indicated.

[0008] The terms "have," "contain," "comprise," "have," and the like are open-ended, and the terms indicate the presence of the specified structures, elements, or features, but do not preclude the presence of additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0009] The term "electrically connected" may describe a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material. The term "electrically coupled" may encompass that one or more intermediate elements configured for signal and / or power transmission may be connected between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. An ohmic contact is a non-rectifying electrical junction.

[0010] When two elements A and B are combined using "or," this should be understood to reveal all possible combinations, i.e., only A, only B, and both A and B, unless explicitly or implicitly defined otherwise. An alternative formulation for the same combinations is "at least one of A and B" or "A and / or B." The same applies, mutatis mutandis, to combinations of more than two elements.

[0011] Ranges specified for physical dimensions include the limiting values. For example, a range for a parameter y from a to b is a ≤ y ≤ b. The same applies to ranges with a limit such as "at most" and "at least."

[0012] The main components of a layer or structure made of a chemical compound or alloy are those elements whose atoms form the chemical compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0013] The term "on" should not be interpreted to mean only "directly on." Rather, when an element is positioned "on" another element (e.g., a layer "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" the substrate).

[0014] The description and drawings merely illustrate the principles of the disclosure. Furthermore, any examples provided herein are primarily intended to be illustrative only, to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to the advancement of the art. All statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to include equivalents thereof.

[0015] Some of the examples below are described in connection with a silicon carbide substrate. Alternatively, another wide-bandgap semiconductor substrate, e.g., a wide-bandgap wafer, may be processed, e.g., comprising a wide-bandgap semiconductor material other than silicon carbide. The wide-bandgap semiconductor wafer may have a bandgap larger than the bandgap of silicon (1.12 eV). For example, the wide-bandgap semiconductor wafer may be a gallium arsenide (GaAs) wafer. In some examples, the semiconductor body may be based on a silicon substrate.

[0016] Some of the illustrated examples depict n-channel MOSFETs or IGBTs. However, the examples described here can also be applied to p-channel devices, such as p-channel MOSFETs or IGBTs.

[0017] It should be understood that the disclosure of multiple steps, processes, operations, steps, or functions disclosed in the specification or claims should not be construed as being in the specific order unless explicitly or implicitly indicated otherwise, e.g., by terms such as "thereafter," for example, for technical reasons. Therefore, the disclosure of multiple steps or functions does not limit them to any particular order unless those steps or functions are not interchangeable for technical reasons. Further, in some examples, a single step, function, process, operation, or step may include or be broken down into multiple sub-steps, functions, processes, operations, or steps.Such sub-steps may be included and be part of the disclosure of that single step unless explicitly excluded.

[0018] An example of a method for manufacturing a semiconductor device will be described with reference to the flowchart of Fig. 1 illustrates.

[0019] The process feature S100 comprises forming doped regions in a SiC semiconductor body at a first surface of the SiC semiconductor body.

[0020] The process feature S110 comprises forming an ohmic contact to at least a portion of the doped regions on the first surface of the SiC semiconductor body.

[0021] After performing process features S100 and S110, process feature S120 includes forming a gate dielectric on the SiC semiconductor body.

[0022] The semiconductor device may, for example, be part of an integrated circuit or may be a discrete semiconductor device or a semiconductor module. The semiconductor device may, for example, be or may comprise an insulated gate field-effect transistor (IGFET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET), or an insulated gate bipolar transistor (IGBT). The semiconductor device may be a vertical semiconductor device having a load current flow between the first surface and a second surface opposite the first surface along a vertical direction. The vertical power semiconductor device may be configured to conduct currents of more than 1 A, or more than 10 A, or more than 30 A, or more than 50 A, or more than 75 A, or even more than 100 A, and may further be configured to conduct voltages between load electrodes, e.g.between the collector and emitter of an IGBT or between the drain and source of a MOSFET, in the range of several hundred to several thousand volts, e.g., 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, 10 kV. The blocking voltage can, for example, correspond to a voltage class specified in a datasheet for the power semiconductor device.

[0023] The semiconductor device may be based on a SiC semiconductor body made of a crystalline SiC material. The crystalline SiC material may, for example, have a hexagonal crystal lattice. For example, the semiconductor material may be 2H-SiC (2H polytype SiC), 6H-SiC, or 15R-SiC. According to one example, the semiconductor material is 4H polytype silicon carbide (4H-SiC). The SiC semiconductor body may comprise or consist of a semiconductor substrate having no, one, or more than one semiconductor layer thereon, e.g., epitaxially grown layers. One of the semiconductor layers may, for example, be a doped semiconductor layer of a current spreading layer.

[0024] The first surface may define a front surface or a top surface of the SiC semiconductor body, and the SiC semiconductor body may further have a second surface, which may, for example, be a back surface or a rear surface of the SiC semiconductor body. The SiC semiconductor body may, for example, be attached to a lead frame via the second surface. Bond pads may be arranged over the first surface of the SiC semiconductor body, and bond wires may, for example, be bonded to the bond pads.

[0025] To achieve a desired current-carrying capacity, the SiC semiconductor device can be configured by a plurality of parallel-connected SiC semiconductor device cells. The parallel-connected SiC semiconductor device cells can, for example, be SiC semiconductor device cells formed in the shape of a strip or a strip segment. Of course, the SiC semiconductor device cells can also have any other shape, e.g., circular, elliptical, polygonal, such as hexagonal or octahedral. The semiconductor device cells can be arranged in a transistor cell region of the SiC semiconductor body. The transistor cell region can be a region in which an emitter region of an IGBT (or a source region of a MOSFET) and a collector region of an IGBT (or a drain region of a MOSFET) are arranged opposite each other along a vertical direction.In the transistor cell region, a load current can enter or exit the SiC semiconductor body of the semiconductor device, e.g., via contact plugs or contact lines on the top surface of the mesa. The semiconductor device may further comprise an edge termination region, which may comprise a termination structure. In a blocking mode or in a reverse-biased mode of the semiconductor device, the blocking voltage between the transistor cell region and a field-free region drops laterally across the termination structure. The termination structure may have a higher or slightly lower voltage blocking capability than the transistor cell region. The termination structure may, for example, comprise a junction termination extension (JTE) with or without varying lateral doping (VLD), one or more laterally separated guard rings, or any combination thereof.

[0026] Forming the doped regions may comprise at least one masked or unmasked ion implantation process, e.g., unmasked with respect to a transistor cell region. The ion implantation process may, for example, be based on an ion implantation mask patterned by photolithography. The ion implantation mask may, for example, be a hard mask. Forming the doped regions may comprise introducing n- and / or p-dopants into the SiC semiconductor body. For example, dopants in a semiconductor body comprising SiC may comprise Al, B, Be, Ga, or any combination thereof for p-doping, and N, P, or any combination thereof for n-doping.

[0027] For example, forming the ohmic contact may involve processing temperatures exceeding 850°C. Forming the ohmic contact may involve a silicidation process, such as a Ni-based silicidation process, such as NiSi, which involves processing temperatures of 900°C or higher.

[0028] By forming the ohmic contact on the doped regions before the gate dielectric is formed, the formation of the ohmic contact no longer represents a temperature constraint on the selection of gate dielectric materials. For example, gate dielectric materials can degrade if the ohmic contact is formed after the gate dielectric at temperatures exceeding the crystallization temperature of the gate dielectric. High-k dielectric materials, such as Al2O3, ZrO2, HfO2, AlN, aluminum silicate AlSiOx, silicon-doped HfO2, lanthanum-doped HfO2, TiO2, Y2O3 or Si3N4, ONO (oxide-nitride-oxide), or any stacked combination thereof, can be used. Given the processing sequence described in the examples herein, dielectric materials such as HfO2 and / or ZrO2 with crystallization temperatures in the range of 600 °C to 800 °C can be used.This makes it possible to improve a method for manufacturing a semiconductor device.

[0029] For example, forming the ohmic contact may involve processing the SiC semiconductor body at temperatures higher than a crystallization temperature of the gate dielectric. For example, forming the ohmic contact may exceed temperatures of 900°C for forming a Ni-based silicide.

[0030] For example, prior to forming the ohmic contact, the method may include forming a gate trench in the SiC semiconductor body at the first surface.

[0031] For example, forming the doped regions may include forming a source or emitter layer of a first conductivity type. Forming the doped regions may include forming a body layer of a second conductivity type. The method may further include patterning the source layer into source regions and patterning the body layer into body regions by etching through the source layer and etching through the body layer when forming the gate trench. The source regions and the body regions may form at least a portion of the doped regions.

[0032] For example, the method may further comprise filling the gate trench with an auxiliary material prior to forming the ohmic contact. The method may further comprise removing the auxiliary material from the gate trench after forming the ohmic contact and prior to forming the gate dielectric. For example, the auxiliary material may be selected with respect to etch selectivity to an underlying material in the gate trench on which it is formed. This allows the underlying material to act as an etch stop when the auxiliary material is removed. For example, the auxiliary material may be polycrystalline silicon or silicon nitride, or an oxide of silicon.

[0033] For example, the method may further comprise forming a dielectric interlayer over the auxiliary material and the first surface of the SiC semiconductor body prior to removing the auxiliary material. The method may further comprise exposing an upper surface region of the auxiliary material by forming an opening in the dielectric interlayer. The dielectric interlayer may remain as part of a wiring region over the first surface of the SiC semiconductor body, e.g., as an insulating layer between the SiC semiconductor body and a bottommost wiring level of the wiring region, or may be replaced by another dielectric interlayer.The interlayer dielectric can also prevent diffusion and impurities from penetrating the SiC semiconductor body and can further cover the ohmic contact to protect it from damage caused by processes applied to the SiC semiconductor body, such as atomic layer deposition and ALD chemistry. Exemplary materials for the interlayer dielectric are SiO2 or SiN, but any other materials suitable for the above purpose(s) can be used.

[0034] For example, the method may further comprise forming a metal layer structure. A first portion of the metal layer structure may be formed on the gate dielectric and may form a gate electrode. A second portion of the metal layer structure may be formed on the ohmic contact. For example, the metal layer structure may be or include a Ti, TiN, or Ti / TiN layer.

[0035] For example, the method may further comprise forming an interlayer dielectric on the first surface of the SiC semiconductor body prior to forming the gate dielectric. The method may further comprise exposing a gate region of the SiC semiconductor body at the first surface of the SiC semiconductor body. Exposing the gate region of the SiC semiconductor body at the first surface may comprise forming an opening in the interlayer dielectric. Thereafter, the method may further comprise forming the gate dielectric on the exposed gate region of the SiC semiconductor body at the first surface of the SiC semiconductor body. The interlayer dielectric may remain as part of a wiring region above the first surface of the SiC semiconductor body or may be replaced by another interlayer dielectric.The gate dielectric on the exposed gate area can, for example, define a planar MOSFET or IGBT.

[0036] For example, the method may further comprise exposing a contact region of the SiC semiconductor body at the first surface of the SiC semiconductor body after forming the interlayer dielectric layer and before exposing the gate region. Exposing the contact region of the SiC semiconductor body at the first surface may comprise forming an opening in the interlayer dielectric layer. Thereafter, the method may further comprise forming the ohmic contact on the exposed contact region of the SiC semiconductor body at the first surface of the SiC semiconductor body.

[0037] For example, the method may further comprise forming a metal layer structure. A first portion of the metal layer structure may be formed on the gate dielectric, e.g., on a planar gate dielectric. The first portion of the metal layer structure may form a gate electrode. A second portion of the metal layer structure may be formed on the ohmic contact. For example, the metal layer structure may be or comprise a Ti, TiN, or Ti / TiN layer.

[0038] For example, the method may further comprise, after forming the ohmic contact, forming a gate trench in the SiC semiconductor body at the first surface.

[0039] For example, the method may further comprise forming a source or emitter layer of a first conductivity type. The method may further comprise forming a body layer of a second conductivity type. The method may further comprise patterning the source layer into source regions and patterning the body layer into body regions by etching through the source layer and etching through the body layer when forming the gate trench. The source regions and the body regions may form at least a portion of the doped regions.

[0040] For example, the method may further comprise forming an interlayer dielectric on the first surface of the SiC semiconductor body prior to forming the gate trench. The method may further comprise exposing a gate region of the SiC semiconductor body at the first surface of the SiC semiconductor body. Exposing the gate region of the SiC semiconductor body at the first surface may comprise forming an opening in the interlayer dielectric. Thereafter, the method may further comprise forming the gate trench in the SiC semiconductor body at the first surface. The interlayer dielectric may remain as part of a wiring region above the first surface of the SiC semiconductor body or may be replaced by another interlayer dielectric. The gate dielectric on the exposed gate region may define, for example, a planar MOSFET or IGBT.

[0041] For example, the dielectric interlayer may be formed prior to forming the ohmic contact. The method may further comprise exposing a contact region of the SiC semiconductor body at the first surface of the SiC semiconductor body. Exposing the contact region of the SiC semiconductor body at the first surface may comprise forming an opening in the dielectric interlayer. Thereafter, the method may further comprise forming the ohmic contact on the exposed contact region of the SiC semiconductor body at the first surface of the SiC semiconductor body.

[0042] For example, the method may further comprise forming the doped regions, including forming a source layer of a first conductivity type. Forming the doped regions may further comprise forming a body layer of a second conductivity type. Forming the doped regions may further comprise patterning the source layer into source regions and patterning the body layer into body regions by etching through the source layer and etching through the body layer when forming gate trenches. The source regions and the body regions may form at least a portion of the doped regions. The method may further comprise filling the gate trenches with an auxiliary material prior to forming the ohmic contact. The method may further comprise removing the auxiliary material from the gate trenches after forming the ohmic contact and prior to forming the gate dielectric.For example, the auxiliary material may be selected with respect to etch selectivity relative to an underlying material in the gate trench on which it is formed. This allows the underlying material to act as an etch stop when the auxiliary material is removed. For example, the auxiliary material may be polycrystalline silicon, silicon nitride, or a silicon oxide.

[0043] For example, the method may include forming a dielectric interlayer over the auxiliary material and the first surface of the SiC semiconductor body prior to forming the ohmic contact. The method may further include exposing a contact region of the SiC semiconductor body at the first surface of the SiC semiconductor body. Exposing the contact region of the SiC semiconductor body at the first surface may include forming an opening in the dielectric interlayer. Thereafter, the method may further include forming the ohmic contact on the exposed contact region of the SiC semiconductor body at the first surface of the SiC semiconductor body.

[0044] For example, the method may include exposing an upper surface region of the auxiliary material by forming an opening in the dielectric interlayer prior to removing the auxiliary material. The dielectric interlayer, or a portion thereof, may remain as part of a wiring region above the first surface of the SiC semiconductor body. Thereafter, the method may further include forming the gate dielectric. For example, the semiconductor device may be a FinFET.

[0045] For example, forming the gate dielectric may include forming a high-k dielectric. For example, the high-k dielectric material may include Al2O3, ZrO2, HfO2, AlN, aluminum silicate AlSiOx, silicon-doped HfO2, lanthanum-doped HfO2, TiO2, Y2O3 or Si3N4, ONO (oxide-nitride-oxide), mixtures thereof, or any stacked combination thereof. The high-k dielectric may be formed by any suitable film formation technique, e.g., atomic layer deposition (ALD) and / or chemical vapor deposition. The selection of the film formation technique may depend, for example, on the film formation temperature required for the particular film formation technique.

[0046] Details regarding the structure or function or technical utility of features described above with respect to a semiconductor device, such as an FET or IGBT, equally apply to the exemplary methods described below. Processing the SiC semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0047] The process features may include subprocesses. For example, some or all subprocesses of one process feature described herein may be executed before, after, or between subprocesses of another process feature described herein.

[0048] With reference to the schematic cross-sectional views, Fig. 2A to Fig. 2F for illustrating process features of an exemplary method of manufacturing a semiconductor device 100. The semiconductor device is illustrated as a trench MOSFET.

[0049] With reference to the schematic cross-sectional view of Fig. 2A, doped regions are formed in a SiC semiconductor body 106, which has an n - doped drift region 1065. The doped regions comprise an n +-doped source region 1011, a p-doped body region 1021, and a p-doped auxiliary region 1031. A gate trench 110 is formed in the SiC semiconductor body 106 at a first surface 1061 of the SiC semiconductor body 106. A sacrificial layer 118, e.g., a sacrificial oxide layer, is formed on the first surface 1061 of the SiC semiconductor body 106 and on sidewalls and a bottom surface of the gate trench 110. The gate trench 110 and the sacrificial layer 118 may be formed before, after, or between processes for forming the doped regions.

[0050] With reference to the schematic cross-sectional view of Fig. 2B, the gate trench 110 is filled with an auxiliary material 112. A dielectric interlayer 114 as part of a dielectric interlayer structure 113 is formed on the surface 1061 of the SiC semiconductor body 106 and patterned by a mask 115, e.g., a resist mask, for defining a contact opening to the first surface 1061 of the SiC semiconductor body 106.

[0051] With reference to the schematic cross-sectional view of Fig. 2C, an ohmic contact 108 is formed on the region of the first surface 1061 of the SiC semiconductor body exposed by the contact opening, e.g., by a silicidation process. The ohmic contact 108 is covered by a protective interlayer dielectric layer 1142 as part of the interlayer dielectric structure 113. The protective interlayer dielectric layer 1142 can prevent diffusion and contamination and can protect the ohmic contact, e.g., from ALD chemistry. Optionally, rapid thermal processing (RTP) can be performed.

[0052] With reference to the schematic cross-sectional view of Fig. 2D, an upper surface region of the auxiliary material is exposed by forming an opening 1145 in the dielectric intermediate structure 113. The auxiliary material 112 is removed from the gate trench 110, e.g., by an etching process.

[0053] With reference to the schematic cross-sectional view of Fig. 2E, the sacrificial layer 118 is removed from the gate trench 110, e.g., by an etching process. A gate dielectric 1101 is formed on at least the bottom and sidewalls of the gate trench 110, e.g., by one or more high-k layer deposition techniques. A gate electrode 1102 is formed on the gate dielectric 1101 and recessed up to a top surface of the intermediate dielectric structure 113 or up to a top surface of the gate dielectric 1101 deposited on the intermediate dielectric structure 113.

[0054] With reference to the schematic cross-sectional view of Fig. 2F, a second dielectric interlayer 1143 is formed as part of the dielectric structure 113 above the SiC semiconductor body 106. A contact opening is formed, e.g., by a masked etching process, in the dielectric interlayer 113 to expose the ohmic contact 108. The contact opening is filled with a contact plug extending into a first wiring level 1161, e.g., a metal layer closest to the first surface 1061, of a wiring region 116 above the SiC semiconductor body 106.

[0055] With reference to the schematic cross-sectional views of Fig. 3A to Fig. 3D illustrates process features of another exemplary method for manufacturing a semiconductor device 100. The process features of Fig. 3A to Fig. 3D illustrate a modification of the Fig. 2A to Fig. 2F illustrated process characteristics.

[0056] The Fig. The process feature illustrated in Figure 3A is similar to that shown in Fig. 2A. With reference to Fig. 3B, the sacrificial layer 118 is removed from the gate trench 110 before the gate trench 110 is filled with the auxiliary material 112. The formation of the ohmic contact 108 and the removal of the auxiliary material 112 from the Fig. 3B to Fig. 3D are similar to those illustrated with reference to Fig. 2B to Fig. 2D. The formation of the gate dielectric 1101, the gate electrode 1102, the second dielectric interlayer 1143 and the first wiring level 1161 may be carried out as described with reference to Fig. 2E and Fig. 2F follow the steps described above.

[0057] With reference to the schematic cross-sectional views of Fig. 4A to Fig. 4C illustrates process features of another exemplary method for manufacturing a semiconductor device 100. The process features of Fig. 4A to Fig. 4C illustrate a modification of the Fig. 2A to Fig. 2F illustrated process characteristics.

[0058] The Fig. The process feature illustrated in Figure 4A is similar to that shown in Fig. 2A. With reference to Fig. 4B will be the training of Fig. 2B, the dielectric interlayer 114 is omitted, and the mask 115 for defining the contact opening for the ohmic contact 108 is formed on the SiC semiconductor body 106 after filling the gate trench 110 with the auxiliary material 112. After forming the ohmic contact 108 and removing the mask 115, the protective dielectric interlayer 1142 is formed as shown in Fig. 4C illustrates the process characteristics as described with reference to Fig. 2D to Fig. 2F described can follow.

[0059] Similar to the provisions referred to in Fig. 3A to Fig. 3D, the removal of the sacrificial layer 118 from the gate trench 110 prior to filling the gate trench 110 with the auxiliary material 112 may also be applied to the exemplary process features of Fig. 4A to Fig. 4C can be applied.

[0060] The schematic cross-sectional views of Fig. 5A to Fig. 5F are used to illustrate process features of an example method for manufacturing a semiconductor device 100. The semiconductor device is exemplified as a planar MOSFET.

[0061] With reference to the schematic cross-sectional view of Fig. 5A, doped regions are formed in the SiC semiconductor body 106, which has an n- doped drift region 1065. The doped regions comprise an n + -doped source region 1011, a p-doped body region 1021 and a p + -doped body contact area 1041. Similar to the Fig. 2A, a capping dielectric 1181 is formed as part of the intermediate dielectric structure 113 on the first surface 1061 of the SiC semiconductor body 106.

[0062] With reference to the schematic cross-sectional view of Fig. 5B, a dielectric interlayer 114 is formed as part of a dielectric interlayer structure 113 over the surface 1061 of the SiC semiconductor body 106 and patterned by a mask 115, e.g., a resist mask, for defining a contact opening to the first surface 1061 of the SiC semiconductor body 106.

[0063] With reference to the schematic cross-sectional view of Fig. 5C, an ohmic contact 108 is formed on the region of the first surface 1061 of the SiC semiconductor body exposed by the contact opening, e.g., by a silicidation process. The ohmic contact 108 is covered by a protective interlayer dielectric 1142 as part of the interlayer dielectric structure 113. The protective interlayer dielectric 1142 may prevent diffusion and contamination and may protect the ohmic contact, e.g., from ALD chemistry.

[0064] With reference to the schematic cross-sectional view of Fig. 5D, a planar gate region is exposed on the first surface 1061 by forming an opening 1145 in the dielectric intermediate structure 113, e.g., by an etching process.

[0065] With reference to the schematic cross-sectional view of Fig. 5E, a gate dielectric 1101 is formed at least on the exposed planar gate region at the first surface 1061, e.g., by one or more high-k layer deposition techniques. A gate electrode 1102 is formed on the gate dielectric 1101 and recessed up to a top surface of the interlayer dielectric structure 113 or up to a top surface of the gate dielectric layer 1101 deposited on the interlayer dielectric structure 113. A second interlayer dielectric layer 1143, as part of the dielectric structure 113, is formed over the protective interlayer dielectric layer 1142.

[0066] With reference to the schematic cross-sectional view of Fig. 5F, a contact opening is formed, e.g., by a masked etching process, in the dielectric intermediate structure 113 to expose the ohmic contact 108. The contact opening is filled with a contact plug extending into a first wiring level 1161, e.g., a metal layer closest to the first surface 1061, of a wiring region 116 above the SiC semiconductor body 106.

[0067] Similar to the provisions referred to in Fig. 4A to Fig. 4C, the omission of the dielectric interlayer 114 may also apply to the exemplary process features of Fig. 5A to Fig. 5F can be applied.

[0068] The schematic cross-sectional views of Fig. 6A to Fig. 6F are used to illustrate process features of an example method of manufacturing a semiconductor device 100. The semiconductor device is illustrated as a trench MOSFET.

[0069] With reference to the schematic cross-sectional view of Fig. 6A, doped regions are formed in the SiC semiconductor body 106, which has an n - doped drift region 1065. The doped regions comprise an n + -doped source region 1011, a p-doped body region 1021 and a p-doped auxiliary region 1031. A sacrificial layer 118, e.g., a sacrificial oxide layer, is formed on the first surface 1061 of the SiC semiconductor body 106.

[0070] With reference to the schematic cross-sectional view of Fig. 6B, a dielectric interlayer 114 is formed as part of a dielectric interlayer structure 113 on the surface 1061 of the SiC semiconductor body 106 and patterned by a mask 115, e.g., a resist mask, for defining a contact opening to the first surface 1061 of the SiC semiconductor body 106.

[0071] With reference to the schematic cross-sectional view of Fig. 6C, an ohmic contact 108 is formed on the region of the first surface 1061 of the SiC semiconductor body exposed by the contact opening, e.g., by a silicidation process. The ohmic contact 108 is covered by a protective interlayer dielectric 1142 as part of the interlayer dielectric structure 113. The protective interlayer dielectric 1142 may prevent diffusion and contamination and may protect the ohmic contact 108, e.g., from ALD chemistry.

[0072] With reference to the schematic cross-sectional view of Fig. 6D, a trench gate region is exposed on the first surface 1061 by forming an opening 1145 in the dielectric intermediate structure 113. A gate trench 110 is formed in the SiC semiconductor body 106, e.g., by an etching process.

[0073] With reference to the schematic cross-sectional view of Fig. 6E, a gate dielectric 1101 is formed at least on the bottom and sidewalls of the gate trench 110, e.g., by one or more high-k layer deposition techniques. A gate electrode 1102 is formed on the gate dielectric 1101 and recessed up to a top surface of the intermediate dielectric structure 113 or up to a top surface of the gate dielectric layer 1101 deposited on the intermediate dielectric structure 113.

[0074] With reference to the schematic cross-sectional view of Fig. 6F, a second dielectric interlayer 1143 is formed as part of the dielectric structure 113 over the protective dielectric interlayer 1142. A contact opening is formed, e.g., by a masked etch process, in the dielectric interlayer 113 to expose the ohmic contact 108. The contact opening is filled with a contact plug extending into a first wiring level 1161, e.g., a metal layer closest to the first surface 1061, of a wiring region 116 over the SiC semiconductor body 106.

[0075] Similar to the provisions referred to in Fig. 4A to Fig. 4C, the omission of the dielectric interlayer 114 may also apply to the exemplary process features of Fig. 6A to Fig. 6F. In addition, the sacrificial layer 118 can also be removed before forming the ohmic contact 108.

[0076] The schematic cross-sectional views of Fig. 7A to Fig. 7F are used to illustrate process features of an example method of manufacturing a semiconductor device 100. The semiconductor device is illustrated as a FinFET.

[0077] With reference to the schematic cross-sectional view of Fig. 7A, doped regions are formed in a SiC semiconductor body 106, which has an n - doped drift region 1065. The doped regions comprise an n + -doped source region 1011 and a p-doped body region 1021. A gate trench 110 is formed in the SiC semiconductor body 106 at a first surface 1061 of the SiC semiconductor body 106. A sacrificial layer 118, e.g., a sacrificial oxide layer, is formed on the first surface 1061 of the SiC semiconductor body 106 and on sidewalls and a bottom surface of the gate trench 110.

[0078] With reference to the schematic cross-sectional view of Fig. 7B, the gate trench 110 is filled with an auxiliary material 112. A dielectric interlayer 114 as part of a dielectric interlayer structure 113 is formed on the surface 1061 of the SiC semiconductor body 106 and patterned by a mask 115, e.g., a resist mask, for defining a contact opening to the first surface 1061 of the SiC semiconductor body 106.

[0079] With reference to the schematic cross-sectional view of Fig. 7C, an ohmic contact 108 is formed on the region of the first surface 1061 of the SiC semiconductor body exposed by the contact opening, e.g., by a silicidation process. The ohmic contact 108 is covered by a protective interlayer dielectric 1142 as part of the interlayer dielectric 113. The protective interlayer dielectric 1142 may prevent diffusion and contamination and may protect the ohmic contact 108, e.g., from ALD chemistry.

[0080] With reference to the schematic cross-sectional view of Fig. 7D, an upper surface region of the auxiliary material is exposed by forming an opening 1145 in the dielectric intermediate structure 113. The auxiliary material 112 is removed from the gate trench 110, e.g., by an etching process.

[0081] With reference to the schematic cross-sectional view of Fig. 7E, the sacrificial layer 118 is removed from the gate trench 110, e.g., by an etching process. A gate dielectric 1101 is formed on at least the bottom and sidewalls of the gate trench 110, e.g., by one or more high-k layer deposition techniques. A gate electrode 1102 is formed on the gate dielectric 1101 and recessed down to a top surface of the intermediate dielectric structure 113 or down to a top surface of the gate dielectric layer deposited on the intermediate dielectric structure 113.

[0082] With reference to the schematic cross-sectional view of Fig. 7F, a second dielectric interlayer 1143 is formed as part of the dielectric structure 113 above the SiC semiconductor body 106. A contact opening is formed, e.g., by a masked etch process, in the dielectric interlayer 113 to expose the ohmic contact 108. The contact opening is filled with a contact plug extending into a first wiring level 1161, e.g., a metal layer closest to the first surface 1061, of a wiring region 116 above the SiC semiconductor body 106.

[0083] The schematic cross-sectional views of Fig. 8A to Fig. 8M are used to illustrate process features of an example method of manufacturing a semiconductor device 100. The semiconductor device is illustrated as a trench MOSFET.

[0084] With reference to the schematic cross-sectional view of Fig. 8A, doped regions are formed in a SiC semiconductor body 106, which has an n - doped drift region 1065. The doped regions comprise an n + -doped source region 1011 and a p-doped body region 1021, a p-doped lower auxiliary region 1051, and a p-doped upper auxiliary region 1052. A gate trench 110 is formed in the SiC semiconductor body 106 at a first surface 1061 of the SiC semiconductor body 106. A sacrificial layer 118, e.g., a sacrificial oxide layer, is formed on the first surface 1061 of the SiC semiconductor body 106 and on sidewalls and a bottom surface of the gate trench 110.

[0085] With reference to the schematic cross-sectional view of Fig. 8B, the gate trench 110 is filled with an auxiliary material 112, e.g., polycrystalline silicon. An interlayer dielectric layer 114 and a second interlayer dielectric layer 1143 as part of an interlayer dielectric structure 113 are formed on the surface 1061 of the SiC semiconductor body 106 and patterned by a mask, e.g., a resist mask, to define a contact opening to the first surface 1061 of the SiC semiconductor body 106. An ohmic contact 108 is formed on the region of the first surface 1061 of the SiC semiconductor body exposed by the contact opening, e.g., by a silicidation process. The ohmic contact 108 is covered by a protective interlayer dielectric layer 1142 as part of the interlayer dielectric 113.

[0086] With reference to the schematic cross-sectional view of Fig. 8C, a mask 1151 is formed over the dielectric intermediate structure 113, which includes an opening directly above the gate trench 110.

[0087] With reference to the schematic cross-sectional view of Fig. 8D, an upper surface region of the auxiliary material 112 is exposed by forming an opening 1146 in the dielectric intermediate structure 113.

[0088] With reference to the schematic cross-sectional view of Fig. 8E, the auxiliary material 112 is removed from the gate trench 110, e.g., by an etching process.

[0089] With reference to the schematic cross-sectional view of Fig. 8F, the sacrificial layer 118 is removed from the gate trench 110, e.g., by an etching process.

[0090] With reference to the schematic cross-sectional view of Fig. 8G, a gate dielectric 1101 is formed on the bottom surface, on the sidewalls of the gate trench 110, and on the protective dielectric interlayer 1142, e.g., by one or more high-k layer deposition techniques.

[0091] With reference to the schematic cross-sectional view of Fig. 8H, a sacrificial layer 1121, e.g., a resist pattern defined by lithography, is formed on the gate dielectric 1101. A contact opening is formed, e.g., by a masked etch process, in the sacrificial layer 1121, the gate dielectric 1101, and the protective dielectric interlayer 1142 to expose the ohmic contact 108.

[0092] With reference to the schematic cross-sectional view of Fig. 8l, the sacrificial layer 1121 is removed and a conductive liner 120, e.g., a Ti / TiN liner, is formed inside and outside the gate trench 110.

[0093] With reference to the schematic cross-sectional view of Fig. 8J, the conductive liner 120 is patterned by an etching process using an etch mask 1151. The patterned conductive layer 120 remains as the gate electrode 1102 in the gate trench 110 and as a contact liner 1081 on the ohmic contact 108, which is electrically isolated from the gate electrode 1102.

[0094] With reference to the schematic cross-sectional view of Fig. 8K, a third dielectric interlayer 1144 is formed as part of a dielectric interlayer structure 113 over the SiC semiconductor body 106 and fills the gate trench 110.

[0095] With reference to the schematic cross-sectional view of Fig. 8L, a contact opening is formed, for example, by a masked etching process in the third dielectric interlayer 1144 to expose the contact liner 1081.

[0096] With reference to the schematic cross-sectional view of Fig. 8M, the contact opening is filled with a contact plug extending into a first wiring level 1161, e.g., a metal layer closest to the first surface 1061, of a wiring region 116 above the SiC semiconductor body 106.

[0097] The schematic cross-sectional views of Fig. 8A to Fig. 8M, which illustrate process features of an exemplary method for fabricating a trench MOSFET, may also be applied to fabricate a planar MOSFET, as shown in the schematic cross-sectional views of Fig. 9A to Fig. 9C illustrates.

[0098] With reference to Fig. 9A, a planar MOSFET including a sacrificial gate dielectric 1103 and a sacrificial gate electrode 1104 may be formed by process features including, for example, a sacrificial gate oxide and an ohmic contact 108 formed after the sacrificial gate oxide.

[0099] With reference to Fig. 9B, a planar gate region is exposed on the first surface 1061 by forming an opening in the dielectric intermediate structure 113, e.g., by an etching process. The sacrificial gate electrode 1104 is removed, and the sacrificial gate dielectric 1103 is removed and replaced by the gate dielectric 1102, e.g., a high-k dielectric. The structure described with reference to Fig. 8H to Fig. 8M can also be applied. This leads to the planar MOSFET as shown in Fig. 9C illustrates.

[0100] Another example of a method for manufacturing a semiconductor device will be described with reference to the flowchart of Fig. 10 and further exemplified in the cross-sectional views of Fig. 11A to Fig. 11l illustrates.

[0101] The process feature S200 comprises forming doped regions in a SiC semiconductor body at a first surface of the SiC semiconductor body (see e.g. Fig. 11A).

[0102] The process feature S210 comprises forming a gate trench in the SiC semiconductor body at the first surface (see, for example, Fig. 11A).

[0103] The process feature S220 includes forming a gate dielectric, e.g., an oxide of silicon, such as SiO2, in the gate trench and filling the gate trench with an auxiliary material (see, e.g., Fig. 11A).

[0104] The process feature S230 comprises forming an ohmic contact to at least a portion of the doped regions on the first surface of the SiC semiconductor body (see, e.g., Fig. 11B).

[0105] The process characteristics S240 and S250 are then executed.

[0106] The process feature S240 includes the removal of the auxiliary material from the gate trench (see e.g. Fig. 11C to Fig. 11E).

[0107] Process feature S250 includes forming a metal layer structure. A first portion of the metal layer structure may be formed on the gate dielectric and forms a gate electrode. A second portion of the metal layer structure may be formed on the ohmic contact (see, e.g., Fig. 11F to Fig. 11L).

[0108] The aspects and features mentioned and described together with one or more of the previously described examples and figures may also be combined with one or more of the other examples to replace a similar feature of the other example or to additionally incorporate the feature into the other example.

[0109] Although specific embodiments have been illustrated and described herein, it will be apparent to those skilled in the art that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims

[1] A method of manufacturing a semiconductor device (100), the method comprising: Forming doped regions (1011, 1021, 1031) in a SiC semiconductor body (106) at a first surface (1061) of the SiC semiconductor body (106); Forming an ohmic contact (108) to at least a portion of the doped regions (1011, 1021, 1031) on the first surface (1061) of the SiC semiconductor body (106); and thereafter Forming a gate dielectric (1101) on the SiC semiconductor body (106), and wherein the method further comprises: prior to forming the ohmic contact (108), forming a gate trench (110) in the SiC semiconductor body (106) at the first surface (1061); Filling the gate trench (110) with an auxiliary material (112) before forming the ohmic contact (108); and Removing the auxiliary material (112) from the gate trench (110) after forming the ohmic contact (108) and before forming the gate dielectric (1101). [2] The method of the preceding claim, wherein forming the ohmic contact (108) comprises processing the SiC semiconductor body (106) at temperatures higher than a crystallization temperature of the gate dielectric. [3] Method according to one of the preceding claims, wherein the formation of the doped regions (1011, 1012, 1013) comprises: Forming a source layer of a first conductivity type and forming a body layer of a second conductivity type; and Structuring the source layer into source regions and structuring the body layer into body regions by etching through the source layer and etching through the body layer when forming the gate trench (110), wherein the source regions and the body regions form at least a portion of the doped regions (1011, 1021, 1031). [4] Method according to the preceding claim, further comprising: Forming a dielectric intermediate layer (114) over the auxiliary material (112) and the first surface (1061) of the SiC semiconductor body (106) before removing the auxiliary material (112); and Exposing an upper surface region of the auxiliary material (112) by forming an opening (1145) in the dielectric interlayer (114), wherein the dielectric interlayer (114) remains as part of a wiring region (116) above the first surface (1061) of the SiC semiconductor body (106) or can be replaced by another dielectric interlayer. [5] A method of manufacturing a semiconductor device (100), the method comprising: Forming doped regions (1011, 1021, 1031) in a SiC semiconductor body (106) at a first surface (1061) of the SiC semiconductor body (106); Forming an ohmic contact (108) to at least a portion of the doped regions (1011, 1021, 1031) on the first surface (1061) of the SiC semiconductor body (106); and thereafter Forming a gate dielectric (1101) on the SiC semiconductor body (106), and wherein the method further comprises: Forming a dielectric interlayer (114) on the first surface (1061) of the SiC semiconductor body (106) before forming the gate dielectric (1101); and Exposing a gate region of the SiC semiconductor body (106) at the first surface (1061) of the SiC semiconductor body (106), wherein exposing the gate region of the SiC semiconductor body (106) at the first surface (1061) comprises forming an opening in the dielectric interlayer (114) and then forming the gate dielectric (1101) on the exposed gate region of the SiC semiconductor body (106) at the first surface (1061) of the SiC semiconductor body (106), and wherein the dielectric interlayer (114) remains as part of a wiring region (116) above the first surface (1061) of the SiC semiconductor body (106) or is replaced by another dielectric interlayer. [6] Method according to the preceding claim, further comprising: Exposing a contact region of the SiC semiconductor body (106) on the first surface (1061) of the SiC semiconductor body (106) after forming the dielectric interlayer (114) and before exposing the gate region, wherein exposing the contact region of the SiC semiconductor body (106) on the first surface (1061) comprises forming an opening in the dielectric interlayer (114) and thereafter forming the ohmic contact (108) on the exposed contact region of the SiC semiconductor body (106) on the first surface (1061) of the SiC semiconductor body (106). [7] The method of claim 5, further comprising forming a metal layer structure, wherein a first portion of the metal layer structure is formed on the gate dielectric (1101) and forms a gate electrode and a second portion of the metal layer structure is formed on the ohmic contact (108). [8] A method of manufacturing a semiconductor device (100), the method comprising: Forming doped regions (1011, 1021, 1031) in a SiC semiconductor body (106) at a first surface (1061) of the SiC semiconductor body (106); Forming an ohmic contact (108) to at least a portion of the doped regions (1011, 1021, 1031) on the first surface (1061) of the SiC semiconductor body (106); and thereafter Forming a gate dielectric (1101) on the SiC semiconductor body (106), and wherein the method further comprises: after forming the ohmic contact (108), forming a gate trench (110) in the SiC semiconductor body (106) at the first surface (1061), and Forming a dielectric interlayer (114) on the first surface (1061) of the SiC semiconductor body (106) before forming the gate trench (110); Exposing a gate region of the SiC semiconductor body (106) at the first surface (1061) of the SiC semiconductor body (106), wherein exposing the gate region of the SiC semiconductor body (106) at the first surface (1061) comprises forming an opening in the dielectric interlayer (114) and then forming the gate trench (110) in the SiC semiconductor body (106) at the first surface (1061), and wherein the dielectric interlayer (114) remains as part of a wiring region (116) above the first surface (1061) of the SiC semiconductor body (106) or is replaced by another dielectric interlayer. [9] Method according to the preceding claim, wherein the formation of the doped regions (1011, 1012, 1013) comprises Forming a source layer of a first conductivity type and forming a body layer of a second conductivity type; and Structuring the source layer into source regions and structuring the body layer into body regions by etching through the source layer and etching through the body layer when forming the gate trench (110), wherein the source regions and the body regions form at least a portion of the doped regions (1011, 1021, 1031). [10] The method according to any one of the two preceding claims, wherein the dielectric interlayer (114) is formed prior to forming the ohmic contact (108), the method further comprising: Exposing a contact region of the SiC semiconductor body (106) on the first surface (1061) of the SiC semiconductor body (106), wherein the exposing of the contact region of the SiC semiconductor body (106) on the first surface (1061) comprises forming an opening in the dielectric interlayer (114) and then forming the ohmic contact (108) on the exposed contact region of the SiC semiconductor body (106) on the first surface (1061) of the SiC semiconductor body (106). [11] A method of manufacturing a semiconductor device (100), the method comprising: Forming doped regions (1011, 1021, 1031) in a SiC semiconductor body (106) at a first surface (1061) of the SiC semiconductor body (106); Forming an ohmic contact (108) to at least a portion of the doped regions (1011, 1021, 1031) on the first surface (1061) of the SiC semiconductor body (106); and thereafter Forming a gate dielectric (1101) on the SiC semiconductor body (106); and wherein forming the doped regions (1011, 1012, 1013) comprises forming a source layer of a first conductivity type and forming a body layer of a second conductivity type, patterning the source layer into source regions and patterning the body layer into body regions by etching through the source layer and etching through the body layer when forming gate trenches (110), wherein the source regions and the body regions form at least a portion of the doped regions (1011, 1021, 1031); Filling the gate trenches (110) with an auxiliary material (112) before forming the ohmic contact (108); and Removing the auxiliary material (112) from the gate trenches (110) after forming the ohmic contact (108) and before forming the gate dielectric (1101). [12] Method according to the preceding claim, further comprising: Forming a dielectric intermediate layer (114) over the auxiliary material (112) and the first surface (1061) of the SiC semiconductor body (106) before forming the ohmic contact (108); and Exposing a contact region of the SiC semiconductor body (106) on the first surface (1061) of the SiC semiconductor body (106), wherein the exposing of the contact region of the SiC semiconductor body (106) on the first surface (1061) comprises forming an opening in the dielectric interlayer (114) and then forming the ohmic contact (108) on the exposed contact region of the SiC semiconductor body (106) on the first surface (1061) of the SiC semiconductor body (106). [13] Method according to the preceding claim, further comprising: Exposing an upper surface region of the auxiliary material (112) by forming an opening in the dielectric interlayer (114) before removing the auxiliary material (112), wherein the dielectric interlayer (114) remains as part of a wiring region (116) above the first surface (1061) of the SiC semiconductor body (106); and thereafter Formation of the gate dielectric (1101). [14] The method of the preceding claim, wherein the semiconductor device is a FinFET. [15] The method of any preceding claim, wherein forming the gate dielectric (110) comprises forming a high-k dielectric.

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