CONFIGUREABLE PIN DRIVER CIRCUIT OUTPUT IMPEDCANCE

Abstract

Pin driver output stage (800) which features the following: a push-pull output stage circuit (806) comprising output transistors (808, 810) configured to support bidirectional current signals at an output node (802); a bias current control (302) configured to adjust a bias current supplied to the output transistors (808, 810) of the push-pull output stage circuit (806) to match an impedance characteristic of the push-pull output stage circuit (806) at the output node (802); a first and a second resistor (Rbasep, Rbasen) which are coupled to the respective base terminals of the output transistors (808, 810); and a feedback control (706) configured to selectively supply a feedback current signal to the first and second resistors (Rbasep, Rbasen) to match the impedance characteristic of the push-pull output stage circuit (806) at the output node (802).

Description

BACKGROUND

[0001] A test system for testing electronic devices may include a pin driver circuit that provides a voltage test pulse to a device under test (DUT). In response, the test system may be configured to measure a response from the DUT, for example, to determine whether the DUT meets one or more predefined operating parameters. A test system may optionally include multiple driver circuits, such as a Class AB driver circuit and a Class A driver circuit, to provide circuit test signals with different amplitudes or timing characteristics. In one example, the test system is configured to measure a response from a DUT using an active load and a comparator circuit to detect transitions at a DUT pin.

[0002] A system for testing digital integrated circuits (ICs) can include a driver circuit designed to supply multiple voltage levels (e.g., Vhigh, Vlow, and Vterm) to a device under test (DUT). The DUT can have bidirectional (I / O) capabilities, as it can both provide and receive a stimulus. The Vhigh and Vlow levels of the driver circuit are used to stimulate a DUT in its "input state," and Vterm acts as the termination for the DUT in its "output state." The process of switching between Vhigh, Vlow, and Vterm can be designed as a collection of three switches, with one terminal of each switch connected to either Vhigh, Vlow, or Vterm, and the other terminal connected to a 50-ohm resistor, which is then connected to the DUT node. Transitions between the three levels can be achieved by opening and closing the corresponding switches, with, for example, only one switch being closed at any given time.

[0003] DE 10 2021 106 859 A1 relates to a multi-mode comparator system that can be useful for automated testing with high bandwidth and low power. The system can include an amplification stage configured to drive a high-impedance input of a comparator output stage, wherein the amplification stage has a differential switching stage coupled to an adjustable-impedance circuit, and an impedance magnitude property of the adjustable-impedance circuit corresponds to a bandwidth property of the amplification stage. The comparator output stage can include a buffer circuit coupled to a low-impedance comparator output node. In a higher-speed mode, the buffer circuit can provide a reference voltage for a switched output signal at the output node, and in a lower-power mode, the buffer circuit can provide the switched output signal at the output node.

[0004] DE 10 2015 218 758 A1 relates to compression control by matching power amplifier loads. A power amplifier module can include a power amplifier with a cascode transistor pair. The cascode transistor pair can comprise a first transistor and a second transistor. The power amplifier module can include a power amplifier bias control unit with a current comparator designed to compare a first base current of the first transistor with a second base current of the second transistor to obtain a reference value. The power amplifier module can include a saturation control unit designed to output a reference signal based on the reference value to an impedance matching network.The impedance matching network can be designed to change the load impedance of a load line that is electrically connected to the power amplifier, at least partially, based on the reference signal.

[0005] DE 36 02 908 A1 relates to an amplifier circuit for amplifying an alternating voltage. An amplifier circuit comprises a first amplifier stage and an output stage. The first amplifier stage consists of two complementary transistors connected in series via their collectors at a common point, with their collectors connected via their collector resistors. The output stage consists of two complementary transistors connected in series via their collectors at a common point. The base of the transistors in the output stage is connected to the collector of the corresponding transistor in the first amplifier stage.The two connection points of the two stages are connected by a resistor or impedance, which directly provides negative feedback from the output signal of the amplifier circuit to the input of the output stage and is intended to enable signals with a high frequency mixture to be transmitted up to high frequencies without significant phase errors. SUMMARY

[0006] The inventors of the present invention have recognized, among other things, that one problem to be solved involves providing an automated test system for supplying test signals to and measuring response signals from a device under test (DUT). The problem may consist of providing a system that is relatively small, inexpensive to manufacture, consumes little power, or offers better signal fidelity compared to previous systems.

[0007] In one example, the challenge might be maintaining a stable and known impedance characteristic at the DUT interface of the test system. An ideal impedance characteristic at the DUT interface might conventionally be 50 ohms, but other conventions or impedance values ​​may be used for specific tests or devices. If a stable or known impedance characteristic is not maintained, DUT signals can be affected or corrupted. Sources of corruption include, for example, losses due to the skin effect, dielectric loading, conductor resistance, and waveform reflections, among others. Such signal corruption sources can contribute to undesirable changes in a DUT signal as the signal travels between the DUT and, for example, a comparator designed to measure changes in the DUT signal.The unwanted changes to the DUT signal can contribute to signal timing errors due to propagation delays or transmission line effects, which in turn can lead to incorrect or faulty test results.

[0008] The inventor of the present invention recognized that providing a physical 50-ohm output resistance at the DUT interface is insufficient in some scenarios and impractical in others. The inventor of the present invention further recognized that the impedance at the DUT interface is a function of several elements of the test system's output stage, including an "incremental impedance" of transistors comprising the test system's output stage.

[0009] In one example, a solution to this and other problems may include or utilize a test system comprising a comparator circuit coupled to a DUT node, an active load coupled to the DUT node, and an output stage circuit coupled to the DUT node. The output stage circuit may be configured to provide a predetermined impedance characteristic at the DUT node that is essentially invariant over a predetermined range of DUT currents. In one example, the output stage circuit includes a class-AB driver circuit with output transistors provided in a push-pull configuration. The output stage circuit may further include a bias current controller configured to provide a bias current to the output transistors of the driver circuit based on an initial control input.In one example, the output stage circuit further features a feedback control configured to provide a feedback current at the respective base terminals of the output transistors of the driver circuit, based on a second control input. The magnitude of the feedback current can be based on the DUT current. A user or another control system can supply control signals to the first and second control inputs to adjust the impedance of the output stage, thereby achieving a more precise impedance characteristic or an optimal impedance characteristic at the DUT interface.

[0010] In one example, a solution to the problems mentioned above might include a method for adjusting the characteristic output impedance of an output stage of a pin driver circuit. The method might involve receiving a first control input at a bias current controller and, in response, supplying a bias current to transistors in the output stage of the pin driver circuit. The magnitude of the bias current could correspond to a value of the first control input. The method might further involve receiving a second control input at a feedback controller and, in response, supplying a feedback current to the respective base terminals of the transistors in the output stage of the pin driver circuit. The magnitude of the feedback current could correspond to a value of the second control input.In this example, the characteristic output impedance of the output stage corresponds to an impedance at an output node coupled to the emitter terminals of the transistors in the output stage.

[0011] This summary is not intended to provide an exclusive or exhaustive explanation of the invention. The full description is included to provide further information about the present patent application. BRIEF DESCRIPTION OF THE MULTIPLE VIEWS OF THE DRAWINGS

[0012] To easily identify the discussion of a particular element or action, the most significant digit(s) in a reference number refer to the number of the figure in which the element is first introduced. Fig. Figure 1 generally illustrates an example of a first test system that includes a pin driver. Fig. Figure 2 generally illustrates an example of an output stage of a pin driver. Fig. Figure 3 generally illustrates an example of a pin driver output stage with bias current control. Fig. Figure 4 illustrates a first diagram showing a relationship between the DUT current and the output stage impedance. Fig. Figure 5 generally illustrates an example of part of a pin driver output stage with degeneration resistors. Fig. Figure 6 illustrates a second diagram showing a relationship between the DUT current and the output stage impedance. Fig. Figure 7 illustrates a general first example of a pin driver output stage with bias current control and feedback control. Fig. Figure 8 generally illustrates a second example of a pin driver output stage with bias current control and feedback control. Fig. Figure 9 illustrates in general an example of a procedure for matching a characteristic output impedance of an output stage of a pin driver circuit. DETAILED DESCRIPTION

[0013] A pin driver circuit of a test system can deliver a voltage pulse stimulus to a device under test (DUT) at a predetermined time and can optionally measure a response signal from the DUT. The system can be configured to provide high-fidelity output signal pulses over a relatively wide range of output signal magnitudes to accommodate various tests and different types of devices under test.

[0014] In one example, a test system might incorporate a pin driver architecture capable of providing high-fidelity stimulus signals with minimal overshoot or peaking of high-frequency signals, thereby improving pulse edge placement accuracy and signal bandwidth during high- or low-power operation. In another example, a test system might include one or more driver stages, such as a Class A or Class AB driver stage, configured to provide a variety of pulse signals. The systems might include control circuitry for precise adjustment of switching voltage and current signals, as well as for controlling an operating mode and monitoring or measuring comparator activity.

[0015] In one example, multiple drivers or driver stages can be used to provide a test system that can be trained to test a variety of semiconductor devices with varying voltage and speed requirements. Furthermore, multiple drivers can be used to enhance or enable multiple-signal level testing, or "multiplexing," for physical layer testing. During physical layer testing, multiple drivers can be switched on simultaneously to deliver different stimuli or drive signals to a device under test (DUT).

[0016] In one example, a pin driver stage of a test system forms part of the interface between the tester and the DUT. The pin driver stage may be responsible for establishing the timing accuracy of the test system. That is, the pin driver stage may be configured to deliver the edges of the DUT stimulus signal precisely, essentially independent of environmental or other factors. In some examples, the pin driver stage is configured to support current stimulus signals with higher frequency and lower voltage, as well as current stimulus signals with lower frequency and higher voltage. In one example, the pin driver stage maintains a specific characteristic impedance (e.g., 50 ohms) that is optimized for bandwidth and timing accuracy. The characteristic impedance may, for example, be matched to the impedance of a transmission line that couples the test system to the DUT.

[0017] A test system may include a comparator circuit or comparator stage designed to receive voltage or current response signals from a device under test (DUT) at high speed. A comparator is generally a decision element that provides information about the relationship between at least two input signals. For example, a comparator may provide a digital output (such as a logic high or logic low signal) indicating the relationship between a signal from a DUT and a reference signal, such as a reference voltage signal. The comparator may include one or more gain stages, which may be connected in series, for example, to achieve a high gain response.

[0018] In some cases, high-speed ATE (Automatic Test Equipment) systems have sufficiently high bandwidth that non-idealities in the transmission medium between the device under test (DUT) and the ATE pin electronics can limit the overall performance of the system. This transmission medium, or transmission path, generally includes multiple cables, connectors, PCB traces, and pogo pins electrically coupled to the DUT. The losses associated with such components primarily manifest as the skin effect, where the resistance experienced by the propagating signal is a function of the signal frequency. Since any signal can be represented by a superposition of many frequency components, certain components of the signal experience greater losses than others, creating a dispersive effect that impairs the signals communicated with the DUT.If the original signal is to be transmitted to the pin electronics with minimal distortion, great care must be taken in the design of the transmission path. In some cases, the frequency components present in high-speed signals are so high that even the best quality transmission path can cause significant signal integrity degradation. In such cases, the receiver in the pin electronics, which is usually a comparator, may incorporate or use a compensation circuit arrangement to compensate for the expected transmission losses.

[0019] Fig. Figure 1 illustrates, in general, a first exemplary test system 100, which shows a test system topology comprising multiple driver stages, a load, and a comparator stage. The first exemplary test system 100 has a driver system comprising a first driver AB 102, which may be a class AB driver circuit, and a first driver A 104, which may be a class A driver circuit. The first exemplary test system 100 may further include an output element, such as a first resistor 106, which may be configured to provide a predetermined output or load impedance. In one example, the first exemplary test system 100 includes a comparator circuit 122 or a first load circuit 108, which may, for example, include an active load or other load device.In one example, the test system is configured to provide a first output current 120, i_OUT, at a DUT interface or DUT node 130. The DUT node 130 can be coupled to a DUT 124 using a loaded signal path 132. In some examples, the first resistor 106 and the loaded signal path 132 have matching impedance characteristics.

[0020] In one example, the first driver AB 102 can be configured to generate a voltage stimulus signal by selecting between parallel-connected diode bridges, each bridge being driven by a unique, dedicated DC voltage level. In the first exemplary test system 100 of Fig. 1. DC voltages Vih 110 and Vil 112 control diode bridges in the first driver AB 102. A voltage buffer stage can follow the switching stage, providing power amplification that can be used, for example, to generate large currents for a 50-ohm DUT environment.

[0021] In contrast to the first driver AB 102, the first driver A 104 can be configured to generate transitions at the DUT node 130 using a relatively large current switching stage, which can be directly coupled to the DUT node 130. A current switching stage in the first driver A 104 can alternately switch current into and out of the DUT node 130 in response to a control signal Swing 118, which can be, for example, a voltage control signal. The first driver A 104 can, for example, provide high-speed operation because it may not have the disadvantages of the class AB voltage buffer stage with its associated bandwidth limitations and other performance restrictions.

[0022] In one example, the first driver A104 can be configured to provide a relatively low-amplitude signal at the DUT node 130. For instance, the first driver A104 can provide a signal with a voltage swing of approximately 2 volts. The first driver AB102 can be configured to provide a relatively high-amplitude signal at the DUT node 130, e.g., -1.5 to +7 volts. The first driver A104 generally operates at a higher switching speed or bandwidth than the first driver AB102. In another example, the first driver AB102 can be configured to absorb switching currents from the first driver A104. That is, the first driver AB102 can act as a buffer into which the first driver A104 can introduce current, e.g., through the first resistor 106.

[0023] One or both of the first driver AB 102 and the first driver A 104 can be selected to meet different DUT test requirements that a single driver cannot otherwise fulfill. While both driver circuits can provide DUT waveforms, for example, the first driver AB 102 can be configured to provide stimulus signals with a larger amplitude and lower bandwidth, and the first driver A 104 can be configured to provide stimulus signals with a lower amplitude and higher bandwidth. In other examples, a single driver (e.g., the first driver AB 102) can be used.

[0024] In one example, the first driver AB 102 and the first driver A 104 do not share a common enable pin. Instead, each driver circuit has independent enable control via pins EnAB 114 and ENA 116. This independent enable control allows the first driver AB 102 to act as a low-speed, high-voltage stimulus source and to serve as a static non-transition buffer to absorb switching currents from the first driver A 104.

[0025] Fig. Figure 1 features the comparator circuit 122. The comparator circuit 122 can include a single-stage or multi-stage comparator configured to receive a signal from the DUT 124, for example, via the DUT node 130 and the loaded signal path 132. The comparator circuit 122 can compare the received signals with a comparator reference signal 126 (e.g., Vth) and provide a differential comparator output signal 128 (e.g., OP) as a response. For example, the comparator circuit 122 can receive a voltage response signal from the DUT 124 and compare the amplitude of the voltage response signal with the amplitude of the comparator reference signal 126. The comparator circuit 122 can provide information about the amplitude relationship using the differential comparator output signal 128, which, for example, B. has a digital signal or a logic output signal.

[0026] Fig. Figure 2 illustrates a general example of a simplified output stage 200 for a pin driver, which may, for example, include an output stage of the first driver AB 102. The simplified output stage 200 has a buffer that receives a switching voltage signal at a voltage input node 206 and provides a buffered representation of the switching voltage signal at the DUT node 130. Resistance, inductance, and capacitance characteristics of the buffer produce a characteristic output stage impedance, or driver output impedance, 204, which is provided at the DUT node 130. In one example, the overall driver output impedance 204 is a function of an output resistance 210 and a characteristic incremental impedance, or AB stage output impedance, 202 of the driver.For example, the driver output impedance 204 can be represented by the series connection of the resistance of the output resistor 210 and an impedance of the transistor devices coupled to the output of the driver, which depends on the bias current.

[0027] The simplified output stage 200 features a network of devices, including push-pull output transistors qnA and qpA, and reference path transistors qp and qn. In the example of Fig. 2 A first current source ibiasp provides a current signal to an emitter of the reference path transistor qp, and a second current source ibiasn provides a current signal to an emitter of the reference path transistor qn. The reference path transistors are coupled to the voltage input node 206 to receive the switching voltage signal and thereby control the current in the reference path transistors.

[0028] The output transistors qnA and qpA have NPN and PNP devices (or arrays of such devices), respectively, connected in series between a voltage source VCC and a voltage reference VEE. The emitters of the output transistors qnA and qpA are coupled to an intermediate output node 208. In one example, the intermediate output node 208 is coupled to the DUT node 130 via an output resistor 210, Rpoly, which may be, for example, a fixed-value polysilicon resistor (or another). In this example, the driver output impedance 204 can be represented by connecting the AB-stage output impedance 202 in series, for example, at the intermediate output node 208, and the output resistor 210.

[0029] In one example, the impedance or resistance characteristic of the output resistor 210 can be controlled in various ways. For instance, the output resistor 210 can be a laser-trimmed thin-film resistor device whose value is fixed at the manufacturing site. However, the laser trimming process can be expensive or impractical in some manufacturing processes, and large resistors can introduce undesirable capacitive effects. In another example, the output resistor 210 can be an array of devices (e.g., MOSFET switches or other devices) with an impedance characteristic that depends on the number of parallel devices that are enabled or disabled. This solution can have insufficient bandwidth or voltage characteristics and a relatively significant temperature dependence.In another example, the output resistor 210 can have multiple parallel resistors, and the impedance characteristic of the parallel circuit can be adjusted by switching different legs of the resistor network into or out of the DUT current signal path. This solution can be problematic at high switching frequencies, for example, due to parasitic capacitance effects associated with switches in each resistor leg. In an example featuring MOS-based switches, a DUT voltage range may be restricted to prevent damage to the MOS devices from voltages outside a predetermined envelope of a safe operating range. Another solution is required to ensure a stable output impedance characteristic (e.g., 50 ohms) for the output stage of a pin driver.

[0030] In one example, a voltage difference between the bases of the push-pull output transistors qnA and qpA generates a bias current through the transistors. To support higher bandwidths or faster output signals at DUT node 130, the first and second current sources ibiasp and ibiasn can provide larger current signals, and the output transistors qnA and qpA can, in turn, be physically large (or have respective combinations of smaller devices or arrays connected in parallel). However, using a large bias current signal affects the AB-stage output impedance 202 of the driver.In some examples, the influence of the bias current on the AB-stage output impedance 202 is significant and causes a mismatch between the impedance at DUT node 130 and the DUT itself, and the transmission line coupled to DUT node 130. This can lead to poor performance and timing errors. In other words, if the impedance characteristics at DUT node 130 and the DUT do not match, signal deviations due to reflections into the signal path can be introduced, affecting the timing accuracy and thus the performance of the test system.

[0031] In one example, the bias current can be controlled to adjust or control the class AB output impedance 202 and thus the driver output impedance 204 for the class AB output stage. For example, during operation in the non-saturation region, the incremental emitter impedance of a bipolar transistor (here re) may depend on current and temperature, e.g. re=kTq / Ie, where T is the temperature, k the Boltzmann constant, q the electron charge, and Ie the bias current flowing through the device. At room temperature, re is approximately 25 mV / e. In other words, the output impedance of a bipolar transistor is a function of the bias current in the device. This resistance / current relationship can be used to change the output impedance of a transistor used in an output stage, for example, to change the AB stage output impedance. By differentiating the emitter impedance function, it can be shown, for example, that the output impedance decreases linearly with increasing bias current. Therefore, the output impedance can be controlled by intentionally changing the bias current.

[0032] Fig. Figure 3 illustrates a simplified example of the output stage 200 with a bias current controller 302 and base resistors associated with the output transistors. The bias current controller 302 can be configured to change a voltage difference between the bases of the push-pull output transistors qnA and qpA, thereby changing the magnitude of the bias current in the transistors. The magnitude of the bias current affects the AB-stage output impedance 202 or ABoutZ, as described above. In one example, the bias current controller 302 establishes the voltage difference partly by introducing or diverting a current through the base resistors Rbasep and Rbasen, which are coupled to the output transistors qnA and qpA, respectively.

[0033] In the example of Fig. 3. The bias current controller 302 generates a bias current, / e, of 1 mA in the output transistors qnA and qpA. When the bias current is 1 mA, the emitter impedance at each of the output transistors is re=kTq / Ie=25mV1mA=25Ω. The AB stage output impedance 202 has the parallel connection of the output transistors qnA and qpA, and accordingly the AB stage output impedance 202 can be calculated as 12.5 ohms, e.g. when the DUT current is zero (i.e. when the driver does not introduce or draw any current into the DUT node 130).

[0034] Fig. Figure 4 illustrates a general first diagram 400, which shows a relationship between the DUT current at DUT node 130 and the AB stage output impedance 202, for example, for the simplified output stage 200. The first diagram 400 generally shows that the AB stage output impedance 202 decreases as the magnitude of the DUT current increases. At high currents (draining or injecting) at DUT node 130, the AB stage output impedance 202 approaches zero. At medium DUT currents, the AB stage output impedance 202 lies between approximately zero and 12.5 ohms.

[0035] In one example, if the bias current is increased to 2 mA, the emitter impedance is re=kTq / Ie=25mV2mA=12.5Ω for each output transistor. In this example, the AB-stage output impedance 202, with the output transistors connected in parallel, provides the AB-stage output impedance 202 at 6.25 ohms, for example, when the DUT current is zero (i.e., when the driver is not injecting or diverting any current into the DUT node 130).

[0036] Based on the relationship between the bias current in the output transistors and the AB-stage output impedance 202, feedback or a control loop can be provided to generate a bias current to achieve an adjustable impedance characteristic for the pin driver. For example, the bias current can be used to mitigate or account for the effects of variations in the resistance value of the output resistor 210. For instance, the output resistor 210 may be a thin-film resistor with some resistance variability due to manufacturing variations (e.g., ±1%, ±5%, ±10%, or some other variation). This variability of the output resistor 210 can be accommodated by adjusting the bias current in the output transistors, thereby changing the AB-stage output impedance 202 coupled to the output resistor 210.

[0037] For example, to ensure a 50-ohm load from the perspective of the DUT at DUT node 130, the pin driver can provide a 50-ohm load that is a series combination of the output resistor 210 and the AB-stage output impedance 202. If the resistance value of the output resistor 210 is, for example, approximately 44 ohms, the bias current supplied to the output transistors qnA and qpA can be set to approximately 2 mA by the bias current controller 302, so that with a DUT current of zero at the driver output impedance 204, the series combination of the incremental impedance of 6.25 ohms of the transistors and the resistance value of the physical resistance of 44 ohms is approximately 50 ohms.

[0038] The inventor of the present invention has recognized that the output impedance 202 of the push-pull output stage can be made essentially insensitive to DUT current by providing an emitter resistor in series with the output transistors qnA and qpA. Fig. Figure 5 illustrates, in general terms, an example of a portion of the simplified output stage 200 with emitter resistors or degeneration resistors coupled to the emitter terminals of the output transistors qnA and qpA. In the example of Fig. 5. The emitter resistors exhibit the same resistance characteristic R. OPTIMAL The term “optimal” can refer to a value of each of the emitter resistors chosen to be approximately equal to or equal to the incremental impedance of the output transistor when the current magnitude at DUT node 130 is zero (i.e., when DUT node 130 is neither introducing nor diverting any current into the DUT).

[0039] Fig. Figure 6 generally illustrates an example of a second diagram 600, which shows a relationship between DUT current and the AB stage output impedance 202, such as for the simplified output stage 200 with emitter resistors from the example of Fig. 5. In an example featuring degeneration resistances with the “optimal” value described above, the second diagram 600 generally shows that the AB-stage output impedance 202 nominally increases with increasing DUT current from zero, but then at or near R OPTIMAL transient. That is, at high currents (drainage or introduction) at DUT node 130, the AB step output impedance approaches 202 R. OPTIMAL For example, in a state of fully commutated DUT current input 602, in which the entire DUT current is supplied through the NPN transistor qnA, the AB stage output impedance is 202 R. OPTIMALIn a state of fully commutated DUT current derivation 604, in which the entire DUT current is derivated through the PNP transistor qpA, the AB stage output impedance 202 R OPTIMAL Therefore, the inclusion of the degeneration resistors at the emitters of the output transistors helps to stabilize the AB-stage output impedance 202 for most of the DUT current operating range and allows the AB-stage output impedance 202 to be substantially independent of the DUT current.

[0040] In a specific example, let's assume that the incremental impedance of each of the output stage transistors is 25 ohms, which in turn gives R OPTIMALThe incremental impedance of each degeneration resistor is 25 ohms. In this example, the series connection of the incremental impedance of the NPN transistor qnA and its degeneration resistor is 50 ohms, and the series connection of the incremental impedance of the PNP transistor qpA and its degeneration resistor is 50 ohms. The parallel connection of such impedances thus provides 25 ohms across the AB stage output impedance 202. When the driver supplies a large DUT current, the PNP transistor qpA is effectively switched off, and all of the DUT current flows through the NPN transistor qnA. The effective impedance, or incremental impedance, of transistor qnA is low in this case. Similarly, if the driver receives or dissipates a large DUT current, the NPN transistor qnA is effectively switched off, and the entire DUT current flows through the PNP transistor qpA.

[0041] In one example, a high-speed feedback circuit can be provided to work in conjunction with the bias current control feedback loop. The high-speed feedback circuit can be configured to apply a user-configurable amount of output current to the base resistors Rbasep and Rbasen, effectively converting the base resistors into emitter degradation resistors. The base resistors can remain physically coupled to the bases of the output transistors; the high-speed feedback makes them appear as if they were in series with the output stage resistors.

[0042] In one example, the bias current control 302 is a lower-bandwidth control loop that supplies a user-specified amount of bias current to the output transistors to compensate for uncertainty or variability in the resistance value of the output resistor 210. The higher-bandwidth control loop provides a feedback signal that applies a user-specified amount of feedback current to the base resistors of the output transistors to "transform" the base resistors into emitter degradation resistors with the optimal resistance value, as described above. This effectively modifies the emitter degradation behavior of the output transistors and changes the AB-stage output impedance 202. In other words, by changing the emitter degradation behavior of the output stage, an optimal state is created that makes the driver output impedance essentially independent of the DUT current.

[0043] Fig. Figure 7 illustrates a general first example of a pin driver output stage with bias current control and feedback control. The example of Fig. The circuit features a first compensated output stage 700, which may include a bias current control 302 and a feedback control 706. The bias current control 302 may be configured to control the differential voltage across the bases of the output transistors qnA and qpA to generate a controlled bias current through the output transistors. The feedback control 706 may be configured to control feedback current signals applied to the base resistors Rbasep and Rbasen, respectively. The bias current control 302 and the feedback control 706 determine the AB-stage output impedance 202 of the first compensated output stage 700 and contribute to ensuring that the driver output impedance 204 is at an optimal value to maximize signal fidelity.

[0044] In one example, the bias current controller 302 is configured to receive a tuning parameter, such as a first control signal, at a first control input 702. The first control signal can be, for example, an analog or digital control signal that defines the magnitude of the differential voltage to be applied across the bases of the output transistors, which in turn defines the magnitude of the bias current in the transistors. In one example, the first control signal is set or provided by a user, or it is automatically updated by other aspects of the test system, which includes the first compensated output stage 700. In another example, the bias current controller 302 includes a scaled-down simulation circuit that represents or corresponds to the output stage circuit.

[0045] In one example, the feedback control 706 is configured to receive another tuning parameter, such as a second control signal, at a second control input 704. The second control signal can, for example, be an analog or digital control signal that defines the magnitude of a current signal to be applied to the bases of the output transistors, which in turn defines the magnitude of a voltage generated across the base resistors Rbasep and Rbasen. In one example, the second control signal is set or provided by a user, or updated automatically by other aspects of the test system, which includes the first compensated output stage 700. In another example, using the feedback control 706 to apply a current signal to the base resistors is electrically similar to providing degeneration or emitter resistors across the emitters of the output transistors qnA and qpA.In some examples, the 706 feedback control can be used to apply the current signals to the base resistors, and degeneration or emitter resistors may also be provided.

[0046] In one example, an optimal state of the output stage occurs when the current signals supplied by the feedback control 706, applied to the first and second base resistors, generate a voltage that is essentially equal to the voltage generated by the DUT current at DUT node 130, thereby producing a driver output impedance 204 that is essentially independent of the DUT current. In this example, the DUT current can be a bidirectional current signal applied to the AB stage output impedance 202 or the effective impedance of the output stage's push-pull output transistors.

[0047] In one example, if the first control signal at the first control input 702 specifies a minimum bias current for the output transistors qnA and qpA of the first compensated output stage 700, the second control signal at the second control input 704 can specify a minimum feedback current to maintain or optimize the AB stage output impedance 202 for a given DUT current. In some examples, the first control signal can be a function of the second control signal, or the second control signal can be a function of the first control signal.

[0048] Fig. Figure 8 illustrates a second example of a pin driver output stage 800, which may, for example, include part of the first driver AB 102 or the first exemplary test system 100. The output stage 800 may generally be the simplified output stage 200 or the first compensated output stage 700 from the examples in Figure 8. Fig. 2 or Fig. 7. For example, output stage 800 can have an intermediate output node 802, which is coupled to DUT node 130 via output resistor 210. Output stage 800 provides an adjustable output impedance at intermediate output node 802. For example, the output impedance of output stage 800 can be changed based on the magnitude of the DUT current at DUT node 130.

[0049] The output stage 800 in the example of Fig. The device 8 has an input node 804 configured to receive a switching voltage signal. The switching voltage signal is buffered or amplified by the output stage 800 and delivered to the DUT node 130 via a push-pull output stage circuit 806, which includes the intermediate output node 802.

[0050] The push-pull output stage circuit 806 comprises a first output transistor 808 (e.g., an NPN transistor) and a second output transistor 810 (e.g., a PNP transistor). The first output transistor 808 and the second output transistor 810 can optionally each have arrays of similarly configured transistors. In one example, a first degeneration resistor 812 is coupled to the emitter of the first output transistor 808, and a second degeneration resistor 814 is coupled to the emitter of the second output transistor 810. The first degeneration resistor 812 and the second degeneration resistor 814 can be coupled at the intermediate output node 802. The intermediate output node 802 can be coupled via the output resistor 210 to a device under test (DUT) at the DUT node 130.In one example, the first output transistor 808 corresponds to the output transistor array qnA, and the second output transistor 810 corresponds to the output transistor array qpA from the previously described examples of different output stages for a pin driver.

[0051] The output stage 800 also features an example of the bias current control 302, which is coupled, for example, between the bases of the first output transistor 808 and the second output transistor 810. The bias current control 302 generates a differential voltage between the bases of the output transistors to control the magnitude of a bias current flowing through the push-pull output stage circuit 806, thereby modifying the impedance characteristic of the push-pull output stage circuit 806. That is, the bias current influences the incremental impedance of the first output transistor 808 and the second output transistor 810, which in turn influences the output impedance of the output stage 800, such as at the intermediate output node 208 or the DUT node 130.

[0052] In one example, the bias current controller 302 has a scaled copy of all or part of the circuit arrangement comprising the output stage 800. For example, the bias current controller 302 may have a one-to-eighth scale copy of the circuit arrangement of the output stage 800. The bias current controller 302 has the first control input 702, which is configured to receive a control signal for a current generator 816. The current generator 816 may, for example, have a current source (which may include a PTAT current generator) that provides a current signal within a predetermined range of current signal quantities, e.g., B. between 1 / 8 and 1 / 4 mA (e.g., corresponding to one eighth of the expected 1 to 2 mA swing of the bias current for the push-pull output stage circuit 806, e.g., if the bias current control 302 has a one-to-eighth copy of the output stage circuit).Accordingly, the controlled current provided by the smaller, lower-power bias current controller 302 can be used to apply higher main stage bias currents to the push-pull output stage circuit 806.

[0053] Output stage 800 further includes an example of the feedback control 706, which can be configured to supply feedback current signals to respective base resistors of the first output transistor 808 and the second output transistor 810. In one example, the feedback control 706 incorporates a current-selectable DAC to monitor and respond to the current in the push-pull output stage circuit 806 by controlling a folded cascode amplifier to supply a feedback current signal to a base resistor. The use of the folded cascode configuration helps to ensure high output impedance, high gain, and high bandwidth of the feedback control 706, which in turn allows the base resistors Rbasep and Rbasen to be small or have a low resistance (e.g., 100 ohms).Accordingly, the feedback loop implemented by the feedback controller 706 can be fast and respond to changes in the DUT current at the DUT node 130. The transistor networks, designated with multiple "y" devices, each have buffers designed to absorb the current of the high-speed feedback loop and maintain a constant voltage on one side of each of the base resistors Rbasep and Rbasen.

[0054] The example of Fig. Figure 8 shows an instance of the feedback controller 706, which has an array of NPN devices, coupled to the current input side of the push-pull output stage circuit 806. A similar instance of the feedback controller 706, which has an array of PNP devices, can be coupled to the current output side of the push-pull output stage circuit 806.

[0055] During operation, an optimal state of the output stage 800 can be achieved, where the output impedance (e.g., at DUT node 130) is essentially independent of the DUT current at DUT node 130, even for different magnitudes of lead-in or lead-out DUT currents. First voltages can be generated by the feedback current signals from the feedback controller 706, applied to each base resistor. A second voltage can be generated by the DUT current applied to the incremental impedance of the transistors in the push-pull output stage circuit 806, and the incremental impedance can be a function of the bias current applied by the bias current controller 302. The optimal state can occur when the first and second voltages are essentially equal.

[0056] Various modifications can be made to the output stage 800 to adjust the size of the trim range for the output impedance of the push-pull output stage 806 or the bandwidth of the output stage 800. For example, a larger trim range can be achieved by increasing the resistance values ​​of the base resistors Rbasep and Rbasen. However, such resistance increases can decrease the overall bandwidth of the output stage 800 and reduce the bandwidth or speed of the feedback control 706, which in turn can lead to ringing or faults under some operating conditions.

[0057] In one example, a larger trim range can be achieved by increasing the gain of the feedback control 706 or the magnitude of the feedback control signals. However, increasing the gain can interfere with the upstream driver circuitry (i.e., before the base resistors Rbase in the signal chain), require physically larger devices in the feedback control 706, and consume more current. In another example, a larger trim range can be achieved by decreasing the minimum bias current in the output transistors, but this results in bandwidth limitations at low bias currents.

[0058] In one example, the overall bandwidth of the output stage 800 can be increased by decreasing the resistance characteristics of the base resistors Rbasep and Rbasen and by reducing the gain of the feedback control 706. However, such changes can affect the stability of the output impedance characteristic of the push-pull output stage circuit 806. As can be seen, the optimization of the output stage 800 depends on balancing these and other competing considerations.

[0059] Fig.Figure 9 illustrates a general example of Method 900, which features the use of bias current control and feedback control in an output stage of a pin driver circuit. In one example, Method 900 includes or uses the bias current control 302 and the feedback control 706 to modify an output impedance characteristic of the output stage of the pin driver circuit to ensure that the pin driver circuit provides an impedance-stable load (e.g., 50 ohms) at a DUT interface.

[0060] In Procedure 902, Procedure 900 may include receiving an initial control signal input at a bias current controller, such as the bias current controller 302. The initial control signal input may be an analog or digital control signal provided by a user or other control system and configured to update or adjust an output impedance magnitude characteristic of the output stage of the pin driver circuit. The output impedance magnitude corresponds to an impedance at an output node of the pin driver, such as at or coupled to the emitter terminals of transistors in the output stage.

[0061] In Procedure 904, the bias current controller 302 can be configured, in response to receiving the first control signal input, to supply a bias current to the transistors in the output stage of the pin driver circuit, the magnitude of which corresponds to a value of the first control signal input. For example, in Procedure 904, the bias current controller 302 can control a differential voltage applied to transistors in a class-AB push-pull output stage to change the magnitude of the bias current in the transistors. In one example, Procedure 904 features the use of a scaled simulation of the output stage to generate the voltage signal that causes the bias current to flow through the output transistors of the output stage.

[0062] In Procedure 906, Procedure 900 may involve receiving a second control signal input at a feedback controller, such as the feedback controller 706. The second control signal input may be an analog or digital control signal provided by a user or other control system and configured to update or adjust the impedance size characteristic of the output stage of the pin driver circuit. In Procedure 908, the feedback controller 706 may, in response to receiving the second control signal input, be configured to provide feedback current signals at respective base terminals of the transistors in the output stage of the pin driver circuit. In one example, the feedback current signals are applied to respective base resistors coupled to the base terminals of the transistors in the push-pull output stage.In one example, one magnitude of the feedback current signals corresponds to one value of the second control signal input.

[0063] In one example, procedure 900 might involve sensing a DUT current signal at operation 910. Operation 910 might involve sensing the direction or magnitude of the DUT current signal. If the direction or magnitude of the DUT current signal changes, then at operation 912, output stage 800 might involve updating or changing the first control signal input and / or the second control signal input to maintain a predefined output impedance characteristic (e.g., 50 ohms) for the pin driver.

[0064] Several aspects of the present disclosure may assist in providing a solution to the problems identified herein in connection with test systems, as illustrated in the following examples.Example 1 may include a pin driver circuit comprising: a push-pull output stage circuit having output transistors configured to support bidirectional current signals at an output node; a bias current control configured to adjust a bias current supplied to the output transistors of the output stage circuit to match an impedance characteristic of the output stage circuit at the output node; a first and a second resistor coupled to respective base terminals of the output transistors; and a feedback circuit configured to selectively supply a feedback current signal to the first and second resistors to match the impedance characteristic of the output stage circuit at the output node.

[0065] In Example 2, the subject of Example 1 exhibits the following: the impedance characteristic of the output stage circuit at the output node is essentially independent of the magnitude of the bidirectional current signals at the output node.

[0066] In Example 3, the subject of Example 2 exhibits the following: the feedback current signal is applied to the first and second resistors to provide a first voltage; the bidirectional current signals apply a second voltage to an incremental impedance of the output transistors; and the impedance characteristic of the output stage circuit at the output node is essentially independent of the magnitude of the bidirectional current signals at the output node when the first and second voltages are of the same magnitude.

[0067] In Example 4, the subject of Examples 1-3 exhibits the following: the magnitude of the feedback current signal is smaller than the magnitude of a current signal at the output node.

[0068] In Example 5, the subject of Examples 1-4 exhibits the following: the magnitude of the feedback current signal is a function of the magnitude of the current signal at the output node and an output impedance tuning parameter.

[0069] In Example 6, the subject of Examples 1-5 comprises the following: a data input configured to receive an output impedance tuning parameter specifying a bias current magnitude and the feedback current signal magnitude.

[0070] In Example 7, the subject of Examples 1-6 is as follows: the bias current control is configured to change a quantity of the bias current in coordination with a change in the quantity of the feedback current signal.

[0071] In Example 8, the subject of Examples 1-7 exhibits the following: the bias current control has a scaled-down simulation circuit of the push-pull output stage circuit.

[0072] In Example 9, the subject of Examples 1-8 has the following: the feedback circuit has a first folded cascode amplifier circuit that provides a first feedback current signal to the first resistor, and a second folded cascode amplifier circuit that provides a second feedback current signal to the second resistor.

[0073] In Example 10, the subject of Examples 1-9 comprises: A fixed-value polysilicon resistor coupled between the output node of the output stage circuit and a DUT node (Device Under Test).

[0074] In Example 11, the subject of Example 10 has the following: degeneration resistors coupled between the emitter terminals of the output transistors and the output node.

[0075] Example 12 is a system comprising: a comparator circuit coupled to a DUT (Device Under Test) node; an active load coupled to the DUT node; and an output stage circuit coupled to the DUT node, wherein the output stage circuit is configured to provide at the DUT node a predetermined impedance characteristic that is substantially invariant over a predetermined range of DUT currents, wherein the output stage circuit comprises: a class AB driver circuit; a bias current control configured to provide, based on a first control input, a bias current for output transistors of the driver circuit; and a feedback control configured to provide, based on a second control input, a feedback current at respective base terminals of the output transistors of the driver circuit.

[0076] In Example 13, the subject of Example 12 shows that if the first control input specifies a minimum bias current for the output transistors of the driver circuit, the second control input specifies a maximum feedback current in order to maintain the specified impedance characteristic for the output stage.

[0077] In Example 14, the subject of Examples 12-13 indicates that if the first control input specifies a maximum bias current for the output transistors of the driver circuit, the second control input specifies a minimum feedback current or a feedback current of zero in order to maintain the specified impedance characteristic for the output stage.

[0078] In Example 15, the subject of Examples 12-14 is as follows: the first control input is a function of the second control input, or the second control input is a function of the first control input.

[0079] In Example 16, the subject of Examples 12-15 exhibits the following: the output stage circuit has an output resistance coupled between the DUT node and an output node of the output transistors.

[0080] In Example 17, the subject of Example 16 has the following: the class AB driver circuit has a push-pull output stage which has the output transistors, wherein the output transistors have a first array of NPN transistors coupled at the output node to a second array of PNP transistors.

[0081] In Example 18, the subject of Examples 16-17 features the following: the class AB driver circuit has a push-pull output stage comprising the output transistors, wherein the output transistors have a first transistor coupled to the output node via a first degeneration resistor and a second transistor coupled to the output node via a second degeneration resistor.

[0082] In Example 19, the subject of Examples 16-18 comprises the following: base resistors, each coupled to the base terminals of the output transistors, the base resistors being configured to receive the feedback current from the feedback control.

[0083] In Example 20, the subject of Examples 12-19 exhibits the following: the bias current control has a scaled-down replica of the class AB driver circuit.

[0084] In Example 21, the subject of Examples 12-20 is: a user interface designed to receive the first control input and the second control input from a user.

[0085] In Example 22, the subject of Examples 12-21 has the following: the output stage, configured to provide, at the DUT node, a characteristic 50-ohm impedance.

[0086] Example 23 is a method for adjusting a characteristic output impedance of an output stage of a pin driver circuit, wherein the method comprises: receiving a first control signal input at a bias current controller and, in response thereto, supplying a bias current to transistors in the output stage of the pin driver circuit, wherein a magnitude of the bias current corresponds to a value of the first control signal input; and receiving a second control signal input at a feedback controller and, in response thereto, supplying a feedback current to respective base terminals of the transistors in the output stage of the pin driver circuit, wherein a magnitude of the feedback current corresponds to a value of the second control signal input; wherein the characteristic output impedance corresponds to an impedance at an output node coupled to emitter terminals of the transistors in the output stage.

[0087] In Example 24, the subject of Example 23 comprises: supplying the bias current to transistors in the output stage of the pin driver circuit, comprising supplying a bias current to transistors of a class AB push-pull output stage.

[0088] In Example 25, the subject of Examples 23-24 is as follows: providing the feedback current at the respective base terminals of the transistors, comprising supplying the feedback current to resistors coupled to the respective base terminals of the transistors.

[0089] In Example 26, the subject of Examples 23-25 ​​is as follows: providing the bias current using a current source that has a scaled replica of the output stage.

[0090] In Example 27, the subject of Examples 23-26 is as follows: receiving information about the magnitude of an output current signal at the output node and, in response to this, changing the value of the first control signal input and / or the value of the second control signal input to maintain the characteristic output impedance.

[0091] Example 28 is at least one machine-readable medium containing instructions which, when executed by a processing circuit arrangement, cause the processing circuit arrangement to perform operations to implement one of Examples 1-27.

[0092] Example 29 is an establishment comprising means to implement one of Examples 1-27.

[0093] Example 30 is a system for implementing one of Examples 1-27.

[0094] In this document, the terms "a" or "an" are used, as is customary in patent documents, to include one or more than one, irrespective of any other instances or uses of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive "or", so that "A or B" includes "A but not B", "B but not A", and "A and B" unless otherwise specified. In this document, the terms "including" and "in which" are used as the equivalents of the respective terms "including" and "whereby" in plain English.

[0095] In the following claims, the terms "including" and "comprising" are open expressions, meaning that a system, device, article, composition, formulation, or process that includes elements in addition to those listed under such a term in a claim will still be considered to fall within the scope of protection of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as designations and are not intended to be interpreted as numerical specifications for their objects.

[0096] The process examples described here may be at least partially machine- or computer-implemented. Some examples may include a computer-readable or machine-readable medium encoded with instructions capable of configuring an electronic device to perform procedures or circuit operations, or circuit configuration instructions, as described in the examples above. An implementation of such procedures may include code such as microcode, assembly language code, code of a higher-level programming language, or the like. Such code may contain computer-readable instructions for performing various procedures. The code may form parts of computer program products.Furthermore, in one example, the code can be stored tangibly on one or more tangible, non-volatile, or persistent computer-readable media, such as during execution or at other times. Examples of such tangible computer-readable media include hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cartridges, memory cards or flash drives, random access memory (RAM), read-only memory (ROM), and the like.

[0097] According to one aspect, a test system can supply a test signal to or receive a test signal from a device under test (DUT) via a first signal path. The test system can be configured to provide a stable impedance (e.g., 50 ohms) at the DUT interface. In one example, the stable impedance comprises a physical polysilicon resistor in series with an output stage of a driver circuit of the test system. The output stage impedance can be a function of the incremental impedance of transistors in a push-pull output circuit. In another example, a control loop is provided to change a bias condition for the transistors to adjust the output stage impedance.

Claims

[1] Pin driver output stage (800) which includes the following: a push-pull output stage circuit (806) comprising output transistors (808, 810) configured to support bidirectional current signals at an output node (802); a bias current control (302) configured to adjust a bias current supplied to the output transistors (808, 810) of the push-pull output stage circuit (806) to match an impedance characteristic of the push-pull output stage circuit (806) at the output node (802); a first and a second resistor (Rbasep, Rbasen) which are coupled to the respective base terminals of the output transistors (808, 810); and a feedback control (706) configured to selectively supply a feedback current signal to the first and second resistors (Rbasep, Rbasen) to match the impedance characteristic of the push-pull output stage circuit (806) at the output node (802). [2] Pin driver output stage (800) according to claim 1, wherein the impedance characteristic of the push-pull output stage circuit (806) at the output node (802) is essentially independent of the magnitude of the bidirectional current signals at the output node (802). [3] Pin driver output stage (800) according to claim 1 or 2, wherein: the feedback current signal is applied to the first and second resistors (Rbasep, Rbasen) to provide an initial voltage; The bidirectional current signals apply a second voltage to an incremental impedance of the output transistors (808, 810); and The impedance characteristic of the push-pull output stage circuit (806) at the output node (802) is essentially independent of the magnitude of the bidirectional current signals at the output node (802) if the first and second voltages have the same magnitude. [4] Pin driver output stage (800) according to one of the preceding claims, wherein a magnitude of the feedback current signal is a function of the magnitude of the current signal at the output node (802) and an output impedance tuning parameter. [5] Pin driver output stage (800) according to one of the preceding claims, comprising a data input configured to receive an output impedance tuning parameter which specifies a magnitude of the bias current and the magnitude of the feedback current signal. [6] Pin driver output stage (800) according to one of the preceding claims, wherein the bias current control (302) is configured to change the magnitude of the bias current in coordination with a change in the magnitude of the feedback current signal. [7] Pin driver output stage (800) according to one of the preceding claims, wherein the bias current control (302) comprises a scaled-down emulation circuit of the push-pull output stage circuit (806). [8] Pin driver output stage (800) according to one of the preceding claims, wherein the feedback control (706) comprises a first folded cascode amplifier circuit which supplies a first feedback current signal to the first resistor (Rbasep) and a second folded cascode amplifier circuit which supplies a second feedback current signal to the second resistor (Rbasen). [9] Pin driver output stage (800) according to any one of the preceding claims, comprising: a fixed-value polysilicon resistor (Rpoly) coupled between the output node (802) of the push-pull output stage circuit (806) and a DUT node (130) of a device under test; and Degeneration resistors coupled between the emitter terminals of the output transistors (808, 810) and the output node (802). [10] Test system (100) comprising the following: a comparator circuit (122) coupled to a node of a device to be tested, hereinafter referred to as DUT node (130); an active load (108) coupled to the DUT node (130); and a push-pull output stage circuit (806) coupled to the DUT node (130), wherein the push-pull output stage circuit (806) is configured to provide a predetermined impedance characteristic at the DUT node (130) which is essentially invariant over a predetermined range of DUT currents, wherein the push-pull output stage circuit (806) has the following features: a class AB driver circuit (102); a bias current control (302) configured to provide, based on a first control input, a bias current for output transistors (808, 810) of the class-AB driver circuit (102); and a feedback control (706) configured to provide, based on a second control input, a feedback current at respective base terminals of the output transistors (808, 810) of the class AB driver circuit (102). [11] Test system (100) according to claim 10, wherein, if the first control input specifies a minimum bias current for the output transistors (808, 810) of the class AB driver circuit (102), the second control input specifies a maximum feedback current in order to maintain the predetermined impedance characteristic for the push-pull output stage circuit (806). [12] Test system (100) according to claim 10 or 11, wherein, if the first control input specifies a maximum bias current for the output transistors (808, 810) of the class AB driver circuit (102), the second control input specifies a minimum feedback current or a feedback current of zero in order to maintain the predetermined impedance characteristic for the push-pull output stage circuit (806). [13] Test system (100) according to one of claims 10 to 12, wherein the push-pull output stage circuit (806) has an output resistor coupled between the DUT node (130) and an output node (802) of the output transistors (808, 810), wherein the class AB driver circuit (102) has a push-pull output stage comprising the output transistors (808, 810), and wherein the output transistors (808, 810) comprise a first array of NPN transistors coupled at the output node (802) to a second array of PNP transistors. [14] Test system (100) according to one of claims 10 to 12, wherein the output stage circuit (806) has an output resistor coupled between the DUT node (130) and an output node (802) of the output transistors (808, 810), wherein the class AB driver circuit (102) has a push-pull output stage circuit (806) comprising the output transistors (808, 810), and wherein the output transistors (808, 810) comprise a first transistor coupled to the output node (802) via a first degeneration resistor, and a second transistor coupled to the output node (802) via a second degeneration resistor. [15] Test system (100) according to one of claims 10 to 14, comprising base resistors which are each coupled to base terminals of the output transistors (808, 810), wherein the base resistors are configured to receive the feedback current from the feedback control (706), wherein the output stage circuit (806) has an output resistor which is coupled between the DUT node (130) and an output node (802) of the output transistors (808, 810). [16] Method (900) for matching a characteristic output impedance of a push-pull output stage circuit (806) of a pin driver output stage (800), wherein the method comprises: Receiving an initial control signal input at a bias current controller (302) and, in response, supplying a bias current to output transistors (808, 810) in the push-pull output stage circuit (806) of the pin driver output stage (800), wherein a magnitude of the bias current corresponds to a value of the initial control signal input; and Receiving a second control signal input at a feedback control (706) and, in response thereto, providing a feedback current at respective base terminals of the output transistors (808, 810) in the push-pull output stage circuit (806) of the pin driver output stage (800), wherein a magnitude of the feedback current corresponds to a value of the second control signal input; wherein the characteristic output impedance corresponds to an impedance at an output node (802) coupled to emitter terminals of the output transistors (808, 810) in the push-pull output stage circuit (806). [17] Method according to claim 16, wherein supplying the bias current to output transistors (808, 810) in the push-pull output stage circuit (806) of the pin driver output stage (800) comprises supplying a bias current to transistors of a class AB push-pull output stage. [18] Method according to claim 16 or 17, wherein the provision of the feedback current at the respective base terminals of the output transistors (808, 810) comprises supplying the feedback current to resistors coupled to the respective base terminals of the output transistors (808, 810). [19] Method according to any one of claims 16 to 18, wherein providing the bias current comprises using a current source (816) which has a scaled replica of the push-pull output stage circuit (806). [20] Method according to any one of claims 16 to 19, comprising receiving information about the magnitude of an output current signal at the output node (802) and, in response thereto, changing the value of the first control signal input and / or the value of the second control signal input to maintain the characteristic output impedance.

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