DISPLAY DEVICE

Abstract

The present disclosure provides a display device (100) comprising a first passivation layer (PAS1), comprising a first insulating layer (PAS13) and a second insulating layer (PAS14) arranged on a section of the first insulating layer (PAS13), and a second passivation layer (PAS2) formed such that it covers the first passivation layer (PAS1), and which offers the advantage of preventing the ingress of oxygen or moisture into an encapsulation layer.

Description

TECHNICAL FIELD

[0001] The present application relates to electronic devices having displays, and particularly, for example without limitation, relates to display devices capable of preventing moisture or oxygen from penetrating an encapsulation layer. BACKGROUND

[0002] With the development of an information-oriented society, the demand for display devices for displaying images has increased. Recently, various types of display devices, such as liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), and the like, have been developed and widely used.

[0003] A display panel included in a display device may have a display area and a non-display area.

[0004] The display area of ​​the display panel may have a through-hole, and an optical device may be arranged below the through-hole.

[0005] The description provided in the discussion of the related art section should not be considered prior art simply because it is mentioned in or associated with that section. The discussion of the related art section may contain information describing one or more aspects of the subject technology, and the description in that section does not limit the invention. OVERVIEW

[0006] In a case where such a through hole is formed in a display panel for installing an optical device in a display device, the display device may be affected by the intrusion of moisture into the display panel.

[0007] To solve this problem, one or more aspects of the present disclosure may provide a display device capable of preventing moisture or oxygen from penetrating an encapsulation layer.

[0008] One or more aspects of the present disclosure may provide a display device having an encapsulation layer capable of preventing moisture ingress during the process of forming a through-hole.

[0009] One or more aspects of the present disclosure may provide a display device having a second encapsulation layer disposed on a first encapsulation layer that is an inorganic layer, has high spreadability, and is capable of preventing moisture or oxygen from penetrating the first encapsulation layer.

[0010] One or more aspects of the present disclosure may provide a display device capable of preventing moisture or oxygen from entering an encapsulation and thereby operating at low power.

[0011] In accordance with one aspect of the present disclosure, a display device according to claim 1 is provided. Further embodiments are described in the dependent claims. In accordance with one or more exemplary embodiments of the present disclosure, a display device may be provided comprising a substrate having a through-hole and a surrounding region surrounding the through-hole, a first passivation layer disposed on the substrate and comprising a first insulating layer and a second insulating layer disposed on a portion of the first insulating layer, and a second passivation layer formed to cover the first passivation layer.

[0012] In one or more aspects, the substrate may include a first substrate and a second substrate with an intermediate insulating layer disposed therebetween.

[0013] In one or more aspects, the second passivation layer may be configured to cover a side surface of the second insulating layer and a portion of a top surface of the first insulating layer.

[0014] In one or more aspects, the second passivation layer may be arranged in a step structure.

[0015] In one or more aspects, the first passivation layer may be arranged in a step structure.

[0016] In one or more aspects, the first passivation layer may be arranged to be spaced apart from the via, and the second passivation layer may be arranged adjacent to the via.

[0017] In one or more aspects, the second insulating layer may include a groove region in which a plurality of grooves are arranged.

[0018] In accordance with one or more aspects of the present disclosure, a display device capable of preventing moisture or oxygen from penetrating an encapsulation layer may be provided.

[0019] In accordance with one or more aspects of the present disclosure, a display device may be provided having an encapsulation layer capable of preventing moisture from entering during the process of forming a through-hole.

[0020] In accordance with one or more aspects of the present disclosure, a display device may be provided that includes a second encapsulation layer disposed on a first encapsulation layer that is an inorganic layer, has high spreadability, and is capable of preventing moisture or oxygen from penetrating into the first encapsulation layer.

[0021] In accordance with one or more aspects of the present disclosure, a display device capable of preventing moisture or oxygen from penetrating an encapsulation layer and thereby being driven at low power may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are provided to provide a further understanding of the disclosure and are incorporated in and constitute a part of the disclosure, illustrate aspects of the disclosure and, together with the description, serve to explain principles of the disclosure. In the drawings: Fig. 1A, Fig. 1B and Fig. 1C are plan views illustrating an exemplary display device according to aspects of the present disclosure; Fig. 2 illustrates an exemplary system configuration of the display device according to aspects of the present disclosure; Fig. 3 is an exemplary cross-section of a display area in the display device according to aspects of the present disclosure; Fig. 4 is an enlarged plan view illustrating an exemplary structure of an optical portion of the display panel in the display device according to aspects of the present disclosure; Fig. Fig. 5 is a cross-sectional view taken along a line II' in the optical region of the Fig. 4; Fig. 6 and Fig. 7 are cross-sectional views along a line II' in the optical region of the Fig. 4; Fig. 8 to Fig. 11 are cross-sectional views showing a boundary region between a contact hole and a surrounding region in Fig. 4 represent; and Fig. 12 and Fig. 13 are plan views showing a marginal area between the contact hole and the surrounding area in Fig. 4 represent.

[0023] Throughout the drawings and detailed description, unless otherwise noted, the same drawing reference symbols should be understood to refer to the same elements, features, and structures. The sizes, lengths, and thicknesses of layers, regions, and elements, as well as their representation, may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, the structures, embodiments, implementations, methods, and operations described herein are not limited to the specific example or examples set forth herein and may be changed as is known in the art unless otherwise noted. Like reference numerals refer to like elements throughout unless otherwise noted. Names of the respective elements used in the following explanations were chosen only for convenience in preparing the application and may therefore differ from those used in actual products.Advantages and features of the present disclosure and the methods of implementation are illustrated by the following exemplary embodiments, which are described with reference to the accompanying drawings. However, the present disclosure may be embodied in various forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be sufficiently thorough and complete to aid those skilled in the art to fully understand the scope of the present disclosure. Moreover, the protected scope of the present disclosure is defined by the claims and their equivalents.In the following description, when the detailed description of the relevant known function or configuration may unnecessarily obscure aspects of the present disclosure, a detailed description of such known function or configuration may be omitted. The shapes, sizes, ratios, angles, numbers, and the like illustrated in the drawings to describe various exemplary embodiments of the present disclosure are merely examples. Therefore, the present disclosure is not limited to the illustrations in the drawings. When the terms "comprise," "having," "include," "contain," "arrange," "consist," "formed of," and the like are used, one or more other elements may be added unless the term, such as "only," is used.An element described in the singular form is intended to include a plurality of elements and vice versa, unless the context clearly indicates otherwise.

[0025] When describing a temporal relationship, for example when describing the temporal sequence as "after", "subsequent", "next", and "before", a case that is not continuous may be included unless "just", "immediate", or "direct" is used.

[0026] Although the terms "first," "second," A, B, (a), (b), and the like may be used herein to describe various elements, these elements should not be interpreted as being limited by these terms, as they are not used to define a particular order or ranking. These terms are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the present disclosure.

[0027] It should be understood that the term "at least one" encompasses all combinations involving any element. For example, "at least one of a first element, a second element, and a third element" can include all combinations of two or more elements selected from the first, second, and third elements, as well as each individual element of the first, second, and third elements.

[0028] When it is mentioned that a first element is "connected or coupled", "touches or overlaps", etc., to a second element, this should be interpreted to mean that not only the first element may be "directly connected or coupled" to the second element, or "directly touches or overlaps", but also a third element may be "interposed" between the first and second elements, or the first and second elements may be "connected or coupled", "touch or overlap", etc., to each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "touch or overlap", etc., to each other.

[0029] When describing positional relationships, for example, when describing the positional relationship between two parts using terms such as "on," "over," "under," "above," "beneath," "next to," "beside," or the like, one or more other parts may be disposed between the two parts unless a more limiting term such as "immediate," "direct," or "close" is used. For example, when one element or layer is disposed "on top of" another element or layer, a third element or layer may be interposed therebetween. Furthermore, the terms "left," "right," "top," "bottom," "downward," "upward," "upper," "lower," and the like refer to any frame of reference.

[0030] Furthermore, whenever any dimensions, relative sizes, etc. are mentioned, it should be noted that numerical values ​​for elements or characteristics, or corresponding information (e.g., level, range, etc.), may have a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no corresponding description is provided. Furthermore, the term "may" includes all meanings of the term "can."

[0031] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Fig. 1A, Fig. 1B and Fig. 1C are plan views illustrating an exemplary display device 100 according to aspects of the present disclosure.

[0033] Referring to the Fig. 1A, Fig. 1B and Fig. 1C, in one or more exemplary embodiments, the display device 100 may include a display panel 110 for displaying an image, one or more optical electronic devices (11 and / or 12), and the like. Here, an optical electronic device may be referred to as a light detector, a light receiver, or a light-sensitive device. An optical electronic device may include one or more of a camera, a camera lens, a sensor, a sensor for detecting images, or the like.

[0034] The display panel 110 may have a display area AA in which an image can be displayed and a non-display area NA in which no image is displayed.

[0035] A plurality of subpixels may be arranged in the display area AA, and a plurality of types of signal lines for driving the plurality of subpixels may be arranged therein, but are not limited to this.

[0036] The non-display area NA may refer to an area outside the display area AA. Multiple types of signal lines may be arranged in the non-display area NA, and multiple types of drive circuits may be connected thereto. At least a portion of the non-display area NA may be curved so as not to be visible from the front of the display device 100, or it may be covered by a housing or shell (not shown) of the display device 100. The non-display area NA may also be referred to as an edge area or a bezel area.

[0037] Referring to Fig. 1A, Fig. 1B and Fig. 1C, in one or more aspects of the display device 100, one or more optical electronic devices (11 and / or 12) may be manufactured independently of and installed within the display panel 110 and may be disposed below or in a lower portion of the display panel 110 (an opposite side of a viewing surface thereof), but are not limited thereto. Alternatively, one or more optical electronic devices (11 and / or 12) may be formed integrally with the display panel 110.

[0038] Light may enter the front side (the viewing surface) of the display panel 110, pass through the display panel 110, and reach one or more optical electronic devices (11 and / or 12) located below or in the lower portion of the display panel 110 (the opposite side of the viewing surface).

[0039] The one or more optical electronic devices (11 and / or 12) may be devices capable of receiving or detecting light passing through the display panel 110 and performing a predetermined function based on the received light. For example, the one or more optical electronic devices (11 and / or 12) may include one or more of the following: a device for capturing images, such as a camera (an image sensor) and / or the like; or a sensor, such as a proximity sensor, an illuminance sensor, and / or the like.

[0040] Referring to Fig. 1A, Fig. 1B and Fig. 1C, the display panel 110 may, in one or more aspects, include, but is not limited to, one or more optical areas (OA1 and / or OA2). As in the example of Fig. 1A, the display panel 110 may include the first optical area OA1. As in the example of Fig. 1B, the display panel 110 may include the first optical region OA1 and the second optical region OA2.

[0041] With reference to Fig. 1A, Fig. 1B and Fig. 1C, the one or more optical regions (OA1 and / or OA2) may be one or more regions that overlap the one or more optical electronic devices (11 and / or 12). For example, the optical region OA1 is a region that overlaps the first optical electronic device 11, and the optical region OA2 is a region that overlaps the second optical electronic device 12.

[0042] As in the example of Fig. As shown in Figure 1A, the display area AA may be arranged outside the first optical area OA1. The display area AA may be configured to surround the first optical area OA1. For example, at least a portion of the first optical area OA1 may overlap the first optical electronic device 11. Fig. 1A illustrates a front view and a side view of the exemplary display device according to aspects of the present disclosure.

[0043] As in the example of Fig. 1B, the display area AA may be arranged outside the first optical area OA1 and the second optical area OA2. The display area AA may be configured to surround the first optical area OA1 and the second optical area OA2. Referring to Fig. 1B, a portion of the display area AA may be present between the first optical area OA1 and the second optical area OA2. In this implementation, at least a portion of the first optical area OA1 may overlap the first optical electronic device 11, and at least a portion of the second optical area OA2 may overlap the second optical electronic device 12. Fig. 1B illustrates a front view, a left side view, and a right side view of the exemplary display device according to aspects of the present disclosure.

[0044] As in the example of Fig. 1C, the display area AA may be arranged outside the first optical area OA1 and the second optical area OA2. The display area AA may be configured to surround the first optical area OA1 and the second optical area OA2. Referring to Fig. 1C, the display area AA may not be present between the first optical area OA1 and the second optical area OA2. For example, the first optical area OA1 and the second optical area OA2 may touch each other (e.g., directly touch), but are not limited thereto. In this implementation, at least a portion of the first optical area OA1 may overlap the first optical electronic device 11, and at least a portion of the second optical area OA2 may overlap the second optical electronic device 12. Fig. 1C illustrates a front view, a left side view, and a right side view of the exemplary display device according to aspects of the present disclosure.

[0045] In one or more aspects, it is required that the one or more optical regions (OA1 and / or OA2) be formed with a light-transmissive structure. For example, in order for light to pass through the one or more optical electronic devices (11 and / or 12), it may be required that the one or more optical regions (OA1 and / or OA2) have a light-transmissive structure.

[0046] In one or more aspects, the one or more optical electronic devices (11 and / or 12) that need to receive light may be exposed in the front side (viewing surface) of the display panel 110 or the display device 100, but are not limited thereto.

[0047] It should be noted that although the one or more optical electronic devices (11 and / or 12) are devices that need to receive light, the one or more optical electronic devices (11 and / or 12) may be arranged on the back of the display panel 110 (for example, on an opposite side of the viewing surface thereof) and may thereby receive light that has passed through the display panel 110.

[0048] In one example, the first optical electronic device 11 may be, for example, a camera, and the second optical electronic device 12 may be, for example, but not limited to, a sensor. The sensor may be a proximity sensor, an illuminance sensor, an infrared sensor, and / or the like. For example, the camera may be a camera lens, an image sensor, or a unit including at least one of the camera lens and the image sensor, and the sensor may be an infrared sensor capable of detecting infrared light.

[0049] In another example, the first optical electronic device 11 may be a sensor, for example, and the second optical electronic device 12 may be a camera, for example. For example, the camera may be a camera lens, an image sensor, or a unit including at least one of the camera lens and the image sensor, and the sensor may be an infrared sensor capable of detecting infrared light.

[0050] For convenience of description, discussions are provided below based on examples where the first optical electronic device 11 is a camera and the second optical electronic device 12 is a sensor, but are not limited thereto. However, it should be understood that the scope of the present disclosure includes embodiments where the first optical electronic device 11 is the sensor and the second optical electronic device 12 is the camera. The camera may, for example, be a camera lens, an image sensor, or a unit including at least one of the camera lens and the image sensor.

[0051] In an example where the first optical electronic device 11 is a camera, this camera may be arranged on the back (e.g., below or in a lower portion) of the display panel 110 and may be a front-facing camera capable of capturing objects or images in a front direction of the display panel 110. Accordingly, a user may capture an image or an object through the first optical electronic device 11, such as a camera, while looking at the viewing surface of the display panel 110.

[0052] In the examples of Fig. 1A, Fig. 1B and Fig. 1C, the first optical region OA1 may have various shapes, such as a circle, an ellipse, a square, a hexagon, an octagon, or the like, without being limited thereto. In the examples of Fig. 1B and Fig. 1C, the second optical region OA2 may have various shapes, such as, but not limited to, a circle, an ellipse, a square, a hexagon, an octagon, or the like. The first optical region OA1 and the second optical region OA2 may have the same or substantially or nearly the same shape, or they may have different shapes.

[0053] Referring to Fig. 1C, in the example where the first optical region OA1 and the second optical region OA2 touch each other (e.g., directly touch each other), the entire optical region including the first optical region OA1 and the second optical region OA2 may also have various shapes, such as, but not limited to, a circle, an ellipse, a square, a hexagon, an octagon, or the like.

[0054] In the following, to simplify the descriptions regarding the shapes of the optical regions (OA1 and OA2), it is assumed that each of the first optical region OA1 and the second optical region OA2 has a circular shape. However, it should be understood that the scope of the present disclosure includes examples in which at least one of the first optical region OA1 and the second optical region OA2 has a shape other than a circular shape, such as, but not limited to, an ellipse, a quadrilateral, a hexagon, an octagon, or the like.

[0055] In one or more aspects, when an implementation in which the optical regions (OA1 and OA2) are surrounded by the display region AA is applied to the display device 100, this type of display device 100 may be referred to as a display applying a hole-in-active area (HiAA) technology.

[0056] In examples where this HiAA technology is applied to the display device 100, no camera exposure notch may be formed in the display panel 110. To apply this technology, the display device 100 may have a camera hole formed for camera exposure.

[0057] Since no notch needs to be formed in the display panel 110, the display device 100 can have further advantages in that the size of the bezel area is reduced and the degree of freedom in design is improved because such restrictions on the design are eliminated.

[0058] Fig. 2 illustrates an exemplary system configuration of the display device 100 according to aspects of the present disclosure.

[0059] Referring to Fig. 2, the display device 100 may include the display panel 110 and a display drive circuit as components for displaying one or more images.

[0060] The display drive circuit may be a circuit for driving the display panel 110 and may include a data drive circuit 220, a gate drive circuit 230, a display controller 240, and other circuit components.

[0061] The display panel 110 may include a display area AA in which an image can be displayed, and a non-display area NA in which no image is displayed. The non-display area NA may be an area outside the display area AA and may also be referred to as an edge area or a bezel area. All or part of the non-display area NA may be an area visible from the front of the display device 100, a area that is curved and not visible from the front of the display device 100, or an area covered by a housing or case (not shown) of the display device 100.

[0062] The display panel 110 may include, but is not limited to, a substrate SUB and a plurality of subpixels SP arranged on the substrate SUB. The display panel 110 may further include various types of signal lines for driving the plurality of subpixels SP. Likewise, the display panel 110 may include one or more optical regions (OA1 and / or OA2).

[0063] In one or more aspects, the display device 100 may be a liquid crystal display (LCD), a plasma display (PDP), a field emission display (FED), or the like, or a self-emissive display device in which light is emitted from the display panel 110 itself, such as an organic light-emitting display (OLED) and a micro-LED (micro light-emitting diode) display. In the example where the display device 100 is a self-emissive display, each of the plurality of subpixels SP may include a light-emitting element.

[0064] For example, the display device 100 according to aspects of the present disclosure may be an organic light-emitting display device in which light-emitting elements ED are implemented using organic light-emitting diodes (OLEDs). In another example, the display device 100 according to aspects of the present disclosure may be an inorganic light-emitting display device in which light-emitting elements are implemented using light-emitting diodes based on inorganic material. In another example, the display device 100 according to aspects of the present disclosure may be a quantum dot display device implemented with quantum dots, which are self-emissive semiconductor crystals, as light-emitting elements. However, the present disclosure is not limited thereto.

[0065] The structure of each of the plurality of subpixels SP may be configured or configured differently according to the types of display devices 100. In an example where display device 100 is a self-emissive display device having self-emissive subpixels SP, each subpixel SP may include a self-emissive light-emitting element, one or more transistors, one or more capacitors, and the like.

[0066] The different types of signal lines may include, for example, a plurality of data lines DL for transmitting data signals (which may be referred to as data voltages or image signals), a plurality of gate lines GL for transmitting gate signals (which may be referred to as scanning signals), and the like.

[0067] The plurality of data lines DL and the plurality of gate lines GL may overlap each other. Each of the plurality of data lines DL may be configured to extend in a first direction. Each of the plurality of gate lines GL may be configured to extend in a second direction different from the first direction.

[0068] For example, the first direction may be, but is not limited to, the column direction or vertical direction, and the second direction may be, the row direction or horizontal direction. In another example, the first direction may be, the row direction or horizontal direction, and the second direction may be, the column direction or vertical direction.

[0069] The data drive circuit 220 may be a circuit for driving the plurality of data lines DL and may supply data signals to the plurality of data lines DL. The gate drive circuit 230 may be a circuit for driving a plurality of gate lines GL and may supply gate signals to the plurality of gate lines GL.

[0070] The display control device 240 may be a device for controlling the data drive circuit 220 and the gate drive circuit 230, and may control drive timings for the plurality of data lines DL and drive timings for the plurality of gate lines GL.

[0071] Specifically, the display control device 240 may supply a data drive control signal DCS to the data drive circuit 220 for controlling the data drive circuit 220, and a gate drive control signal GCS to the gate drive circuit 230 for controlling the gate drive circuit 230.

[0072] The display controller 240 may receive input image data from a host system 250 and supply image data DATA to the data drive circuit 220 based on the input image data.

[0073] The data drive circuit 220 may supply data signals to the plurality of data lines DL according to the drive timing of the display control device 240.

[0074] The data drive circuit 220 may receive digital image data DATA from the display controller 240, convert the received image data DATA into analog data signals, and output the resulting analog data signals to the plurality of data lines DL.

[0075] The gate drive circuit 230 may supply gate signals to the plurality of gate lines GL according to the timing of the display control device 240. The gate drive circuit 230 may receive a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage, along with various gate drive control signals GCS, generate gate signals, and supply the generated gate signals to the plurality of gate lines GL.

[0076] In one or more aspects, the data drive circuit 220 may be connected to the display panel 110 using an adhesive tape automated bonding (TAB) technique, or connected to a conductive pad, such as a bonding pad, of the display panel 110 using a chip-on-glass (COG) technique or a chip-on-panel (COP) technique, or connected to the display panel 110 using a chip-on-film (COF) technique, but not limited thereto.

[0077] In one or more aspects, the gate drive circuit 230 may be connected to the display panel 110 using the tape automated bonding (TAB) technique, or connected to a conductive pad, such as a bonding pad, of the display panel 110 using the chip-on-glass (COG) technique or the chip-on-panel (COP) technique, or connected to the display panel 110 using the chip-on-film (COF) technique. In one or more aspects, the gate drive circuit 230 may be disposed in the non-display area NA of the display panel 110 using, but is not limited to, a gate-in-panel (GIP) technique. Alternatively, the gate drive circuit 230 may be disposed in the display area AA of the display panel 110. The gate drive circuit 230 may be disposed on the substrate SUB or connected to the substrate SUB.In an example where the gate drive circuit 230 is implemented using the GIP technique, the gate drive circuit 230 may be arranged in the non-display area NA of the substrate SUB. In an example where the gate drive circuit 230 is implemented using the chip-on-glass (COG) technique, the chip-on-film (COF) technique, or the like, the gate drive circuit 230 may be connected to the substrate SUB.

[0078] In one or more aspects, at least one of the data drive circuit 220 and the gate drive circuit 230 may be arranged in the display area AA of the display panel 110. For example, at least one of the data drive circuit 220 and the gate drive circuit 230 may be configured not to overlap the subpixels SP, or may be configured to overlap one or more or all of the subpixels SP, or at least respective one or more portions of one or more subpixels, but is not limited thereto.

[0079] The data drive circuit 220 may be disposed on and / or electrically connected to only one side or portion (e.g., a top edge or a bottom edge) of the display panel 110, but is not limited thereto. In one or more aspects, the data drive circuit 220 may be disposed on and / or electrically connected to two sides or portions (e.g., a top edge and a bottom edge) of the display panel 110, but is not limited thereto, or disposed on and / or electrically connected to at least two of four sides or portions (e.g., the top edge, the bottom edge, a left edge, and a right edge) of the display panel 110, according to drive schemes, panel layout schemes, or the like.

[0080] The gate drive circuit 230 may be disposed on and / or electrically connected to one side or portion (e.g., a left edge or a right edge) of the display panel 110, but is not limited thereto. Likewise, the gate drive circuit 230 may be disposed on and / or electrically connected to at least two of four sides or portions (e.g., a top edge, a bottom edge, the left edge, and the right edge) of the panel 110, but is not limited thereto, according to drive schemes, panel layout schemes, or the like. For example, the gate drive circuit 230 may be disposed on and / or electrically connected to two sides or portions (e.g., a left edge and a right edge) of the panel 110, but is not limited thereto.

[0081] The display control device 240 may be implemented in a component separate from the data drive circuit 220 or integrated into the data drive circuit 220 and thus implemented in an integrated circuit.

[0082] The display controller 240 may be a timing controller used in typical display technology, or a control unit or device that can perform other control functions in addition to the function of the typical timing controller. In one or more example embodiments, the display controller 240 may be a control unit or device other than the timing controller, or circuitry or a component included in the control unit or device. The display controller 240 may be implemented with various circuits or electronic components, such as, but not limited to, an integrated circuit (IC), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a processor, and / or the like.

[0083] The display control device 240 may be mounted on a circuit board, a flexible circuit board, and / or the like, and electrically connected to the gate drive circuit 230 and the data drive circuit 220 through the circuit board, the flexible circuit board, and / or the like.

[0084] The display controller 240 may transmit and receive signals to and from the data drive circuit 220 via one or more predefined interfaces. Such interfaces may include, for example, a Low Voltage Differential Signaling (LVDS) interface, an Embedded Clock Point-to-Point (EPI) interface, a Serial Peripheral Interface (SPI) interface, and the like. Similarly, the display controller 240 may transmit and receive signals to and from the gate drive circuit 230 via one or more predefined interfaces.

[0085] In one or more aspects, to further provide a touch sensor function as well as an image display function, the display device 100 may further include at least one touch sensor and a touch detection circuit capable of detecting the occurrence of a touch event by a touch object such as a finger, a stylus, or the like, or detecting a corresponding touch location (or touch coordinates) by scanning the touch sensor and the like.

[0086] As an example, the touch detection circuitry may include, but is not limited to, a touch driver circuitry 260 capable of generating and providing touch detection data by driving and sensing the touch sensor, a touch controller 270 capable of detecting the occurrence of a touch event or the touch location (or touch coordinates) using the touch detection data, and one or more other components.

[0087] As an example, the touch sensor may include, but is not limited to, a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to the touch drive circuit 260.

[0088] The touch sensor may be implemented in the form of a touch panel outside the display panel 110 or formed integrally with the display panel 110. In the example where the touch sensor is implemented in the form of the touch panel outside the display panel 110, such a touch sensor may be referred to as an add-on type. In the example where the add-on type of touch sensor is arranged in the display device 100, the touch panel and the display panel 110 may be manufactured separately and combined in an assembly process. The add-on type of touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0089] In the example where the touch sensor is formed integrally with the display panel 110, the touch sensor may be formed on the substrate SUB during the process of manufacturing the display panel 110 together with signal lines and electrodes related to display driving.

[0090] The touch drive circuit 260 may supply a touch drive signal to at least one of a plurality of touch electrodes and may sample at least one of the plurality of touch electrodes to generate touch sensor data.

[0091] The touch detection circuit may perform touch detection. For example, the touch detection circuit may perform touch detection using, but is not limited to, a self-capacitance detection technique or a mutual capacitance detection technique.

[0092] In the example where the touch detection circuit performs touch detection by the self-capacitance detection technique, the touch detection circuit may perform touch detection based on a capacitance between each touch electrode and a touch object (e.g., a finger, a stylus, and the like).

[0093] According to the self-capacitance detection technique, each of a plurality of touch electrodes can serve as both a drive touch electrode and a detect touch electrode. Touch drive circuit 260 can drive all or one or more of the plurality of touch electrodes and sense all or one or more of the plurality of touch electrodes.

[0094] In the example where the touch detection circuit performs the touch detection by the mutual capacitance detection technique, the touch detection circuit may perform the touch detection based on a capacitance between touch electrodes.

[0095] According to the mutual capacitance detection technique, a plurality of touch electrodes can be divided into drive touch electrodes and detection touch electrodes. The touch drive circuit 260 can drive the drive touch electrodes and sense the detection touch electrodes.

[0096] The touch drive circuit 260 and the touch control device 270 included in the touch detection circuit may be implemented in separate devices or in a single device, but are not limited thereto. Furthermore, the touch drive circuit 260 and the data drive circuit 220 may be implemented in separate devices or in a single device, but are not limited thereto.

[0097] The display device 100 may further include a power supply circuit for supplying various types of power to the display drive circuit and / or the touch detection circuit.

[0098] In some aspects, the display device 100 may be, but is not limited to, a mobile terminal, such as a notebook computer, a smartphone, a tablet, or the like, or a monitor, a television (TV), or the like. Such devices may be configured in various types, sizes, and shapes. The display device 100 according to aspects of the present disclosure is not so limited and may include various types, sizes, and shapes of display devices configured to display information or images.

[0099] Fig. 3 is an exemplary cross-sectional view of a portion of the display area AA of the display panel 110 according to aspects of the present disclosure.

[0100] Referring to Fig. 3, a substrate SUB may be arranged at the lower end of the display panel 110. For example, the substrate SUB may include a first substrate SUB1, an interlayer insulating layer IPD, and a second substrate SUB2. The interlayer insulating layer IPD may be interposed between the first substrate SUB1 and the second substrate SUB2. As shown in Fig. As shown in Figure 3, the interlayer insulating layer IPD may be disposed on the first substrate SUB1, and the second substrate SUB2 may be disposed on the interlayer insulating layer IPD, but is not limited thereto. Since the substrate SUB includes the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2, the substrate SUB may prevent or reduce the intrusion of moisture or oxygen into the display panel 110. The first substrate SUB1 and the second substrate SUB2 may be, for example, polyimide (PI) substrates, but are not limited thereto. The first substrate SUB1 may be referred to as a first primary PI substrate, and the second substrate SUB2 may be referred to as a second PI substrate.

[0101] With reference to Fig. 3, various types of structures (ACT, SD1, GATE) for forming one or more transistors, such as a drive transistor DRT and the like, various types of insulating layers (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PASO) and various types of metal structures (TM, GM, ML1, ML2) may be arranged on or above the substrate SUB.

[0102] Referring to Fig. 3, a multi-buffer layer MBUF may be arranged on the second substrate SUB2, and a first active buffer layer ABUF1 may be arranged on the multi-buffer layer MBUF.

[0103] A first metal layer ML1 and a second metal layer ML2 may be disposed on the first active buffer layer ABUF1. For example, the first metal layer ML1 and the second metal layer ML2 may be light-shielding layers LS for shielding light.

[0104] A second active buffer layer ABUF2 can be arranged on the first metal layer ML1 and the second metal layer ML2. In particular, the second active buffer layer ABUF2 can be arranged on the first active buffer layer ABUF1, the first metal layer ML1, and the second metal layer ML2. The active layer ACT of a drive transistor DRT can be arranged on the second active buffer layer ABUF2.

[0105] A gate insulating layer Gl may be formed to cover the active layer ACT. Specifically, the gate insulating layer Gl may be formed to cover the second active buffer layer ABUF2 and the active layer ACT.

[0106] The gate electrode GATE of the drive transistor DRT can be patterned and arranged on the gate insulating layer Gl. In one aspect, a gate material layer GM can be arranged on the gate insulating layer Gl together with the gate electrode GATE of the drive transistor DRT, at a location different from a location where the drive transistor DRT is arranged.

[0107] A first interlayer insulating layer ILD1 may be formed to cover the gate electrode GATE and the gate material layer GM. In particular, the first interlayer insulating layer ILD1 may be formed to cover the gate insulating layer GI, the gate electrode GATE, and the gate material layer GM. A metal pattern TM may be patterned and disposed on the first interlayer insulating layer ILD1. The metal pattern TM may be disposed at a location different from the location where the drive transistor DRT is formed. A second interlayer insulating layer ILD2 may be formed to cover the metal pattern TM on the first interlayer insulating layer ILD1. In particular, the second interlayer insulating layer ILD2 may be formed to cover the metal pattern TM and the first interlayer insulating layer ILD1.

[0108] Two first source-drain electrode structures SD1 may be patterned and arranged on the second interlayer insulation layer ILD2. One of the two first source-drain electrode structures SD1 may be a source node of the drive transistor DRT, and the other may be a drain node of the drive transistor DRT.

[0109] The two first source-drain electrode structures SD1 may be electrically connected in an associated manner to a first side portion and a second side portion of the active layer ACT through contact holes formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1 and the gate insulating layer Gl.

[0110] Referring to Fig. 3, the second interlayer insulation layer ILD2 may include a second-first interlayer insulation layer ILD2-1 and a second-second interlayer insulation layer ILD2-2. The second-first interlayer insulation layer ILD2-1 may be formed to cover the metal structure TM. In particular, the second-first interlayer insulation layer ILD2-1 may be formed to cover the metal structure TM and the first interlayer insulation layer ILD1. The second-second interlayer insulation layer ILD2-2 may be arranged on the second-first interlayer insulation layer ILD2-1.

[0111] A portion of the active layer ACT that overlaps the gate electrode GATE may serve as a channel region. One of the two first source-drain electrode structures SD1 of the drive transistor DRT may be connected to the first side portion of the channel region of the active layer ACT, and the other of the two first source-drain electrode structures SD1 may be connected to the second side portion of the channel region of the active layer ACT.

[0112] A passivation layer PAS0 may be formed to cover the two first source-drain electrode structures SD1. In particular, the passivation layer PAS0 may be formed to cover the two first source-drain electrode structures SD1 and the second-second intermediate insulation layer ILD2-2. A planarization layer PLN may be arranged on the passivation layer PAS0. The planarization layer PLN may include a first planarization layer PLN1 and a second planarization layer PLN2.

[0113] The first planarization layer PLN1 can be arranged on the passivation layer PAS0. The second planarization layer PLN2 can be arranged on the first planarization layer PLN1.

[0114] A second source-drain electrode structure SD2 may be patterned and disposed on the first planarization layer PLN1. The second source-drain electrode structure SD2 may be connected to one of the two first source-drain electrode structures SD1 through a contact hole formed in the first planarization layer PLN1.

[0115] The second planarization layer PLN2 may be formed to cover the second source-drain electrode structure SD2. In particular, the second planarization layer PLN2 may be disposed on the first planarization layer PLN1 and the second source-drain electrode structure SD2. Afterward, a portion of the second planarization layer PLN2 may be removed by etching. A light-emitting element ED of a subpixel SP may be disposed on the second planarization layer PLN2.

[0116] According to an exemplary stacked structure of the light-emitting element ED, an anode electrode AE ​​may be arranged on the second planarization layer PLN2. The anode electrode AE ​​may be electrically connected to the second source-drain electrode structure SD2 through a contact hole formed in the second planarization layer PLN2. The anode electrode AE ​​may have a multilayer structure including a light-transmitting conductive layer and a non-light-transmitting conductive layer with high reflectivity. The light-transmitting conductive layer may be made of a material with a relatively high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the non-light-transmitting conductive layer may have a single-layer or multilayer structure containing Al, Ag, Cu, Pb, Mo, Ti, or an alloy thereof.

[0117] A dam BANK may be formed to cover a portion of the anode electrode AE. In particular, the dam BANK may be formed to cover a portion of the anode electrode AE ​​and the second planarization layer PLN2. A portion of the dam BANK corresponding to the light-emitting region EA of the subpixel SP may be open. The dam BANK may include an insulating material. For example, the dam BANK may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin, etc. Alternatively, the dam BANK may include an inorganic insulating material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide, etc. Likewise, the dam BANK may include a black dye to absorb externally incident light.

[0118] A portion of the anode electrode AE ​​may be exposed through the opening (opened portion) of the dam BANK. At least a portion of an emission layer EL may be disposed on at least one side surface of the dam BANK and in the opening (opened portion) of the dam BANK. The entire emission layer EL, or at least a portion thereof, may be disposed between adjacent dams.

[0119] In the opening of the dam BANK, the emission layer EL can touch the anode electrode AE. A cathode electrode CE can be arranged on the emission layer EL. In particular, the cathode electrode CE can be arranged on the emission layer EL and a portion of the dam BANK.

[0120] The light-emitting element ED may be formed by the anode electrode AE, the emission layer EL, and the cathode electrode CE. The emission layer EL may include an organic material layer. For example, the emission layer EL may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), but the present disclosure is not limited thereto.

[0121] An encapsulation layer ENCAP can be arranged on the stack of the light-emitting element ED.

[0122] The encapsulation layer ENCAP can comprise a single-layer stack or a multi-layer stack. For example, as shown in Fig. As shown in Figure 3, the encapsulation layer ENCAP may comprise a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2. The second encapsulation layer PCL may be inserted between the first encapsulation layer PAS1 and the third encapsulation layer PAS2.

[0123] For example, the first encapsulation layer PAS1 and the third encapsulation layer PAS2 may be inorganic layers, and the second encapsulation layer PCL may be an organic layer, but is not limited thereto. For example, among the first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2, the second encapsulation layer PCL may have a greatest thickness, but is not limited thereto. In this example, the second encapsulation layer PCL may serve as a planarization layer. The first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2 may also be referred to as the first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer, respectively.

[0124] The first encapsulation layer PAS1 may be disposed on the cathode electrode CE and may be disposed closest to the stack of the light-emitting element ED. The first encapsulation layer PAS1 may comprise an inorganic insulating material that can be deposited at a low temperature. In one or more aspects, the first encapsulation layer PAS1 may comprise a plurality of insulating layers. For example, the first encapsulation layer PAS1 may comprise, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like. Since the first encapsulation layer PAS1 is deposited in a low-temperature atmosphere during the deposition process, the first encapsulation layer PAS1 may prevent the emission layer EL, which comprises an organic material susceptible to a high-temperature atmosphere, from being damaged.

[0125] The second encapsulation layer PCL may have a smaller area or size in a plan view than the first encapsulation layer PAS1. For example, the second encapsulation layer PCL may be formed exposing both ends or edges of the first encapsulation layer PAS1. The second encapsulation layer PCL may serve as a buffer to relieve stress between corresponding layers while the display device 100 is bent or flexed, and may also serve to improve planarization performance. For example, the second encapsulation layer PCL may comprise an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, silicon oxycarbon (SiOC), or the like. The second encapsulation layer PCL may be formed, for example, by an inkjet process.

[0126] The third encapsulation layer PAS2 may be disposed over the substrate SUB over which the second encapsulation layer PCL is disposed, and formed such that the respective top and side surfaces of the second encapsulation layer PCL and the first encapsulation layer PAS1 are covered. The third encapsulation layer PAS2 may minimize or prevent moisture or oxygen from penetrating the first encapsulation layer PAS1 and the second encapsulation layer PCL. For example, the third encapsulation layer PAS2 may comprise an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like.

[0127] Referring to Fig. 3, in an example where a touch sensor TS is embedded in the display panel 110, a touch sensor TS may be arranged on the encapsulation layer ENCAP. The structure of the touch sensor will be described in detail below.

[0128] A touch buffer layer T-BUF can be arranged on the encapsulation layer ENCAP. In particular, the touch buffer layer T-BUF can be arranged on the third encapsulation layer PAS2. The touch sensor TS can be arranged on the touch buffer layer T-BUF.

[0129] The touch sensor TS may include the touch sensor metals TSM and at least one bridge metal BRG arranged in different layers. The touch sensor metals TSM may be arranged on the bridge metal BRG and a portion of the inter-touch insulation layer T-ILD.

[0130] A touch interlayer insulation layer T-ILD may be disposed between the touch sensor metals TSM and the bridge metal BRG.

[0131] For example, the touch sensor metals TSM may include a first touch sensor metal TSM, a second touch sensor metal TSM, and a third touch sensor metal TSM disposed adjacent to each other. In an example where the third touch sensor metal TSM is disposed between the first touch sensor metal TSM and the second touch sensor metal TSM, and the first touch sensor metal TSM and the second touch sensor metal TSM need to be electrically connected to each other, the first touch sensor metal TSM and the second touch sensor metal TSM may be electrically connected to each other by the bridge metal BRG disposed in a different layer. The bridge metal BRG may be electrically insulated from the third touch sensor metal TSM by the inter-touch insulation layer T-ILD.

[0132] During the assembly of the touch sensor TS in the display panel 110, a chemical solution (e.g., a developer or etchant) used in the corresponding process or moisture may be generated or introduced from outside the display panel 110. In this situation, by disposing the touch sensor TS on the touch buffer layer T-BUF, such a chemical solution or moisture can be prevented from penetrating the emission layer EL comprising an organic material during the manufacturing process of the touch sensor TS. Accordingly, the touch buffer layer T-BUF can prevent damage to the emission layer EL, which is susceptible to a chemical solution or moisture.

[0133] To prevent damage to the emission layer EL, which comprises an organic material susceptible to high temperatures, the touch buffer layer T-BUF may be formed at a low temperature of less than or equal to a predetermined temperature (for example, 100 degrees (°C)) and using an organic insulating material with a low dielectric constant of 1 to 3. For example, the touch buffer layer T-BUF may comprise an acrylic-based material, an epoxy-based material, or a siloxane-based material. When the display device 100 is bent, the encapsulation layer ENCAP may be damaged, and the touch sensor metal disposed on the touch buffer layer T-BUF may crack or break.Even if the display device 100 is bent, the touch buffer layer T-BUF comprising the organic insulating material and having the planarization performance can prevent the damage of the encapsulation layer ENCAP and / or the cracking or breakage of the metals (TSM, BRG) included in the touch sensor TS.

[0134] A protective layer PAC may be formed to cover the touch sensor TS. The protective layer PAC may be, for example, an organic insulating layer. In particular, the protective layer PAC may be configured to cover the touch sensor TS and the touch interlayer insulation layer T-ILD.

[0135] Fig. 4 is an enlarged plan view illustrating an exemplary optical area structure of the display panel 110 in the display device 100 according to aspects of the present disclosure.

[0136] Referring to Fig. 4, an optical region OA may be arranged in the display region AA. A plurality of pixels (not shown) may be arranged adjacent to the optical region OA. The optical region OA may be one of the first optical region OA1 or the second optical region OA2 in the above-described Fig. 1A to Fig. 1C.

[0137] Referring to Fig. 4, in one or more exemplary embodiments, the optical region OA may include a through-hole TH and a surrounding region SA surrounding the through-hole TH, and the display region AA may be located outside the surrounding region SA. One or more rough structures RP may be located in the surrounding region SA. For example, subpixels for displaying images may not be located in the optical region OA.

[0138] In one or more aspects, an optical electronic device disposed below the display panel may be arranged to partially overlap the through-hole TH. This optical electronic device may be the first optical electronic device 11 described above.

[0139] The through-hole TH can be formed by cutting and removing a corresponding portion of the substrate along a cutting line. The shape of the through-hole TH can be as shown in Fig. 4, may be circular, but may have various shapes, such as, but not limited to, oval, square, hexagonal or octagonal.

[0140] The rough structure RP can have an inner rough structure IRP and an outer rough structure ORP.

[0141] Referring to Fig. 4, an outer wall DMO may be arranged in the surrounding area SA. For example, the outer wall DMO may be arranged between the inner rough structure IRP and the outer rough structure ORP, such that the outer wall DMO separates the two structures (IRP and ORP) from each other. The structure of the outer wall DMO is shown in Fig. 5 are described in detail.

[0142] In one or more aspects, an inner wall (in Fig. 4 not shown) in the display area AA. For example, the inner wall may be arranged outside the inner rough structure IRP. The inner wall may be formed in such a way that it prevents an encapsulation layer (for example, the second encapsulation layer PCL of the Fig. 3) overflows to the outside of the display area AA. The structure of the inner wall is shown in Fig. 5 are described in detail.

[0143] The shape of each ridge may correspond to the shape of the through-hole TH and have a closed curve surrounding the through-hole TH. For example, each ridge and the through-hole TH may have different closed curve shapes or closed curves with the same shape and different sizes. For example, each ridge and the through-hole TH may have the same shape, such as circular shapes with a common center, and be arranged such that they are spaced apart by a predetermined interval. Each ridge structure may include, but is not limited to, a stack of three layers arranged on the substrate SUB.

[0144] The shape of the rough structure RP may correspond to the shape of the through-hole TH and have a closed curve shape surrounding the through-hole TH. For example, the rough structure RP and the through-hole TH may have different closed curve shapes or have closed curve shapes with the same shape but different sizes. For example, as shown in Fig. 4, the rough structure RP and the through hole TH have the same shape, such as circular shapes with a common center, and are arranged such that they are spaced apart from each other with a predetermined gap.

[0145] A plurality of subpixels may be arranged in the display area AA, and each subpixel may include a light-emitting element. In an example where the light-emitting elements are organic light-emitting elements, such as organic light-emitting diodes, emission layers (not shown) may be arranged in the display area AA, and the emission layers may be, but are not limited to, organic emission layers containing an organic material.

[0146] These organic emission layers may be formed such that they extend to at least a portion of the optical region OA.

[0147] Moisture can penetrate the organic emissive layers, and in this situation, defects such as subpixel darkening can occur. Moisture can penetrate the area where the through-hole TH is located.

[0148] An inorganic encapsulation layer (for example, the above-described inorganic encapsulation layer PAS1) may be disposed on the rough structure RP. Moisture may penetrate through the inorganic encapsulation layer, and in this situation, the rough structure RP may cause a path through which moisture penetrates the inorganic encapsulation layer to be extended. According to this implementation, the rough structure RP may prevent moisture penetrating through the via hole TH and the like from entering an emission layer disposed in the display region AA.

[0149] Fig. Fig. 5 is a cross-sectional view taken along a line II' in the optical area OA of the Fig. 4.

[0150] Referring to Fig. 4 and Fig. 5, the optical region OA may include the through-hole TH and the surrounding region SA surrounding the through-hole TH, and the display region AA may be arranged outside the surrounding region SA.

[0151] In one or more aspects, an optical electronic device disposed below the display panel may be formed to partially overlap the through-hole TH. This optical electronic device may be the first optical electronic device 11 described above.

[0152] Referring to Fig. 5, the display device 100 may, in one or more aspects, include wall structures, such as the inner wall DMI disposed in the display area AA, the outer wall DMO disposed in the surrounding area SA, and the like. For example, the outer wall DMO may be disposed between the inner rough structure IRP and the outer rough structure ORP such that the outer wall DMO separates the two structures (IRP and ORP) from each other. Each wall structure may include, but is not limited to, a stack of three layers disposed on the substrate SUB. For example, at least one of the wall structures may include a first layer formed from a portion of a planarization layer, a second layer formed from a portion of a dam BANK, and a third layer formed from a portion of a spacer (not shown).The inner wall DMI may be formed in such a way that it prevents an encapsulation layer (for example the second encapsulation layer PCL of the . Fig. 3) overflows towards the outside of the display area AA.

[0153] As such a planarization layer, Fig. 5 shows the first planarization layer and second planarization layer (PLN1 and PLN2). In the inner wall DMI, at least a portion of an emission layer EL may be arranged on the portion of the spacer.

[0154] In one or more aspects, one or more elements included in a light-emitting element may be stacked on the outer wall DMO. For example, the emission layer EL and a common electrode (not shown) may be stacked on the outer wall DMO such that the emission layer EL and the common electrode extend along or across the outer wall DMO.

[0155] In one or more aspects, a rough structure may be formed inside and outside the outer wall DMO. The rough structure may include an inner rough structure IRP and an outer rough structure ORP. For example, the rough structure may include one or more ridges and one or more valleys formed in at least one surface of at least one intermediate insulation layer (e.g., ILD1, ILD2-1, ILD2-2, and / or the like).

[0156] The emission layer EL can be arranged in at least a portion of the rough structure. The emission layer EL can be an organic emission layer EL containing an organic material, but is not limited thereto. The emission layer EL can extend from the display region AA to at least a portion of the surrounding region SA.

[0157] Referring to Fig. 5, in one or more aspects, the emission layer EL may be disposed discontinuously over the inner rough structure IRP and the outer rough structure ORP. According to these implementations, even if moisture penetrating through the through-hole TH penetrates to the emission layer EL disposed in the surrounding area SA, the moisture can be prevented from penetrating the emission layer EL disposed in the display area AA. Since the emission layer EL is disposed discontinuously in the rough structures, the display device 100 or the display panel 110 can provide the advantage of lengthening a path through which moisture penetrates and preventing moisture flowing into the emission layer from reaching the display area AA.

[0158] Fig. 6 and Fig. 7 are cross-sectional views along a line II' in the optical area OA of the Fig. 4.

[0159] In the following, from the Fig. 7, discussions about the same or substantially the same configurations as those shown in Fig. 3 shown configurations of the display panel 110 are omitted for the sake of simplicity.

[0160] A substrate SUB may be arranged at the lower end of the display panel 110. The substrate SUB may include a first substrate SUB1, an interlayer insulating layer IPD, and a second substrate SUB2. The interlayer insulating layer IPD may be interposed between the first substrate SUB1 and the second substrate SUB2.

[0161] A buffer layer BUF may be arranged on the substrate SUB. The buffer layer BUF may include a multiple buffer layer MBUF, a first active buffer layer ABUF1, a second active buffer layer ABUF2, and a gate insulating layer GI.

[0162] A gate electrode GATE of the drive transistor DRT can be patterned and arranged on the buffer layer BUF.

[0163] A first interlayer insulation layer ILD1 may be formed to cover the buffer layer BUF and the gate electrode GATE.

[0164] A metal structure TM may be patterned and disposed on the first interlayer insulation layer ILD1. The metal structure TM may be disposed at a location different from the location where the drive transistor DRT is formed.

[0165] A second-first interlayer insulating layer ILD2-1 may be formed to cover the metal structure TM. Specifically, the second-first interlayer insulating layer ILD2-1 may be formed to cover the first interlayer insulating layer ILD1 and the metal structure TM.

[0166] A second-second interlayer insulating layer ILD2-2 may be disposed on the second-first interlayer insulating layer ILD2-1. After the second-second interlayer insulating layer ILD2-2 is disposed on the second-first interlayer insulating layer ILD2-1, a portion of the second-second interlayer insulating layer ILD2-2 may be removed by etching. The second-second interlayer insulating layer ILD2-2, a portion of which has been removed by etching, may be divided into a plurality of portions, and some of the divided plurality of portions may be included in the rough structure and the one or more ridges.

[0167] A first source-drain electrode structure SD1 may be patterned and disposed on the second interlayer insulation layer ILD2. For example, the first source-drain electrode structure SD1 may be patterned and disposed on the second interlayer insulation layer ILD2-2.

[0168] A passivation layer PAS0 may be disposed on the second-second interlayer insulation layer ILD2-2. Specifically, the passivation layer PAS0 may be formed to cover the two first source-drain electrode structures SD1 and the second-second interlayer insulation layer ILD2-2. The passivation layer PAS0 may be disposed in the display region AA and formed to cover the first source-drain electrode structure SD1.

[0169] A first planarization layer PLN1 may be arranged on the passivation layer PAS0.

[0170] A second source-drain electrode structure SD2 may be patterned and arranged on the first planarization layer PLN1.

[0171] After the second source-drain electrode structure SD2 has been arranged, a second planarization layer PLN2 may be deposited on the first planarization layer PLN1 and the second source-drain electrode structure SD2. Thereafter, a portion of the second planarization layer PLN2 may be removed by etching. The second planarization layer PLN2, a portion of which has been removed by etching, may be divided into a plurality of sections, and some of the divided plurality of sections may be included in the rough structure and the one or more ridges.

[0172] A dam BANK may be arranged on the second planarization layer PLN2. After that, a portion of the dam BANK may be removed by etching. The dam BANK, from which a portion has been removed by etching, may be divided into a plurality of portions, and some of the divided plurality of portions may be included in the rough structure and the one or more embankments. A spacer (not shown) may be arranged on the dam BANK. After that, a portion of the spacer may be removed by etching. The spacer, from which a portion has been removed by etching, may be divided into a plurality of portions, and some of the divided plurality of portions may be included in the rough structure and the one or more embankments.

[0173] An emission layer EL can be arranged on the dam bank. The entire emission layer EL or at least a portion thereof can be arranged between adjacent dams. Since the emission layer EL is deposited on the entire surface as well as on the dam bank within a predefined area, a portion of the emission layer EL can be arranged on the upper surface of the rough structure and the upper surface of the one or more embankments.

[0174] A first encapsulation layer PAS1 may be formed to cover the emission layer EL, the rough structure, the one or more ridges, and the like. The first encapsulation layer PAS1 may comprise an inorganic insulating material that can be deposited at a low temperature.

[0175] A second encapsulation layer PCL can be arranged on the first encapsulation layer PAS1. In particular, the second encapsulation layer PCL can be arranged on a partial region of the first encapsulation layer PAS1.

[0176] A third encapsulation layer PAS2 can be arranged on the second encapsulation layer PCL.

[0177] A touch buffer layer T-BUF can be arranged on the encapsulation layer ENCAP. In particular, the touch buffer layer T-BUF can be arranged on the third encapsulation layer PAS2.

[0178] A bridge metal BRG can be patterned and disposed on the touch buffer layer T-BUF.

[0179] A touch interlayer insulation layer (T-ILD) may be formed to cover the touch buffer layer (T-BUF) and the bridge metal (BRG). Touch sensor metals (TSM) may be disposed on the touch interlayer insulation layer (T-ILD). One or more portions of the touch interlayer insulation layer (T-ILD) may be etched, allowing the touch interlayer insulation layer (T-ILD) to include a plurality of contact holes.

[0180] The touch sensor metals TSM can be electrically connected to the bridge metal BRG through contact holes of the touch interlayer insulation layer T-ILD.

[0181] A protective layer PAC may be formed to cover the touch interlayer insulation layer T-ILD and the touch sensor metals TSM. The protective layer PAC may, for example, be an organic insulating layer.

[0182] Referring to Fig. 6, the outer rough structure ORP may be disposed in the surrounding area SA adjacent to the through-hole TH. The outer wall DMO may be disposed outside the outer rough structure ORP. The inner rough structure IRP may be disposed outside the outer wall DMO. The inner wall DMI may be disposed outside the inner rough structure IRP. A portion of the entire rough structure, including the inner rough structure IRP and the outer rough structure ORP, may be disposed outside the inner wall DMI.

[0183] Referring to Fig. 6, a cutting line may run along or touch the outer rough structure ORP. A side surface of the outer rough structure ORP may correspond to a boundary or edge region of the through-hole TH. This means that the boundary or edge region of the through-hole TH may correspond to a side surface of the protective layer PAC, a side surface of the outer rough structure ORP, a side surface of the buffer layer BUF, and a side surface of the substrate SUB.

[0184] In contrast, referring to Fig. 7, in contrast to Fig. 6, a boundary or edge area of ​​the through hole TH in Fig. 7 correspond to a side surface of the protective layer PAC and a side surface of the substrate SUB. Elements (i.e., stacked elements) on the substrate SUB other than the protective layer PAC may be arranged to be spaced apart from the cutting line. This implementation can prevent elements (i.e., stacked elements), such as the outer rough structure ORP and the like, from being damaged during the process of forming the through-hole TH. The cutting line may be referred to as a cutting region.

[0185] In one or more aspects, the first encapsulation layer PAS1 may include a plurality of insulating layers. For example, the first encapsulation layer PAS1 may be arranged in the combined form of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). For example, the first encapsulation layer PAS1 may include three insulating layers, but is not limited thereto. For example, the bottom layer of the first encapsulation layer PAS1 may include silicon nitride (SiNx). The middle layer of the first encapsulation layer PAS1 may include silicon oxynitride (SiON). The top layer of the first encapsulation layer PAS1 may include silicon oxide (SiOx).

[0186] In the example where the top layer of the first encapsulation layer PAS1 comprises silicon oxide (SiOx), the second encapsulation layer PCL can be arranged, spreading more easily on the first encapsulation layer PAS1. However, if the top layer of the first encapsulation layer PAS1 comprises silicon oxide (SiOx), oxygen can penetrate through the top layer of the first encapsulation layer PAS1, which comprises silicon oxide (SiOx).

[0187] To address this problem, one or more aspects of the present disclosure may provide the display device 100 capable of preventing oxygen from penetrating an encapsulation layer.

[0188] One or more aspects of the present disclosure may provide the display device 100 having an encapsulation layer capable of preventing moisture from entering during the process of forming a through-hole.

[0189] One or more aspects of the present disclosure may provide the display device 100 having a second encapsulation layer disposed on a first encapsulation layer that is an inorganic layer, has high spreadability, and is capable of preventing oxygen from penetrating into the first encapsulation layer.

[0190] One or more aspects of the present disclosure may provide the display device 100 capable of preventing oxygen penetration into an encapsulation layer and thereby operating at low power.

[0191] One or more exemplary embodiments of the present disclosure are discussed in detail below.

[0192] Fig. 8 to Fig. 11 are cross-sectional views showing a marginal area between the contact hole TH and the surrounding area in Fig. 4 represent.

[0193] Fig. 6 and Fig. 8 illustrate a first enlarged area A1 of the display panel 110.

[0194] The substrate SUB may be arranged at the lower end of the display panel 110. The substrate SUB may include the through-hole TH and the surrounding area SA. The substrate SUB may include glass, plastic, or a flexible polymer film. For example, the flexible polymer film may be made of any one of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetylcellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), which is only an example and is not necessarily limited thereto.

[0195] The buffer layer BUF can be arranged on the substrate SUB.

[0196] The first encapsulation layer PAS1 may be arranged on the buffer layer BUF. The first encapsulation layer PAS1 may have a stepped end, but is not limited thereto.

[0197] The first encapsulation layer PAS1 can comprise a plurality of insulating layers. The plurality of insulating layers can comprise three or four layers, without being limited thereto, although more or fewer layers are also possible. For example, the first encapsulation layer PAS1 can comprise two layers.

[0198] Referring to Fig. 8, in the example where the first encapsulation layer PAS1 is formed from a stack of four layers, the first encapsulation layer PAS1 may include, but is not limited to, a first insulating layer PAS11 comprising silicon nitride (SiNx), a second insulating layer PAS12 comprising silicon oxynitride (SiON) disposed on the first insulating layer PAS11, a third insulating layer PAS13 comprising silicon oxynitride (SiON) disposed on the second insulating layer PAS12, and a fourth insulating layer PAS14 comprising silicon oxide (SiOx) disposed on a portion of the third insulating layer PAS13.Alternatively, in the example where the first encapsulation layer PAS1 is formed from a stack of two layers, the first encapsulation layer PAS1 may include the third insulating layer PAS13 and the fourth insulating layer PAS14 disposed on a portion of the third insulating layer PAS13.

[0199] In the example where the first encapsulation layer PAS1 is formed from a stack of three layers, the first encapsulation layer PAS1 may include, but is not limited to, a first insulating layer comprising silicon nitride (SiNx), a second insulating layer comprising silicon oxynitride (SiON), and a third insulating layer comprising silicon oxide (SiOx).

[0200] In the example of Fig. 8, the lower layer PAS11 of the first encapsulation layer PAS1 may comprise silicon nitride (SiNx), and the uppermost layer PAS14 of the first encapsulation layer PAS1 may comprise silicon oxide (SiOx). For convenience of explanation, discussions are provided below based on examples in which the first encapsulation layer PAS1 is formed from the four-layer stack.

[0201] Referring to Fig. 8, the lower layer PAS11 may have a width (i.e., a distance between the two opposite ends) that is greater than that of the uppermost layer PAS14. For example, the lower layer PAS11 may extend rightward beyond the right edge of the upper layer PAS14. Similarly, the second insulating layer PAS12 and the third insulating layer PAS13 may have a width (i.e., a distance between the two opposite ends) that is greater than that of the uppermost layer PAS14, but are not limited thereto. For example, the second insulating layer PAS12 and the third insulating layer PAS13 may extend rightward beyond the right edge of the uppermost layer PAS14, but are not limited thereto.

[0202] Referring to Fig. 8, the fourth insulating layer PAS14 may be arranged on a portion of the third insulating layer PAS13.

[0203] A portion of the first encapsulation layer PAS1 may be disposed adjacent to the through-hole TH. Each of the first insulating layer PAS11, the second insulating layer PAS12, and the third insulating layer PAS13 may be disposed adjacent to the through-hole TH.

[0204] The fourth insulating layer PAS14 may be arranged such that it is spaced apart from the through-hole TH. In one or more aspects, the fourth insulating layer PAS14 may be arranged within a predetermined range on the entire upper surface of the third insulating layer PAS13, and the fourth insulating layer PAS14 may not be arranged on a portion of the third insulating layer PAS13 adjacent to the through-hole TH. In one or more aspects, the third encapsulation layer PAS2 may be arranged on the first encapsulation layer PAS1. For example, the third encapsulation layer PAS2 may be arranged on the portion of the third insulating layer PAS13 adjacent to the through-hole TH and the fourth insulating layer PAS14.

[0205] The third encapsulation layer PAS2 may be formed to cover the first encapsulation layer PAS1.

[0206] The third encapsulation layer PAS2 may be formed to cover a side surface (e.g., a right side surface) of the fourth insulating layer PAS14 and a portion of the third insulating layer PAS13.

[0207] The third encapsulation layer PAS2 can be arranged in a step structure.

[0208] Referring to Fig. 8, a portion of the third encapsulation layer PAS2 located on the right side of the surrounding region SA may be arranged parallel to the fourth insulating layer PAS14 in the horizontal direction and formed to overlap the third insulating layer PAS13 in the vertical direction. A portion of the third encapsulation layer PAS2 located on the left side of the surrounding region SA may be formed to overlap the third insulating layer PAS13 in the vertical direction. The portion of the third encapsulation layer PAS2 located on the left side of the surrounding region SA may be arranged higher than the portion of the third encapsulation layer PAS2 located on the right side of the surrounding region SA, but is not limited thereto.

[0209] The third encapsulation layer PAS2 may be arranged on the first encapsulation layer PAS1 and adjacent to the through hole TH.

[0210] Each side surface (e.g., each right side surface) of each of the first insulating layer PAS11, the second insulating layer PAS12, the third insulating layer PAS13, and the third encapsulation layer PAS2 may correspond to a cutting line or a cutting region.

[0211] Each of the first insulating layer PAS11, the second insulating layer PAS12, the third insulating layer PAS13 and the third encapsulation layer PAS2 may have a truncated shape in the cutting region.

[0212] Therefore, even if each of the first insulating layer PAS11, the second insulating layer PAS12, the third insulating layer PAS13, and the third encapsulating layer PAS2 is cut along the cutting line, since the third encapsulating layer PAS2 is formed to cover the side surface of the fourth insulating layer PAS14, the fourth insulating layer PAS14 can be protected from moisture penetration.

[0213] Referring to Fig. 7 and Fig. 9 can be a boundary of the through hole TH in Fig. 7 correspond to a side surface of the protective layer PAC and a side surface of the substrate SUB. The first encapsulation layer PAS1 may be arranged such that it is spaced from the through-hole TH. That is, each of the first insulating layer PAS11, the second insulating layer PAS12, the third insulating layer PAS13, and the fourth insulating layer PAS14 may be arranged such that it is spaced from the through-hole TH. The third encapsulation layer PAS2 may be arranged adjacent to the through-hole TH. The first encapsulation layer PAS1 and the third encapsulation layer PAS2 may be arranged in a step structure.

[0214] Referring to Fig. 8 and Fig. 9, the third encapsulation layer PAS2 of the Fig. 9, unlike the third encapsulation layer PAS2 of the Fig. 8, be formed such that it covers an entire side surface (for example, a right side surface) of the first encapsulation layer PAS1.

[0215] The third encapsulation layer PAS2 may have a portion arranged along the side surface of the first encapsulation layer PAS1.

[0216] The third encapsulation layer PAS2 may be formed to cover a respective side surface (e.g., a respective right side surface) of each of a first insulating layer PAS11, a second insulating layer PAS12, a third insulating layer PAS13, and a fourth insulating layer PAS14, and a portion of the upper surface of the substrate SUB. Therefore, a portion of the third encapsulation layer PAS2 that contacts the substrate SUB may be disposed adjacent to the via hole TH. Likewise, the third encapsulation layer PAS2 may be formed to cover a portion of the upper surface of the third insulating layer PAS13 and the upper surface of the fourth insulating layer PAS14. Further, the third encapsulation layer PAS2 may be formed to cover respective side surfaces (e.g., respective right side surfaces) of the buffer layer BUF.

[0217] The third encapsulation layer PAS2 and the substrate SUB may have truncated shapes in the cutting region. Respective side surfaces of the third encapsulation layer PAS2 and the substrate SUB may correspond to the cutting region.

[0218] Therefore, even if each of the third encapsulation layer PAS2 and the substrate SUB is cut along the cutting line, since the third encapsulation layer PAS2 is formed to cover the side surface of the first encapsulation layer PAS1, a fourth insulating layer PAS14 can be protected from moisture penetration.

[0219] With reference to the Fig. 8 and Fig. 10, unlike the fourth insulating layer PAS14 of the Fig. 8, a fourth insulating layer PAS14 of the Fig. 10 may be formed such that a portion of a third insulating layer PAS13 is exposed, and the fourth insulating layer PAS14 may have a portion adjacent to the through hole TH.

[0220] After the fourth insulating layer PAS14 has been deposited within a predetermined range on the entire upper surface of the third insulating layer PAS13, a portion of the fourth insulating layer PAS14 located at a distance from the through-hole TH may be removed by etching.

[0221] By this process, the fourth insulating layer PAS14 may have a first part PAS14a adjacent to the through-hole TH and a second part PAS14b arranged at a distance from the through-hole TH.

[0222] The third encapsulation layer PAS2 may be formed such that it touches a portion of the third insulating layer PAS13 between the first part PAS14a and the second part PAS14b of the fourth insulating layer PAS14. Referring to Fig. 10, the third encapsulation layer PAS2 may have a "T" shape. This means that the third encapsulation layer PAS2 may be formed to cover the first part PAS14a, the second part PAS14b, and the exposed portion of the third insulating layer PAS13.

[0223] The first part PAS14a may be arranged at a distance from the second part PAS14b. Furthermore, the first part PAS14a may not be completely separated from the second part PAS14b, and a region between the first part PAS14a and the second part PAS14b may be a region where a through-hole is formed.

[0224] The first part PAS14a may be arranged adjacent to the through hole TH and formed to overlap the third insulating layer PAS13 in the vertical direction.

[0225] The second part PAS14b may be arranged to be spaced apart from the through-hole TH and formed to overlap the third insulating layer PAS13 in the vertical direction.

[0226] A portion of the third encapsulation layer PAS2 may be arranged in the region between the first part PAS14a and the second part PAS14b, and the third encapsulation layer PAS2 may be arranged in the horizontal direction parallel to the first part PAS14a and the second part PAS14b. In particular, the portion of the third encapsulation layer PAS2 arranged in the region between the first part PAS14a and the second part PAS14b may be arranged in the horizontal direction parallel to the first part PAS14a and the second part PAS14b.

[0227] A respective side surface (e.g., a respective right side surface) of each of the first encapsulation layer PAS1 and the third encapsulation layer PAS2 may correspond to the cutting region. The first encapsulation layer PAS1 and the third encapsulation layer PAS2 may have truncated shapes in the cutting region.

[0228] Referring to Fig. 10, since the second part PAS14b of the fourth insulating layer PAS14 is arranged to be spaced apart from the through-hole TH, the fourth insulating layer PAS14 can be protected from moisture penetration, and since the first part PAS14a of the fourth insulating layer PAS14 is arranged adjacent to the through-hole TH, the first encapsulation layer PAS1 can have a structurally strong end.

[0229] With reference to the Fig. 7 and Fig. 11 can be a boundary of the through hole TH in Fig. 7 correspond to a side surface of the protective layer PAC and a side surface of the substrate SUB. The first encapsulation layer PAS1 may be formed such that it is arranged at a distance from the through-hole TH.

[0230] Referring to Fig. 10 and Fig. 11, unlike the third encapsulation layer PAS2 of the Fig. 10, the third encapsulation layer PAS2 of the Fig. 11 may be formed such that it covers an entire side surface (for example, a right side surface) of the first encapsulation layer PAS1.

[0231] The third encapsulation layer PAS2 may be formed to cover the side surface of the first encapsulation layer PAS1 and a portion of the upper surface of the substrate SUB. Specifically, the third encapsulation layer PAS2 may be formed to cover a respective side surface (e.g., a respective right side surface) of each of a first insulating layer PAS11, a second insulating layer PAS12, a third insulating layer PAS13, and the fourth insulating layer PAS14, and a portion of the upper surface of the substrate SUB. Therefore, a portion of the third encapsulation layer PAS2 that contacts the substrate SUB may be disposed adjacent to the through-hole TH.

[0232] The third encapsulation layer PAS2 may be formed to cover a side surface of the first part PAS14a of the fourth insulating layer PAS14. The third encapsulation layer PAS2 may be formed to cover respective side surfaces (e.g., respective right side surfaces) of the first insulating layer PAS11, the second insulating layer PAS12, and the third insulating layer PAS13. Likewise, the third encapsulation layer PAS2 may be formed to cover respective side surfaces (e.g., respective right side surfaces) of the buffer layer BUF.

[0233] Fig. 12 and Fig. 13 are plan views showing a marginal area between the contact hole (or through hole) TH and the surrounding area SA in Fig. 4 represent.

[0234] Fig. 12 and Fig. 13 illustrate a second enlarged area A2 of the display panel 110.

[0235] Referring to Fig. 12 and Fig. 13, the fourth insulating layer PAS14 may have a groove region in which a plurality of grooves H are arranged.

[0236] A distance between the fourth insulating layer PAS14 and the through-hole TH may be the same or substantially the same as a distance between the fourth insulating layer PAS14 and the through-hole TH shown in Fig. 6. Referring to Fig. 12, a side surface of the fourth insulating layer PAS14 may correspond to the cutting line. In particular, the side surface of the groove region of the fourth insulating layer PAS14 may be arranged adjacent to the cutting line. The groove region of the fourth insulating layer PAS14 may be arranged adjacent to the cutting line.

[0237] A distance between the fourth insulating layer PAS14 and the through-hole TH can be Fig. 13, be the same or substantially the same as a distance between the fourth insulating layer PAS14 and the through-hole TH shown in Fig. 7. Referring to Fig. 13, a side surface of the fourth insulating layer PAS14 may be arranged such that it is spaced apart from the through-hole TH. The groove portion of the fourth insulating layer PAS14 may be arranged such that it is spaced apart from the through-hole TH.

[0238] With reference to Fig. 12 and Fig. 13, since the fourth insulating layer PAS14 has a plurality of grooves H, a moisture penetration distance through the fourth insulating layer PAS14 can be increased.

[0239] The plurality of grooves H can be configured in various shapes to increase the moisture penetration distance. For example, the plurality of grooves H can be arranged such that moisture penetrating the fourth insulating layer PAS14 can move in a zigzag pattern.

[0240] The exemplary embodiments described above will be briefly described below.

[0241] In accordance with the exemplary embodiments described herein, a display device may be provided comprising a substrate having a through-hole and a surrounding region surrounding the through-hole, a first passivation layer disposed on the substrate and including a first insulating layer and a second insulating layer disposed on a portion of the first insulating layer, and a second passivation layer formed to cover the first passivation layer.

[0242] In one or more aspects, the substrate may comprise a first substrate and a second substrate with an intermediate insulating layer interposed therebetween.

[0243] In one or more aspects, the second passivation layer may be formed to cover a side surface of the second insulating layer and a portion of a top surface of the first insulating layer.

[0244] In one or more aspects, the second passivation layer may be arranged in a step structure.

[0245] In one or more aspects, the first passivation layer may be arranged in a step structure.

[0246] In one or more aspects, the first passivation layer may be disposed adjacent to the via, and the second passivation layer may be disposed on the first passivation layer and disposed adjacent to the via.

[0247] In one or more aspects, the first insulating layer may be disposed adjacent to the via hole, and the second insulating layer may be disposed at a distance from the via hole.

[0248] In one or more aspects, the substrate may further include a cutting region that is an edge region between the via hole and the surrounding region, and a side surface of the first insulating layer of the first passivation layer and a side surface of the second passivation layer may correspond to the cutting region.

[0249] In one or more aspects, the second passivation layer may be formed to cover a side surface of the first insulating layer.

[0250] In one or more aspects, the second passivation layer may be formed to cover the side surface of the first insulating layer and a portion of a top surface of the substrate.

[0251] In one or more aspects, the first passivation layer may be arranged to be spaced apart from the via, and the second passivation layer may be arranged adjacent to the via.

[0252] In one or more aspects, the substrate may further include a cutting region that is an edge region between the via hole and the surrounding region, and a side surface of the second passivation layer and a side surface of the substrate may correspond to the cutting region.

[0253] In one or more aspects, the second insulating layer may include a first portion adjacent to the via and a second portion spaced apart from the via.

[0254] In one or more aspects, the second passivation layer may be formed to contact the first insulating layer between the first part of the second insulating layer and the second part of the second insulating layer.

[0255] In one or more aspects, the second passivation layer may be formed to cover a side surface of the first insulating layer and a side surface of the first part of the second insulating layer.

[0256] In one or more aspects, the second passivation layer may be formed to cover the side surface of the first insulating layer and a portion of a top surface of the substrate.

[0257] In one or more aspects, the first passivation layer may be arranged to be spaced apart from the via, and the second passivation layer may be arranged adjacent to the via.

[0258] In one or more aspects, the second insulating layer may include a groove region in which a plurality of grooves are arranged.

[0259] In one or more aspects, the groove region may be disposed adjacent to the through-hole.

[0260] In one or more aspects, the groove portion may be arranged to be spaced apart from the through-hole.

[0261] In one or more aspects, the display device may further include an optical electronic device arranged to overlap the through-hole.

[0262] In one or more aspects, the through-hole may be an area in which no image is displayed.

[0263] In one of the several aspects, the substrate may further include a display region surrounding the surrounding region, and the second passivation layer may be disposed on the display region and the surrounding region.

[0264] A display device according to one or more exemplary embodiments of the present disclosure may be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, variable devices, sliding devices, electronic organizers, electronic books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation devices, car navigation devices, automotive displays, automotive devices, theater devices, theater displays, televisions, wallpaper displays, signage devices, gaming machines, notebook computers, monitors, cameras, camcorders, household appliances, etc., but embodiments of the present disclosure are not limited thereto.

[0265] The above description has been presented to enable any person skilled in the art to make, use, and apply the technical features of the present disclosure, and has been provided as examples in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the principles described herein may be applied to other embodiments and applications without departing from the scope of the present disclosure. The above description and the accompanying drawings provide examples of the technical features of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to represent the scope of the technical features of the present disclosure.

Claims

[1] A display device (100) comprising: a substrate (SUB) having a through-hole (TH) and a surrounding region (SA) surrounding the through-hole (TH); a first passivation layer (PAS1) disposed on the substrate (SUB) and comprising a first insulating layer (PAS13) and a second insulating layer (PAS14) disposed on a portion of the first insulating layer (PAS13); and a second passivation layer (PAS2) formed to cover the first passivation layer (PAS1). [2] The display device (100) according to claim 1, wherein the substrate (SUB) comprises a first substrate (SUB1) and a second substrate (SUB2) with an intermediate insulation layer (IPD) interposed therebetween. [3] The display device (100) according to claim 1 or 2, wherein the second passivation layer (PAS2) is formed to cover a side surface of the second insulating layer (PAS14) and a portion of an upper surface of the first insulating layer (PAS13). [4] The display device (100) according to claim 3, wherein the second passivation layer (PAS2) is arranged in a step structure. [5] The display device (100) according to any one of claims 1 to 4, wherein the first passivation layer (PAS1) is arranged in a step structure. [6] The display device (100) according to any one of claims 1 to 5, wherein the first passivation layer (PAS1) is disposed adjacent to the through-hole (TH) and the second passivation layer (PAS2) is disposed on the first passivation layer (PAS1) and disposed adjacent to the through-hole (TH). [7] The display device (100) according to any one of claims 1 to 6, wherein the first insulating layer (PAS13) is arranged adjacent to the through-hole (TH) and the second insulating layer (PAS14) is arranged to be spaced apart from the through-hole (TH). [8] The display device (100) according to claim 3 or 4, wherein the substrate (SUB) further has a cutting region which is a peripheral region between the through-hole (TH) and the surrounding region (SA), and a side surface of the first insulating layer (PAS13) of the first passivation layer (PAS1) and a side surface of the second passivation layer (PAS2) correspond to the cutting region. [9] The display device (100) according to claim 3 or 4, wherein the second passivation layer (PAS2) is formed to cover a side surface of the first insulating layer (PAS13). [10] The display device (100) according to claim 9, wherein the second passivation layer (PAS2) is formed to cover the side surface of the first insulating layer (PAS13) and a portion of a top surface of the substrate (SUB). [11] The display device (100) according to any one of claims 3, 4, 9 or 10, wherein the first passivation layer (PAS1) is arranged to be spaced apart from the through-hole (TH), and the second passivation layer (PAS2) is arranged adjacent to the through-hole (TH). [12] The display device (100) according to any one of claims 3, 4, 9, 10 or 11, wherein the substrate (SUB) further comprises a cutting region which is a peripheral region between the through-hole (TH) and the surrounding region (SA), and wherein a side surface of the second passivation layer (PAS2) and a side surface of the substrate (SUB) correspond to the cutting region. [13] The display device (100) according to claim 1 or 2, wherein the second insulating layer (PAS14) comprises: a first part (PAS14a) adjacent to the through-hole (TH); and a second part (PAS14b) arranged at a distance from the through-hole (TH). [14] The display device (100) according to claim 13, wherein the second passivation layer (PAS2) is formed to contact the first insulating layer (PAS13) between the first part (PAS14a) of the second insulating layer (PAS14) and the second part (PAS14b) of the second insulating layer (PAS14). [15] The display device (100) according to claim 13 or 14, wherein the second passivation layer (PAS2) is formed to cover a side surface of the first insulating layer (PAS13) and a side surface of the first part (PAS14a) of the second insulating layer (PAS14). [16] The display device (100) according to any one of claims 13 to 15, wherein the second passivation layer (PAS2) is formed to cover the side surface of the first insulating layer (PAS13) and a portion of a top surface of the substrate (SUB). [17] The display device (100) according to any one of claims 1 to 16, wherein the second insulating layer (PAS14) has a groove portion in which a plurality of grooves (H) are arranged. [18] The display device (100) according to claim 17, wherein the groove portion is arranged adjacent to the through hole (TH). [19] The display device (100) according to claim 17, wherein the groove portion is arranged to be spaced apart from the through-hole (TH). [20] The display device (100) according to any one of claims 1 to 19, further comprising an optical electronic device (11, 12) arranged to overlap the through-hole (TH). [21] The display device (100) according to any one of claims 1 to 20, wherein the through-hole (TH) is a region in which no image is displayed. [22] The display device (100) according to any one of claims 1 to 21, wherein the substrate (SUB) further comprises a display region (AA) surrounding the surrounding region (SA), and the second passivating layer (PAS2) is arranged on the display region (AA) and the surrounding region (SA).

Images