Monitoring control signals from circuit breakers in a half-bridge for motor control or other applications

Abstract

In some examples, this disclosure describes a method for controlling a high-side circuit breaker and a low-side circuit breaker arranged in a half-bridge configuration. The method may include driving the gate of the high-side circuit breaker based on high-side pulse modulation (PM) signals; driving a gate of the low-side circuit breaker based on low-side PM signals; and monitoring the high-side PM signals and the low-side PM signals. The high-side PM signals and the low-side PM signals are configured to switch the high-side circuit breaker and the low-side circuit breaker ON and OFF in a complementary manner, and monitoring may include: detecting one or more absences of either the high-side PM signals or the low-side PM signals; and generating a disturbance signal in response to the detection of one or more absences.

Description

Technical area

[0001] This disclosure relates to driver circuits for power switches, and more particularly to techniques and circuits for monitoring the operation of power switches configured in a half-bridge. background

[0002] Power switches are used in a wide variety of applications to control the power delivered to a load. As examples, a power switch may include a field-effect transistor (FET), an insulated-gate bipolar transistor (IGBT), a bipolar transistor (BJT), or another type of power transistor. Examples of FETs may include, but are not limited to, a junction field-effect transistor (JFET), a metal-oxide-semiconductor FET (MOSFET), a double-gate MOSFET, an insulated-gate bipolar transistor (IGBT), any other type of FET, or any combination thereof. Examples of MOSFETs may include, but are not limited to, a PMOS, an NMOS, a DMOS, or another type of MOSFET, or any combination thereof. MOSFETs may be formed in silicon, gallium nitride, silicon carbide, or other materials.

[0003] Power breakers are typically controlled by a driver circuit via pulse modulation, or PM, signals. PM signals generally refer to pulse width modulation (PWM) signals, pulse frequency modulation (PFM) signals, pulse duration modulation signals, pulse density modulation signals, or other types of modulation control signals used to control a power switch. PM control signals can be generated by a processor and communicated to a driver circuit. The driver circuit can amplify the PM control signals to generate PM drive signals that can be applied to the gate of a power switch to control turning the power breaker on / off, and thereby control the average amount of power delivered by the power breaker to a load. Turning the power breaker on / off effectively chops its power delivery into discrete parts. The average value of the voltage and / or current deliveredThe power supplied to a load can be controlled by turning the switch on and off at a high rate. The longer the switch is on compared to the off times, the higher the total power supplied to the load.

[0004] In many applications, two different power switches are configured in a high-side and a low-side configuration, and the on / off switching of the two power switches is synchronized to deliver the required power to a switching node positioned between the high-side and low-side switches. Additionally, in some systems, different sets of high-side and low-side switches may be used to control different phases of a multi-phase device, such as a multi-phase electric motor. Brief description

[0005] According to some embodiments, a driver circuit as defined in claim 1, a method as defined in claim 11, and a system as defined in claim 18 are provided. The dependent claims define further embodiments.

[0006] This disclosure describes circuits and techniques for monitoring power switch control signals, e.g., so-called pulse modulation (PM) signals, associated with a high-side power switch and a low-side power switch arranged in a half-bridge configuration. According to this disclosure, a half-bridge circuit is controlled in a complementary manner, in which the low-side power switch is ON when the high-side power switch is OFF, and the high-side power switch is ON when the low-side power switch is OFF. The techniques of this disclosure may include monitoring PM signals associated with a driver circuit that controls the high-side power switch and the low-side power switch of a half-bridge circuit.The expectation is that, when properly operated, the low-side power switch is ON-controlled by the PM signals when the high-side power switch is OFF-controlled by the PM signals, and the high-side power switch is ON-controlled by the PM signals when the low-side power switch is OFF-controlled by the PM signals. According to this disclosure, the driver circuit may be configured to detect one or more absences of either the high-side PM signals or the low-side PM signals. The driver circuit may be further configured to generate a fault signal in response to detecting the one or more absences. In this case, the one or more missing PM signals on either the high-side or the low-side may indicate a problem with the circuit or the PM signals.

[0007] In some examples, this disclosure describes a driver circuit configured to control a high-side power switch and a low-side power switch arranged in a half-bridge configuration. The driver circuit may include a high-side driver configured to drive a gate of the high-side power switch based on high-side PM signals, and a low-side driver configured to drive a gate of the low-side power switch based on low-side PM signals. The driver circuit may further include logic circuitry configured to monitor the high-side PM signals and the low-side PM signals. The high-side PM signals and the low-side PM signals are configured to switch the high-side power switch and the low-side power switch ON and OFF in a complementary manner.The logic circuit is configured to detect one or more absences of either the high-side PM signals or the low-side PM signals and to generate a fault signal in response to detecting the one or more absences.

[0008] In some examples, this disclosure describes a method for controlling a high-side power switch and a low-side power switch arranged in a half-bridge configuration. The method includes: driving the gate of the high-side power switch based on high-side PM signals; driving a gate of the low-side power switch based on low-side PM signals; and monitoring the high-side PM signals and the low-side PM signals. The high-side PM signals and the low-side PM signals are configured to turn the high-side power switch and the low-side power switch ON and OFF in a complementary manner. Monitoring the high-side PM signals and the low-side PM signals includes detecting one or more absences of either the high-side PM signals or the low-side PM signals; and generating a disturbance signal in response to detecting the one or more absences.

[0009] In some examples, this disclosure describes a system comprising: a three-phase electric motor; and a plurality of half-bridge circuits, each comprising a high-side power switch and a low-side power switch arranged in a half-bridge configuration, wherein each of the half-bridge circuits controls a respective phase of the three-phase electric motor. For each of the plurality of half-bridge circuits, a respective driver circuit is configured to control the high-side power switch and the low-side power switch, and a processor is configured to generate control signals for each of the respective driver circuits. According to this disclosure, each of the respective driver circuits includes a logic circuit configured to monitor high-side PM signals and low-side PM signals.The high-side PM signals and the low-side PM signals are configured to switch the high-side power switch and the low-side power switch ON and OFF in a complementary manner, and the logic circuit is configured to detect one or more absences of either the high-side PM signals or the low-side PM signals and to generate a fault signal in response to detecting the one or more absences.

[0010] Details of these and other examples are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. Short description of the drawings Fig. 1 is a block diagram showing a bridge driver circuit configured to control power switches of an external half-bridge circuit. Fig. 2 is another block diagram showing a bridge driver circuit configured to control power switches of an external half-bridge circuit. Fig. 3 is another block diagram showing a bridge driver circuit configured to control power switches of an external half-bridge circuit. Fig. Figure 4 is a circuit diagram showing three half-bridges arranged to control the operation of a three-phase electric motor. Fig. Figure 5 is a timing diagram showing pulse modulation (PM) signals associated with controlling high-side and low-side power switches of an external half-bridge circuit. Fig. Figure 6 is a timing diagram showing PM signals and loss of signals on a high side. Fig. Figure 7 is a timing diagram showing PM signals and loss of signals on a low side. Fig. 8 is a system diagram consistent with one or more examples of this disclosure. Fig. 9 and Fig. 10 are flowcharts illustrating techniques according to this disclosure. Detailed description

[0011] This disclosure describes circuits and techniques for monitoring power switch control signals, e.g., so-called pulse modulation (PM) signals, associated with a high-side power switch and a low-side power switch arranged in a half-bridge configuration. The techniques may be useful for motor control or other applications using half-bridge circuits. For motor control, the techniques may be applied by one or more driver circuits controlling several different half-bridge circuits to control different phases of a multi-phase electric motor. Half-bridge circuits are also referred to herein as "half-bridges."

[0012] According to this disclosure, the half-bridge circuit is controlled in a complementary manner, where the low-side power switch is ON when the high-side power switch is OFF, and the high-side power switch is ON when the low-side power switch is OFF. The techniques of this disclosure may include monitoring PM signals associated with a driver circuit of the high-side power switch and the low-side power switch of a half-bridge circuit. The expectation is that the low-side power switch is ON-controlled by the PM signals when the high-side power switch is OFF-controlled by the PM signals, and the high-side power switch is ON-controlled by the PM signals when the low-side power switch is OFF-controlled by the PM signals. The driver circuit may be configured to detect one or more absences of either the high-side PM signals or the low-side PM signals.The driver circuit may be further configured to generate a disturbance signal in response to detecting the one or more absences.

[0013] In some cases, a single missing PM signal in either the high-side or low-side may indicate a circuit problem or a signaling problem. However, generating a fault in response to a single missing PM signal may also result in false alarms or incorrect faults. Therefore, in some examples, a counter may be used to detect consecutive instances of missing (but expected) high-side PM signals or low-side PM signals. In this case, the driver circuit may be configured to generate a fault signal in response to detecting a plurality of consecutive absences, e.g., two or more consecutive absences, likely indicating a signaling problem in the driver circuit or elsewhere.

[0014] PM signals can include input control signals from a processor to a driver circuit, input signals from a digital core of the driver circuit to high-side and low-side drivers, or output signals from the high-side and low-side drivers. Monitoring these different PM signal locations can provide different advantages and disadvantages relative to each other. In some cases, monitoring can be performed at each of these different PM signals, which can help pinpoint a circuit element or circuit location likely causing the problem. When monitoring the output signals from the high-side and low-side drivers, a level-shifting operation may also be desirable to improve the ability to monitor the signals within a smaller voltage range than that provided by the drive signals applied to the gates of the power switches. Several different examples are described in detail below.

[0015] Fig. 1 is a block diagram of a bridge driver circuit 102 configured to control power switches 142, 144 of an external half-bridge circuit 104. Power switches 142 and 144 are arranged in a half-bridge configuration. The high-side power switch 142 may be coupled to a first supply side (e.g., a supply voltage), and the low-side power switch 144 may be coupled to a second supply side (e.g., ground). A switch node 145, located between the high-side power switch 142 and the low-side power switch 144, may correspond to a control node for another device. For example, the switch node 145 may be connected to a multi-phase electric motor, and the external half-bridge circuit 104 may be configured to control a phase of the multi-phase electric motor.

[0016] Bridge driver circuit 102 includes a high-side driver 120 configured to drive a gate of high-side power switch 142 based on high-side PM signals, and bridge driver circuit 102 also includes a low-side driver 122 configured to drive a gate of low-side power switch 144 based on low-side PM signals. The high-side PM signals and the low-side PM signals are generally configured to turn the high-side power switch 142 and the low-side power switch 144 ON and OFF in a complementary manner. In other words, when operating in a complementary manner, the low-side power switch 144 is ON-controlled when the high-side power switch 142 is OFF-controlled, and the high-side power switch 142 is ON-controlled when the low-side power switch 144 is OFF-controlled.

[0017] In the Fig. 1, the bridge driver circuit 102 includes a digital core 110 that provides a digital interface with an external processor (in Fig. 1 not shown). The external processor may be connected to the bridge driver circuit 102 via input pins 132, 134 to the digital core 110. The high-side driver 120 and the low-side driver 122 may be connected to the digital core via pins 136, 138. Output pins (in Fig. 1 not shown) may connect the high-side driver 120 to the high-side power switch 142 and may connect the low-side driver 122 to the low-side power switch 144.

[0018] High-side driver 120 and low-side driver 122 may be configured to generate PM drive signals (e.g., PWM_drive_HS and PWM_drive_LS) based on PM control signals (e.g., PWM_out_HS and PWM_out_LS). High-side driver 120 and low-side driver 122 may each include an amplifier, a DC / DC power converter, a regulator, and / or one or more power switches that generate PM drive signals at the voltage level required to control high-side power switch 142 and low-side power switch 144.

[0019] The PM signals generally refer to any Fig. 1. Accordingly, the PM signals may take different forms (e.g., different voltage levels or amplitudes) as the signals propagate through the bridge driver circuit 102. In general, however, PM signals typically comprise square waves that define a high level (ON) and a low level (OFF). For example, the PM signals may include PWM_in_HS and PWM_in_LS, PWM_out_HS and PWM_out_LS, or PWM_drive_HS and PWM_drive_LS. This disclosure describes monitoring PM signals to detect unwanted absences, and monitoring different types of PM signals may have different benefits.

[0020] In the Fig. In the example shown in Figure 1, the digital core 110 includes a logic circuit 112 configured to monitor the high-side PM signals and the low-side PM signals. In this example, the monitored signals correspond to PMW_in_HS and PWM_in_LS received from the external processor at input pins 132, 134. The logic circuit 112 is configured to detect one or more absences of either the high-side PM signals or the low-side PM signals and to generate a fault signal (e.g., back to the external processor or other controller) in response to detecting the one or more absences. The logic circuit 112 may, for example, be configured to communicate the fault signal to the processor.

[0021] In some cases, a single missing PM signal in either the high-side or low-side may indicate a circuit problem or a signaling problem. However, generating a disturbance in response to a single missing PM signal may also result in false alarms or inaccurate disturbances. Accordingly, to reduce potential false alarms, logic circuit 112 includes a counter 114 configured to count consecutive absences of either the high-side PM signals or the low-side PM signals, and logic circuit 112 may be configured to generate the disturbance signal in response to a count of counter 114 reaching a count threshold. In this manner, counter 114 operates as a filtering mechanism, requiring consecutive missing (albeit expected) PM signals before logic circuit 112 generates the disturbance signal. The count threshold may, for example, be greater than 1 and less than 8.For motor control applications, a count threshold of 3 is typically sufficient to quickly identify problems while also limiting false alarms.

[0022] Again, in the Fig. 1, the high-side driver 120 is configured to generate high-side PM drive signals (PWM_drive_HS) based on high-side PM control signals (PWM_out_HS) output by the digital core 110, and the low-side driver 122 is configured to generate low-side PM drive signals (PWM_drive_LS) based on low-side PM control signals (PWM_out_LS) output by the digital core 110. In the example of Fig. 1, logic circuit 112 is configured to monitor PM control signals (e.g., PMW_in_HS and PWM_in_LS) at pins 132, 134 and detect the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the PM control signals (e.g., PMW_in_HS and PWM_in_LS) at pins 132, 134. In other words, the PM control signals monitored in bridge driver circuit 102 include input signals from a processor to a digital core 110. Therefore, a disturbance generated by logic 112 can pinpoint the signaling problem as likely coming from something upstream of digital logic 110, such as problems with the external processor, problems with pins 132, 134, or problems with the external wires connecting pins 132, 134 connect to the external processor.

[0023] Fig. 2 is a block diagram of an example bridge driver circuit 202 configured to control power switches 242, 244 of an external half-bridge circuit 204. Fig. 2 is the Fig. 1 in some aspects. Power switches 242 and 244 are arranged in a half-bridge configuration. The high-side power switch 242 may be coupled to a first supply side (e.g., a supply voltage), and the low-side power switch 244 may be coupled to a second supply side (e.g., ground). A switch node 245, located between the high-side power switch 242 and the low-side power switch 244, may correspond to a control node for another device. For example, the switch node 245 may be connected to a multi-phase electric motor, and the external half-bridge circuit 204 may be configured to control a phase of the multi-phase electric motor.

[0024] Bridge driver circuit 202 includes a high-side driver 220 configured to drive a gate of high-side power switch 242 based on high-side PM signals, and bridge driver circuit 202 also includes a low-side driver 222 configured to drive a gate of low-side power switch 244 based on low-side PM signals. The high-side PM signals and the low-side PM signals are generally configured to turn the high-side power switch 242 and the low-side power switch 244 ON and OFF in a complementary manner. In other words, when operating in a complementary manner, the low-side power switch 244 is ON-controlled when the high-side power switch 242 is OFF-controlled, and the high-side power switch 242 is ON-controlled when the low-side power switch 244 is OFF-controlled.

[0025] As in Fig. The example shown in Figure 1 includes the bridge driver circuit 202 of Fig. 2 a digital core 210 which has a digital interface with an external processor (in Fig. 2 not shown). The external processor may be connected to the bridge driver circuit 202 via input pins 232, 234 to the digital core 210. The high-side driver 220 and the low-side driver 222 may be connected to the digital core via pins 236, 238. Output pins (in Fig. 2 not shown) may connect the high-side driver 220 to the high-side power switch 242 and may connect the low-side driver 222 to the low-side power switch 244.

[0026] High-side driver 220 and low-side driver 222 may be configured to generate PM drive signals (e.g., PWM_drive_HS and PWM_drive_LS) based on PM control signals (e.g., PWM_out_HS and PWM_out_LS). High-side driver 220 and low-side driver 222 may include an amplifier, a DC / DC power converter, a regulator, and / or one or more power switches that generate PM drive signals at the level required to control high-side power switch 242 and low-side power switch 244.

[0027] As with the Fig. The example shown in Figure 1 refers to Fig. 2, the PM signals generally refer to any of the illustrated PWM signals. Accordingly, the PM signals may take different forms (e.g., different levels or amplitudes) as the signals propagate through the bridge driver circuit 202. In general, however, PM signals typically comprise square waves defining a high level (ON) and a low level (OFF). For example, the PM signals may include PWM_in_HS and PWM_in_LS, PWM_out_HS and PWM_out_LS, or PWM_drive_HS and PWM_drive_LS. This disclosure describes monitoring PM signals to detect unwanted absences, and monitoring different types of PM signals may have different benefits.

[0028] In the Fig. In the example shown in Figure 2, the bridge driver circuit 202 includes a logic circuit 212 configured to monitor the high-side PM signals and the low-side PM signals. In this example, the monitored signals correspond to PMW_out_HS and PWM_out_LS, which are the signals output by the digital core 210 at pins 236, 238. The logic circuit 212 is configured to detect one or more absences of either the high-side PM signals or the low-side PM signals and to generate a fault signal (e.g., back to the external processor or other controller) in response to detecting the one or more absences. The logic circuit 212 may, for example, be configured to communicate the fault signal to the processor.

[0029] Again, a single missing PM signal in either the high-side or low-side may indicate a circuit problem or a signaling problem. However, generating a disturbance in response to a single missing PM signal may also result in false alarms or inaccurate disturbances. Accordingly, to reduce potential false alarms, logic circuit 212 includes a counter 214 configured to count consecutive absences of either the high-side PM signals or the low-side PM signals, and logic circuit 212 may generate the disturbance signal in response to a count of counter 214 reaching a count threshold. In this manner, counter 214 operates as a filtering mechanism, requiring consecutive missing (albeit expected) PM signals before logic circuit 212 generates the disturbance signal. The count threshold may, for example, be greater than 1 and less than 8.For motor control applications, a count threshold of 3 is typically sufficient to quickly identify problems while also limiting false alarms.

[0030] The high-side driver 220 is configured to generate high-side PM drive signals (PWM_drive_HS) based on high-side PM control signals (PWM_out_HS) output by the digital core 210, and the low-side driver 222 is configured to generate low-side PM drive signals (PWM_drive_LS) based on low-side PM control signals (PWM_out_LS) output by the digital core 210. Unlike Fig. 1 is the logic circuit 212 in the example of Fig. 2 configured to monitor other PM control signals (e.g., PMW_out_HS and PWM_out_LS) at pins 236, 238, and detect the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the PM control signals (e.g., PMW_out_HS and PWM_out_LS) at pins 236, 238. In other words, the PM control signals monitored in the bridge driver circuit 202 include output signals from the digital core 210. Therefore, a disturbance generated by logic 212 may generally be a signaling problem coming from the digital core 210, problems with the external processor, problems with pins 232, 234, problems with pins 236, 238, or problems with the external wires connecting pins 232, 234 to the external processor. Accordingly, the Fig. 2 has more potential errors than the example of Fig. 1, although it is somewhat less precise in identifying the cause of the error.

[0031] It is also possible to use the example of Fig. 1 with that of Fig. 2 to help pinpoint the location of any fault. For example, if both logic circuit 112 and logic circuit 212 were used within bridge driver circuit 102 or 202, then a fault identified by logic circuit 212 and not identified by logic circuit 112 would indicate a problem with digital core 110, 210, and a fault identified by logic circuit 212 and identified by logic circuit 112 would likely indicate problems with the external processor, problems with pins 132, 232, 134, 234, or problems with the external wires connecting pins 132, 232, 134, 234 to the external processor.

[0032] Fig. 3 is another block diagram of an example bridge driver circuit 302 configured to control power switches 342, 344 of an external half-bridge circuit 304. Fig. 3 is the Fig. 1 and Fig. 2 in some aspects. Power switches 342 and 344 are arranged in a half-bridge configuration. The high-side power switch 342 may be coupled to a first supply side (e.g., a supply voltage), and the low-side power switch 344 may be coupled to a second supply side (e.g., ground). Of course, in the examples of Fig. 1, Fig. 2 or Fig. 3 other high-side or low-side supplies can also be used (e.g., a floating or ground reference voltage). As in Fig. 1 and Fig. 2 is located in Fig. 3, a switch node 345 is located between high-side power switch 342 and low-side power switch 344 and may correspond to a control node for another device. For example, switch node 345 may be connected to a multi-phase electric motor, and external half-bridge circuit 304 may be configured to control a phase of the multi-phase electric motor.

[0033] As in other examples, the bridge driver circuit 302 in Fig. 3, a high-side driver 320 configured to drive a gate of high-side power switch 342 based on high-side PM signals, and the bridge driver circuit 302 also includes a low-side driver 322 configured to drive a gate of low-side power switch 344 based on low-side PM signals. The high-side PM signals and the low-side PM signals are generally configured to switch the high-side power switch 342 and the low-side power switch 344 ON and OFF in a complementary manner. In other words, when operating in a complementary manner, the low-side power switch 344 is ON-controlled when the high-side power switch 342 is OFF-controlled, and the high-side power switch 342 is ON-controlled when the low-side power switch 344 is OFF-controlled.

[0034] As in Fig. 1 and Fig. The example shown in Figure 2 includes the bridge driver circuit 302 of Fig. 3 a digital core 310 which has a digital interface with an external processor (in Fig. 3 not shown). The external processor may be connected to the bridge driver circuit 302 via input pins 332, 334 with the digital core 310. The high-side driver 320 and the low-side driver 322 may be connected to the digital core via pins 336, 338.

[0035] Output pins 352, 353 (i.e., outputs of the bridge driver circuit 302) may connect the high-side driver 320 to the high-side power switch 342 and may connect the low-side driver 322 to the low-side power switch 344.

[0036] High-side driver 320 and low-side driver 322 may be configured to generate PM drive signals (e.g., PWM_drive_HS and PWM_drive_LS) based on PM control signals (e.g., PWM_out_HS and PWM_out_LS). High-side driver 320 and low-side driver 322 may include an amplifier, a DC / DC power converter, a regulator, and / or one or more power switches that generate PM drive signals at the level required to control high-side power switch 342 and low-side power switch 344.

[0037] As with the Fig. 1 and Fig. 2 examples shown refer to Fig. 3, the PM signals generally refer to any of the illustrated PWM signals. Accordingly, the PM signals may take different forms (e.g., different levels or amplitudes) as the signals propagate through the bridge driver circuit 302. In general, however, PM signals typically comprise square waves defining a high level (ON) and a low level (OFF). For example, the PM signals may include PWM_in_HS and PWM_in_LS, PWM_out_HS and PWM_out_LS, or PWM drive_HS and PWM_drive_LS. This disclosure describes monitoring PM signals to detect unwanted absences, and monitoring different types of PM signals may have different benefits.

[0038] In the Fig. 3, the bridge driver circuit 302 includes a logic circuit 312 configured to monitor the high-side PM signals and the low-side PM signals. In this example, the bridge driver circuit 302 further includes a level shifter circuit 360 configured to level-shift versions of PWM_drive_HS and PWM_drive_LS, which may include feedback signals having lower amplitudes than the PM drive signals. In this case, the monitored signals correspond to PMW_FB_HS and PWM_FB_LS, which are level-shifted versions of the high-side PM drive signals and the low-side PM drive signals. As in other examples, the logic circuit 312 is configured to detect one or more absences of either the high-side PM signals or the low-side PM signals and to generate a disturbance signal (e.g.,back to the external processor or other controller) in response to detecting the one or more absences. Logic circuit 312 may, for example, be configured to communicate the fault signal to the processor.

[0039] As with other examples, the Fig. 3, a single missing PM signal in either the high-side or the low-side may indicate a circuit problem or a signaling problem. However, generating a disturbance in response to a single missing PM signal may also result in false alarms or inaccurate disturbances. Accordingly, to reduce potential false alarms, logic circuit 312 includes a counter 314 configured to count consecutive absences of either the high-side PM signals or the low-side PM signals, and logic circuit 312 may generate the disturbance signal in response to a count of counter 314 reaching a count threshold. In this manner, counter 314 operates as a filtering mechanism, requiring consecutive missing (albeit expected) PM signals before logic circuit 312 generates the disturbance signal. The count threshold may, for example, be greater than 1 and less than 8.Again, as indicated above, for motor control applications, a count threshold of 3 is typically sufficient to quickly identify problems while also limiting false alarms.

[0040] The high-side driver 320 is configured to generate high-side PM drive signals (PWM_drive_HS) based on high-side PM control signals (PWM_out_HS) output by the digital core 310, and the low-side driver 322 is configured to generate low-side PM drive signals (PWM_drive_LS) based on low-side PM control signals (PWM_out_LS) output by the digital core 310. Unlike in Fig. 1 and Fig. 2 is in the example of Fig. 3 Logic circuit 312 configured to monitor different PM signals (e.g., level-shifted versions of the PM driver signals shown as PMW_FB_HS and PWM_FB_LS) at pins 352, 354, and detect the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the level-shifted PM control signals (e.g., PMW_FB_HS and PWM_FB_LS) at pins 352, 354. In other words, the PM signals monitored in bridge driver circuit 302 are level-shifted versions of the driver signals sent from bridge driver circuit 302 to external half-bridge 304.Therefore, a fault generated by logic 312 may generally indicate a problem originating from drivers 320, 322, a problem with output pins 352, 354, a problem with digital core 310, problems with the external processor, problems with pins 332, 334, problems with pins 336, 338, or problems with the external wires connecting pins 332, 334 to the external processor. Accordingly, the fault described in . Fig. 3 even more potential errors than the examples of Fig. 1 and Fig. 2, although it is somewhat less precise in identifying the cause of the error.

[0041] It is also possible to use the examples of Fig. 1, Fig. 2 and Fig. 3 to help pinpoint the location of any fault. For example, if logic circuits 112, 212, and 312 were all used within bridge driver circuits 102, 202, and 302, then a fault identified by one logic circuit and not identified by another logic circuit may help pinpoint the location of the problem within bridge driver circuits 102, 202, and 302, whereas a fault identified by all logic circuits 112, 212, and 312 (if used in combination) would indicate a likely problem external to bridge driver circuits 102, 202, and 302.

[0042] Fig. Figure 4 is a circuit diagram showing three half-bridges (e.g., three half-bridge circuits) arranged to control the operation of an electric motor 420. Power switches 404A and 406A define a first half-bridge circuit, power switches 404B and 406B define a second half-bridge circuit, and power switches 404C and 406C define a third half-bridge circuit. Each in Fig. 4 can be compared to the half-bridge circuits 104, 204, 304 of Fig. 1 - 3 be similar and each in Fig. 4 can be replaced by a half-bridge driver circuit similar to the external half-bridge driver circuit 102, 202 or 302 of Fig. 1 - 3. Separate bridge driver circuits (similar to bridge driver circuits 102, 202, 302) could also be used for each Fig. The circuit breaker shown in Figure 3 can be used.

[0043] Accordingly, in this disclosure, a plurality of high-side drivers 120, 220, 320 and a plurality of low-side drivers 122, 222, 322 are configured to control a plurality of half-bridge circuits, such as in Fig. 4, wherein the plurality of half-bridge circuits are configured to control a multi-phase electric motor 420. In this case, a respective bridge driver circuit 102, 202, 302 for each of the plurality of half-bridge circuits includes a respective logic circuit 112, 212, 312 configured to detect one or more absences of either the high-side PM signals or the low-side PM signals for a respective one of the plurality of half-bridges and generate the fault signal in response to detecting the one or more absences. Counters 114, 214, 314 can enhance fault detection, wherein the respective logic circuit 112, 212, 312 defines a count threshold at which consecutive absences of expected PM signals indicate the fault.

[0044] In general, a motor drive circuit or system often uses half-bridge circuits. Half-bridge circuits may include two MOSFETs driven by a bridge driver circuit. Bridge driver ICs used in motor control applications for brushless DC motors, or BLDC (Brushless Direct Current) motors, typically have six PWM control inputs (two inputs per half-bridge), which are controlled externally by a processor (e.g., a microcontroller).

[0045] In circuits or systems used in safety-critical environments, the MOSFET control capabilities of the circuits may need to be tested for proper operation. The microcontroller can control the PWM inputs (which may include, for example, turn-on and turn-off requests). This rotates and controls the motor. The control signals for a half-bridge are typically set alternately high and low.

[0046] In the case where a PWM control input does not propagate correctly through the bridge driver circuit (e.g., due to an open pin event, missing bond wires, internal IC single point failures, or other problems), the motor control scheme may be severely impacted (e.g., causing a reduction or even loss of motor torque), although no error will be reported if the circuit interprets the event as an intended microcontroller request.

[0047] The circuits and techniques described here can provide a technical solution for detecting and reporting a PWM control scheme that does not properly alternate the high-side and low-side drivers in each PWM cycle.

[0048] In some BLDC motor control systems, a processor or microcontroller may be responsible for detecting an unintended OFF situation by performing a plausibility check of the motor current and phase feedback function. However, with this approach, problems can only be detected through external safety measures, which imply increased complexity and limitations at the system level, as unintended motor torque reduction is difficult to evaluate in real time, as it involves a disturbance in the PWM signal propagation path. Thus, a downside of this approach is that it cannot be reliably applied in all BLDC motor control systems.If a single current detection is used for all three motor phases, the plausibility check cannot be performed because there is no redundancy at the microcontroller level to use as a detection mechanism of an unintended OFF event due to loss of a PWM control signal.

[0049] The technical solutions proposed here can monitor the PWM control scheme for each half-bridge driver circuit. In BLDC motor control circuits and systems, each half-bridge is expected to receive a PWM control pattern that ensures alternating high-side and low-side MOSFET phases during each PWM period.

[0050] The bridge driver circuits described here can implement digital logic that strictly checks for the presence of alternation on two (e.g., high-side and low-side) pins of the PWM control of each half-bridge. If an ON request for a MOSFET in the half-bridge is detected multiple times without any complementary ON request, a fault can be reported via an SPI register or via a device fault pin, if such a pin is available on the microcontroller.

[0051] Various advantages of this approach can include: - The correct PWM functionality is continuously monitored during operation, no self-test or plausibility check is required - The digital logic used to detect the PWM alternation presence does not limit the motor control scheme in any way - This approach provides full system-level flexibility to adjust the number of consecutive PWM ON detections on a MOSFET, although the complementary ON requirement is missing.

[0052] Thus, the described circuits and techniques provide a simple and effective mechanism for detecting and reporting a stuck OFF condition on a PWM input pin. By implementing monitoring in the bridge driver circuit, it may also be possible to reduce the external processing load that would otherwise be required for external sanity checks.

[0053] Fig. Figure 5 is a timing diagram showing PM signals associated with controlling high-side and low-side power switches of an external half-bridge circuit. Fig. The PM signals illustrated in Figure 5 are labeled PWM HS (for the high-side transistor) and PWM LS (for the low-side transistor). PWM HS and PWM LS can be assigned to any of the Fig. 1 - 3 discussed PWM signals. Fig. Figure 5 generally shows normal operation of the PM signals, where the PWM HS and the PWM LS define alternating and complementary ON and OFF states.

[0054] Fig. Figure 6 is a timing diagram showing PM signals and signal loss on a high side. The PM signals in Fig. 6 are those of Fig. 5 similar, but in Fig. 6 there is a lack of the PM signal at locations 601, 602 and 603. A logic circuit 112, 212, 312 may be configured to Fig. 6 and to count any absences of expected PM signals. For example, a counter 114, 214, 314 may count absences of the PM signal at locations 601, 602, and 603, e.g., as shown at locations 601, 602, and 603, incrementing a count to 1, 2, 3, respectively. The logic circuit 112, 212, 312 may respond to the count reaching a threshold, e.g., B. Counter = 3 at location 603. When the counter 114, 214, 314 reaches this threshold (e.g., Counter = 3), the logic circuit 112, 212, 312 may output a fault to a control processor, which may take appropriate action, such as blocking the bridge driver 102, 202, 302 or operating the bridge driver 102, 202, 302 in a safe mode. The safe mode for motor control may include a lower-power mode than normal operation and may facilitate a so-called "limp home" operation of an electric vehicle.The electric motor may have reduced torque and horsepower in the "Limp Home" mode than in the electric vehicle's normal operating mode.

[0055] Fig. 7 is a timing diagram showing Fig. 6 is similar in many respects. Fig. 6 missing (but expected) PM signals on the high side, Fig. 7 missing (but expected) PM signals on the low side. A logic circuit 112, 212, 312 can be configured to Fig. 7 and to count any absences of expected PM signals. For example, consistent with Fig. 7, a counter 114, 214, 314 counts absences of the PM signal at locations 701, 702, and 703, e.g., incrementing a count value to 1, 2, 3, respectively, as shown at locations 701, 702, and 703. The logic circuit 712, 712, 712 may respond to the count value reaching a threshold, e.g., B. Counter = 3 at location 703. When the counter 114, 214, 314 reaches this threshold (e.g., Counter = 3), the logic circuit 112, 212, 312 may output a fault to a control processor, which may take appropriate action, such as blocking the bridge driver 102, 202, 302 or operating the bridge driver 102, 202, 302 in a safe mode. Again, the safe mode for motor control may include a lower power mode than normal operation and may facilitate a so-called "limp home" operation of an electric vehicle.The electric motor may have reduced torque and horsepower in the "Limp Home" mode than in the electric vehicle's normal operating mode.

[0056] Fig. Figures 5 - 7 generally represent scenarios where a logic high level implies a corresponding MOSFET ON request. The PWM control scheme for a MOSFET half-bridge is shown in Fig. 5 correctly applied. In contrast, the PWM control signals can be forced to either the low-side (LS) or the high-side (HS), resulting in Fig. 6 and Fig. 7 a special MOSFET PWM input is stuck OFF, which implies a problem.

[0057] With the proposed implementation described here, there can be a digital logic for each half-bridge (for monitoring PWM_HS, PWM_LS pin pairs) in which the following control scheme is applied to the synchronized internal PWM signals: - A PWM low-high transition (no matter if HS or LS) in logic 112, 212, 312 enables a state machine. - For the next PWM low-high transition: - if it is on the complementary PWM input, the state machine is restarted - if it is on the same PWM input as the previous transition, then an error counter 114, 214, 314 is started - a PWM low-high transition detection on complementary PWM input resets the error counter 114, 214, 314 - When the error count reaches a configured value or consecutive PWM ON requests occur on the same MOSFET, PWM stuck on the complementary PWM input is reported (e.g., to processor 801) and the system responds (e.g., such as by reporting the error, turning OFF the corresponding half-bridge, modifying system operation to operate in a safe state, or possibly turning OFF all MOSFETs).

[0058] Fig. 8 is a system diagram consistent with one or more examples of this disclosure. A processor 801 generates PM control signals and provides the PM control signals to bridge driver circuits 802A, 802B, 802C. The bridge driver circuits generate PM control signals based on the PM control signals and drive three different half-bridge circuits 804A, 804B, 804C to control these three phases of a brushless DC motor, or BLDC motor, 806. The BLDC motor 806 may correspond to any BLDC motor application, and the electric vehicle motor is merely one example application.

[0059] The bridge driver circuits 802A, 802B, 802C may each correspond to bridge driver circuits 102, 202, or 302. If a fault is detected by the logic circuit 112, 212, 312 for any of the bridge driver circuits 802A, 802B, 802C, the respective bridge driver circuit may return a fault signal to the processor 801, and the processor may take appropriate action to ensure safe operation of the system, such as blocking the system, blocking the respective bridge driver circuit that issued the fault, or possibly implementing a different "safe" or "low power" mode of operation for some or all of the bridge driver circuits 802A, 802B, 802C.

[0060] Fig. 9 and Fig. 10 are flowcharts illustrating techniques according to this disclosure. Fig. 9 may also be viewed as a state diagram illustrating a control scheme performed by a bridge driver circuit consistent with this disclosure.

[0061] In the Fig. In the example shown in Figure 9, after starting up a bridge driver circuit 102, 202, 302 (902), a logic circuit 112, 212, 312 may determine whether a half-bridge circuit 104, 204, 304 is enabled to permit PWM control (904). If so (YES branch of 904), the logic circuit 112, 212, 312 may wait until PWM_HS or PWM_LS-ON requests are detected (906). Fig. 9, the PWM_HS and PWM_LS ON requests may correspond to any of the PM signals described here. Upon detecting a PWM_ON request (YES branch of 908), logic circuitry 112, 212, 312 may then wait for a next PWM_ON request (910). If the next ON request comes from a different PWM input, e.g., a different high-side or low-side (not a branch of 912), counter 114, 214, 314 is reset (914). However, if the next ON request comes from the same PWM input (YES branch of 912), counter 114, 214, 314 is incremented. This process continues as long as the counter 114, 214, or 314 has not yet reached its limit or threshold (no branch from 918). If the counter 114, 214, or 314 reaches its limit or threshold (YES branch from 918), this means that a certain (e.g., predefined) number of consecutive PM signals is missing (although expected).In this case, the logic circuit 112, 212, 312 may report the missing PWM operations (920), e.g., by sending a fault signal back to the processor 801.

[0062] Fig. 10 is another flowchart consistent with this disclosure. As in Fig. As shown in Figure 10, a bridge driver circuit 102, 202, 302 drives a high-side transistor 142, 242, 342 (1001) and drives a low-side transistor 144, 244, 344 (1002) in a complementary manner. Doing so, logic circuit 112, 212, 312 monitors the PM signals (1003) to check for missing or absent signals. If there are no missing PM signals (no branch from 1004), counter 114, 214, 314 is reset (1005). Upon detecting a missing PM signal on either the high-side or low-side, logic circuit 112, 212, 312 increments a count (1006). Normal control continues as long as the counter 114, 214, 314 has not yet reached its counting threshold (“No” branch of 1007).Once the counter 114, 214, 314 has not yet reached its count threshold ("Yes" branch of 1107), indicating a predefined number of consecutive absent PM signals on either the high side or the low side, the logic circuit 112, 212, 312 may output a fault signal back to the processor 801 (1008). Thus, the logic circuit 112, 212, 312, maintains consistent with . Fig. 9 and Fig. 10, a count value indicative of consecutive absences of either high-side PM signals or low-side PM signals, and, in response to the count value reaching a count threshold, generates the disturbance signal.

[0063] The circuits and techniques described here can be part of a safety mechanism designed to ensure safe operation of an electric motor and other circuits attached to the electric motor. The techniques described can improve fault detection in a motor control system. Indeed, the techniques can significantly reduce packet failure rates in circuit- and system-level safety analysis.

[0064] By using an internal PWM monitoring state machine for each half-bridge: - Bridge driver circuits may be capable of detecting package faults (open pins or missing bond wires) or system faults (fault events on PCB traces or microcontroller IOs) that cannot otherwise be detected or differentiated by typical external safety mechanisms (sanity checks) at the microcontroller or processor level; - the microcontroller or processor can outsource this more reliable detection, which may eliminate or reduce the need for plausibility checks at the system level; - at the system level, the missing or stuck PWM scenarios can be clearly identified by direct monitoring mechanisms, instead of indirect measurements of motor phase pins (phase feedback monitoring) or drain-source monitoring of MOSFETs or periodic sanity checks that imply interrupting the intended motor operation; - PWM monitoring can be performed on each PWM cycle, thus defining a continuous testing and monitoring scheme.

[0065] The techniques described in this disclosure may be implemented, at least in part, in circuitry, hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented within one or more logic elements, processors, including one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuitry, as well as any combinations of such components.The term "processor" or "processing circuitry" may generally refer to any of the foregoing logic circuitry, alone or in combination with other logic circuitry, or any other equivalent circuitry. A hardware-comprising control unit may also perform one or more of the techniques of this disclosure.

[0066] Such hardware, software, and firmware may be implemented within the same device or within separate devices to support the various operations and functions described in this disclosure. Furthermore, any of the described units, modules, or components may be implemented together or separately as discrete but cooperating logic devices. Representation of various features as modules or units is intended to emphasize different functional aspects and does not necessarily imply that such modules or units must be implemented by separate hardware or software components. Rather, functionality associated with one or more modules or units may be performed by separate hardware or software components or may be integrated within common or separate hardware or software components.

[0067] It may also be possible for one or more aspects of this disclosure to be performed in software, in which case the techniques described in this disclosure may also be implemented or encoded in a computer-readable medium, such as a computer-readable storage medium containing instructions. Instructions embedded or encoded in a computer-readable storage medium may cause a programmable processor or other processor to perform the method, for example, upon execution of the instructions. Computer-readable storage media may include random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EFPROM), flash memory, or other computer-readable media.

[0068] The following paragraphs may illustrate one or more aspects of the disclosure.

[0069] Paragraph 1 - A driver circuit configured to control a high-side power switch and a low-side power switch arranged in a half-bridge configuration, the driver circuit comprising: a high-side driver configured to drive a gate of the high-side power switch based on high-side PM signals; a low-side driver configured to drive a gate of the low-side power switch based on low-side PM signals;and a logic circuit configured to monitor the high-side PM signals and the low-side PM signals, wherein the high-side PM signals and the low-side PM signals are configured to switch the high-side power switch and the low-side power switch ON and OFF in a complementary manner, and wherein the logic circuit is configured to detect one or more absences of either the high-side PM signals or the low-side PM signals and to generate a fault signal in response to detecting the one or more absences.;

[0070] Paragraph 2 - The driver circuit of paragraph 1, wherein the logic circuit is arranged to communicate the fault signal to a processor.

[0071] Paragraph 3 - The driver circuit of paragraph 1 or 2, wherein the high-side driver is configured to generate high-side PM driver signals based on high-side PM control signals output from a digital core, wherein the low-side driver is configured to generate low-side PM driver signals based on low-side PM control signals output from the digital core, and wherein the logic circuit is configured to monitor PM control signals and detect the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the PM control signals.

[0072] Paragraph 4 - The driver circuit of paragraph 3, wherein the PM control signals comprise input signals from a processor to the digital core.

[0073] Paragraph 5 - The driver circuit of paragraph 3, wherein the PM control signals comprise the high-side PM control signals output from the digital core to the high-side driver and the low-side PM control signals output from the digital core to the low-side driver.

[0074] Paragraph 6 - The driver circuit of paragraph 1 or 2, further comprising a level shifter circuit, wherein the high-side driver is configured to generate high-side PM driver signals based on high-side PM control signals output from a digital core, wherein the low-side driver is configured to generate low-side PM driver signals based on low-side PM control signals output from the digital core, wherein the level shifter circuit is configured to generate level-shifted versions of the high-side PM driver signals and the low-side PM driver signals,and wherein the logic circuit is configured to monitor the level-shifted versions of the high-side PM driver signals and the low-side PM driver signals and detect the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the level-shifted versions of the high-side PM driver signals and the low-side PM driver signals.

[0075] Paragraph 7 - The driver circuit of any one of paragraphs 1-6, wherein the logic includes a counter configured to count consecutive absences of either the high-side PM signals or the low-side PM signals, and generate the disturbance signal in response to a count value of the counter reaching a count threshold.

[0076] Paragraph 8 - The driver circuit of paragraph 7, wherein the count threshold is greater than 1 and less than 8.

[0077] Paragraph 9 - The driver circuit of paragraph 8, where the count threshold is 3.

[0078] Paragraph 10 - The driver circuit of any one of paragraphs 1-9, further comprising a plurality of high-side drivers and a plurality of low-side drivers configured to control a plurality of half-bridges.

[0079] Paragraph 11 - The driver circuit of paragraph 10, wherein the plurality of half-bridges is configured to control a multi-phase electric motor.

[0080] Paragraph 12 - The driver circuit of paragraph 10 or 11, wherein for each of the plurality of half-bridges, the driver circuit includes a respective logic circuit configured to detect one or more absences of either the high-side PM signals or the low-side PM signals for a respective one of the plurality of half-bridges and generate the disturbance signal in response to detecting the one or more absences.

[0081] Paragraph 13 - A method for controlling a high-side power switch and a low-side power switch arranged in a half-bridge configuration, the method comprising: driving a gate of the high-side power switch based on high-side PM signals; driving a gate of the low-side power switch based on low-side PM signals; and monitoring the high-side PM signals and the low-side PM signals, wherein the high-side PM signals and the low-side PM signals are configured to turn the high-side power switch and the low-side power switch ON and OFF in a complementary manner, and wherein monitoring includes: detecting one or more absences of either the high-side PM signals or the low-side PM signals; and generating a disturbance signal in response to detecting the one or more absences.

[0082] Paragraph 14 - The method of paragraph 13, further comprising: communicating the fault signal to a processor.

[0083] Paragraph 15 - The method of paragraph 13 or 14, wherein a high-side driver is configured to generate high-side PM drive signals based on high-side PM control signals output from a digital core, wherein a low-side driver is configured to generate low-side PM drive signals based on low-side PM control signals output from the digital core, and wherein monitoring the high-side PM signals and the low-side PM signals includes monitoring PM control signals and detecting the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the PM control signals.

[0084] Paragraph 16 - The method of paragraph 13 or 14, wherein a high-side driver is configured to generate high-side PM driver signals based on high-side PM control signals output from a digital core, wherein a low-side driver is configured to generate low-side PM driver signals based on low-side PM control signals output from the digital core, wherein a level shifter circuit is configured to generate level-shifted versions of the high-side PM driver signals and the low-side PM driver signals, and wherein monitoring the high-side PM signals and the low-side PM signals monitoring the level-shifted versions of the high-side PM driver signals and the low-side PM driver signals and detecting the one or more absences of either the high-side PM signals or the Low-side PM signals, based on monitoring the level-shifted versions of the high-side PM driver signals and the low-side PM driver signals,contains.,

[0085] Paragraph 17 - The method of any of paragraphs 13-16, further comprising: maintaining a count value indicative of consecutive absences of either the high-side PM signals or the low-side PM signals; and generating the disturbance signal in response to the count value reaching a count threshold.

[0086] Paragraph 18 - The procedure of paragraph 17, where the count threshold is greater than 1 and less than 6.

[0087] Paragraph 19 - The method of any one of paragraphs 13-18, the method comprising a method for controlling a plurality of high-side drivers and a plurality of low-side drivers configured to control a plurality of half-bridges, the plurality of half-bridges configured to control a multi-phase electric motor.

[0088] Paragraph 20 - The method of paragraph 19, further comprising, for each of the plurality of half-bridges, detecting one or more absences of either the high-side PM signals or the low-side PM signals for a respective one of the plurality of half-bridges and generating the disturbance signal in response to detecting the one or more absences.

[0089] Paragraph 21 - A system comprising: a three-phase electric motor; a plurality of half-bridge circuits, each comprising a high-side power switch and a low-side power switch arranged in a half-bridge configuration, each of the half-bridge circuits controlling a respective phase of the three-phase electric motor; for each of the plurality of half-bridge circuits, a respective driver circuit configured to control the high-side power switch and the low-side power switch;and a processor configured to generate control signals for each of the respective driver circuits, wherein: each of the respective driver circuits includes: a logic circuit configured to monitor high-side pulse modulation (PM) signals and low-side PM signals, wherein the high-side PM signals and the low-side PM signals are configured to switch the high-side power switch and the low-side power switch ON and OFF in a complementary manner, and wherein the logic circuit is configured to detect one or more absences of either the high-side PM signals or the low-side PM signals and to generate a fault signal in response to detecting the one or more absences.;

[0090] Paragraph 22 - The system of paragraph 21, wherein for each of the respective driver circuits: a high-side driver is configured to generate high-side PM drive signals based on high-side PM control signals output from a digital core coupled to the processor, a low-side driver is configured to generate low-side PM drive signals based on low-side PM control signals output from the digital core coupled to the processor, and the logic circuit is configured to monitor PM control signals and detect the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the PM control signals.

[0091] Paragraph 23 - The system of paragraph 21, wherein each of the respective driver circuits includes a level shifter circuit, wherein for each of the respective driver circuits: a high-side driver is configured to generate high-side PM driver signals based on high-side PM control signals output from a digital core connected to the processor, a low-side driver is configured to generate low-side PM driver signals based on low-side PM control signals output from the digital core connected to the processor, the level shifter circuit is configured to generate level-shifted versions of the high-side PM driver signals and the low-side PM driver signals,and the logic circuit is configured to monitor the level-shifted versions of the high-side PM driver signals and the low-side PM driver signals and detect the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the level-shifted versions of the high-side PM driver signals and the low-side PM driver signals.

[0092] Various features and aspects have been described in this disclosure. These and other features and aspects are within the scope of the following claims.

Claims

[1] A driver circuit configured to control a high-side power switch and a low-side power switch arranged in a half-bridge configuration, the driver circuit comprising: a high-side driver configured to drive a gate of the high-side power switch based on high-side pulse modulation signals; a low-side driver configured to drive a gate of the low-side power switch based on low-side pulse modulation signals; and a logic circuit configured to monitor the high-side pulse modulation signals and the low-side pulse modulation signals, wherein the high-side pulse modulation signals and the low-side pulse modulation signals are configured to switch the high-side power switch and the low-side power switch ON and OFF in a complementary manner, and wherein the logic circuit is configured to detect one or more absences of either the high-side pulse modulation signals or the low-side pulse modulation signals and to generate a disturbance signal in response to detecting the one or more absences. [2] The driver circuit of claim 1, wherein the logic circuit is configured to communicate the fault signal to a processor. [3] Driver circuit according to claim 1 or 2, wherein the high-side driver is configured to generate high-side pulse modulation drive signals based on high-side pulse modulation control signals output from a digital core, wherein the low-side driver is configured to generate low-side pulse modulation drive signals based on low-side pulse modulation control signals output from the digital core, and wherein the logic circuit is configured to monitor pulse modulation control signals and detect the one or more absences of either the high-side pulse modulation signals or the low-side pulse modulation signals based on monitoring the pulse modulation control signals. [4] A driver circuit according to claim 3, wherein the pulse modulation control signals comprise at least one of the following: - Input signals from a processor to the digital core; or - the high-side pulse modulation control signals output from the digital core to the high-side driver and the low-side pulse modulation control signals output from the digital core to the low-side driver. [5] Driver circuit according to one of claims 1 to 4, further comprising a level shift circuit, wherein the high-side driver is configured to generate high-side pulse modulation drive signals based on high-side pulse modulation control signals output from a digital core, wherein the low-side driver is configured to generate low-side pulse modulation drive signals based on low-side pulse modulation control signals output from the digital core, wherein the level shifter circuit is configured to generate level-shifted versions of the high-side pulse modulation driver signals and the low-side pulse modulation driver signals, and wherein the logic circuit is configured to monitor the level-shifted versions of the high-side pulse modulation drive signals and the low-side pulse modulation drive signals and detect the one or more absences of either the high-side pulse modulation signals or the low-side pulse modulation signals based on monitoring the level-shifted versions of the high-side pulse modulation drive signals and the low-side pulse modulation drive signals. [6] The driver circuit of any one of claims 1 to 5, wherein the logic circuit includes a counter configured to count consecutive absences of either the high-side pulse modulation signals or the low-side pulse modulation signals and generate the disturbance signal in response to a count value of the counter reaching a count threshold. [7] The driver circuit of claim 6, wherein the count threshold is greater than 1 and less than 8 or wherein the count threshold is 3. [8] Driver circuit according to one of claims 1 to 7, further comprising a plurality of high-side drivers and a plurality of low-side drivers arranged to control a plurality of half-bridges. [9] Driver circuit according to claim 8, wherein the plurality of half bridges are arranged to control a multi-phase electric motor. [10] The driver circuit of claim 8 or 9, wherein for each of the plurality of half-bridges, the driver circuit includes a respective logic circuit configured to detect one or more absences of either the high-side pulse modulation signals or the low-side pulse modulation signals for a respective one of the plurality of half-bridges and generate the disturbance signal in response to detecting the one or more absences. [11] A method for controlling a high-side power switch and a low-side power switch arranged in a half-bridge configuration, the method comprising: Driving a gate of the high-side power switch based on high-side pulse modulation (pulse modulation) signals; Driving a gate of the low-side power switch based on low-side pulse modulation signals; and Monitoring the high-side pulse modulation signals and the low-side pulse modulation signals, wherein the high-side pulse modulation signals and the low-side pulse modulation signals are configured to switch the high-side power switch and the low-side power switch ON and OFF in a complementary manner, and where monitoring includes: Detecting one or more absences of either the high-side pulse modulation signals or the low-side pulse modulation signals; and Generating a disturbance signal in response to detecting the one or more absences. [12] The method of claim 11, further comprising: Communicating the fault signal to a processor. [13] Method according to claim 11 or 12, wherein a high-side driver is configured to generate high-side pulse modulation drive signals based on high-side pulse modulation control signals output from a digital core, wherein a low-side driver is configured to generate low-side pulse modulation drive signals based on low-side pulse modulation control signals output from the digital core, and wherein monitoring the high-side pulse modulation signals and the low-side pulse modulation signals includes monitoring pulse modulation control signals and detecting the one or more absences of either the high-side pulse modulation signals or the low-side pulse modulation signals based on monitoring the pulse modulation control signals. [14] Method according to one of claims 11 to 13, wherein a high-side driver is configured to generate high-side pulse modulation drive signals based on high-side pulse modulation control signals output from a digital core, wherein a low-side driver is configured to generate low-side pulse modulation drive signals based on low-side pulse modulation control signals output from the digital core, wherein a level shifter circuit is arranged to generate level-shifted versions of the high-side pulse modulation drive signals and the low-side pulse modulation drive signals, and wherein monitoring the high-side pulse modulation signals and the low-side pulse modulation signals includes monitoring the level-shifted versions of the high-side pulse modulation drive signals and the low-side pulse modulation drive signals, and detecting the one or more absences of either the high-side pulse modulation signals or the low-side pulse modulation signals based on monitoring the level-shifted versions of the high-side pulse modulation drive signals and the low-side pulse modulation drive signals. [15] A method according to any one of claims 11 to 14, further comprising: Maintaining a count value indicating consecutive absences of either the high-side pulse modulation signals or the low-side pulse modulation signals; and Generating the disturbance signal in response to the count value reaching a count threshold, optionally wherein the count threshold is greater than 1 and less than 6. [16] The method of any one of claims 11 to 15, wherein the method comprises controlling a plurality of high-side drivers and a plurality of low-side drivers configured to control a plurality of half-bridges, wherein the plurality of half-bridges is configured to control a multi-phase electric motor. [17] The method of claim 16, further comprising, for each of the plurality of half-bridges, detecting one or more absences of either the high-side pulse modulation signals or the low-side pulse modulation signals for a respective one of the plurality of half-bridges and generating the disturbance signal in response to detecting the one or more absences. [18] System comprising: a three-phase electric motor; a plurality of half-bridge circuits each comprising a high-side power switch and a low-side power switch arranged in a half-bridge configuration, each of the half-bridge circuits controlling a respective phase of the three-phase electric motor; for each of the plurality of half-bridge circuits, a respective driver circuit configured to control the high-side power switch and the low-side power switch; and a processor configured to generate control signals for each of the respective driver circuits, wherein: each of the respective driver circuits includes: a logic circuit configured to monitor high-side pulse modulation signals and low-side pulse modulation signals, wherein the high-side pulse modulation signals and the low-side pulse modulation signals are configured to switch the high-side power switch and the low-side power switch ON and OFF in a complementary manner, and wherein the logic circuit is configured to detect one or more absences of either the high-side pulse modulation signals or the low-side Pulse modulation signals and for generating a disturbance signal in response to detecting the one or more absences. [19] The system of claim 18, wherein for each of the respective driver circuits: a high-side driver is configured to generate high-side pulse modulation driver signals based on high-side pulse modulation control signals output by a digital core connected to the processor, a low-side driver is configured to generate low-side pulse modulation driver signals based on low-side pulse modulation control signals output by the digital core connected to the processor, and the logic circuit is arranged to monitor pulse modulation control signals and detect one or the multiple absences of either the high-side pulse modulation signals or the low-side Pulse modulation signals based on monitoring the pulse modulation control signals. [20] The system of claim 18 or 19, wherein each of the respective driver circuits includes a level shifter circuit, wherein for each of the respective driver circuits: a high-side driver is configured to generate high-side pulse modulation driver signals based on high-side pulse modulation control signals output by a digital core connected to the processor, a low-side driver is configured to generate low-side pulse modulation driver signals based on low-side pulse modulation control signals output by the digital core connected to the processor, the level shifter circuit is configured to generate level-shifted versions of the high-side pulse modulation driver signals and the low-side pulse modulation driver signals, and the logic circuit is configured to monitor the level-shifted versions of the high-side pulse modulation drive signals and the low-side pulse modulation drive signals and detect the one or more absences of either the high-side pulse modulation signals or the low-side pulse modulation signals based on monitoring the level-shifted versions of the high-side pulse modulation drive signals and the low-side pulse modulation drive signals.

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