Stress-relieved sawn quad flat no lead semiconductor package

Abstract

A semiconductor package features a relief recess in the molding compound that extends around the circumference over the conductors. The relief recess has a width greater than the thickness of the conductors beneath it. Top surfaces of the conductors may be exposed at the relief recess or covered by the molding compound beneath it. In either case, the height difference between the molding compound beneath the relief recess and the conductors beneath it is less than the thickness of the conductors beneath it. Much of the exposed side surface of the conductors is characteristic of sawn surfaces, including conductors that are free of vertical grooves or burrs along their lower edges. The semiconductor package is singulated by sawing through the conductors.

Description

TECHNICAL FIELD

[0001] This disclosure relates to the field of semiconductor packages. In particular, but not exclusively, this disclosure relates to quad-flat no-lead semiconductor packages. BACKGROUND

[0002] Quad-Flat No-Lead (QFN) packages have become a popular choice for compact and high-performance integrated circuit (IC) packaging. QFN packages have metal pads on the bottom of the package, enabling higher pin density in a smaller form factor. QFN packages have shorter electrical paths, resulting in lower inductance, reduced parasitic capacitance, and improved high-frequency performance. QFN packages offer simplified assembly processes, increased automation compatibility, and lower bill of materials costs. SUMMARY

[0003] A semiconductor package includes leads around a perimeter of the semiconductor package and a microelectronic component electrically coupled to a plurality of leads. An electrically insulating molding compound contacts the leads and the microelectronic component. The molding compound is recessed around the perimeter to provide a relief recess over a portion of each of the leads. The relief recess has a relief width that is greater than a thickness of the leads below the relief recess. In one aspect, the top surfaces of the leads may be exposed at the relief recess. In another aspect, the top surfaces of the leads may be covered by the molding compound below the relief recess. In both aspects, a height difference between the molding compound below the relief recess and the leads below the relief recess is less than the thickness of the leads below the relief recess.Exposed side surfaces of a majority of the conduits are characteristic of sawn surfaces. In one aspect, the characteristics of sawn surfaces may include that the exposed side surfaces of the majority of the conduits are free of vertical grooves. In another aspect, the characteristics of sawn surfaces may also include that the exposed side surfaces of the majority of the conduits have ridges along their lower edges.

[0004] The semiconductor package is formed by electrically coupling the microelectronic component to the leads and forming the molding compound on the leads and on the microelectronic component. A relief recess is formed in the molding compound around the perimeter above the leads, such that the molding compound is laterally recessed around the perimeter to provide the relief recess. The semiconductor package is singulated by sawing through the leads. In one aspect, the molding compound can be laterally recessed before the semiconductor package is singulated. In another aspect, the molding compound can be laterally recessed after the semiconductor package is singulated. SHORT DESCRIPTION OF THE CHARACTERS Fig. 1A to Fig. 1H are top, cross-sectional, and perspective views of a semiconductor package with a relief recess shown in successive stages of an exemplary formation process. Fig. 2A to Fig. 2H are top, cross-sectional, and perspective views of another semiconductor package having a relief recess shown in successive stages of an exemplary formation process. Fig. 3A to Fig. 3D are cross-sectional and perspective views of another semiconductor package with a relief recess shown in successive stages of an exemplary formation process. Fig. 4A and Fig. 4B are cross-sections of another semiconductor package with a relief recess shown in successive stages of an exemplary formation process. Fig. 5A to Fig. 5C are cross-sections of another semiconductor package with a relief recess shown in successive stages of an exemplary formation process. Fig. 6A to Fig. 6C are cross-sections of another semiconductor package with a relief recess shown in successive stages of an exemplary formation process. Fig. Figure 7 is a cross-section of a semiconductor package being singulated by a punching process. Fig. Figure 8 is a cross-section of a semiconductor package with exposed side surfaces of leads characteristic of sawn surfaces. DETAILED DESCRIPTION

[0005] The present disclosure is described with reference to the accompanying figures. The figures are not drawn to scale and are provided solely for the purpose of illustrating the disclosure. Hereinafter, some aspects of the disclosure are described by way of illustration with reference to example applications. It should be understood that numerous specific details, relationships, and procedures are set forth in order to provide an understanding of the disclosure. The present disclosure is not limited to the illustrated order of acts or events, as some acts may occur in different orders and / or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology according to the present disclosure.

[0006] A semiconductor package has leads around a perimeter of the semiconductor package. The leads are attached to a lead frame. A microelectronic component is electrically coupled to a plurality of leads. An electrically insulating molding compound is formed on the leads and the microelectronic component. The molding compound is recessed around the perimeter to provide a relief recess over a portion of each of the leads. The relief recess has a relief width, in a direction perpendicular to the perimeter, that is greater than a thickness of the leads below the relief recess. In one version, the relief recess may be formed such that the top surfaces of the leads are exposed at the relief recess. In another version, the relief recess may be formed such that the top surfaces of the leads may be covered with the molding compound below the relief recess.A height difference between the molding compound under the relief recess and the lines under the relief recess is less than the thickness of the lines under the relief recess.

[0007] The semiconductor package is singulated by sawing through the leads. Singulation by sawing enables the simultaneous formation of multiple semiconductor packages using the lead frame at the same time because the molding compound can be formed on all semiconductor packages in a single operation, which is not cost-effective for stamped (coined) singulation. Exposed side surfaces of a majority of the leads are characteristic of sawn surfaces. In one aspect, the characteristics of sawn surfaces may include the exposed side surfaces of the majority of the leads being free of vertical grooves. In another aspect, the characteristics of sawn surfaces may also include the exposed side surfaces of the majority of the leads having ridges along lower edges. In one version, the molding compound may be laterally recessed before the semiconductor package is singulated.In another version, the molding compound can be laterally recessed after the semiconductor package has been separated.

[0008] In an electronic system containing the semiconductor package, the leads are attached to a substrate, such as a printed circuit board, with solder joints connecting the leads to terminals on the substrate. Stresses develop in the solder joints due to the differential thermal expansion between the semiconductor package and the substrate. The relief cavity can advantageously reduce stress by reducing the transfer of stress in the molding compound to the leads.

[0009] It should be noted that terms such as above, below, above, below, and beneath may be used in this disclosure. These terms are not to be construed to limit the position or orientation of any structure or element, but are to be used to provide a spatial relationship between structures or elements.

[0010] The Fig. 1A to Fig. 1H are top, cross-sectional, and perspective views of a semiconductor package with a relief recess shown in successive stages of an exemplary formation process. Fig. 1A is a top view of the semiconductor package, and Fig. 1B is a cross-section of the semiconductor package in Fig. 1A in a first stage of education. With reference to the Fig. 1A and Fig. 1B, the semiconductor package 100 is formed using a lead frame 102. The lead frame 102 of this example accommodates additional semiconductor packages 100a besides the semiconductor package 100.

[0011] The semiconductor package 100 includes a plurality of leads 104 of the lead frame 102. Likewise, the additional semiconductor packages 100a also include a plurality of additional leads 104a of the lead frame 102. The semiconductor package 100 of this example includes a die pad 106 of the lead frame 102. Likewise, the additional semiconductor packages 100a also include additional die pads that are not specifically shown.

[0012] A microelectronic component 108 is attached to the die pad 106. The microelectronic component 108 may be configured as an integrated circuit, a discrete component such as a power transistor, a passive component such as a transformer or a filter, a MEMS (micro electromechanical system) component, a sensor, an actuator, a microfluidic component, or an electro-optical component such as a micromirror array component. The microelectronic component 108 may be attached to the die pad 106 by a die attach material 110, such as solder, an electrically conductive adhesive, an electrically insulating adhesive, or a eutectic metal alloy. Additional microelectronic components, not specifically shown, are attached to the additional die pads of the additional semiconductor packages 100a.

[0013] Electrical connections 112 are formed between the microelectronic component 108 and the leads 104. The electrical connections 112 may be wire connections 112, as shown in the Fig. 1A and Fig. 1B. Alternatively, the electrical connections 112 may be implemented, for example, as ribbon bonds, clips, leads on resin-coated copper, or solder bumps.

[0014] The molding compound 114 is formed on the lead frame 102, including the leads 104 and the additional leads 104a, the microelectronic component 108, and the electrical connections 112. The molding compound 114, in this example, is formed between a lower mold plate 116a and an upper mold plate 116b. The lower mold plate 116a contacts the lower surfaces of the leads 104. The molding compound 114 is electrically insulating. The molding compound 114 may include, for example, epoxy. The molding compound 114 may include filler particles such as silicon dioxide particles or aluminum oxide particles to reduce a thermal expansion coefficient of the molding compound 114.

[0015] Fig. 1C is a top view of the semiconductor package 100, and Fig. 1D is a cross-section of the semiconductor package 100 of Fig. 1C at a later stage of education. With reference to the Fig. 1C and Fig. 1D, the molding compound 114 is laterally recessed to provide a relief recess 118 in the molding compound 114 above the leads 104 and to provide additional relief recesses 118a in the molding compound 114 above the additional leads 104a. In this example, the relief recess 118 and the additional relief recesses 118a are formed by a relief sawing process using a relief saw blade 120. The relief recess 118 has a relief width 122, in a direction perpendicular to a perimeter 124 of the semiconductor package 100, that is greater than a line thickness 126 of the leads 104 below the relief recess 118. The relief saw blade 120 may form the relief recess 118 and the additional relief recesses 118a in a single pass, as shown in Fig. 1D. Alternatively, the relief recess 118 and the additional relief recesses 118a may be formed by two or more passes of the relief saw blade 120. Forming the relief recess 118 by the relief sawing process may advantageously provide flexibility to accommodate a wide variety of package dimensions and may advantageously offer low manufacturing costs compared to forming the relief recess 118 using package-specific molds. In this example, the upper surfaces of the leads 104 are not exposed by forming the relief recess 118, i.e., a portion of the molding compound 114 is left above the leads 104 below the relief recess 118, which may advantageously protect the leads 104 from contamination or chemical degradation.

[0016] Fig. 1E is a top view of the semiconductor package 100, and Fig. 1F is a cross-section of the semiconductor package 100 of Fig. 1E at a later stage of education. With reference to the Fig. 1E and Fig. 1F, the semiconductor package 100 and the additional semiconductor packages 100a are mounted on a saw band 128, also referred to as a saw foil 128. The semiconductor package 100 is singulated from the additional semiconductor packages 100a by a singulation sawing process using a singulation saw blade 130. The singulation sawing process cuts through and separates the leads 104 of the semiconductor package 100 and the additional leads 104a of the additional semiconductor packages 100a, as well as the molding compound 114 between the semiconductor package 100 and the additional semiconductor packages 100a. The semiconductor package 100 and the additional semiconductor packages 100a are then removed from the saw band 128. During the singulation sawing process, side surfaces 132 of the leads 104 are exposed. A large part of the exposed side surfaces 132 is characteristic of sawn surfaces.Details of the exposed side surfaces 132, which are characteristic of sawn surfaces, are described with reference to FIG. Fig. 8 revealed.

[0017] Fig. 1G is a perspective of the semiconductor package 100 after singulation, and Fig. 1H is a cross-section of the semiconductor package 100 of Fig. 1G. With reference to the Fig. 1G and Fig. 1H, a height difference 134 between the molding compound 114 below the relief recess 118 and the leads 104 below the relief recess 118 is smaller than the lead thickness 126 of the leads 104 below the relief recess 118, which may advantageously reduce the stress in the molding compound 114 and the leads 104 compared to a similar semiconductor package with thicker molding compound above the leads. An upper half 138 of a side surface 136 of the relief recess 118 along the molding compound 114 may be vertical with respect to a top surface 140 of the molding compound 114, thereby providing a larger area for the top surface 140, which may advantageously facilitate a subsequent vacuum pick-and-place operation when soldering the semiconductor package 100 to a printed circuit board. An inner corner 142 of the relief recess 118 may have a rounded profile, as in Fig. 1H, which can advantageously reduce the stress concentration in the molding compound 114 and the lines 104.

[0018] Fig. 2A to Fig. 2H are top, cross-sectional, and perspective views of another semiconductor package having a relief recess shown in successive stages of an exemplary formation process. Fig. 2A is a top view of the semiconductor package, and Fig. 2B is a cross-section of the semiconductor package in Fig. 2A in a first stage of education. With reference to the Fig. 2A and Fig. 2B, the semiconductor package 200 is formed using a lead frame 202. The lead frame 202 of this example accommodates additional semiconductor packages 200a besides the semiconductor package 200. The semiconductor package 200 includes a plurality of leads 204 of the lead frame 202. Likewise, the additional semiconductor packages 200a also include a plurality of additional leads 204a of the lead frame 202.

[0019] A microelectronic component 208 is attached to the leads 204 via electrical connections 212. In this example, the electrical connections 212 may be implemented as solder bumps, as shown in the Fig. 2A and Fig. 2B. Additional microelectronic components, not specifically shown, are attached to the additional leads 204a of the additional semiconductor package 200a.

[0020] The molding compound 214 is formed on the lead frame 202, including the leads 204 and the additional leads 204a, the microelectronic component 208, and the electrical connections 212. The molding compound 214, in this example, is formed between a lower mold plate 216a and an upper mold plate 216b. In this example, a compressible mold release film 244 is located between the lower mold plate 216a and the lower surfaces of the leads 204. The molding compound 214 is electrically insulating. The compressible mold release film 244 is compressed between the lower mold plate 216a and the leads 204, thereby depressing the molding compound 214 from the lower surfaces of the leads 204 so that the leads 204 extend below a lower surface of the molding compound 214.

[0021] Fig. 2C is a top view of the semiconductor package 200, and Fig. 2D is a cross-section of the semiconductor package 200 of Fig. 2C at a later stage of education. With reference to the Fig. 2C and Fig. 2D, a relief recess 218 is formed in the molding compound 214 over the leads 204, and additional relief recesses 218a are formed in the molding compound 214 over the additional leads 204a. In this example, the relief recess 218 and the additional relief recesses 218a are formed by a relief sawing process using a relief saw blade 220, similar to that described with reference to FIG. Fig. 1C and Fig. 1D. In this example, the stress relief saw blade 220 cuts down to the leads 204, exposing upper surfaces of the leads 204 below the stress relief recess 218, which may advantageously provide further stress relief compared to a similar semiconductor package with molding compound covering the leads. In this example, the stress relief saw blade 220 may optionally remove a portion of the leads 204. The stress relief recess 218 has a stress relief width 222, in a direction perpendicular to a perimeter 224 of the semiconductor package 200, that is greater than a lead thickness 226 of the leads 204 below the stress relief recess 218.

[0022] Fig. 2E is a top view of the semiconductor package 200, and Fig. 2F is a cross-section of the semiconductor package 200 of Fig. 2E at a later stage of education. With reference to the Fig. 2E and Fig. 2F, the semiconductor package 200 and the additional semiconductor packages 200a are mounted on a saw band 228. The semiconductor package 200 is singulated from the additional semiconductor packages 200a by a singulation sawing process using a singulation saw blade 230. The singulation sawing process cuts through and separates the leads 204 of the semiconductor package 200 from the lead frame 202 and similarly for the additional leads 204a of the additional semiconductor package 200a. The sawing process also cuts through and separates the molding compound 214 between the semiconductor package 200 and the additional semiconductor packages 200a. The semiconductor package 200 and the additional semiconductor packages 200a are subsequently removed from the saw band 228. During the singulation sawing process, side surfaces 232 of the leads 204 are exposed. A large part of the exposed side surfaces 232 is characteristic of sawn surfaces.

[0023] Fig. 2G is a perspective of the semiconductor package 200 after singulation, and Fig. 2H is a cross-section of the semiconductor package 200 of Fig. 2G. With reference to the Fig. 2G and Fig. 2H, as a result of the relief sawing process, which cuts down to the leads 204, thereby exposing the upper surfaces of the leads 204, the molding compound 214 below the relief recess 218 and the leads 204 below the relief recess 218 are substantially coplanar. Thus, a height difference between the molding compound 214 below the relief recess 218 and the leads 204 below the relief recess 218 is approximately zero and, in any case, much less than the lead thickness 226 of the leads 204 below the relief recess 218, which can advantageously reduce the stress in the molding compound 214 and the leads 204.

[0024] Fig. 3A to Fig. 3D are cross-sectional and perspective views of another semiconductor package with a relief recess shown in successive stages of an exemplary formation process. Fig. 3A is a cross-section of the semiconductor package in a first stage of formation. Referring to Fig. 3A, the semiconductor package 300 is formed with a lead frame 302. The lead frame 302 of this example can accommodate additional semiconductor packages 300a in addition to the semiconductor package 300. The semiconductor package 300 includes a plurality of leads 304 and a die pad 306 of the lead frame 302. Similarly, the additional semiconductor packages 300a each include a plurality of additional leads 304a and additional die pads (not shown) of the lead frame 302.

[0025] A microelectronic component 308 is attached to the die pad 306 by a die attach material 310. Additional microelectronic components, not specifically shown, are attached to the additional die pads of the additional semiconductor packages 300a. Electrical connections 312, implemented in this example as wire bonds 312, are formed between the microelectronic component 308 and the leads 304. Additional electrical connections are formed between the additional microelectronic components and the additional leads 304a.

[0026] The molding compound 314 is formed on the lead frame 302, including the leads 304 and the additional leads 304a, the microelectronic component 308 and the additional microelectronic components, and the electrical connections 312 and the additional electrical connections. The molding compound 314 may be formed using mold plates, as described with reference to Fig. 1B. Molding compound 314 is electrically insulating.

[0027] Fig. 3B is a cross-section of the semiconductor package 300 in a subsequent stage of formation. The molding compound 314 is laterally recessed to provide a relief recess 318 above the leads 304 and additional relief recesses 318a above the additional leads 304a. In this example, the relief recess 318 and the additional relief recesses 318a may be formed by an ablation process using a laser ablation tool 346 to remove material from the molding compound 314. The relief recess 318 has a relief width 322, in a direction perpendicular to a perimeter 324 of the semiconductor package 300, that is greater than a lead thickness 326 of the leads 304 below the relief recess 318.In one version of this example, the laser ablation tool 346 can be moved in two orthogonal directions across the semiconductor package 300 while the semiconductor package 300 is held stationary to form the relief recess 318. In another version, the laser ablation tool 346 can be held stationary while the semiconductor package 300 is moved in two orthogonal directions beneath the laser ablation tool 346. In another version, the laser ablation tool 346 can be moved in a first direction while the semiconductor package 300 is moved in a second, orthogonal direction. In this example, the upper surfaces of the leads 304 are not exposed by forming the relief recess 318, that is, a portion of the molding compound 314 is left above the leads 304 below the relief recess 318, which can advantageously protect the leads 304 from contamination or chemical degradation.Forming the relief recess 318 through the ablation process with the laser ablation tool 346 can advantageously improve throughput and reduce breakage compared to sawing.

[0028] Thereafter, the semiconductor package 300 is singulated from the additional semiconductor packages 300a by a singulation sawing process using a saw blade, which is not specifically shown. The singulation sawing process cuts through and separates the leads 304 of the semiconductor package 300 from the lead frame 302 and similarly for the additional leads 304a of the additional semiconductor package 300a. The sawing process also cuts through and separates the molding compound 314 between the semiconductor package 300 and the additional semiconductor packages 300a. In the singulation sawing process, exposed side surfaces 332, in Fig. 3C, which produces lines 304, with a majority of the exposed side surfaces 332 being characteristic of sawn surfaces.

[0029] Fig. 3C is a perspective of the semiconductor package 300 after singulation, and Fig. 3D is a cross-section of the semiconductor package 300 of Fig. 3C. With reference to the Fig. 3C and Fig. 3D, a height difference 334 between the molding compound 314 under the relief recess 318 and the leads 304 under the relief recess 318 is smaller than the lead thickness 326 of the leads 304 under the relief recess 318, which may provide the advantage of reduced stress in the molding compound 314 and the leads 304.

[0030] Fig. 4A and Fig. 4B are cross-sectional views of another semiconductor package with a relief recess shown in successive stages of an exemplary formation process. Referring to Fig. 4A, the semiconductor package 400 is formed with a lead frame 402. The lead frame 402 of this example accommodates additional semiconductor packages 400a in addition to the semiconductor package 400. The semiconductor package 400 includes a plurality of leads 404 of the lead frame 402. Likewise, the additional semiconductor packages 400a also include a plurality of additional leads 404a of the lead frame 402.

[0031] A microelectronic component 408 is attached to the leads 404 via electrical connections 412. In this example, the electrical connections 412 may be implemented as solder bumps. Additional microelectronic components, not specifically shown, are attached to the additional leads 404a of the additional semiconductor package 400a.

[0032] Molding compound 414 is formed on lead frame 402, including leads 404 and additional leads 404a, microelectronic component 408 and additional microelectronic components, and electrical connections 412 and additional electrical connections. Molding compound 414 is electrically insulating.

[0033] A relief recess 418 is formed in the molding compound 414 above the leads 404, and additional relief recesses 418a are formed in the molding compound 414 above the additional leads 404a. In this example, the relief recess 418 and the additional relief recesses 418a are formed by a machining operation with a cutting tool 448 that removes the molding compound 414. Forming the relief recess 418 by the machining operation can advantageously provide lower setup costs and higher throughput compared to other methods. During machining, the upper surfaces of the leads 404 may remain covered by a portion of the molding compound 414 below the relief recess 418. Alternatively, the upper surfaces of the leads 404 may be exposed by forming the relief recess 418.The relief recess 418 has a relief width 422, in a direction perpendicular to a circumference 424 of the semiconductor package 400, that is greater than a line thickness 426 of the lines 404 under the relief recess 418.

[0034] With reference to Fig. 4B, the semiconductor package 400 is singulated by a sawing process that creates exposed side surfaces 432 of the leads 404. At least a majority of the exposed side surfaces 432 are characteristic of sawn surfaces. A height difference 434 between the molding compound 414 below the relief recess 418 and the leads 404 below the relief recess 418 is smaller than the lead thickness 426 of the leads 404 below the relief recess 418, which may provide the advantage of reduced stress in the molding compound 414 and the leads 404.

[0035] The Fig. 5A to Fig. 5C are cross-sectional views of another semiconductor package with a relief recess shown in successive stages of an exemplary formation process. Referring to Fig. 5A, which shows the semiconductor package 500 in a first stage of formation, the semiconductor package 500 is formed using a lead frame 502. The lead frame 502 of this example can accommodate additional semiconductor packages 500a besides the semiconductor package 500. The semiconductor package 500 includes a plurality of leads 504 and a die pad 506. Similarly, the additional semiconductor packages 500a each include a plurality of additional leads 504a and additional die pads, not specifically shown.

[0036] A microelectronic component 508 is attached to the die pad 506 by a die attach material 510. Additional microelectronic components, not specifically shown, are attached to the additional die pads of the additional semiconductor packages 500a. Electrical connections 512, which may be implemented as wire bonds 512, may be formed between the microelectronic component 508 and the leads 504. Additional electrical connections, not specifically shown, are formed between the additional microelectronic components and the additional leads 504a.

[0037] The molding compound 514 is formed on the lead frame 502, including on the leads 504 and the additional leads 504a, on the microelectronic component 508 and the additional microelectronic components, and on the electrical connections 512 and the additional electrical connections. The molding compound 514 is electrically insulating. The molding compound 514 is formed between a lower mold plate 516a and an upper mold plate 516b. The upper mold plate 516b of this example has relief recess protrusions 550 extending vertically downward near the leads 504 and the additional leads 504a in areas for a relief recess 518 above the leads 504, and additional relief recesses 518a above the additional leads 504a. The lower mold plate 516a contacts the lower surfaces of the leads 504.

[0038] With reference to Fig. 5B, the lower mold plate 516a and the upper mold plate 516b are separated from the semiconductor package 500 and the additional semiconductor packages 500a. The relief recess 518 and the additional relief recesses 518a are formed by the relief recess projections 550. The relief recess 518 and the additional relief recesses 518a may have conical profiles, as shown in Fig. 5B to facilitate the separation of the upper mold plate 516b from the semiconductor package 500 and the additional semiconductor packages 500a. Forming the relief recess 518 using the relief recess protrusions 550 of the upper mold plate 516b concurrently with the formation of the mold compound 514 can advantageously reduce manufacturing costs and improve throughput compared to forming the relief recess 518 through a separate process.

[0039] With reference to Fig. 5C, the semiconductor package 500 is singulated by a sawing process that creates exposed side surfaces 532 of the lines 504. At least a majority of the exposed side surfaces 532 are characteristic of sawn surfaces. Details of the properties of sawn surfaces are described with reference to Fig. 8 revealed.

[0040] The Fig. 6A to Fig. 6C are cross-sectional views of another semiconductor package with a relief recess shown in successive stages of an exemplary formation process. Referring to Fig. 6A, semiconductor package 600 is shown in a first stage of formation. Semiconductor package 600 is formed using a lead frame 602 that can accommodate additional semiconductor packages 600a adjacent to semiconductor package 600. Semiconductor package 600 includes a plurality of leads 604 and a die pad 606, and the additional semiconductor packages 600a each include a plurality of additional leads 604a and additional die pads, not specifically shown.

[0041] A microelectronic component 608 is attached to the die pad 606 by a die attach material 610, and additional microelectronic components, not specifically shown, are attached to the additional die pads of the additional semiconductor packages 600a. Electrical connections 612 are formed between the microelectronic component 608 and the leads 604, and additional electrical connections, not specifically shown, are formed between the additional microelectronic components and the additional leads 604a.

[0042] Molding compound 614 is formed on lead frame 602, including leads 604 and additional leads 604a, microelectronic component 608 and additional microelectronic components, and electrical connections 612 and additional electrical connections. Molding compound 614 is electrically insulating. Molding compound 614 may be formed between a lower mold plate 616a and an upper mold plate 616b.

[0043] With reference to Fig. 6B, the semiconductor package 600 is singulated from the additional semiconductor packages 600a by a singulation sawing process with a singulation saw blade 630. The singulation sawing process cuts through and separates the leads 604 of the semiconductor package 600 and the additional leads 604a of additional semiconductor packages 600a, as well as the molding compound 614 between the semiconductor package 600 and the additional semiconductor packages 600a. The semiconductor package 600 and the additional semiconductor packages 600a may be mounted on a saw band or other substrate for the singulation sawing process. The singulation sawing process creates exposed side surfaces 632 of the leads 604; a majority of the exposed side surfaces 632 are characteristic of sawn surfaces.

[0044] With reference to Fig. 6C, after singulation of the semiconductor package 600, a relief recess 618 is formed in the molding compound 614 above the leads 604. The relief recess 618 can be formed by an ablation process using a laser ablation tool 646, as shown in Fig. 6C, or may be formed by another process, such as a machining operation or a relief sawing operation. The relief recess 618 has a relief width 622, in a direction perpendicular to a perimeter 624 of the semiconductor package 600, that is greater than a line thickness 626 of the lines 604 below the relief recess 618.

[0045] In a version of this in Fig. 6C, the upper surfaces of the leads 604 may remain covered by a portion of the molding compound 614 below the relief recess 618, such that a height difference 634 between the molding compound 614 below the relief recess 618 and the leads 604 below the relief recess 618 is smaller than a line thickness 626 of the leads 604 below the relief recess 618. In another version, the upper surfaces of the leads 604 may be exposed by forming the relief recess 618, wherein the height difference 634 between the molding compound 614 and the leads 604 is then still smaller than the line thickness 626 of the leads 604.

[0046] Forming the relief recess 618 after singulation of the semiconductor package 600 may advantageously enable the formation of relief recesses in stock semiconductor packages that have already been singulated, for example, as needed on a product basis.

[0047] Fig. 7 is a cross-section of a semiconductor package singulated by a punching process. The semiconductor package 700 includes a molding compound 714 and leads 704 extending to a perimeter 724 of the semiconductor package 700. The leads 704 have exposed side surfaces 732 with vertical grooves 752 resulting from the punching singulation process.

[0048] Fig.8 is a cross-section of a semiconductor package with exposed side surfaces of leads characteristic of sawn surfaces. The semiconductor package 800 includes a molding compound 814 and leads 804 extending to a perimeter 824 of the semiconductor package 800. The leads 804 have exposed side surfaces 832 that are free of vertical ridges because they were singulated by a dicing sawing process. When the exposed side surfaces 832 are free of vertical ridges, this can result in a more uniform distribution of solder to the exposed side surfaces 832 during subsequent assembly of the semiconductor package 800 on a substrate, such as a printed circuit board. This can advantageously provide more uniform solder connections between the leads 804 and the substrate, thereby improving board-level reliability compared to leads with vertical ridges.The leads 804 have ridges 854 along their bottom edges. The ridges 854 are formed by the dicing process. The ridges 854 can advantageously reduce the lateral movement of the semiconductor package 800 during subsequent assembly of the semiconductor package 800 to the substrate by adhering more firmly to the solder paste on the substrate than to the leads without ridges.

[0049] Various features of the examples disclosed herein may be combined in other configurations of exemplary semiconductor packages. For example, each of the relief recesses 118 to 618 may be formed by a relief sawing process, an ablation process, or a machining process. Each of the relief recesses 118 to 618 may be formed such that the respective leads 104 to 604 remain covered with the molding compound 114 to 614. Each of the relief recesses 118 to 618 may be formed such that the upper surfaces of the respective leads 104 to 604 are exposed. Each of the relief recesses 118 to 618 may be shaped to have an inside corner with rounded profiles.

[0050] Although various embodiments of the present disclosure have been described above, it should be understood that they have been presented only by way of example and not by way of limitation. Numerous changes may be made to the disclosed embodiments in accordance with the present disclosure without departing from the spirit or scope of the disclosure. Therefore, the breadth and scope of the present invention should not be limited by any of the embodiments described above. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.

Claims

[1] Semiconductor package comprising: Leads around a perimeter of the semiconductor package; a microelectronic component electrically coupled to multiple lines; a molding compound that contacts the leads and the microelectronic component, wherein: the molding compound is electrically insulating; the molding compound is recessed around the circumference to provide a relief recess having a relief width greater than a thickness of the lines below the relief recess; a height difference between the molding compound under the relief recess and the lines under the relief recess is less than the thickness of the lines under the relief recess; and exposed side surfaces of a large part of the cables are characteristic of sawn surfaces. [2] The semiconductor package according to claim 1, wherein an upper half of a side surface of the relief recess along the molding compound is vertical with respect to an upper surface of the molding compound. [3] The semiconductor package of claim 1, wherein the leads are exposed at the relief recess. [4] The semiconductor package of claim 1, wherein upper surfaces of the leads are exposed below the relief recess. [5] The semiconductor package of claim 1, wherein upper surfaces of the leads are covered by the molding compound under the relief recess. [6] The semiconductor package of claim 1, wherein the exposed side surfaces of the majority of the lines that are characteristic of sawn surfaces comprise the exposed side surfaces of the majority of the lines that are free of vertical grooves. [7] The semiconductor package of claim 1, wherein the exposed side surfaces of the majority of the leads that are characteristic of sawn surfaces include the exposed side surfaces of the majority of the leads that have ridges along lower edges. [8] The semiconductor package of claim 1, wherein the leads extend below a lower surface of the molding compound. [9] A method of forming a semiconductor package, comprising: electrically coupling a microelectronic component to leads extending to a perimeter of the semiconductor package; Forming a molding compound on the leads and on the microelectronic component, the molding compound being electrically insulating; laterally recessing the molding compound around the circumference to provide a relief recess having a relief width greater than a thickness of the lines below the relief recess; Separating the semiconductor package by sawing through the lines. [10] Method according to claim 9, wherein by lateral recessing of the molding compound a height difference is created between the molding compound under the relief recess and the lines under the relief recess which is less than the thickness of the lines under the relief recess. [11] The method of claim 9, wherein the lateral recessing of the molding compound is performed before the singulation of the semiconductor package. [12] The method according to claim 9, wherein the lateral recessing of the molding compound is carried out by removing a part of the molding compound by a sawing process. [13] The method according to claim 9, wherein the lateral recessing of the molding compound is carried out by removing a portion of the molding compound by an ablation process. [14] The method according to claim 9, wherein the lateral recessing of the molding compound is carried out by removing a part of the molding compound by a machining process. [15] The method according to claim 9, wherein the lateral relief of the molding compound is carried out by molding the molding compound using a mold plate having webs corresponding to the relief recess. [16] The method of claim 9, wherein the lateral recessing of the molding compound exposes the lines. [17] The method of claim 9, wherein the lateral recessing of the molding compound removes upper portions of the conduits. [18] The method of claim 9, wherein the molding compound is formed such that the conduits extend below a lower surface of the molding compound. [19] The method according to claim 9, wherein the lateral recessing of the molding compound is carried out after the singulation of the semiconductor package. [20] Semiconductor package comprising: Leads around a perimeter of the semiconductor package; a microelectronic component electrically coupled to a plurality of lines; and a molding compound that contacts the leads and the microelectronic component, wherein: the molding compound is electrically insulating; the molding compound is recessed around the circumference to provide a relief recess; the relief recess has a relief width that is greater than a thickness of the lines under the relief recess; an upper half of a side surface of the relief recess along the molding compound is vertical with respect to an upper surface of the molding compound; an inner corner of the relief recess has a rounded profile; a height difference between the molding compound under the relief recess and the lines under the relief recess is less than the thickness of the lines under the relief recess; and exposed side surfaces of a large part of the cables are characteristic of sawn surfaces. [21] A method of forming a plurality of semiconductor packages, comprising: electrically coupling a plurality of microelectronic components to leads of a lead frame, the leads extending to perimeters of the plurality of semiconductor packages; Simultaneously forming a molding compound on the leads and on the plurality of microelectronic components, the molding compound being electrically insulating; laterally recessing the molding compound around the perimeters to provide relief recesses having a relief width greater than a thickness of the lines under the relief recesses; and Separating the semiconductor packages by sawing through the lines.

Images