STORAGE SYSTEM AND METHOD FOR REORDERING DATA

Abstract

According to one embodiment, a storage system (1) includes a non-volatile memory (12) and a controller (11). The controller (11) includes a counter (131) that counts the number of accesses to data stored in the non-volatile memory in a first unit, the first unit being a unit of access to data from the host.The controller (11) determines whether a read command received from a host is a sequential read or random read command, increments a counter value corresponding to the data specified by the read command if the read command is the random read command, and, in a process of moving first data from a first block to a second block based on the counter value, controls a rearrangement of the first data from the first block in the second block if the first data has a size of the first unit and needs to be arranged across two pages in the second block.

Description

AREA

[0001] Embodiments described herein generally relate to a storage system and method for reordering data. BACKGROUND

[0002] Storage systems with flash memory such as solid-state drives (SSDs) are widely used.

[0003] In this type of storage system, when the flash memory is exhausted, the data of the unit of access from the host for sending and receiving data to and from the storage system, called a cluster (sector), may need to be arranged across a plurality of pages of the flash memory.

[0004] Arranging clusters across multiple pages of flash memory may impact storage system performance. BRIEF DESCRIPTION OF THE DRAWINGS Fig. is a diagram showing an example of a configuration of a storage system of an embodiment. Fig. is a first graph showing an example of a factor of performance deterioration caused by exhaustion of a NAND memory of the memory system of the embodiment. Fig. is a second graph showing an example of a factor of performance deterioration caused by exhaustion of a NAND memory of the memory system of the embodiment. Fig. is a third graph illustrating an example of a factor of performance degradation of the embodiment caused by exhaustion of a NAND memory of the memory system. Fig. is a diagram illustrating a method of controlling an arrangement of clusters performed by the storage system of the embodiment. Fig. is a graphical representation illustrating a method for responding to a case where clusters located across two pages occur during compaction of the memory system of the embodiment. Fig. is a diagram illustrating an example in which the memory system of the embodiment adaptively controls the arrangement of clusters after the exhaustion of the NAND memory. Fig. is a flowchart showing an operation flow at the time of receiving a read command of the memory system of the embodiment. Fig. is a flowchart showing an operation flow of compression in the storage system of the embodiment. DETAILED DESCRIPTION

[0005] Generally, according to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks, each of which includes a plurality of pages. The controller is connectable to a host and controls the non-volatile memory. The controller includes a counter that counts a number of accesses to data stored in the non-volatile memory in a first unit, wherein the first unit is a unit of access to data from the host.The controller determines whether a read command received from the host is a sequential read command or a random read command; increments a value of the counter corresponding to data specified by the read command when the read command is the random read command; and, in a process of moving first data of a first block to a second block based on the value of the counter, controls a rearrangement of the first data of the first block in the second block when the first data has a size of the first unit and needs to be arranged across two pages in the second block.

[0006] Embodiments are described below with reference to the accompanying drawings.

[0007] Fig. is a diagram showing an example of a configuration of a storage system 1 of the embodiment. An example of a connection between the storage system 1 and a host 2 is also shown in Fig. shown. Storage system 1 and host 2 are connected by an interface that conforms, for example, to the PCI Express™ (PCIe™) standard.

[0008] The memory system 1 includes a controller 11 and a NAND memory 12.

[0009] The controller 11 controls a process of writing data to the NAND memory 12 and a process of reading data from the NAND memory 12 in response to commands from the host 2. The controller 11 independently executes the process of writing data to the NAND memory 12 and reading data from the NAND memory 12 for the purpose of optimizing the state of the NAND memory 12 and the like, independent of the commands from the host 2. The controller 10 is configured, for example, as a system on a chip (SoC).

[0010] The NAND memory 12 is a storage medium including a plurality of blocks, each including a plurality of pages, and data cannot be overwritten in a memory area to which data has already been written. Updating the data stored in the NAND memory 12 is performed by invalidating the original data and separately writing new data. To enable data to be rewritten in the memory area where the invalidated data is stored, the controller 11 executes a process called compaction, garbage collection, or the like (hereinafter referred to as compaction). When executing compaction, the controller 11 independently executes the process of writing data to and reading data from the NAND memory 12, independent of commands from the host 2.

[0011] The controller 11 includes a host interface unit 110, a control unit 120, and a NAND interface unit 130. These can be implemented by a program executed by the CPU or by hardware such as electrical circuits.

[0012] Host interface unit 110 is a processing unit that acts as a front-end. Host interface unit 110 controls, for example, communication with host 2 via a protocol compliant with the NVM Express™ (NVMe™) standard.

[0013] The control unit 120 is a processing unit that functions as a core of the controller 11. The control unit 120 controls the process of writing data to the NAND memory 12 and the process of reading data from the NAND memory 12 in response to commands from the host 2, in cooperation with the host interface unit 110 and the NAND interface unit 130. The above-described data writing and reading processes, which are autonomously executed by the controller 11, are also executed as internal processes of the storage system 1 under the control of the control unit 120.

[0014] The NAND interface unit 130 is a processing unit that acts as a backend and controls the sending and receiving of data to and from the NAND memory 12. The NAND interface unit 130 includes an access counter 131. The use of the access counter 131 and the like will be described in detail below.

[0015] An example of a factor in the deterioration of the performance of the memory system 1 caused by the exhaustion of the NAND memory 12 will be described with reference to Fig. until Fig. described.

[0016] Fig. shows an example of changes in the arrangement of ECC frames in a page of the memory system 1 caused by the depletion of the NAND memory 12 when a fixed payload length method is applied. The fixed payload length method is a method in which an error correction code (ECC) frame length is made variable while a payload length is fixed.

[0017] When receiving a write command from host 2, controller 11 generates an ECC frame. The ECC frame is a combination of the payload of a write target received from host 2 and the ECC (parity) to detect and correct errors when this payload is read. Controller 11 writes the generated ECC frame to NAND memory 12.

[0018] The NAND memory 12 includes a plurality of blocks. The block is a data erasure unit in the NAND memory 12. Each of the plurality of blocks includes a plurality of pages. The page is a data write unit in the NAND memory 12. When storing the ECC frame in each of the blocks, the controller 11 controls the arrangement of the ECC frame for each of a predetermined number of pages of the plurality of pages included in the block. In other words, the controller 11 controls the arrangement of the ECC frames by using the storage area on a predetermined number of pages as a bin. Fig. shows an example of arranging the ECC frames by using the two-page memory area as one bin.

[0019] As NAND memory 12 becomes exhausted, errors that may occur in the payload data increase. Accordingly, the ECC code length for error correction must be increased. When ECC frames are generated using the fixed-payload-length method, the length of the payload data in each ECC frame is constant, while the ECC code length is variable. For this reason, the length of the ECC frame increases with the increase in the ECC code length. In other words, the ECC frame in the fixed-payload-length method is variable in length. Furthermore, the length of the payload data in the fixed-payload-length method is the same length as the cluster described above, that is, the unit of access to data from host 2.

[0020] Fig. shows an example in which the number of ECC frames that can be arranged every two pages decreases to eight, seven, and six as the NAND memory 12 becomes exhausted ((A) → (B) → (C)). When the condition that the ECC code length must be increased is met (i.e., the degree of exhaustion of the NAND memory 12 exceeds a certain extent), the ECC code length becomes longer, and the number of ECC frames that can be arranged on one page decreases. Fig. "Threshold exceeded" indicates that the condition under which the ECC code length must be increased is met. Reducing the number of ECC frames that controller 11 writes to a page group for a slot is also referred to as "cluster collapsing" or the like.

[0021] In addition, Fig. also a state in which an ECC frame is arranged across two pages (a1), that is, a cluster is arranged across two pages. If a cluster is arranged across two pages, the performance of the storage system 1 may deteriorate. An influence of the cluster arranged across two pages on the performance of the storage system 1 is described below.

[0022] On the other hand, Fig. an example of the degradation of the performance of the memory system 1 caused by the exhaustion of the NAND memory 12 in a case where the fixed frame length method is applied in which the ECC frame length is fixed and the payload length is variable. Fig. also shows an example where the ECC frames are arranged by using the memory area for two pages as one bin.

[0023] Fig. Figure 12 shows an example where the ratio of the ECC code length in the ECC frame arranged on each page increases as the NAND memory 12 is exhausted ((A) → (B) → (C)). As described above, the ECC code length for error correction becomes longer as the NAND memory 12 is exhausted. In the fixed frame length method, the payload length and the ECC code length are variable to keep the length of each ECC frame constant. For this reason, the payload length in the ECC frame becomes shorter.

[0024] In the fixed frame length method, the number of ECC frames that can be placed on each page does not fluctuate when the NAND memory 12 is exhausted. In other words, it is not possible for an ECC frame to be placed across two pages. However, since the length of the payload data in each ECC frame becomes shorter, it may happen that a cluster, which is the data of the unit of access from host 2, is placed in two separate ECC frames. The two ECC frames designated by code b1 in Fig. are two ECC frames in which a particular cluster is divided and arranged, and two ECC frames are each arranged to be divided into two pages.

[0025] In other words, even with the fixed frame length method, a situation may occur where a cluster is located across two pages. If a cluster is located across two pages, the performance of the storage system 1 may be degraded.

[0026] Now, an influence of the cluster arranged over two pages on the performance of the storage system 1 will be discussed with reference to Fig. described. Fig. shows an example in which the method with fixed payload length is applied.

[0027] Assume that NAND memory 12 includes two levels, and that data is written and read at each level. In this case, controller 11 can write and read data to and from NAND memory 12 in parallel for each level, every two ECC frames.

[0028] In addition, it is assumed that a compartment of each block is formed by two sides belonging to two different levels. Fig. shows an example of the arrangement of ECC frames within two sides of a compartment in block M and an example of the arrangement of ECC frames within two sides of a compartment in block N.

[0029] Assume that the storage system 1 is currently reading a cluster of block M at level 1 from the NAND memory 12 (c1). At this time, assuming, for example, that a read command is received from the host 2 addressing the cluster of block N at level 0, the controller 11 can immediately execute the process of reading the cluster from the NAND memory 12 (c2). On the other hand, if, for example, a read command is received from the host 2 addressing a cluster located across block N of level 0 and block N of level 1, the controller 11 cannot execute the process of reading the cluster from the NAND memory 12 until the reading of the previous cluster, denoted by the code c1, is completed (c3).

[0030] In other words, the latency of a read command process for a cluster that is located only at level 0 or level 1 is determined by the state of the level its own cluster is in. In contrast, the latency of a read command process for a cluster that is located across levels 0 and 1 is determined by the states of both levels the cluster is in. For this reason, reading a cluster that is located across two levels may take longer than reading a cluster that is located only at one level.

[0031] Thus, the performance of storage system 1 may degrade if the cluster is arranged across two pages. Furthermore, the performance of storage system 1 is more likely to degrade if data is read and written more frequently to the cluster arranged across two levels.

[0032] Fig. shows an example of a case where the fixed payload length method is applied, but the situation is the same in a case where the fixed frame length method is applied. Consider a case where two ECC frames enclosing a specific cluster are located in two different pages, and a read command addressing the cluster is received from Host 2. At this time, a situation may arise where reading an ECC frame corresponding to the cluster can be performed immediately, but reading the other ECC frame must be waited for.

[0033] The memory system 1 of the present embodiment can suppress the performance degradation caused by the cluster being arranged across two pages due to the exhaustion of the NAND memory 12. The mechanism of the memory system 1 of the present embodiment will be described with reference to Fig. described.

[0034] Host 2 issues a read command to storage system 1 to read multiple clusters. When host 2 performs either sequential reading or random reading, a certain number or more read commands are continuously issued because the data for multiple clusters is the target. When host 2 issues a read command, the read command is received by host interface unit 110 of controller 11.

[0035] The host interface unit 110 transmits the read command to the control unit 120. Upon receiving the read command, the control unit 120 first translates a logical address specified by the read command into a physical address. This process is called address resolution or the like. The logical address is an address that indicates a position in the logical address space, that is, the logical position of the NAND memory 12. The physical address is an address that indicates a position in the physical address space, that is, the physical position of the NAND memory 12. For address resolution, the control unit 120 manages information that holds the correspondence between the logical address and the physical address. The information that holds the correspondence is called a logical-physical address translation table or the like.

[0036] The control unit 120 sends instructions to the NAND interface unit 130 to read data (ECC frames) from the location in the NAND memory 12 specified by the translated physical address. The NAND interface unit 130 communicates with the NAND memory 12 to output the instructed data (ECC frames) to the NAND memory 12. The NAND interface unit 130 delivers the data (ECC frames) obtained from the NAND memory 12 to the control unit 120.

[0037] Upon receiving the ECC frame, control unit 120 checks whether an error occurs in the payload data in the ECC frame by using the ECC in the ECC frame. If an error occurs, control unit 120 corrects the error using the ECC. Control unit 120 transmits the error-corrected payload data to host interface unit 110 as needed.

[0038] The host interface unit 110 sends the payload data received from the control unit 120 to the host 2 in response to the read command.

[0039] In addition to the basic operations described above at the time of receiving the read command, the host interface unit 110 first determines whether the read command received from the host 2 is a command related to sequential reading or random reading in the storage system 1 of the embodiment. As described above, a certain number of read commands are continuously issued when the host 2 executes either sequential reading or random reading. Therefore, the host interface unit 110 determines whether the logical addresses specified in these read command groups are continuous or not. The host interface unit 110 determines that the read command is the sequential read command when the addresses are continuous, and determines that the read command is the random read command when the addresses are not continuous.

[0040] The host interface unit 110 notifies the NAND interface unit 130, via the control unit 120, of the determination result of sequential reading or random reading at the time of receiving the read command. The NAND interface unit 130, upon receiving the determination result that the read command is a random read command, increments the value of the counter in the access counter 131 corresponding to the read target data to be read by the read command. In other words, the access counter 131 is a counter for counting the number of random reads of each data.

[0041] Incidentally, the determination of whether the read command is a sequential read or random read command may be performed by the NAND interface unit 130 instead of the host interface unit 110. In this case, the NAND interface unit 130 determines whether the physical addresses of an instruction group continuously sent from the control unit 120 are continuous or not. The NAND interface unit 130 determines that the read command is a sequential read command when the addresses are continuous, and determines that the read command is a random read command when the addresses are not continuous.

[0042] Furthermore, in the fixed payload length method, the NAND interface unit 130 may use the data unit to count the number of random reads in the access counter 131 for each ECC frame or each cluster, that is, in a unit of access from the host 2. In the fixed payload length method, counting the number of random reads for each ECC frame is essentially the same as counting the number of random reads for each cluster, that is, in a unit of access from the host 2. On the other hand, in the fixed frame length method, it is desirable to perform counting the number of random reads for each cluster, that is, in a unit of access from the host 2. In the fixed frame length method, managing a combination of two ECC frames distributed by the cluster is possible by counting the number of random reads for each frame cluster.In other words, it is possible to prevent the number of random reads of the clusters distributed in two ECC frames from being counted twice as large as the actual number, and the like.

[0043] Next, with reference to Fig. a method for controlling the arrangement of clusters to suppress the degradation of performance caused by the exhaustion of the flash memory, using the number of random read operations counted by the access counter 131.

[0044] As described above, the controller 11 performs compaction as needed. A typical example of compaction is to move data in N (N is a natural number greater than or equal to two) blocks, excluding invalidated data in M ​​(M is a natural number less than N) blocks, so that the memory area of ​​N - M blocks can be reused. Another example of scheduling for executing compaction is when the number of remaining blocks to which data can be written falls below a threshold.

[0045] Fig. is a graphical representation showing the cluster arrangement control performed by the storage system. In Fig. Two pages in the upper row are pages for a compartment in a target block of the move during compression. Two pages in the lower row are pages for a compartment in the target block of the move during compression. Fig. It is assumed that the method with fixed payload length is used. In Fig. “Small,” “large,” and “medium” indicate the relative size of the number of random read operations counted by the access counter 131 within the compartment. In Fig. "Small," "medium," and "large" are shown in order of the smaller number of random reads. Controller 11 determines "small," "large," and "medium" by comparatively evaluating the number of random reads in the first bin, which is counted by access counter 131.

[0046] As in Fig. As shown, the ECC frame including data 3 with a large number of random reads is arranged across two pages before performing compaction. When compaction is performed, the controller 11 obtains the value of the access counter 131 from the NAND interface unit 130 and, based on this value, controls the rearrangement of the ECC frame into the relocation target block.

[0047] More specifically, the controller 11 shifts the ECC frame of the relocation source block to the relocation destination block, so that instead of the ECC frame including the data 3 with a large number of random reads, the ECC frame including the data with a small number of random reads is arranged across the two sides.

[0048] Controller 11 arranges the ECC frame that encloses data with a "large" number of random reads across two pages, instead of the ECC frame that encloses data with a "small" number of random reads. However, controller 11 may arrange the ECC frame that encloses data with a "small" number of random reads across two pages, instead of the ECC frame that encloses data with a "medium" number of random reads.

[0049] For example, the controller 11 selects the ECC frame that includes the data with the smallest number of random reads among the data to be moved as a candidate to be arranged across two pages.

[0050] For example, the controller 11 can control the arrangement of ECC frames on each of two or more pages. If the controller 11 controls the arrangement of ECC frames on each of four pages, boundaries of three pages exist within a bin formed by four pages. If ECC frames are arranged on two of the three page boundaries, the controller 11 selects two sets of data in the order of a smaller number of random reads and arranges two ECC frames enclosing the data on the boundary of two pages. In other words, the controller 11 arranges the ECC frames so that the two ECC frames enclosing the data are arranged across the two pages.

[0051] In other words, the memory system 1 of the embodiment reduces the access frequency of the clusters arranged across two pages by arranging those ECC frames including the data with a small number of random read operations across the two pages, thereby achieving the suppression of the deterioration of the performance.

[0052] Even if the number of random reads of the data arranged across two pages in the bin enclosing the page can be determined as "large," but the number of random reads relative to the storage system 1 as a whole can be determined as "small," the controller 11 can omit the control of the reordering caused by an exchange of the ECC frames. For example, if the number of random reads of the data arranged across two pages is less than the threshold, that data can also be arranged across two pages at the relocation destination. In other words, it can be controlled so that those data whose number of random reads is greater than or equal to a threshold are not arranged across two pages. The threshold can be determined based on the upper limit of the latency of the read command process.In this case, the generation of overhead can be suppressed as much as possible in the range where the performance can be maintained.

[0053] Incidentally, when the fixed frame length method is applied, the controller 11 arranges two ECC frames enclosing the cluster with the smallest number of random reads among the data to be moved on different pages.

[0054] By the way, Fig. An example of a case where the number of ECC frames that can be arranged on two pages for one bin is the same for the source block of relocation and the destination block of relocation during compaction. The degree of depletion of the NAND memory 12 at the time of writing data to the destination block of relocation by compaction may be more advanced than the degree of depletion of the NAND memory 12 at the time of writing data to the source block of relocation. At this time, the number of ECC frames that can be arranged in the destination block of relocation is less than that in the source block of relocation.

[0055] In this case, there is no cluster arranged across two pages in the source block of the relocation, but a cluster arranged across two pages may occur in the destination block of the relocation. The arrangement control of clusters in a case where clusters arranged across two pages are generated in the destination block of the relocation during compaction will be explained with reference to Fig. described. Fig. is a graphical representation showing the cluster arrangement control performed by the storage system. It is assumed that the fixed payload length method is used.

[0056] During compaction, the controller 11 reads the ECC frame from the relocation source block and checks for errors in the payload using the ECC. If an error is detected, the controller 11 corrects the error using the ECC. When relocating the payload to the relocation destination block, the controller 11 generates a new ECC and creates an ECC frame that includes the payload and the new ECC. The code length of the ECC generated after the NAND memory 12 is exhausted is longer than the code length of the previous ECC. Accordingly, the length of the ECC frame becomes longer in the fixed payload length method.

[0057] Fig. shows an example where an ECC frame must be placed across two pages during compaction to move data from the source block of the move before cluster collapsing to the destination block of the move after cluster collapsing.

[0058] The controller 11 uses, for example, the memory area of ​​a static random access memory (SRAM) (not shown) in the controller 11 or a dynamic RAM (DRAM) (not shown) connected to the controller 11 as the work area. The controller 11 first attempts to arrange the ECC frames scheduled to be written to the relocation target block in the work area configured as the relocation target block, and checks whether or not the ECC frame arranged across two pages exists in the relocation target block. If the ECC exists, the controller 11 controls the writing of the ECC frame to the relocation target block so that the ECC frame including the data with a small number of random reads is arranged across the two pages.

[0059] Fig. shows an example where an ECC frame including data 4 with a small number of random reads is arranged across two pages. When the ECC frame is mechanically rearranged according to the order in the relocation source block to the relocation destination block, the ECC frame including data 3 with a large number of random reads is arranged across two pages. Therefore, instead of the ECC frame including data 3 with a large number of random reads, the controller 11 arranges the ECC frame including data 4 with a small number of random reads across the two pages.

[0060] Thus, the memory system 1 of the embodiment can adaptively control the rearrangement of data according to the progress of depletion of the NAND memory 12 to suppress the deterioration of performance.

[0061] Furthermore, in the fixed frame length method, clusters in the relocation source block are not distributed into two ECC frames, but clusters in the relocation destination block may be distributed into two ECC frames when the NAND memory 12 becomes exhausted. Furthermore, two ECC frames into which the clusters are distributed may need to be arranged on two separate pages. In such a case, the controller 11 may select two ECC frames in which the data (clusters) are distributed with a small number of random reads as candidates for the ECC frames to be arranged on two separate pages.

[0062] Furthermore, cluster collapsing continues and conversely, ECC frames in the source block of the move are arranged across two pages during compaction, while ECC frames in the target block of the move do not necessarily have to be arranged across two pages. Fig. shows an example of a case where ECC frames are no longer arranged across two pages as a result of the progression of cluster collapsing.

[0063] Furthermore, in the fixed frame length method, for example, if the number of ECC frames that can be arranged on each page is a multiple of the number of ECC frames that are distributed among clusters, as cluster collapsing proceeds, clusters in the relocation source block are arranged across two pages, but there may be no clusters arranged across the two pages in the relocation destination block.

[0064] Fig. is a flowchart showing an operation flow at the time of receiving the read command of the storage system 1 of the embodiment.

[0065] When a read command is received (S101: Yes), the controller 11 determines the read type of the read command (S102). Specifically, the controller 11 determines whether the read type is sequential read or random read.

[0066] If the read type is random read (S103: Yes), the controller 11 increments the value of the access counter 131 corresponding to the data specified by the read command (S104). If the read type is sequential read (S103: No), the controller 11 skips the process of step S104, that is, incrementing the value of the access counter 131 corresponding to the data.

[0067] Fig. is a flowchart showing an operation flow of compression in the storage system 1 of the embodiment.

[0068] The controller 11 first determines whether the number of ECC frames in the page group of the relocation destination is equal to the number of ECC frames included in the page group of the relocation source (S201). If the number of ECC frames is equal (S201: Yes), the process in S202 is skipped. If the number of ECC frames is not equal (S201: No), the data of the page group of the relocation source is arranged in a work area, which is regarded as the page group of the relocation destination (S202). The controller 11 checks whether or not data arranged across two pages exists (S203).

[0069] If there is data arranged across two pages (S203: Yes), the controller 11 changes the arrangement of the data in the page group of the move target in the work area based on the value of the access counter 131, so that the data is arranged across two pages with a small number of random read operations (S204). If there is no data arranged across two pages (S203: No), the controller 11 skips the process in step S204.

[0070] Then, the controller 11 writes the data arranged in the work area into the page group of the move destination (S205).

[0071] As described above, the storage system 1 of the embodiment counts the number of random reads and controls the cluster with a small number of random reads to be arranged across two pages in the relocation target block. In other words, the storage system 1 relocates data in such a way as to reduce the access frequency of clusters arranged across two pages.

[0072] The memory system 1 of the embodiment can thereby reduce the performance degradation associated with the exhaustion of the NAND memory 12.

[0073] Although specific embodiments have been described, these embodiments are presented for exemplary purposes only and are not intended to limit the scope of the inventions. Of course, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the embodiments described herein may be made without departing from the scope of the inventions.

[0074] Further aspects and embodiments are described below.

[0075] According to a first aspect, a storage system is provided, comprising: a non-volatile memory including a plurality of blocks each including a plurality of pages; and a controller connectable to a host and configured to control the non-volatile memory, wherein the controller includes a counter that counts a number of accesses to data stored in the non-volatile memory in a first unit, the first unit being a unit of access to data from the host, and the controller is configured for this: to determine whether a read command received from the host is a sequential read or a random read command; to increment a value of the counter corresponding to data specified by the read command if the read command is the random read command; and in a process of moving first data of a first block to a second block, to control a rearrangement of the first data of the first block into the second block based on the value of the counter when the first data has a size of the first unit and needs to be arranged across two pages in the second block.

[0076] According to at least one embodiment, the controller is further configured to generate a frame including payload data received from the host and an error correction code for detecting and correcting an error in the payload data, and to write the frame to the non-volatile memory, and a length of the payload is the first unit.

[0077] According to at least one embodiment, the controller is further configured to generate a frame including payload data received from the host and an error correction code for detecting and correcting an error in the payload data, and to write the frame to the non-volatile memory, and a length of the frame is not changed before and after the process of moving the first data of the first block to the second block.

[0078] According to at least one embodiment, the controller is configured to control an arrangement of the first data in each block of the non-volatile memory for each first number of pages among the plurality of pages included in each block, and to control the rearrangement of the first data of the first block into the second block so that a value of the counter becomes data in which small data is arranged over two pages, into data arranged on the first number of pages.

[0079] According to at least one embodiment, the controller is configured to control the rearrangement of the first data of the first block into the second block such that a value of the counter does not become data in which data greater than or equal to a threshold is arranged across two pages.

[0080] According to at least one embodiment, the controller is configured to compare a first logical address specified by a first read command, which indicates a logical location of the non-volatile memory, with a second logical address specified by a second read command following the first read command, and to determine whether the first read command and the second read command are the sequential read or random read commands.

[0081] According to at least one embodiment, the controller is configured to: compare a first physical address with a second physical address, the first physical address indicating a physical location of the non-volatile memory associated with a first logical address indicating a logical location of the non-volatile memory specified by a first read command, the second physical address being associated with a second logical address specified by a second read command following the first read command; and to determine whether the first read command and the second read command are the sequential read or random read commands.

[0082] According to at least one embodiment, the controller is configured to: generate each of a plurality of frames including payload data received from the host and an error correction code for detecting and correcting an error in the payload data, and write the plurality of frames to the non-volatile memory when a write command is received from the host, when the controller moves the first data from the first block to the second block by a first method, counting the number of accesses to the data by the counter for each of a plurality of frames stored in the second block, when the controller moves the first data from the first block to the second block by a second method, counting the number of accesses to the data by the counter for each element from the first unit of the first data stored in the second block, the first method makes a length of the frame to be stored in the second block different from a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the payload data included in the frame to be stored in the second block equal to a length of the payload data included in the frame stored in the first block, and the second method makes a length of the frame to be stored in the second block equal to a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the payload data included in the frame to be stored in the second block different from a length of the payload data included in the frame stored in the first block.

[0083] According to at least one embodiment, the controller is configured to: to control the rearrangement of the first data of the first block into the second block so that a frame including data for which a value of the counter is greater than or equal to a threshold value is not arranged across two pages when the frame is generated in the first method, and to control the rearrangement of the first data of the first block into the second block so that two frames on which data having a counter value greater than or equal to a threshold value is distributed are not arranged on two separate pages when the frame is generated in the second method.

[0084] According to at least one embodiment, the controller is configured to: to skip incrementing the counter value if the read command is the sequential read command.

[0085] According to a second aspect, a method is provided performed by a controller connectable to a host and configured to control a non-volatile memory including a plurality of blocks each comprising a plurality of pages, the method comprising: Determining that a read command received from the host is the random read command; in response to determining that the read command is the random read command, incrementing a value of a counter corresponding to data specified by the read command, of counters for counting a number of accesses to data stored in the non-volatile memory for each unit of access from the host or for each frame, the frame including payload data received from the host and an error correction code for detecting and correcting an error in the payload data; and in a process of moving first data of a first block to a second block, controlling rearrangement of the first data of the first block into the second block based on the value of the counter when arranging data in the unit of access from the host or the frame in the second block across two pages.

[0086] According to at least one embodiment, the method further comprises: Generating a frame including payload data received from the host and an error correction code for detecting and correcting an error in the payload data; and Writing the frame to the non-volatile memory, where a length of the payload is the unit of access.

[0087] According to at least one embodiment, the method further comprises: Generating a frame including payload data received from the host and an error correction code for detecting and correcting an error in the payload data; and Writing the frame to the non-volatile memory, where a length of the frame is not changed before and after the process of moving the first data of the first block to the second block.

[0088] According to at least one embodiment, the method further comprises: controlling an arrangement of the first data into each block of the non-volatile memory for each first number of pages among the plurality of pages included in each block; and Controlling rearrangement of the first data of the first block into the second block so that a value of the counter becomes data in which small data is arranged across two pages into data arranged on the first number of pages.

[0089] According to at least one embodiment, the method further comprises: Controlling the rearrangement of the first data of the first block into the second block so that a value of the counter does not become data in which data greater than or equal to a threshold is arranged across two pages.

[0090] According to at least one embodiment, the method further comprises: Comparing a first logical address indicating a logical position of the non-volatile memory specified by a first read command with a second logical address specified by a second read command following the first read command; and Determine that the first read command and the second read command are the random read commands.

[0091] According to at least one embodiment, the method further comprises: Comparing a first physical address with a second physical address, wherein the first physical address indicates a physical location of the non-volatile memory associated with a first logical address indicating a logical location of the non-volatile memory specified by a first read command, wherein the second physical address is associated with a second logical address specified by a second read command following the first read command, and Determine that the first read command and the second read command are the random read commands.

[0092] According to at least one embodiment, the method further comprises: generating each of a plurality of frames including payload data received from the host and an error correction code for detecting and correcting an error in the payload data, and writing the plurality of frames to the non-volatile memory; in the first data shifted from the first block to the second block by a first method, counting the number of accesses to the data by the counter for each of the frames of the second block; and in the first data, which are moved from the first block to the second block by a second method, for each element from the first unit, counting the number of accesses to the data by the counter, where the first method makes a length of the frame to be stored in the second block different from a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the payload data included in the frame to be stored in the second block equal to a length of the payload data included in the frame stored in the first block, and the second method makes a length of the frame to be stored in the second block equal to a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the payload data included in the frame to be stored in the second block different from a length of the payload data included in the frame stored in the first block.

[0093] According to at least one embodiment, the method further comprises: when generating the frame by the first method, controlling the rearrangement of the first data of the first block into the second block so that a frame including data in which a value of the counter is greater than or equal to a threshold value is not arranged across two pages; and when generating the frame by the second method, controlling the rearrangement of the first data of the first block into the second block so that two frames on which data having a value of the counter greater than or equal to a threshold is distributed are not arranged on two separate pages.

[0094] According to at least one embodiment, the method further comprises: Skipping incrementing the value of the counter corresponding to data specified by the read command in response to determining that the read command is the sequential read command.

Claims

[1] Storage system (1), comprising: a non-volatile memory (12) including a plurality of blocks each including a plurality of pages; and a controller (11) connectable to a host and configured to control the non-volatile memory, wherein the controller (11) includes a counter (131) that counts a number of accesses to data stored in the non-volatile memory in a first unit, the first unit being a unit of access to data from the host, and the controller (11) is configured for: to determine whether a read command received from the host is a sequential read or a random read command; to increment a value of the counter corresponding to data specified by the read command if the read command is the random read command; and in a process of moving first data of a first block to a second block, to control a rearrangement of the first data of the first block into the second block based on the value of the counter when the first data has a size of the first unit and needs to be arranged across two pages in the second block. [2] Storage system (1) according to claim 1, wherein the controller (11) is further configured to generate a frame including payload data received from the host and an error correction code for detecting and correcting an error in the payload data, and to write the frame to the non-volatile memory (12), and a length of the payload is the first unit. [3] Storage system (1) according to claim 1, wherein the controller (11) is further configured to generate a frame including payload data received from the host and an error correction code for detecting and correcting an error in the payload data, and to write the frame to the non-volatile memory (12), and a length of the frame is not changed before and after the process of moving the first data of the first block to the second block. [4] Storage system (1) according to claims 1 to 3, wherein the controller (11) is configured to: controlling an arrangement of the first data in each block of the non-volatile memory (12) for each first number of pages from the plurality of pages included in each block, and to control the rearrangement of the first data of the first block into the second block so that a value of the counter becomes data in which small data is arranged over two pages, into data arranged on the first number of pages. [5] The storage system (1) according to claim 1 to 3, wherein the controller (11) is configured to control the rearrangement of the first data of the first block into the second block so that a value of the counter does not become data in which data greater than or equal to a threshold value is arranged across two pages. [6] The memory system (1) according to any one of the preceding claims, wherein the controller (11) is configured to compare a first logical address specified by a first read command, which indicates a logical position of the non-volatile memory (12), with a second logical address specified by a second read command following the first read command, and to determine whether the first read command and the second read command are the sequential read or random read commands. [7] Storage system (1) according to one of the preceding claims, wherein the controller (11) is configured to: compare a first physical address with a second physical address, the first physical address indicating a physical location of the non-volatile memory associated with a first logical address indicating a logical location of the non-volatile memory specified by a first read command, the second physical address being associated with a second logical address specified by a second read command following the first read command; and to determine whether the first read command and the second read command are the sequential read or random read commands. [8] Storage system (1) according to one of the preceding claims, wherein the controller (11) is configured to: generate each of a plurality of frames including payload data received from the host and an error correction code for detecting and correcting an error in the payload data, and write the plurality of frames to the non-volatile memory when a write command is received from the host, when the controller moves the first data from the first block to the second block by a first method, counting the number of accesses to the data by the counter for each of a plurality of frames stored in the second block, when the controller moves the first data from the first block to the second block by a second method, counting the number of accesses to the data by the counter for each element from the first unit of the first data stored in the second block, the first method makes a length of the frame to be stored in the second block different from a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the payload data included in the frame to be stored in the second block equal to a length of the payload data included in the frame stored in the first block, and the second method makes a length of the frame to be stored in the second block equal to a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the payload data included in the frame to be stored in the second block different from a length of the payload data included in the frame stored in the first block. [9] The storage system (1) of claim 8, wherein the controller (11) is configured to: to control the rearrangement of the first data of the first block into the second block so that a frame including data for which a value of the counter is greater than or equal to a threshold value is not arranged across two pages when the frame is generated in the first method, and to control the rearrangement of the first data of the first block into the second block so that two frames on which data having a counter value greater than or equal to a threshold value is distributed are not arranged on two separate pages when the frame is generated in the second method. [10] The storage system (1) of claim 1, wherein the controller (11) is configured to: to skip incrementing the counter value if the read command is the sequential read command. [11] A method for rearranging data performed by a controller (11) connectable to a host and configured to control a non-volatile memory including a plurality of blocks each comprising a plurality of pages, the method comprising: Determining (S102) that a read command received from the host is the random read command; in response to determining that the read command is the random read command (S103: Yes), incrementing (S104) a value of a counter corresponding to data specified by the read command, of counters for counting a number of accesses to data stored in the non-volatile memory for each unit of access from the host or for each frame, the frame including payload data received from the host and an error correction code for detecting and correcting an error of the payload data; and in a process of moving first data of a first block to a second block, controlling (S204) rearranging the first data of the first block into the second block based on the value of the counter when arranging data in the unit of access from the host or the frame in the second block across two pages. [12] The method of claim 11, further comprising: Generating a frame including payload data received from the host and an error correction code for detecting and correcting an error in the payload data; and Writing the frame to the non-volatile memory, where a length of the payload is the unit of access. [13] The method of claim 11, further comprising: Generating a frame including payload data received from the host and an error correction code for detecting and correcting an error in the payload data; and Writing the frame to the non-volatile memory, where a length of the frame is not changed before and after the process of moving the first data of the first block to the second block. [14] The method of claims 11 to 13, further comprising: controlling an arrangement of the first data into each block of the non-volatile memory for each first number of pages among the plurality of pages included in each block; and Controlling rearrangement of the first data of the first block into the second block so that a value of the counter becomes data in which small data is arranged across two pages into data arranged on the first number of pages. [15] The method of claims 11 to 13, further comprising: Controlling the rearrangement of the first data of the first block into the second block so that a value of the counter does not become data in which data greater than or equal to a threshold is arranged across two pages. [16] The method of claims 11 to 14, further comprising: Comparing a first logical address indicating a logical position of the non-volatile memory specified by a first read command with a second logical address specified by a second read command following the first read command; and Determine that the first read command and the second read command are the random read commands. [17] The method of claims 11 to 16, further comprising: Comparing a first physical address with a second physical address, wherein the first physical address indicates a physical location of the non-volatile memory associated with a first logical address indicating a logical location of the non-volatile memory specified by a first read command, wherein the second physical address is associated with a second logical address specified by a second read command following the first read command, and Determine that the first read command and the second read command are the random read commands. [18] The method of claims 11 to 17, further comprising: generating each of a plurality of frames including payload data received from the host and an error correction code for detecting and correcting an error in the payload data, and writing the plurality of frames to the non-volatile memory; in the first data shifted from the first block to the second block by a first method, counting the number of accesses to the data by the counter for each of the frames of the second block; and in the first data, which are moved from the first block to the second block by a second method, for each element from the first unit, counting the number of accesses to the data by the counter, where the first method makes a length of the frame to be stored in the second block different from a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the payload data included in the frame to be stored in the second block equal to a length of the payload data included in the frame stored in the first block, and the second method makes a length of the frame to be stored in the second block equal to a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the payload data included in the frame to be stored in the second block different from a length of the payload data included in the frame stored in the first block. [19] The method of claim 18, further comprising: when generating the frame by the first method, controlling the rearrangement of the first data of the first block into the second block so that a frame including data in which a value of the counter is greater than or equal to a threshold value is not arranged across two pages; and when generating the frame by the second method, controlling the rearrangement of the first data of the first block into the second block so that two frames on which data having a value of the counter greater than or equal to a threshold is distributed are not arranged on two separate pages. [20] The method of claims 11 to 19, further comprising: Skipping incrementing the value of the counter corresponding to data specified by the read command in response to determining that the read command is the sequential read command.

Images