Method for manufacturing a semiconductor device and semiconductor device

Abstract

comprising a method for manufacturing a semiconductor device (100): • a step to form a semiconductor device structure (14) on a second principal surface of a wafer (12) which has a first principal surface and the second principal surface opposite each other; • a step to grind a peripheral part of the second main surface of the wafer (12) on which the semiconductor device structure (14) is formed, partially in a thickness direction starting from the second main surface in the direction of the first main surface; • a step to subdivide the wafer (12) in a direction perpendicular to the thickness direction at a position which is closer to the second principal surface than a depth to which the peripheral part of the wafer (12) is ground, and to subdivide a first subdivided wafer (18) which does not contain the semiconductor device structure (14) starting from the wafer (12); • a step to grind a peripheral part of a subdivided surface of the first subdivided wafer (18); and • a step to form a semiconductor device structure (14) on the subdivided area of ​​the first subdivided wafer (18), wherein the peripheral part of the subdivided area is ground.

Description

Background of the invention: Area

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. background

[0002] JP 2021-52178 A discloses a technique for reducing substrate costs by using a thinly sliced ​​wafer as a basis for epitaxial growth.

[0003] However, the process described above requires chamfering a wafer before cutting. Chamfering reduces the wafer diameter, which may prevent transport and processing using the same equipment as for a wafer before processing, or may necessitate adapting the equipment to accommodate the change in wafer diameter.

[0004] From US 2017 / 0053829 A1, it is known that a wafer formed from a SiC substrate with a first surface and a second surface is subdivided into individual chips. A starting point formed by a laser has a depth corresponding to the finished thickness of each chip along each division line formed on the first surface. The focal point of the laser beam is set in the SiC substrate at a predetermined distance from the second surface. The laser beam is directed at the second surface and moved relative to the SiC substrate, thereby forming cracks along a C-plane. By applying an external force, the wafer is separated into a first wafer with the first surface and a second wafer with the second surface.

[0005] US 2006 / 0038260 A1 discloses a conveying system for a semiconductor wafer that can be used before and after the adhesion of a substrate without modification. This allows for less stringent requirements regarding the wafer's finishing accuracy and the positioning accuracy between the wafer and substrate, thus improving manufacturing efficiency. The wafer has a step section at its edge that is deeper than the finished thickness and can be removed by partially abrading the back surface. Summary

[0006] In view of the problems described above, it is an objective of the present disclosure to provide a method for manufacturing a semiconductor device and a semiconductor device which are capable of carrying out transport and processing using the same apparatus as for a wafer prior to processing, by limiting a reduction with respect to the wafer diameter.

[0007] The features and advantages of the present disclosure can be summarized as follows.

[0008] A method for manufacturing a semiconductor device according to the present disclosure comprises: a step for forming a semiconductor device structure on a second principal face of a wafer, which has a first principal face and the second principal face opposite each other; a step for grinding a peripheral part of the second principal face of the wafer, on which the semiconductor device structure is formed, partially in a thickness direction starting from the second principal face in the direction of the first principal face; a step for subdividing the wafer in a direction perpendicular to the thickness direction at a position which is closer to the second principal face than a depth to which the peripheral part of the wafer is ground, and for subdividing a first subdivided wafer, which does not contain the semiconductor device structure, starting from the wafer;a step to grind a peripheral part of a subdivided area of ​​the first subdivided wafer; and a step to form a semiconductor device structure on the subdivided area of ​​the first subdivided wafer, wherein the peripheral part of the subdivided area is ground.

[0009] Other and further tasks, features and benefits of the revelation will become clearer from the following description. Brief description of the characters Fig. Figure 1 is a view showing a semiconductor device according to the first embodiment of the present disclosure. Fig. Figure 2 is a view showing a grinding step according to the first embodiment of the present disclosure. Fig. Figure 3 is a view showing a subdivision step according to the first embodiment of the present disclosure. Fig. Figure 4 is a view showing a connection step according to the first embodiment of the present disclosure. Fig. Figure 5 is an enlarged view showing the connection step according to the first embodiment of the present disclosure. Fig. Figure 6 is a view showing a chamfering step according to the first embodiment of the present disclosure. Fig. Figure 7 is a view showing a device design step according to the first embodiment of the present disclosure. Fig. Figure 8 is a view showing a semiconductor device according to a first comparative example. Fig. Figure 9 is a view that shows a subdivision step according to the first comparison example. Fig. Figure 10 is a view showing a chamfering step according to a second comparative example. Fig. Figure 11 is a view showing a subdivision step according to the second comparison example. Fig. Figure 12 is a view showing a modification of the grinding step according to the first embodiment of the present disclosure. Fig. Figure 13 is a view showing a first modification of the connection step according to the first embodiment of the present disclosure. Fig. Figure 14 is a view showing a second modification of the connection step according to the first embodiment of the present disclosure. Fig. Figure 15 is a view showing a modification of the chamfering step according to the first embodiment of the present disclosure. Fig. Figure 16 is a view showing a thickening step according to a second embodiment of the present disclosure. Fig. Figure 17 is a view showing a chamfering step according to the second embodiment of the present disclosure. Fig. Figure 18 is a view showing a device design step according to the second embodiment of the present disclosure. Fig. Figure 19 shows a modification of the chamfering step according to the second embodiment of the present disclosure. Fig. Figure 20 is a view showing a chamfering step according to a third embodiment of the present disclosure. Fig. Figure 21 is a view showing a device design step according to the third embodiment of the present disclosure. Fig. Figure 22 is a view showing a modification of the chamfering step according to the third embodiment of the present disclosure. Fig. Figure 23 is a view showing a grinding step to be carried out by an apparatus formed by attaching a grinding stone to a rotating edge processing machine. Fig. 24 is a view showing a saw loss (kerf loss) which is associated with the grinding step in Fig. 23. Description of the embodiments: First embodiment. [Method for processing a semiconductor device according to a first embodiment of the present disclosure]

[0010] A method for processing a semiconductor device according to a first embodiment of the present disclosure is described. Fig. Figure 1 is a view showing a semiconductor device according to the first embodiment of the present disclosure. A semiconductor device 100 comprises a wafer 12. The wafer 12 is, for example, a monocrystalline SiC wafer having a second principal face opposite a first principal face. It should be noted that the first principal face is a wafer back face, and the second principal face is a wafer front face.

[0011] Wafer 12 can be made of silicon (Si) or of a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include SiC- or GaN-based materials, gallium oxide-based materials, and diamond. Using a wide-bandgap semiconductor in a switching or diode device can increase the voltage withstand capability and allow for a reduction in size.

[0012] One aspect of the present disclosure is cost-efficiency, which is particularly advantageous with regard to a semiconductor device using a wafer that is not readily available. A specific advantageous example is a case in which the wafer 12 is made of SiC. SiC wafers are more difficult to increase in diameter, they are more expensive, and they provide a lower yield than Si wafers due to crystal defects. That is to say, there is a problem in that SiC wafers are not cost-effective.

[0013] Monocrystalline SiC is generally produced by a sublimation process. In this process, the temperature difference within a crystal increases as the wafer diameter increases, leading to a rise in crystal defects. This means that as the wafer diameter increases, SiC wafers become less suitable for substrates with fewer crystal defects.

[0014] The problems with SiC wafers described above can be solved simultaneously by reusing a SiC wafer with fewer crystal defects.

[0015] An epitaxial layer is formed on the second main surface of the wafer 12. A semiconductor device structure 14 is formed on the epitaxial layer. The semiconductor device structure 14 is, for example, a power device structure such as a MOSFET, a diode, or an IGBT. The formation of the semiconductor device structure 14 includes ion implantation and the formation of a surface electrode. It should be noted that the semiconductor device structure 14 is formed within the outermost peripheral part of the wafer 12, which is beveled.

[0016] It should be noted that if wafer 12 is made of GaN, the semiconductor device structure 14 is, for example, a GaN radio frequency device structure. Alternatively, a GaN radio frequency device structure can be formed on the SiC wafer 12.

[0017] Fig. Figure 2 is a view showing a grinding step according to the first embodiment of the present disclosure. In the grinding step of the present embodiment, a peripheral part of the second main surface of the wafer 12 is partially ground in a thickness direction starting from the second main surface and moving towards the first main surface, thereby forming a wafer 16 which has a convex structure in cross-section. This results in the formation of a semiconductor device 102 in which the semiconductor device structure 14 projects from the peripheral part.

[0018] The grinding step can be performed, for example, by an apparatus designed with a grinding wheel attached to a rotating edge-processing machine. The grinding wheel used is adapted to shape a wafer into any desired form by grinding its periphery. Alternatively, the grinding step can be performed by partially cutting the periphery using a singulation device.

[0019] Fig. Figure 23 is a view showing a grinding step to be performed by an apparatus formed by attaching a grinding wheel to a rotating edge-working machine. A view on the left side of Fig. Figure 23 shows a wafer after grinding using a new grinding wheel immediately after replacement. A view on the right side of Fig. Figure 23 shows a wafer after grinding using a worn grinding wheel. Since a large number of wafers are processed using the same grinding wheel, the wheel wears down, and the expected grinding process cannot be carried out. A wafer shape after processing corresponds to the right side in Figure 23. Fig. 23. In this case, the grinding step transforms corners 50 and 51 into a wafer with rounded corners 50a and 51a.

[0020] If corner 50a has a radius of 500 µm or less, dust generation and chipping due to a knife edge (which will be described later) can be reduced. If corner 50a has a smaller radius, i.e., a radius of 300 µm or less, dust generation and chipping can be reduced to a greater extent. If corner 50a has a radius of 100 µm or less, dust generation and chipping due to an edge shape can be largely suppressed.

[0021] Fig. 24 is a view showing a saw loss, which affects the grinding step in Fig. 23 accompanied. A view on the left side in Fig. Figure 24 shows a wafer before splitting, and a view on the right side in Fig. Figure 24 shows a wafer after subdivision. Fig. Figure 24 shows a saw loss which is generated when the grinding step passes corner 51 in the view on the left side. Fig. 23 transforms into a corner 51b with a large radius.

[0022] It should be noted that a saw loss is a so-called material loss, which refers to a portion that is removed as sections during wafer cutting. Specifically, a portion corresponds to a boundary between the wafers after subdivision in the view on the right. Fig. 24 with a saw loss.

[0023] If corner 51b has a large radius as shown in the view on the left in Fig. 24, is a form of an end part as shown in the view on the right in Fig. 24 sharp. Such a sharp shape is subsequently called a knife edge. The knife edge causes chipping and dust generation.

[0024] Chipping and dust generation due to a knife edge are largely prevented when the saw loss at the time of subdivision is larger. That is, even if corner 51b has a large radius, concerns about chipping and dust generation are reduced. For example, if the saw loss at the time of subdivision is greater than 100 µm, a radius of 200 µm or less is tolerated. If the saw loss is less than 100 µm up to 80 µm, a radius of 150 µm or less is tolerated. If the saw loss is much smaller, 60 µm or less, a radius of 100 µm or less is tolerated. It should be noted that if one of the subdivided wafers is machined and reused to rebuild a device, the saw loss and the radius of corner 51b are preferably small.

[0025] Furthermore, if the angle corresponds to a grade of 45 degrees to 135 degrees, dust generation or chipping from a knife edge can be reduced. If the angle is 60 degrees or less than 120 degrees, dust generation or chipping can be reduced to a greater extent. If the angle is 75 degrees or less than 105 degrees, dust generation or chipping from a knife edge can be largely suppressed.

[0026] It should be noted that the grinding width is preferably small. This is because if the grinding width is large, a region with a thin substrate at a peripheral part of the wafer 16 will be large, which can easily cause chipping and cracking. Chipping and cracking are known to occur frequently if the grinding width is 10 mm or more. For this reason, the grinding width is preferably less than 10 mm. A smaller width, such as less than 5 mm, 3 mm, or 1 mm, is preferable.

[0027] The grinding step is preferably performed only to a depth that leaves a substrate thickness of 100 µm or more. This prevents breakage and splintering that occur at the end of a wafer intended for reuse after the subdivision step (as described later).

[0028] Furthermore, the grinding step can be performed before the formation of the epitaxial layer, which is performed before the formation of the semiconductor device structure 14, or it can be performed after the formation of the epitaxial layer. The grinding step is performed outside the semiconductor device structure 14, so that no damage to the semiconductor device structure 14 occurs.

[0029] Fig. Figure 3 is a view showing a subdivision step according to the first embodiment of the present disclosure. In the subdivision step of the present embodiment, the wafer 16 is subdivided in a direction perpendicular to the thickness direction at a position closer to the second principal surface than a depth to which the peripheral part is ground in the wafer 12. By means of this subdivision, the semiconductor device 102 is divided into a subdivided wafer 18, which contains the semiconductor device structure 14, and a subdivided wafer 20, which does not contain the semiconductor device structure 14. That is, the subdivided wafer 20, which does not contain the semiconductor device structure 14, is subdivided starting from the wafer 16.

[0030] At this point, a peripheral part of the subdivided wafer 18 does not become a knife edge. This is because an outermost peripheral part, which could become a knife edge, can be eliminated beforehand by removing the Fig. The grinding step shown in section 2 is performed. This results in a progression of a process to manufacture a semiconductor device without dust generation or chipping in the subdivided wafer 18.

[0031] Furthermore, the wafer diameter of the subdivided wafer 20 is the same as the wafer diameter of the original wafer 12. This is because the grinding step of the present embodiment does not eliminate an outermost peripheral part, unlike a chamfering step (which will be discussed later with reference to Fig. 10 is described). That is, limiting a reduction with respect to a wafer diameter allows transport and processing using the same equipment as for a wafer before processing.

[0032] It should be noted that a method for subdividing the wafer can be a method involving contact with a singulation saw or the like, or a non-contact method using a laser or the like. For example, a laser cutting technique can be used, which provides a modification layer by means of a laser and performs a subdivision in a direction perpendicular to a direction originating from the first main face towards a second main face.

[0033] The substrate thickness of the subdivided wafer 20 is preferably 100 µm or more. This is because if the substrate thickness of the subdivided wafer 20 is small, breakage in subsequent steps may occur. Fig. 4 to 7 may occur, or transport and processing may become difficult due to a significant delay.

[0034] Fig. Figure 4 is a view showing a joining step according to the first embodiment of the present disclosure. In the joining step of the present embodiment, a further subdivided wafer 20 is joined to a first principal surface of the subdivided wafer 20. This results in the formation of a joined wafer 21, which has the same wafer diameter as the original wafer 12. By joining a plurality of subdivided wafers 20, as described above, to increase a substrate thickness, wafer distortion can be prevented to a greater extent than in a case where the subdivided wafer 20 is used individually.

[0035] Fig. Figure 5 is an enlarged view showing the joining step according to the first embodiment of the present disclosure. The joining step of the present embodiment can, for example, be carried out using a technique based on room-temperature joining. At this point, an amorphous layer 24 is formed at the joining interfaces of the joined wafer 21.

[0036] Room temperature joining is a joining method capable of producing a clean interface because a metal layer or similar is not present at the joining interface. The bond strength at the time of joining can be increased by performing a planarization step to flatten at least one of the joining interfaces by polishing prior to the joining process. It should be noted that planarization can be achieved by CMP or similar methods instead of polishing.

[0037] Fig. Figure 6 shows a chamfering step according to the first embodiment of the present disclosure. In the chamfering step of the present embodiment, a peripheral portion on one side of a second main surface of the joined wafer 21 is ground into a chamfered shape. That is, a peripheral portion of a partitioned surface of the partitioned wafer 20 on the side of the second main surface is ground into a chamfered shape. This results in a joined wafer 23 in which a partitioned wafer 30, the peripheral portion of which is ground into a chamfered shape on one side of a second main surface, and the unprocessed partitioned wafer 20 are joined together. Since this step can bring the shape of the joined wafer 21 close to the shape of the original wafer 12, fine-tuning for wafer alignment is unnecessary.

[0038] Fine-tuning of wafer alignment is described in detail. During wafer alignment, a location where the light transmittance is equal to or less than a threshold value at the time of scanning a wafer with laser light is identified as the end of the wafer. If an end of a wafer is processed into a beveled shape, the end of the wafer is easily identified because the surface roughness of the beveled portion makes it unlikely that light will pass through.

[0039] If a wafer is ground in such a way that a cross-section has a convex structure, for example, the end portion of the wafer will be thinner than the middle portion. In this case, the light transmittance at the end portion of the wafer may not be equal to or less than the threshold, and the end portion of the wafer may not be detected.

[0040] For the reason described above, if the wafer is processed by the same apparatus as a general wafer, it is necessary to adjust the light transmission threshold as needed or to define a new threshold that allows for the detection of the end faces of both wafers. In other words, fine-tuning of the wafer orientation is required in any case. In the chamfering step of the present embodiment, the peripheral part on the side of the second main surface of the joined wafer 21 is ground into a chamfered shape. The chamfering step has the advantage that fine-tuning is unnecessary.

[0041] The joined wafer 23 can be processed to achieve a desired substrate thickness throughout, for example by grinding, polishing, CMP, or similar methods. The desired substrate thickness can, for example, be the same as that of wafer 12. Using this configuration, when the joined wafer 23 is reused as a wafer, it is possible to transport and process it using the same equipment as for a wafer prior to processing, without having to make any adjustments that would be necessary due to a difference in substrate thickness.

[0042] Fig. Figure 7 is a view showing a device formation step according to the first embodiment of the present disclosure. In the device formation step of the present embodiment, an epitaxial layer is formed on one side of a second main surface of the joined wafer 23, and the semiconductor device structure 14 is formed on the epitaxial layer. That is, the semiconductor device structure 14 is formed on a partitioned surface of the partitioned wafer 30. It should be noted that the semiconductor device structure 14 is formed within an outermost peripheral part of the partitioned wafer 30, which is chamfered.

[0043] A semiconductor device 108, obtained in the manner described above, has a similar function to the semiconductor device 100. For this reason, the semiconductor device 108 can successively perform the functions described in the Fig. The semiconductor device 100 will undergo the steps shown in 2 to 7.

[0044] As described above, the limits in the Fig. Steps 2 to 7 described result in a reduction of the wafer diameter of a semiconductor device. This enables transport and processing using the same equipment as for a wafer before processing. [Method for processing a semiconductor device according to a comparative example]

[0045] To describe the effects of a semiconductor device according to the present disclosure, a method for processing a semiconductor device according to a comparative example is described. Fig. Figure 8 is a view showing a semiconductor device according to a first comparative example. A semiconductor device 500 has a wafer 502 and a semiconductor device structure 504, and has a similar configuration to the semiconductor device 100.

[0046] Fig. Figure 9 shows a subdivision step according to the first comparative example. In the subdivision step according to the first comparative example, wafer 502 is subdivided in one direction perpendicular to a thickness direction. By means of this subdivision, the semiconductor device 500 is divided into a subdivided wafer 506, which contains the semiconductor device structure 504, and a subdivided wafer 508, which does not contain the semiconductor device structure 504.

[0047] At this point, a peripheral part of the subdivided wafer 506 becomes a thin and sharp knife edge. If a process for manufacturing a semiconductor device using a wafer whose peripheral part is a knife edge has progressed, a support that holds the wafer can be scraped away, resulting in dust or chipping. For this reason, processing is necessary to prevent a peripheral part from becoming a knife edge before performing a wafer subdivision step.

[0048] Fig. Figure 10 is a view showing a chamfering step according to a second comparison example. In the second comparison example, the chamfering step is performed with respect to a semiconductor device 500, which has a similar configuration to that in the first comparison example before a subdivision step.

[0049] In the chamfering step according to the second comparative example, a peripheral part of a wafer 502 is ground such that the peripheral part is penetrated in one thickness direction. That is, an outermost peripheral part of the wafer 502 is removed. This results in the production of a segmented wafer 510, which has a semiconductor device structure 504 and a peripheral part 512 of the wafer that does not contain the semiconductor device structure 504.

[0050] Fig. Figure 11 shows a subdivision step according to the second comparative example. In the subdivision step according to the second comparative example, the subdivided wafer 510 is subdivided in one direction perpendicular to the thickness direction. By means of this subdivision, the subdivided wafer 510 is divided into a subdivided wafer 514, which has the semiconductor device structure 504, and a subdivided wafer 516, which does not have the semiconductor device structure 504.

[0051] At this point, a peripheral part of the subdivided wafer 514 does not become a knife edge. This is because an outermost peripheral part, which could become a knife edge, is eliminated beforehand by removing the material in the Fig. The chamfering step shown in Figure 10 is performed. This results in the progression of a process for manufacturing a semiconductor device without dust generation or chipping in the partitioned wafer 514.

[0052] The diameter of the subdivided wafer 516 is smaller than the diameter of the original wafer 502. This is because the outermost peripheral part is removed by performing the chamfering step, which is described in Fig. Figure 10 shows that this prevents transport and processing using the same apparatus as for a wafer prior to processing at the time of reuse of the subdivided wafer 516, or creates the need to adapt the apparatus so that it can handle a change in wafer diameter. The present disclosure can solve this problem. [Method for processing a semiconductor device according to a modification of the first embodiment of the present disclosure]

[0053] The following illustrates processing methods according to modifications of the present embodiment. Fig. Figure 12 is a view showing a modification of the grinding step according to the first embodiment of the present disclosure. One grinding step of the modification differs from the grinding step in Fig. 2 differs in that the grinding step additionally includes a step to grind the entirety of a peripheral part of a wafer.

[0054] A top view in Fig. Figure 12 shows a view of semiconductor device 100 before the grinding step. A lower view in Fig. Figure 12 shows a semiconductor device 102a after the grinding step. The grinding step of the modification includes a process for grinding the entirety of an outermost peripheral part of a wafer in addition to the grinding step of the first embodiment. For this reason, the wafer diameter of wafer 16a after the grinding step is smaller than the wafer diameter of wafer 12.

[0055] Since one end portion of the back side of wafer 16 is chamfered, the substrate thickness is reduced in the direction of the end portion. This can result in breakage and chipping at the end portion on the back side of wafer 16. The grinding step of the modification prevents breakage and chipping at the end portion by grinding a peripheral portion on the back side of wafer 16a.

[0056] It should be noted that during the grinding step of the modification, it is preferable to have a small width for grinding the entire outermost peripheral part of a wafer, i.e., a small reduction in wafer diameter. This is because if the machining width is large, the wafer diameter of a future reused wafer will be small, which can hinder transport and processing during the formation of a fixture structure.

[0057] If the reduction in wafer diameter is less than 1 mm, it can be achieved by adjusting the apparatus or changing the tool. If the reduction in wafer diameter is less than 0.8 mm, more apparatuses can handle the reduction without any adjustment or tool change. If the reduction in wafer diameter is less than 0.5 mm, many more apparatuses can handle the reduction without any adjustment or tool change. Based on the foregoing, a grinding width for the entirety of a peripheral part of a wafer is preferably less than 1 mm, more preferably less than 0.8 mm, and further preferably less than 0.5 mm.

[0058] The width required to grind the entire outermost peripheral part of a wafer during the grinding step of the modification is much smaller than the width required to machine a peripheral part during the chamfering step, as described in the second comparison example. This is because the chamfering step, as described in the second comparison example, can be achieved by creating a convex structure during the grinding step of the modification. Therefore, the grinding step of the modification exhibits a limitation in terms of reducing the wafer diameter compared to the comparison example.

[0059] Fig. Figure 13 shows a first modification of the joining step according to the first embodiment of the present disclosure. In a joining step of the first modification, the subdivided wafer 20 and a subdivided wafer 22, which has a smaller wafer diameter than the subdivided wafer 20, are joined together. This results in the formation of a joined wafer 21a, which has a convex structure in cross-section. The formation of a joined wafer with a convex structure allows for the omission of a chamfering step, which would otherwise be necessary to prevent warping of the wafer.

[0060] Fig. Figure 14 shows a second modification of the joining step according to the first embodiment of the present disclosure. A joining step of the second modification differs from the first embodiment with respect to a planarization process that is performed prior to joining. Specifically, polishing of a peripheral part of a joining interface is carried out to a greater extent than polishing of a central part of the joining interface. As a result, a peripheral part of a wafer becomes thinner than a central part, and an unjoined region 26 is formed at a peripheral part of a joining interface of a joined wafer 21b.

[0061] The substrate thickness of each of the subdivided wafers that are joined together can be measured by measuring the unjoined region 26, for example, using a light interference wafer thickness measurement. That is, the depth of a connection interface that the joined wafer 21b has can be detected in advance.

[0062] For example, if a wafer is used that has undergone multiple subdivision and interconnection steps, an interconnection interface may be present near the semiconductor device structure 14, which contains a finished semiconductor device. In this case, the finished semiconductor device may suffer from poor characteristics and a deterioration in reliability. The present modification can detect an interconnection interface located near the semiconductor device structure 14 in advance. Therefore, the problem described above can be avoided by grinding and removing any affected interconnection interface.

[0063] It should be noted that moisture will penetrate the unconnected region described above during a subsequent wet etching step. This moisture cannot be removed by centrifugal drying, which would be a post-processing step, and it can cause problems in subsequent manufacturing steps. If the unconnected region is 1 mm or less wide extending from a periphery, the amount of moisture that penetrates is negligible. For this reason, the unconnected region is preferably 1 mm or less wide extending from the periphery of the connected wafer 21b.

[0064] Fig. Figure 15 shows a modification of the chamfering step according to the first embodiment of the present disclosure. In this modification, a chamfering step processes the peripheral part on the side of the second principal surface of the joined wafer 21 such that a cross-section has a convex structure. This results in a joined wafer 23a in which a subdivided wafer 30a, whose inner diameter is reduced due to a uniform grinding of a peripheral part, and a subdivided wafer 20, whose cross-section is configured to have a convex structure by uniform grinding of a peripheral part to a fixed depth, are joined together. That is, the inner diameter of an upper surface of the subdivided wafer 20a is identical to the inner diameter of the subdivided wafer 30a.

[0065] The chamfering step of the present modification can, for example, be applied to the joined wafer 21b according to the second modification of the joining step. In this case, the unjoined region 26 can be removed by the chamfering step. Second embodiment. [Method for processing a semiconductor device according to a second embodiment of the present disclosure]

[0066] Fig. Figure 16 is a view showing a thickening step according to a second embodiment of the present disclosure. In the first embodiment, the joining step is performed to join a plurality of partitioned wafers 20 to prevent warping of the partitioned wafer 20. In the thickening process of the present embodiment, an epitaxial layer 32 is formed on a partitioned wafer 20. This results in the formation of a thick wafer 41, which has the same wafer diameter as the original wafer 12. By increasing a substrate thickness, as described above, warping of the wafer can be prevented to a greater extent than in a case where the partitioned wafer 20 is used individually. It should be noted that the formation of the epitaxial layer can be performed on either a first or a second main surface.

[0067] Preferably, the difference in resistivity between the epitaxial layer 32 and the subdivided wafer 20 is small. This is because if the difference in resistivity between the epitaxial layer 32 and the subdivided wafer 20 becomes large, electrical properties will change, resulting in fluctuations in the electrical properties of the entire semiconductor device during the formation of a semiconductor device structure 14 in a subsequent step.

[0068] If the above-described difference in resistivity is 30 mΩ·m or less, variations in the electrical properties of the entire semiconductor device fall within a range that allows the semiconductor device to be used equivalently to an original semiconductor device. If the above-described difference in resistivity is 15 mΩ·m or less, variations in the electrical properties of the entire semiconductor device fall within an acceptable error range. If the above-described difference in resistivity is 6 mΩ·m or less, there are virtually no variations in the electrical properties of the entire semiconductor device.

[0069] Based on the above, the difference in specific resistance between the epitaxial layer 32 and the subdivided wafer 20 is preferably 30 mΩ·m or less, more preferably 15 mΩ·m or less, and furthermore preferably 6 mΩ·m or less.

[0070] The epitaxial layer 32 is preferably thick. This is because, if the epitaxial layer 32 is thin, the desired effect of suppressing warping of the subdivided wafer 20 cannot be sufficiently achieved.

[0071] If the thickness of the epitaxial layer 32 is 50 µm or more, warping can be sufficiently suppressed, but a defect may occur during transport or suction in the manufacturing apparatus to be used. If the thickness of the epitaxial layer 32 is 100 µm or more, warping can be sufficiently suppressed, and a defect during transport or suction in the manufacturing apparatus to be used hardly occurs. If the thickness of the epitaxial layer 32 is 150 µm, a semiconductor device 114 has a thickness identical to that of a wafer before subdivision, and no defect occurs during transport or suction in the manufacturing apparatus to be used.

[0072] Based on the above, the thickness of the epitaxial layer 32 is preferably 50 µm or more, more preferably 100 µm or more, and furthermore preferably 150 µm.

[0073] Fig. Figure 17 is a view showing a chamfering step according to the second embodiment of the present disclosure. In the chamfering step of the present embodiment, a peripheral part of one side of a second main surface of the thick-layer wafer is processed into a chamfered shape. This results in a thick-layer wafer 43 in which an epitaxial layer 34 is formed on the unprocessed wafer 20, the peripheral part of which is processed into a chamfered shape on one side of a second main surface.

[0074] The thick-film wafer 43 can be processed to achieve a desired substrate thickness, for example by grinding, polishing, CMP, or similar methods. The desired substrate thickness can, for example, be the same as that of wafer 12. With this configuration, when the thick-film wafer 43 is reused, it is possible to transport and process it using the same equipment as for a pre-processed wafer, without having to make any adjustments required due to a difference in substrate thickness.

[0075] Fig. Figure 18 is a view showing a device formation step according to the second embodiment of the present disclosure. In the device formation step of the present embodiment, an epitaxial layer is formed on one side of a second main surface of the thick-film wafer 43, and the semiconductor device structure 14 is formed on the epitaxial layer. It should be noted that the semiconductor device structure 14 is formed within the outermost peripheral part of the epitaxial layer 34, which is chamfered.

[0076] A semiconductor device 118, obtained in the manner described above, has a similar function to the semiconductor device 100. For this reason, the semiconductor device 118 can successively perform the function described in the Fig. 2 to 7 or the Fig. The semiconductor device 100 is subjected to the steps shown in sections 2 and 3 and 16 to 18.

[0077] As described above, the limits in the Fig. Steps 16 to 18 describe a reduction in the wafer diameter of a semiconductor device. This enables transport and processing using the same equipment as for a wafer before processing. [Method for processing a semiconductor device according to a modification of a second embodiment of the present disclosure]

[0078] Fig. Figure 19 shows a modification of the chamfering step according to the second embodiment of the present disclosure. In this modification, a chamfering step processes the peripheral part on the side of the second main surface of the thick-film wafer 41 such that a cross-section has a convex structure. This results in a thick-film wafer 43a in which an epitaxial layer 34a, the peripheral part of which is uniformly ground, is formed on a subdivided wafer 20b, the peripheral part of which is uniformly ground to a fixed depth.

[0079] For example, the chamfering step of the present modification can be performed with respect to a semiconductor device which has a non-connected region 26, such as semiconductor device 104b. In this case, the non-connected region 26 can be removed by the chamfering step. Third embodiment.

[0080] Fig. Figure 20 shows a chamfering step according to a third embodiment of the present disclosure. In the first and second embodiments, a chamfering step is performed after the entire wafer has been thickened to suppress warping of wafer 16. The substrate thickness of a subdivided wafer according to the present embodiment falls within a range where warping does not affect manufacturing steps. For this reason, the subdivided wafer is reused without being thickened.

[0081] This results in a reduction in the number of man-hours required for wafer reuse.

[0082] In the chamfering step of the present embodiment, a peripheral part on one side of a second main surface of a partitioned wafer is processed into a chamfered shape. This results in obtaining a partitioned wafer 30b, wherein a peripheral part of one side of a second main surface thereof is processed into a chamfered shape.

[0083] Fig. Figure 21 is a view showing a device formation step according to the third embodiment of the present disclosure. In the device formation process of the present embodiment, an epitaxial layer is formed on the side of the second main surface of the partitioned wafer 30b, and a semiconductor device structure 14 is formed on the epitaxial layer. It should be noted that the semiconductor device structure 14 is formed within an outermost peripheral part of the partitioned wafer 30b, which is chamfered.

[0084] A semiconductor device 128, obtained in the manner described above, has a similar function to the semiconductor device 100. For this reason, the semiconductor device 128 can successively perform the function described in the Fig. The semiconductor device 100 will undergo the steps shown in 2 to 7.

[0085] As described above, the limits in the Fig. 20 and Fig. The steps shown in 21 demonstrate a reduction in the wafer diameter of a semiconductor device. This enables transport and processing using the same equipment as for a wafer before processing.

[0086] Fig.Figure 22 shows a modification of the chamfering step according to the third embodiment of the present disclosure. In the chamfering step of the modification, a peripheral part of one side of a second principal surface of a partitioned wafer is processed such that a cross-section has a convex structure. This results in obtaining a partitioned wafer 30c, wherein a peripheral part of it is uniformly ground.

[0087] It should be noted that although aspects have been described in the present revelation that join two subdivided wafers, only one joining of a multitude of subdivided wafers is required. That is, details of the present revelation can be applied to one aspect that joins three or more subdivided wafers.

[0088] The following sections describe various aspects of the present revelation together as appendices. (Annex 1)

[0089] comprising a method for manufacturing a semiconductor device: a step to form a semiconductor device structure on a second principal surface of a wafer which has a first principal surface and the second principal surface opposite each other; a step to grind a peripheral part of the second main surface of the wafer, on which the semiconductor device structure is formed, partly in a thickness direction starting from the second main surface in the direction of the first main surface; a step to subdivide the wafer in a direction perpendicular to the thickness direction at a position which is closer to the second principal surface than a depth to which the peripheral part of the wafer is ground, and to subdivide a first subdivided wafer which does not contain the semiconductor device structure starting from the wafer; a step towards grinding a peripheral part of a subdivided surface of the first subdivided wafer; and a step to form a semiconductor device structure on the subdivided area of ​​the first subdivided wafer, wherein the peripheral part of the subdivided area is ground away. (Annex 2)

[0090] Method for manufacturing a semiconductor device according to Annex 1 further comprising a step to join a second subdivided wafer to the first main surface of the first subdivided wafer. (Annex 3)

[0091] Method for manufacturing a semiconductor device according to Annex 2, wherein an amorphous layer is formed at a connection interface between the first subdivided wafer and the second subdivided wafer. (Annex 4)

[0092] further comprising a method for manufacturing a semiconductor device according to Annex 2 or 3 a step to polish and planarize a joining interface of the first subdivided wafer or the second subdivided wafer prior to joining, wherein Polishing is carried out to a greater extent on a peripheral part of the connection interface than polishing on a central part of the connection interface. (Annex 5)

[0093] Method for manufacturing a semiconductor device according to any one of Annexes 1 to 4, wherein a cross-section of the wafer after grinding the peripheral part of the second main surface and before subdivision shows a convex structure. (Annex 6)

[0094] Method for manufacturing a semiconductor device according to Annex 5 further comprising a step towards grinding an entirety of an outermost peripheral part of the wafer before subdividing the wafer. (Annex 7)

[0095] Method for manufacturing a semiconductor device according to any one of Annexes 1 to 6, wherein The peripheral part of the subdivided surface of the first subdivided wafer is ground into a beveled shape. (Annex 8)

[0096] Method for manufacturing a semiconductor device according to any one of Annexes 1 to 6, wherein a cross-section of the wafer after grinding the peripheral part of the subdivided area of ​​the first subdivided wafer and before forming the semiconductor device structure on the subdivided area has a convex structure. (Annex 9)

[0097] Method for manufacturing a semiconductor device according to Annex 1 further comprising a step towards forming an epitaxial layer on the first subdivided wafer. (Annex 10)

[0098] Method for manufacturing a semiconductor device according to any one of Annexes 1 to 9, wherein the wafer is made from a semiconductor with a wide band gap. (Annex 11)

[0099] Including semiconductor device: a first subdivided wafer having a first principal surface and a second principal surface opposite each other, and having a semiconductor device structure on the second principal surface; and a second subdivided wafer, which is connected to the first main surface of the first subdivided wafer, wherein a non-connected region is formed at a peripheral part of a connection interface between the first subdivided wafer and the second subdivided wafer. (Annex 12)

[0100] Semiconductor device according to Annex 11, wherein an amorphous layer is formed at the connection interface. (Annex 13)

[0101] Semiconductor device according to Annex 11 or 12, wherein a peripheral part of the first subdivided wafer is processed into a beveled shape. (Annex 14)

[0102] Semiconductor device according to one of Annexes 11 to 13, wherein The wafer diameter of the first subdivided wafer is smaller than the wafer diameter of the second subdivided wafer. (Annex 15)

[0103] Semiconductor device according to one of Annexes 11 to 14, wherein a cross-section of the second subdivided wafer exhibits a convex structure, and The inner diameter of an upper surface of the second subdivided wafer is identical to the inner diameter of the first subdivided wafer. (Annex 16)

[0104] Including semiconductor device: a first subdivided wafer which has a first main surface and a second main surface opposite each other; an epitaxial layer formed on the second main surface of the first subdivided wafer; and a semiconductor device structure formed on the epitaxial layer, where a cross-section of the first subdivided wafer has a convex structure. (Annex 17)

[0105] Semiconductor device according to Annex 16, wherein the epitaxial layer has a thickness of 50 µm or more. (Annex 18)

[0106] Including semiconductor device: a first subdivided wafer which has a first main surface and a second main surface opposite each other and which has a semiconductor device structure on the second main surface, where a cross-section of the first subdivided wafer has a convex structure.

Claims

[1] A method for manufacturing a semiconductor device comprising: • a step to form a semiconductor device structure (14) on a second principal surface of a wafer (12) which has a first principal surface and the second principal surface opposite each other; • a step to grind a peripheral part of the second main surface of the wafer (12) on which the semiconductor device structure (14) is formed, partially in a thickness direction starting from the second main surface in the direction of the first main surface; • a step to subdivide the wafer (12) in a direction perpendicular to the thickness direction at a position which is closer to the second principal surface than a depth to which the peripheral part of the wafer (12) is ground, and to subdivide a first subdivided wafer (18) which does not contain the semiconductor device structure (14) starting from the wafer (12); • a step to grind a peripheral part of a subdivided surface of the first subdivided wafer (18); and • a step to form a semiconductor device structure (14) on the subdivided area of ​​the first subdivided wafer (18), wherein the peripheral part of the subdivided area is ground. [2] Method for manufacturing a semiconductor device (100) according to claim 1 further comprising a step for connecting a second subdivided wafer (18) to the first main surface of the first subdivided wafer (18). [3] Method for manufacturing a semiconductor device (100) according to claim 2, wherein an amorphous layer (24) is formed at a connection interface between the first subdivided wafer (18) and the second subdivided wafer (18). [4] Method for manufacturing a semiconductor device (100) according to claim 2 or 3 further comprising • a step for polishing and planarizing a joining interface of the first subdivided wafer (18) or the second subdivided wafer (18) prior to joining, wherein • polishing is carried out to a greater extent on a peripheral part of the connection interface than polishing on a central part of the connection interface. [5] Method for manufacturing a semiconductor device (100) according to any one of claims 1 to 4, wherein a cross-section of the wafer (12) has a convex structure after grinding the peripheral part of the second main surface and before subdivision. [6] Method for manufacturing a semiconductor device (100) according to claim 5 further comprising a step for grinding an entirety of an outermost peripheral part of the wafer (12) prior to subdividing the wafer (12). [7] Method for manufacturing a semiconductor device (100) according to any one of claims 1 to 6, wherein the peripheral part of the subdivided surface of the first subdivided wafer (18) is ground into a beveled shape. [8] Method for manufacturing a semiconductor device (100) according to any one of claims 1 to 6, wherein a cross-section of the wafer (12) has a convex structure after grinding the peripheral part of the subdivided area of ​​the first subdivided wafer (18) and before forming the semiconductor device structure (14) on the subdivided area. [9] Method for manufacturing a semiconductor device (100) according to claim 1 further comprising a step for forming an epitaxial layer (32) on the first subdivided wafer (18). [10] Method for manufacturing a semiconductor device (100) according to any one of claims 1 to 9, wherein the wafer (12) is formed from a wide bandgap semiconductor. [11] Semiconductor device (100) comprising: • a first subdivided wafer (18) having a first principal surface and a second principal surface opposite each other, and having a semiconductor device structure (14) on the second principal surface; and • a second subdivided wafer (18) which is connected to the first main surface of the first subdivided wafer (18), wherein • a non-connected region (26) is formed at a peripheral part of a connection interface between the first subdivided wafer (18) and the second subdivided wafer (18). [12] Semiconductor device (100) according to claim 11, wherein an amorphous layer (24) is formed at the connection interface. [13] Semiconductor device (100) according to claim 11 or 12, wherein a peripheral part of the first subdivided wafer (18) is processed into a beveled shape. [14] Semiconductor device (100) according to any one of claims 11 to 13, wherein a wafer (12) diameter of the first partitioned wafer (18) is smaller than a wafer (12) diameter of the second partitioned wafer (18). [15] Semiconductor device (100) according to any one of claims 11 to 14, wherein • a cross-section of the second subdivided wafer (18) exhibits a convex structure, and • an inner diameter of an upper surface of the second subdivided wafer (18) is identical to an inner diameter of the first subdivided wafer (18). [16] Semiconductor device (100) comprising: • a first subdivided wafer (18) having a first principal surface and a second principal surface opposite each other; • an epitaxial layer (32) which is formed on the second main surface of the first subdivided wafer (18); and • a semiconductor device structure (14) which is formed on the epitaxial layer (32), wherein • a cross-section of the first subdivided wafer (18) exhibits a convex structure. [17] Semiconductor device (100) according to claim 16, wherein the epitaxial layer (32) has a thickness of 50 µm or more. [18] Semiconductor device (100) comprising: • a first subdivided wafer (18) having a first main surface and a second main surface opposite each other and having a semiconductor device structure (14) on the second main surface, wherein • a cross-section of the first subdivided wafer (18) exhibits a convex structure.

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