Semiconductor package comprising a first and a second substrate connected by connecting elements of a conductor frame

Abstract

Semiconductor package (20), comprising a plurality of conductors (21.2), comprising first conductor (21.2A) and second conductor (21.2B); a first substrate (22) connected to the first conductors (21.2A); a second substrate (23) connected to one or more connecting elements (11.3); and an encapsulation (24) covering the first and second substrates (22, 23) and inner sections of the first conductor (21.2A) and the second conductor (21.2B).

Description

TECHNICAL BACKGROUND

[0001] The present disclosure relates to a semiconductor package and a method for its manufacture.

[0002] In the field of semiconductor transistor packages, there are some in which two substrates are arranged within a common package containing a conductor frame. Semiconductor transistor dies are deposited onto a first substrate of this package, and at least one semiconductor driver die is deposited onto a second substrate. The contact terminals of the semiconductor dies and the driver dies are connected to the conductors of the conductor frame via bond wires.

[0003] Recently, however, it has become apparent that the manufacturing processes currently used for these semiconductor packages are quite complex and therefore expensive. In particular, the way in which the substrates are currently connected to the conductor frame has proven to be very complex.

[0004] For these and other reasons, there is a need for the present disclosure. SUMMARY

[0005] A first aspect of the present disclosure relates to a semiconductor package comprising a plurality of conductors, including first conductors and second conductors, a first substrate connected to the first conductors, a second substrate connected to one or more connecting elements, and an encapsulation covering the first and second substrates and inner sections of the first conductors and the second conductors.

[0006] One or both of the first and second substrates are one or more of a printed circuit board, a direct copper bonded substrate, a direct aluminum bonded substrate, an active metal braze substrate, an insulated metal substrate, a ceramic layer or a silicon layer.

[0007] The semiconductor package according to the first aspect may further include solder layers between the first substrate and the first conductors and solder layers between the second substrate and the connecting elements.

[0008] The first substrate is designed to accommodate one or more semiconductor transistors, and the second substrate is designed to accommodate one or more semiconductor driver dies.

[0009] A second aspect of the present disclosure relates to a method for manufacturing a semiconductor package, the method comprising: providing a conductor frame comprising a frame, several conductors connected to the frame, comprising first conductors and second conductors, and one or more connecting elements connected to the frame; connecting a first substrate to the first conductors; connecting a second substrate to the connecting elements; attaching one or more semiconductor transistor dies to the first substrate; attaching a driver die to the second substrate; connecting the semiconductor transistor die to the conductors of the conductor frame and to the driver die by bond wires; applying an encapsulation to cover the first and second substrates and inner sections of the conductors of the conductor frame; and removing the frame of the conductor frame.

[0010] Both the first and second substrates can be connected to the first conductors and to the connecting elements of the conductor frame by applying a layer of solder to one or both of the respective connection partners, bringing them into contact with each other, and then performing a soldering reflow process.

[0011] In particular, a single simultaneous soldering reflow process can be performed to connect the first substrate to the first conductors and the second substrate to the connecting elements.

[0012] Alternatively, both the first and second substrates can be connected to the first conductors and the connecting elements of the conductor frame by laser welding one or both of the respective connection partners. In particular, these connections can be made in a single pass of a welding tool.

[0013] The proposal in this disclosure not only strengthens the connections between these connections but also significantly improves line flexibility, as the production line can be operated with a uniform configuration instead of separating DCB packages from conductor frame packages. Implementing this disclosure can streamline the production process, improve UPH (units per hour), and significantly enhance product quality by increasing connection strength by up to 15 times, effectively eliminating the risk of wire damage such as wire breakage and wire sag. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings serve to enhance understanding of the embodiments and are an integral part of this description. The drawings illustrate embodiments and, together with the description, explain the principles underlying them. Other embodiments and many of the intended advantages of the embodiments will become readily apparent upon closer examination of the following detailed description.

[0015] The elements in the drawings are not necessarily to scale with each other. Identical reference numbers denote identical or similar elements. Fig. Figure 1 shows a perspective view of an example of a ladder frame. Fig. Figure 2 shows a perspective view of an example of a semiconductor package without encapsulation at a stage after removal of the conductor frame. Fig. Figure 3 shows a perspective view of a section of an example printed circuit board (PCB). Fig. Figure 4 shows a perspective view of the semiconductor package. Fig. 2 after applying the encapsulation. Fig. Figure 5 shows a flowchart of a process for manufacturing a semiconductor package. DESCRIPTION OF EXECUTION FORMS

[0016] The following detailed description refers to the accompanying drawings, which form part of this description and illustrate specific embodiments in which the disclosure can be practiced. In this context, directional terms such as "top," "bottom," "front," "back," etc., are used in relation to the orientation of the described figure(s). Since components of embodiments can be positioned in a variety of different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of this disclosure.The following detailed description is therefore not to be understood in a restrictive sense, and the scope of the present disclosure is defined by the attached claims.

[0017] It is understood that the features of the various embodiments described herein may be combined with one another, unless expressly stated otherwise.

[0018] As used in this description, the terms "connected," "attached," "connected," "coupled," and / or "electrically connected / coupled" do not imply that the elements or layers must be in direct contact with each other; rather, that no intermediate elements or layers are provided between the "connected," "attached," "connected," "coupled," and / or "electrically connected / coupled" elements. However, according to the disclosure, the above terms may optionally also have the specific meaning that the elements or layers are in direct contact with each other, i.e., that no intermediate elements or layers are provided between the "connected," "attached," "connected," "coupled," and / or "electrically connected / coupled" elements.

[0019] Furthermore, the word "over" in reference to a part, element, or layer of material formed or arranged "over" a surface can be used herein to mean that the part, element, or layer of material is arranged (e.g., placed, formed, deposited, etc.) "indirectly on" the implied surface, with one or more additional parts, elements, or layers positioned between the implied surface and the part, element, or layer of material. However, the word "over" in reference to a part, element, or layer of material formed or arranged "over" a surface can also optionally have the specific meaning that the part, element, or layer of material is arranged (e.g., placed, formed, deposited, etc.) "directly on" the implied surface, i.e., in direct contact with it. DETAILED DESCRIPTION

[0020] The examples of a semiconductor package and a method for manufacturing a semiconductor package can use various types of transistor devices. The examples can also use horizontal or vertical transistor devices, where these structures can be provided in a form in which all contact elements of the transistor device are located on one of the main faces of the semiconductor die (horizontal transistor structures), or in a form in which at least one electrical contact element is located on a first main face of the semiconductor die and at least one further electrical contact element is located on a second main face opposite the main face of the semiconductor die (vertical transistor structures), such as MOS transistor structures or IGBT structures (Insulated Gate Bipolar Transistor structures).Insofar as the transistor dies are designed as power transistor dies, the examples of a semiconductor package revealed below can be classified as so-called intelligent power modules (IPMs).

[0021] According to one embodiment of the semiconductor package, the semiconductor transistor is a power semiconductor transistor. The term "power semiconductor transistor" can refer to a semiconductor that has at least one of the properties of high voltage withstand capability or high current capability. A power semiconductor can be configured for high currents with a maximum current rating of a few amperes, such as 10 A, 250 A, 600 A, 1000 A, or a maximum current rating of up to or even above 1000 A. Similarly, voltages associated with such current ratings can range from a few volts to several tens, hundreds, or even thousands of volts.

[0022] Examples of semiconductor packages can include an encapsulation or encapsulation material in which the semiconductor transistor and the semiconductor driver are embedded. The encapsulation material can be any electrically insulating material, such as any type of molding material, resin material, or epoxy material. The encapsulation material can also be a polymer material, a polyimide material, a thermoplastic material, a silicone material, a ceramic material, or a glass material. Furthermore, the encapsulation material can include any of the aforementioned materials and contain embedded filler materials, such as thermally conductive additives like thermally conductive particles made of materials such as AlO, BNi, AlNi, SiN, diamond, or other thermally conductive particles.

[0023] Examples of semiconductor packages can further include a variety of passive devices, such as resistors, capacitors, inductors, and the like. An NTC (negative temperature coefficient) temperature sensor may also be included. These passive devices can, for example, be connected to the board in close proximity to the driver chip.

[0024] Fig. Figure 1 shows a perspective view of an example of a ladder frame.

[0025] The ladder frame 10 made of Fig. The first ladder frame 11 comprises a first ladder frame 11, which includes a frame 11.1 and several ladders 11.2 connected to the frame 11.1. The several ladders 11.2 include first ladders 11.2A and second ladders 11.2B. Some of the first ladders 11.2A have inner ends that are configured as first connecting elements 11.2AA and extend into the interior of the first ladder frame 11. The first ladder frame further comprises second connecting elements 11.3, which are connected to the frame 11.1 and also extend into the interior of the first ladder frame 11.

[0026] The in Fig. The example shown of the ladder frame 10 comprises a second ladder frame 12, wherein the first and second ladder frames 11 and 12 are connected to each other via their frames 11.1 and 12.1. In this way, several individual ladder frames can be connected to each other.

[0027] The conductor frame 10 can be made of copper or a copper alloy. For example, the conductor frame 10 includes a coating of Ni, Ni / NiP, Ni / NiNiP, or another suitable coating.

[0028] The interior of the first ladder frame 11 is dimensioned so that a first substrate and a second substrate can be accommodated in it and connected and held by the first and second connecting elements 11.2AA and 11.3.

[0029] The first connecting elements 11.2AA are arranged side by side and extend from there into the interior of the first ladder frame 11. The second connecting elements 11.3 are connected to the frame 11.1 at opposite points on the frame 11.1 and also extend from there into the interior of the first ladder frame 11. The second connecting elements 11.3 are formed integrally with the frame 11.1.

[0030] In an embodiment described below, the first substrate is a direct copper bond (DCB) connected to the first connector elements 11.2AA. The second substrate is a printed circuit board (PCB) connected to the second connector elements 11.3.

[0031] Fig. Figure 2 shows a perspective view of an example of a semiconductor package without encapsulation at a stage after removal of the conductor frame.

[0032] The semiconductor package 20 according to Fig. 2 includes conductor 21.2, in particular first conductor 21.2A and second conductor 21.2B, both of which, for example, consist of the first conductors 11.2A and the second conductors 11.2B of the first conductor frame 11 of the conductor frame 10 according to Fig. 1 result. First connecting elements 21.2AA result from the first connecting elements 11.2AA and second connecting elements 21.3 result from the second connecting elements 11.3, as in Fig. 1 shown.

[0033] The semiconductor package 20 further comprises a direct copper bond substrate (DCB substrate) 22, which is connected to the first connector elements 21.2AA, and a printed circuit board (PCB) 23, which is connected to the second connector elements 11.3. The semiconductor package 20 further comprises an encapsulation (omitted here) that covers the first and second substrates and inner sections of the conductors 21.2 (see Fig. 4).

[0034] The DCB 22 contains a central ceramic layer with copper layers on both surfaces. The upper copper layer is divided into individual copper layer sectors 22.1. On each of these copper layer sectors 22.1, a semiconductor transistor die and a semiconductor diode die connected in parallel with the semiconductor transistor die are deposited. The semiconductor transistor die can, for example, be an IGBT die, which has a drain contact on its back side and a source contact, a gate contact, and a source / sense contact on its front side. The semiconductor dies can be connected to the copper layer sectors 22.1 by a number of different methods, including soft solder and solder paste, preform soldering, sintering, or diffusion soldering.

[0035] As in Fig. As shown in Figure 2, the first conductors 21.2A and the second conductors 21.2B are bent at right angles. The first conductors 21.2A are connected to the copper layer segments 22.1 of the DCB 22, on which the semiconductor transistor dies are mounted, via their first connecting elements 21.2AA. The second connecting elements 21.3 are connected to copper layers 23.1 arranged on the printed circuit board 23 via second surface connections. The first and second surface connections can be produced by pre-soldering, which means that they take the form of a thin, planar solder layer applied between the respective connection partners before soldering by a reflow soldering process.

[0036] Fig. Figure 3 shows a perspective view of a section of an example of a printed circuit board (PCB).

[0037] The in Fig. The printed circuit board 23 shown in Figure 3 comprises a circuit containing a driver chip (not shown here). On each of the short sides of the printed circuit board 23, of which only one is shown here, the printed circuit board 23 comprises a copper layer 23.1. These copper layers 23.1 serve to connect to the second connector elements 11.3 of the frame 11.1 of the Fig. to be connected to the first conductor frame 11 shown in 1. These connections have no electrical function, but serve only to hold the printed circuit board 23 to the frame 11 during the manufacturing process.

[0038] The pre-soldering process results in a strong bond strength and, in the case of the connection between the first conductors 21.2A and the copper layer sections 22.1, in an increased current carrying capacity and improved thermal performance.

[0039] Both the connections between the first conductors 21.2A and the copper layer sectors 22.1, and the connections between the connector elements 21.3 and the copper layers 23.1, can be produced by laser welding instead of preform soldering. Other beam welding processes are also possible, such as electron beam welding. In such a case, material-layered connections without a binder layer between the respective joining partners are formed. These connections would also form strong bonds due to the direct Cu-Cu bond.

[0040] As in Fig. As can be seen in Figure 2, all first conductors 21.2A are connected to one of the copper layer sectors 22.1. Most of the first conductors 21.2A are also connected via first bond wires 25 to an upper contact terminal of one of the semiconductor diode dies. Second bond wires 26 are then connected between this contact terminal and the source contact terminal of the associated semiconductor transistor dies, so that both devices are electrically connected in parallel.

[0041] How Fig. As also shown in Figure 2, a circuit containing a semiconductor driver die 23.2 is arranged on the circuit board 23. The circuit is connected to third bond wires 27, which lead to the gate and source / sense contacts of the semiconductor transistor dies. Second conductors 21.2B are connected to the circuit board via further bond wires 28.

[0042] Fig. Figure 4 shows a perspective view of the semiconductor package made of Fig. 2 after applying an encapsulation.

[0043] The semiconductor package 20 according to Fig. 4 is basically the same as the one in connection with Fig. 2 shown and described. The semiconductor package 20 now additionally includes an encapsulation 24, which covers the DCB, the circuit board, and inner sections of the conductors 21.2. The outer sections of the first conductor 21.2A and the second conductor 21.2B, which are bent at right angles, are not covered by the encapsulation. Also within the circular outline is the outer, outwardly exposed end of one of the two first connecting elements 21.3. The other of the two first connecting elements 21.3 is also exposed on the opposite side of the semiconductor package 20.

[0044] Fig. Figure 5 shows a flowchart of a process for manufacturing a semiconductor package.

[0045] The in Fig. Method 100, as illustrated in section 5, comprises providing a conductor frame, comprising a frame, several conductors connected to the frame, including a first conductor and a second conductor, and one or more connecting elements connected to the frame; connecting a first substrate to the first conductors; connecting a second substrate to the connecting elements; attaching one or more semiconductor transistor dies to the first substrate; attaching a driver die to the second substrate; connecting the semiconductor transistor die to the conductors of the conductor frame and to the driver die by means of bond wires; applying an encapsulation to cover the first and second substrates and inner sections of the conductors of the conductor frame; and removing the frame of the conductor frame.

[0046] The outer sections of the conductor 21.2 can then be bent at right angles to obtain a semiconductor package 20, as shown in Fig. 4 shown.

[0047] According to one embodiment of the method, the first substrate comprises a direct copper bond (DCB) and the second substrate comprises a printed circuit board (PCB).

[0048] According to one embodiment of the method, the first conductors comprise integral inner end sections designed as second connecting elements, and the first substrate is connected to the second connecting elements.

[0049] According to one embodiment of the method, connecting the first substrate to the first conductors comprises applying a solder layer to one or both of the first substrate and the first conductors, bringing the first substrate and the first conductors into contact with each other, and performing a solder reflow process to attach the first substrate to the first conductors.

[0050] According to one embodiment of the method, connecting the second substrate to the connecting elements comprises applying a solder layer to one or both of the second substrate and the connecting elements, bringing the second substrate and the connecting elements into contact with each other, and performing a solder reflow process to attach the second substrate to the connecting elements.

[0051] According to one embodiment of the method, the method further comprises a single simultaneous soldering reflow process for connecting the first substrate to the first conductors and the second substrate to the connecting elements.

[0052] In other words, this makes it possible to connect the first conductors to the DCB and the connecting elements to the printed circuit board in a single process. The thin solder preforms are preferably applied to both the first and second substrates during the initial processing. After the substrates are inserted into the frame and the frame connectors are placed on the preform, all connections are processed in a single reflow step. This ensures that both substrates, especially the printed circuit board, are securely held in position during the subsequent forming process. Furthermore, the semiconductor dies could also be permanently soldered to the DCB during the same reflow process if they are mechanically, but not electrically, connected to the DCB during connection step 140.

[0053] According to another embodiment of the method, the method comprises laser welding of both the first conductors to the DCB and the connecting elements to the printed circuit board during a single pass of a welding tool, so that these connections are made during a single step in the manufacturing process.

[0054] It should be noted that the method can be combined with any of the structural features shown and described above in connection with the conductor frame or the semiconductor package.

[0055] Furthermore, although a particular feature or aspect of an embodiment of the disclosure may only be disclosed in relation to one of several implementations, this feature or aspect may be combined with one or more other features or aspects of the other implementations, as is desirable and advantageous for a particular application or applications. Moreover, the terms "comprise," "incorporate," "with," or other variants thereof, as used in the detailed description or the claims, are to be understood as inclusive, similar to the term "consist of." It should also be understood that embodiments of the disclosure may be implemented in discrete circuits, partially integrated circuits, fully integrated circuits, or programming means.Furthermore, the term "exemplary" is to be understood merely as an example and not as the best or optimal solution. It should also be noted that, for the sake of simplicity and clarity, the features and / or elements depicted herein are shown with specific dimensions relative to one another, and that the actual dimensions may differ considerably from those shown here.

[0056] Although specific embodiments have been presented and described herein, it will be clear to the person skilled in the art that a multitude of alternative and / or equivalent implementations can be used in place of the specific embodiments shown and described without departing from the scope of this disclosure. This application is intended to cover all adaptations or variations of the specific embodiments discussed herein. Therefore, this disclosure is intended to be limited only by the claims and their equivalents.

Claims

[1] Semiconductor package (20), comprising a plurality of conductors (21.2), comprising first conductor (21.2A) and second conductor (21.2B); a first substrate (22) that is directly connected to the first conductors (21.2A) via first surface connections; a second substrate (23) that is connected to the second conductors (21.2B) via several bond wires (28); an encapsulation (24) covering the first and second substrates (22, 23) and inner sections of the first conductor (21.2A) and the second conductor (21.2B); and one or more connector elements (11.3) covered by the encapsulation (24), each connector element (11.3) being directly connected to the second substrate (23) via a second surface connection identical to the first surface connections. [2] Semiconductor package (20) according to claim 1, wherein the first substrate (22) is one or more of a direct copper bonded substrate, a direct aluminum bonded substrate, an active metal braze substrate, an isolated metal substrate, a ceramic layer or a silicon layer. [3] Semiconductor package (20) according to claim 1 or 2, wherein the second substrate (23) is a printed circuit board. [4] Semiconductor package (20) according to one of the preceding claims, wherein the first and second surface connections comprise solder layers. [5] Semiconductor package (20) according to any one of the preceding claims, wherein the first and second surface connections comprise welded connections. [6] Semiconductor package (20) according to one of the preceding claims, further comprising one or more semiconductor transistor dies arranged on the first substrate (22). [7] Semiconductor package (20) according to claim 6, wherein the semiconductor transistor comprises one or more of a vertical semiconductor transistor, a power semiconductor transistor, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor, in particular a SiC transistor or a GaN transistor. [8] Semiconductor package (20) according to one of the preceding claims, further comprising a semiconductor driver die (23.2) arranged on the second substrate (23). [9] Semiconductor package (20) according to claims 6 to 8, wherein the semiconductor transistor dies are connected to the driver die (23.2) by bond wires. [10] Method (100) for manufacturing a semiconductor package, the method comprising providing a conductor frame comprising a frame, several conductors connected to the frame, comprising a first conductor and a second conductor, and one or more connecting elements (110) connected to the frame; Connecting a first substrate to the first conductors via first surface connections (120); Connecting a second substrate to the connecting elements via second surface connections that are identical to the first surface connections (130); Attaching one or more semiconductor transistor dies to the first substrate (140); Attaching a driver die to the second substrate (150); connecting the semiconductor transistor die to the driver die via bond wires (160); Connecting the second substrate to the second conductors using bond wires; Applying an encapsulation to cover the first and second substrates and inner sections of the conductors and connecting elements of the conductor frame (170); and Removing the frame of the ladder frame (180). [11] Method according to claim 10, wherein The joining of the first substrate to the first conductors includes the application of a solder layer to one or both of the first substrate and the first conductors; and Bringing the first substrate and the first conductor into contact with each other and performing a soldering reflow process. [12] Method according to claim 10 or 11, wherein The joining of the second substrate to the connecting elements includes the application of a solder layer to one or both of the second substrate and the connecting elements; and Bringing the second substrate and the connecting elements into contact with each other and performing a soldering reflow process. [13] Method according to claim 12, wherein the connection between the first substrate and the first conductors and the connection between the second substrate and the connecting elements are carried out by a single simultaneous soldering reflow process. [14] Method according to claim 10, wherein the joining of the first substrate to the first conductors and the joining of the second substrate to the connecting elements are carried out by laser welding. [15] Method according to claim 14, wherein the connection between the first substrate and the first conductors and the connection between the second substrate and the connecting elements are made by a single pass with a laser welding tool. [16] Semiconductor package (20) according to any one of claims 10 to 15, wherein the semiconductor transistor comprises one or more vertical semiconductor transistors, a semiconductor power transistor, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor power transistor, in particular a SiC transistor or a GaN transistor.

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