MEMORY DEVICES AND STACK MEMORY DEVICES THAT GENERATE A DATA STROBING SIGNAL FOR DATA OUTPUT

Abstract

A memory device includes a base chip configured to generate a first read flag, a second read flag, and a plurality of alignment data strobing signals in response to a clock signal and a control signal, and a memory chip configured to output data stored in a first pseudo-channel included in a memory core as pipe data in response to the first read flag and the alignment data strobing signals and output data stored in a second pseudo-channel included in the memory core as the pipe data in response to the second read flag and the alignment data strobing signals.

Description

BACKGROUND1. Technical FieldSome embodiments of the present disclosure relate to memory devices and stack memory devices that generate data strobe signals for data output.2. Related MatterRecently, stack storage systems such as high bandwidth memory (HBM) devices have been used in a variety of applications due to excellent bandwidth and energy efficiency. In contrast to the existing memory system using a parallel data bus, the stack system includes a stack device consisting of a base chip and a plurality of memory chips interconnected by through-silicon vias (TSVs, hereinafter referred to as "vias"). When the base chip receives data output from the memory chip and transmits the data to a controller during a read operation, the base chip generates a data strobe signal generated in response to a clock signal and transmits the data strobe signal to the memory chip, so that the data may be adjusted to be output from the memory chip in response to the data strobe signal.SUMMARYAccording to an embodiment of the present disclosure, a memory device may include a base chip configured to generate flags that are naturally signals. The word flag should therefore be configured as any type of electrically measurable signal that indicates the occurrence of an event.Generated flags include a first read flag, a second read flag, and a plurality of alignment data strobe signals, all of which may be generated in response to a clock signal and control signals. In other words, flags are "based on" or "responsive to" the occurrence of a clock signal and a control signal.A clock signal A memory chip may be configured to output data stored in a first "pseudo channel." "pipe data" stored in a pseudo channel is data obtained from a data pipe. A "data pipe" is a first-in / first-out (FIFO) buffer. "pipe data" is thus data obtained from a first-in / first-out (FIFO) buffer, commonly known as a "data pipe".In one embodiment, a "pseudo channel" may be physical memory, where individual data elements may be stored in a particular order or sequence and subsequently read from the same memory in the same order in which they were stored.In another embodiment, a "pseudo-channel" may be computer program instructions that, when executed, cause data to be stored in a particular order in physical memory and subsequently read from the same physical memory in the same order in which the data was stored. In other words, a pseudo channel may be implemented with either hardware or software.Pipe data based on the first read flag and the alignment data strobe signals and output data stored in a second pseudo channel included in the memory core as other pipe data based on the second read flag and the alignment data strobe signals.According to an embodiment of the present disclosure, a stack type memory device includes a plurality of memory chips stacked over a base chip. In the present disclosure, the base chip may include an operation control circuit configured to: generate a first read flag in synchronization with alignment data strobe signals when a read operation is performed on a first pseudo channel; and generate a second read flag in synchronization with the alignment data strobe signals when a read operation is performed on a second pseudo channel. In the present disclosure, each of the plurality of memory chips may include a memory core including the first pseudo channel and the second pseudo channel, and may be configured to output pipe data based on the alignment data strobe signals, the first read flag, and the second read flag when a read operation is performed on the first pseudo channel or the second pseudo channel.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a block diagram illustrating a configuration of a stack device according to an embodiment of the present disclosure. FIG. 2 is a block diagram according to an embodiment of an operation control circuit included in the stack memory device shown in FIG. 1. FIG. 3 is a block diagram according to an embodiment of an alignment control circuit included in the operation control circuit shown in FIG. 2. FIGS. 4 to 6 are timing charts illustrating operations of the alignment control circuit shown in FIG. 3. FIG. 7 is a block diagram illustrating a configuration of a stack system according to an embodiment of the present disclosure. FIG. 8 is a block diagram illustrating a configuration of a first memory chip included in the stack memory system shown in FIG. 7.DETAILED DESCRIPTIONIn the following description of embodiments, when a parameter is referred to as "predetermined", it may be meant that a value of the parameter is determined in advance when the parameter is used in a process or an algorithm. The value of the parameter may be set when the process or algorithm starts, or may be set during a period in which the process or algorithm is executed.It should be understood that, although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another element and are not intended to imply an order or number of elements. Thus, a first element could be referred to as a second element in other embodiments in some embodiments without departing from the teachings of the present disclosure.Further, it should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.A logic "high" level and a logic "low" level may be used to describe logic levels of electrical signals. A signal having a logic "high" level can be distinguished from a signal having a logic "low" level. For example, if a signal having a first voltage corresponds to a signal having a logic "high" level, a signal having a second voltage corresponds to a signal having a logic "low" level. In one embodiment, the logic "high" level may be set as a voltage level that is higher than a voltage level of the logic "low" level. In addition, logic levels of signals may be set differently or in opposite directions according to the embodiments. For example, a particular signal having a logic "high" level may be set to have a logic "low" level in one embodiment.The term "logic bit set" may mean a combination of logic levels of bits included in a signal. When the logic level of each of the bits included in the signal is changed, the logic bit set of the signal may be set differently. For example, when the signal includes two bits, when the logic level of each of the two bits included in the signal is "logic low level, logic low level", the logic bit set of the signal may be set as the first logic bit set, and when the logic level of each of the two bits included in the signal is "a logic low level and a logic high level", the logic bit set of the signal may be set as the second logic bit set.Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.FIG. 1 is a block diagram illustrating a configuration of a stack device 10 according to an embodiment of the present disclosure. As shown in FIG. 1, the stack-type memory device 10 may include a base chip 101 that is so called because the "base chip" may be a support or base for a memory chip 103 as shown in FIG. 7.The base chip 101 may include an operation control circuit (OP CTR) 111 and an output pipe (DOUT PIPE) 113. The operation control circuit 111 may receive a control signal CNT and a clock signal CLK from a memory controller (e.g., 233 in FIG. 7 ). The operation control circuit 111 may generate a first pseudo read command RCMD_P 1, a second pseudo read command RCMD_P 2, alignment data strobe signals ADQS, a first read flag RD_F 1, a second read flag RD_F 2, and an output control signal OUT based on the control signal CNT and the clock signal CLK. The operation control circuit 111 may generate the first pseudo read command RCMD_P 1 based on the control signal CNT when a read operation is performed on a first pseudo channel (e.g., PCH 1 in FIG. 8 ). The operation control circuit 111 may generate the second pseudo read command RCMD_P 2 based on the control signal CNT when a read operation is performed on a second pseudo channel (e.g., PCH 2 in FIG. 8 ).The operation control circuit 111 may generate alignment strobe signals ADQS (also referred to as alignment strobe signals), i.e., a plurality of alignment strobe signals in response to internal data strobe signals (e.g., IDQS in FIG. 3 ) that may be generated by dividing the clock signal signal CLK.The operation control circuit 111 may generate the first read flag RD_F 1 in synchronization with at least one data strobe signal ADQS when the read operation is performed on the first pseudo channel. The operation control circuit 111 may generate the second read flag RD_F 2 in synchronization with at least one data strobe signal ADQS when the read operation is performed on the second pseudo channel.The first pseudo channel and the second pseudo channel may be formed by dividing channels (e.g., 243_ 1, 243_ 2, 243_ 3, and 243_ 4 in FIG. 8 ). By providing a pseudo channel mode in which the internal operations for the first pseudo channel and the second pseudo channel are continuously performed, the channel bandwidth efficiency can be improved. The internal operations may include an active operation, a read operation, a write operation, and the like. The operation control circuit 111 may be electrically connected to a read control circuit 121 and a core pipe 127 of the memory chip 103 to apply the first pseudo read command RCMD_P 1 and the second pseudo read command RCMD_P 2 to the read control circuit 121, and apply the alignment data strobe signals ADQS, the first read flag RD_F 1, and the second read flag RD_F 2 to the core pipe 127. The operation control circuit 111 may generate the output control signal OUT for outputting pipe data PDATA stored in the output pipe 113 as output data DOUT when the read operation is performed on the first pseudo channel or the read operation is performed on the second pseudo channel. The output pipe 113 may be electrically connected to the operation control circuit 111 and the core pipe 127 of the memory chip 103 to receive the pipe data PDATA from the core pipe 127 and receive the output control signal OUT from the operation control circuit 111. The output pipe 113 may store the pipe data PDATA and output the stored pipe data PDATA as the output data DOUT based on the output control signal OUT.The memory chip 103 may include the read control circuit (RD CTR) 121, a memory core (MCORE) 123, and the core pipe (CORE PIPE) 127. The read control circuit 121 may control the read operation on the first pseudo channel and the read operation on the second pseudo channel to be continuously performed in the pseudo channel mode in response to the first pseudo read command RCMD_P 1 and the second pseudo read command RCMD_P 2. The storage core 123 may include the channels (e.g., 243_ 1, 243_ 2, 243_ 3, and 243_ 4 in FIG. 8 ), and each of the channels (e.g., 243_ 1, 243_ 2, 243_ 3, and 243_ 4 in FIG. 8 ) may be divided into the first pseudo channel and the second pseudo channel. The read operation on the first pseudo channel may be set as a read operation on the first pseudo channel included in a single channel or a read operation on the first pseudo channel included in each of the plurality of channels. The read operation on the second pseudo channel may be set as a read operation on the second pseudo channel included in a single channel or a read operation on the second pseudo channel included in each of the plurality of channels.The core pipe 127 may receive and store core data CDATA output from the first pseudo channel of the memory core 123 when the read operation is performed on the first pseudo channel, and receive and store the core data CDATA output from the second pseudo channel of the memory core 123 when the read operation is performed on the second pseudo channel. The core pipe 127 may output the core data CDATA stored when the read operation is performed on the first pseudo channel as the pipe data PDATA in response to the first read flag RD_F 1 in synchronization with the alignment data strobe signals ADQS. The core pipe 127 may output the core data CDATA stored when the read operation is performed on the second pseudo channel as the pipe data PDATA in response to the second read flag RD_F 2 in synchronization with the alignment data strobe signals ADQS.The base chip 101 may generate the first read flag RD_F 1, the second read flag RD_F 2, and the alignment data strobe signals ADQS to transmit the first read flag RD_F 1, the second read flag RD_F 2, and the alignment data strobe signals ADQS to the memory chip 103 through vias 220 when the read operation is performed on the first or second pseudo channel of the memory chip 103. When the read operations are performed for the first pseudo channel and the second pseudo channel, the alignment data strobe signals ADQS are shared and used in the data output operation of each of the first and second pseudo channels in response to the first read flag RD_F 1 and the second read flag RD_F 2, thereby reducing the number of vias 220 required when the alignment data strobe signals ADQS are transmitted from the base chip 101 to the memory chip 103. The memory chip 103 may be stacked over the base chip 101. Although the stack type memory device 10 is shown as including a memory chip 103, it shows only the memory chip 103 on which a read operation is performed for convenience of explanation, and it is preferable that a plurality of memory chips are stacked over a base chip 101.FIG. 2 is a block diagram of an operation control circuit 111A according to an embodiment of the operation control circuit 111 shown in FIG. 1. As shown in FIG. 2, the operation control circuit 111A may include a control signal decoder (CNT DEC) 131, an alignment control signal (ALG CTR) 133, and an output control signal generation circuit (OUTEN GEN) 135.The control signal decoder 131 may decode the control signal CNT in response to the clock signal CLK to generate a read command RD_CMD, the first pseudo read command RCMD_P 1, the second pseudo read command RCMD_P 2, and an identification signal SID. The control signal CNT may include a plurality of bits, and a logic bit set of the bits included in the control signal CNT may be set differently for each read command RD_CMD, the first pseudo read command RCMD_P 1, the second pseudo read command RCMD_P 2, and the identification signal SID. The read command RD_CMD may be generated for the read operation on the memory core 123, the first pseudo read command RCMD_P 1 may be generated for the read operation on the first pseudo channel included in the memory core 123, the second pseudo read command RCMD_P 2 may be generated for the read operation on the second pseudo channel included in the memory core 123, and the identification signal SID may be generated to identify one of ranks or one of the plurality of memory chips stacked over the base chip 101. In this embodiment, a logic bit set of bits included in the identification signal SID may be set to select the memory chip 103 or the rank on which the read operation is performed. The control signal decoder 131 may be electrically connected to the alignment control circuit 133 and the output control signal generation circuit 135 to apply the read command RD_CMD, the first pseudo read command RCMD_P 1, the second pseudo read command RCMD_P 2, and the identification signal SID to the alignment control circuit 133, and to apply the read command RD_CMD to the output control signal generation circuit 135.The alignment control circuit 133 may generate the first read flag RD_F 1, the second read flag RD_F 2, and the alignment data strobe signals ADQS in response to the clock signal CLK, the read command RD_CMD, the first pseudo read command RCMD_P 1, the second pseudo read command RCMD_P 2, and the identification signal SID. The alignment control circuit 133 may divide the clock signal CLK to generate the data strobe signals (e.g., IDQS in FIG. 3 ), may delay the data strobe signals to generate delayed data strobe signals (e.g., IDQSd in FIG. 3 ), and may output the delayed data strobe signals as the alignment data strobe signals ADQS. The alignment control circuit 133 may store the identification signal SID in response to the read command RD_CMD, and may generate a first pseudo identification signal (e.g., PSID 1 in FIG. 3 ) from the stored identification signal SID in response to the first pseudo read command RCMD_P 1 when the read operation is performed on the first pseudo channel. The alignment control circuit 133 may store the identification signal SID in response to the read command RD_CMD, and may generate a second pseudo identification signal (e.g., PSID 2 in FIG. 3 ) from the stored identification signal SID in response to the second pseudo read command RCMD_P 2 when a read operation is performed on the second pseudo channel. The alignment control circuit 133 may synthesize the first pseudo identification signal PSID 1 and the second pseudo identification signal PSID 2 to generate a synthetic identification signal (e.g., PSID_S in FIG. 3 ). The alignment control circuit 133 may latch and delay the first pseudo read command RCMD_P 1 to generate a first read command pulse (e.g., RD_CP 1 in FIG. 3 ) when the read operation is performed on the first pseudo channel. The alignment control circuit 133 may latch and delay the second pseudo read command RCMD_P 2 to generate a second read command pulse (e.g., RD_CP 2 in FIG. 3 ) when the read operation is performed on the second pseudo channel. The alignment control circuit 133 may align the synthetic identification signal PSID_S, the first read command pulse RD_CP 1, and the second read command pulse RD_CP 2 in synchronization with the alignment data strobe signals ADQS to generate an alignment identification signal ASID, the first read flag RD_F 1, and the second read flag RD_F 2.The output control signal generation circuit 135 may delay the read command RD_CMD to generate the output control signal OUT for outputting the pipe data PDATA stored in the output pipe 113 as the output data DOUT. Depending on the embodiments, the output control signal generation circuit 135 may be implemented to generate the output control signal OUT in response to the first pseudo read command RCMD_P 1 and the second pseudo read command RCMD_P 2.FIG. 3 is a block diagram of an alignment control circuit 133A according to an embodiment of the alignment control circuit 133 shown in FIG. 2. As shown in FIG. 3, the alignment control circuit 133A may include a first pseudo identification signal generation circuit 141, a second pseudo identification signal generation circuit 143, an internal data strobe signal generation circuit 144, a data strobe signal delay circuit 145, an identification signal synthesis circuit (SID SUM) 146, a pseudo command pulse generation circuit (RD_CP GEN) 148, and an alignment circuit (ALG CIR) 149.The first pseudo identification signal generation circuit 141 may include a first pipe input signal generation circuit (PIN1 GEN) 151, a first latch command pulse generation circuit (RD_LCP1 GEN) 153, a first pipe output signal generation circuit (POUT1 GEN) 155, a first identification signal pipe (SID PIPE1) 157, and a first latch command pulse delay circuit (LCP DLY1) 159.The first pipe input signal generation circuit 151 may generate a first pipe input signal PIN 1 in response to the read command RD_CMD. The first pipe input signal generation circuit 151 may generate the first pipe signal PIN 1 when the read command RD_CMD is generated. The first latch command pulse generation circuit 153 may generate a first latch command pulse RD_LCP 1 in response to the clock signal CLK and the first pseudo read command RCMD_P 1. The first latch command pulse generation circuit 153 may latch the first pseudo read command RCMD_P 1 in synchronization with the clock signal CLK and delay the latched first pseudo read command RCMD_P 1 by a first delay portion (e.g., td 1 in FIG. 4 ) to output the delayed pseudo read command RCMD_P 1 as the first latch command pulse RD_LCP 1. The first pipe output signal generation circuit 155 may generate a first pipe output signal POUT 1 in response to the first latch command pulse RD_LCP 1. The first identification signal pipe 157 may store the identification signal SID in response to the first pipe input signal PIN 1, and may output the stored identification signal SID as the first pseudo identification PSID 1 in response to the first pipe output signal POUT 1. The first latch command pulse delay circuit 159 may delay the first latch command pulse RD_LCP1 to generate a first inverted read command pulse RD_CP1B. The first pseudo identification signal generation circuit 141 may store the identification signal SID when the read command RD_CMD is generated, may output the stored identification signal SID as the first pseudo identification signal PSID 1 when the first delay portion elapses after the first pseudo read command RCMD_P 1 is generated, and may generate the first inverted read command pulse RD_CP 1B in synchronization with the time when the first pseudo identification signal PSID 1 is generated.The second pseudo identification signal generation circuit 143 may include a second pipe input signal generation circuit (PIN2 GEN) 161, a second latch command pulse generation circuit (RD_LCP2 GEN) 163, a second pipe output signal generation circuit (POUT2 GEN) 165, a second identification signal pipe (SID PIPE2) 167, and a second latch command pulse delay circuit (LCP DLY2) 169.The second pipe input signal generation circuit 161 may generate a second pipe input signal PIN 2 in response to the read command RD_CMD. The second pipe input signal generation circuit 161 may generate the second pipe signal PIN 2 when the read command RD_CMD is generated. The second latch command pulse generation circuit 163 may generate a second latch command pulse RD_LCP 2 in response to the clock signal CLK and the second pseudo read command RCMD_P 2. The second latch command pulse generation circuit 163 may latch the second pseudo read command RCMD_P 2 in synchronization with the clock signal CLK and delay the latched second pseudo read command RCMD_P 2 by a second delay portion (e.g., td 2 in FIG. 4 ) to output the delayed second pseudo read command RCMD_P 2 as the second latch command pulse RD_LCP 2. The second pipe output signal generation circuit 165 may generate a second pipe output signal POUT 2 in response to the second latch command pulse RD_LCP 2. The second identification signal pipe 167 may store the identification signal SID in response to the second pipe input signal PIN 2 and output the stored identification signal SID as the second pseudo identification PSID 2 in response to the second pipe output signal POUT 2. The second latch command pulse delay circuit 169 may delay the second latch command pulse RD_LCP 2 to generate a second inverted read command pulse RD_CP 2B. The second pseudo identification signal generation circuit 143 may store the identification signal SID when the read command RD_CMD is generated, may output the stored identification signal SID as the second pseudo identification signal PSID 2 when the second delay portion elapses after the second pseudo read command RCMD_P 2 is generated, and may generate the second inverted read command pulse RD_CP 2B in synchronization with the time when the second pseudo identification signal PSID 2 is generated.The internal data strobe signal generation circuit 144 (i.e., an internal data strobe signal generation circuit) may divide the clock signal CLK to generate the internal data strobe signals IDQS. The internal data strobe signal IDQS may be generated as a two-divided signal of the clock signal CLK, i.e., a signal whose period is twice as long as that of the clock signal CLK, but the present disclosure is not limited thereto. The internal data strobe signals IDQS may include a plurality of signals. As an example, the internal data strobe signals IDQS may include a first internal data strobe signal IDQS 1, a second internal data strobe signal IDQS 2, a third internal data strobe signal IDQS 3, and a fourth internal data strobe signal IDQS 4.The data strobe signal delay circuit 145 may delay the internal data strobe signals IDQS to generate the delayed data strobe signals IDQSd. The delayed data strobe signals IDQSd may include a first delayed data strobe signal IDQSd 1, a second delayed data strobe signal IDQSd 2, a third delayed data strobe signal IDQSd 3, and a fourth delayed data strobe signal IDQSd 4.The identification signal synthesis circuit 146 may be electrically connected to the first pseudo identification signal generation circuit 141 and the second pseudo identification signal generation circuit 143 to receive the first pseudo identification signal PSID 1 from the first pseudo identification signal generation circuit 141 and to receive the second pseudo identification signal PSID 2 from the second pseudo identification signal generation circuit 143. The identification signal synthesis circuit 146 may generate the synthetic identification signal PSID_S in response to the first pseudo identification signal PSID 1 and the second pseudo identification signal PSID 2. The identification signal synthesis circuit 146 may synthesize the first pseudo identification signal PSID 1 generated from the identification signal SID when the read operation is performed on the first pseudo channel and the second pseudo identification signal PSID 2 generated from the identification signal SID when the read operation is performed on the second pseudo channel to generate the synthetic identification signal PSID_S.The pseudo command pulse generation circuit 148 may be electrically connected to the first pseudo identification signal generation circuit 141 and the second pseudo identification signal generation circuit 143 to receive the first inverted read command pulse RD_CP 1B from the first pseudo identification signal generation circuit 141 and to receive the second inverted read command pulse RD_CP 2B from the second pseudo identification signal generation circuit 143. The pseudo command pulse generation circuit 148 may inversely latch the first inverted read command pulse RD_CP 1B to generate the first read command pulse RD_CP 1. The pseudo command pulse generation circuit 148 may inversely latch the second inverted read command pulse RD_CP 2B to generate the second read command pulse RD_CP 2.The alignment circuit 149 may be electrically connected to the data strobe signal delay circuit 145, the identification signal synthesis circuit 146, and the pseudo command pulse generation circuit 148 to receive the delayed data strobe signals IDQSd from the data strobe signal delay circuit 145, receive the synthetic identification signal PSID_S from the identification signal synthesis circuit 146, and receive the first read command pulse RD_CP1 and the second read command pulse RD_CP2 from the pseudo command pulse generation circuit 148. Alignment circuit 149 may generate alignment data strobe signals ADQS in response to delayed data strobe signals IDQSd. The alignment circuit 149 may buffer the delayed data strobe signals IDQSd to output a buffered signal of the delayed data strobe signals IDQSd as the alignment data strobe signals ADQS, but the present disclosure is not limited thereto. The alignment circuit 149 may align the synthetic identification signal PSID_S, the first read command pulse RD_CP 1, and the second read command pulse RD_CP 2 in synchronization with the alignment data strobe signals ADQS to generate the alignment identification signal ASID, the first read flag RD_F 1, and the second read flag RD_F 2. As an example, the alignment circuit 149 may align the synthetic identification signal PSID_S and the first read command pulse RD_CP1 in synchronization with the fourth alignment data strobe signal ADQS4 to generate the alignment identification signal ASID and the first read flag RD_F1, and may align the synthetic identification signal PSID_S and the second read command pulse RD_CP2 in synchronization with the second alignment data strobe signal ADQS2 to generate the alignment identification signal ASID and the second read flag RD_F2.FIGS. 4 to 6 are timing diagrams illustrating the operations of the alignment control circuit 133A shown in FIG. 3.The operation when a read operation is performed on the first pseudo channel will be described with reference to FIGS. 2 to 4 as follows.As shown in FIGS. 2 and 4, the control signal decoder 131 may decode the control signal CNT in response to the clock signal CLK to generate the read command RD_CMD, the first pseudo read command RCMD_P 1, and the identification signal SID. Specifically, the control signal decoder 131 may decode the control signal CNT <1:3> at time T 11 in synchronization with a rising edge of the clock signal CLK to generate the read command RD_CMD for a read operation, may decode the control signal CNT 4 to generate the first pseudo read command RCMD_P 1 for a read operation on the first pseudo channel, and may decode the control signal CNT <5:6> to generate the identification signal SID set to have a logic bit set "X".As shown in FIGS. 3 and 4, the first pipe input signal generation circuit 151 may generate the first pipe input signal PIN 1 when the read command RD_CMD is generated, and the first latch command pulse generation circuit 153 may latch the first pseudo read command RCMD_P 1 at time T 11 in synchronization with the clock signal CLK and delay the latched first pseudo read command RCMD_P 1 by a first delay portion td 1 to generate the first latch command pulse RD_LCP 1 at time T 12. The first pipe output generating circuit 155 may generate the first pipe output POUT 1 in response to the first latch command pulse RD_LCP 1. The first identification signal pipe 157 may store the identification signal SID in response to the first pipe input signal PIN 1 and output the stored identification signal SID as the first pseudo identification signal PSID 1 in response to the first pipe output signal POUT 1. A logic bit set of the first pseudo identification signal PSID 1 may be set to "Y 1" and the logic bit set "Y 1" may be set to be the same as the logic bit set "X", but the present disclosure is not limited thereto. The first latch command pulse delay circuit 159 may delay the first latch command pulse RD_LCP1 to generate the first inverted read command pulse RD_CP1B.The operation when a read operation is performed on the second pseudo channel will be described with reference to FIGS. 2, 3 and 5 as follows.As shown in FIGS. 2 and 5, the control signal decoder 131 may decode the control signal CNT in response to the clock signal CLK to generate the read command RD_CMD, the second pseudo read command RCMD_P 2, and the identification signal SID. Specifically, the control signal decoder 131 may decode the control signal CNT <1:3> at time T 21 in synchronization with a rising edge of the clock signal CLK to generate the read command RD_CMD for a read operation, may decode the control signal CNT<4> to generate the second pseudo read command RCMD_P 2 for a read operation on the second pseudo channel, and may decode the control signal CNT <5:6> to generate the identification signal SID set to have a logic bit set "X".As shown in FIGS. 3 and 5, the second pipe input signal generation circuit 161 may generate the second pipe input signal PIN 2 when the read command RD_CMD is generated, and the second latch command pulse generation circuit 163 may latch the second pseudo read command RCMD_P 2 at time T 21 in synchronization with the clock signal CLK and delay the latched second pseudo read command RCMD_P 2 by a second delay portion td 2 to generate the second latch command pulse RD_LCP 2 at time T 22. The second pipe output signal generation circuit 165 may generate the second pipe output signal POUT 2 in response to the second latch command pulse RD_LCP 2. The second identification signal pipe 167 may store the identification signal SID in response to the second pipe input signal PIN 2 and output the stored identification signal SID as the second pseudo identification signal PSID 2 in response to the second pipe output signal POUT 2. A logic bit set of the second pseudo identification signal PSID 2 may be set to "Y 2", and the logic bit set "Y 2" may be set to be the same as the logic bit set "X", but the present disclosure is not limited thereto. The second latch command pulse delay circuit 169 may delay the second latch command pulse RD_LCP 2 to generate the second inverted read command pulse RD_CP 2B.The operations when the read operation on the first pseudo channel and the read operation on the second pseudo channel are sequentially performed will be described with reference to FIGS. 3 and 6 as follows.As shown in FIGS. 3 and 6, when the first pseudo identification signal PSID 1 set to have a logic bit set "Y 1" is generated on the first pseudo channel at time T 31 and time T 35 according to the read operation and the second pseudo identification signal PSID 2 set to have a logic bit set "Y 2" is generated on the second pseudo channel at time T 33 according to the read operation, the alignment circuit 149 may align the synthetic identification signal PSID_S generated by synthesizing the first pseudo identification signal PSID 1 in synchronization with the fourth alignment data strobe signal ADQS 4 to generate the alignment identification signal ASID set to:, having the logic bit set "Y1" at time T32 and time T36, and may align the synthetic identification signal PSID_S generated by synthesizing the second pseudo identification signal PSID2 in synchronization with the second alignment data strobe signal ADQS2 to generate the alignment identification signal ASID set to have the logic bit set "Y2" at time T34. When the first inverted read command pulse RD_CP 1B is generated at time T 31 and time T 35 according to the read operation on the first pseudo channel and the second inverted read command pulse RD_CP 2B is generated at time T 33 according to the read operation on the second pseudo channel, the alignment circuit 149 may generate the first read flag RD_F 1 at time T 32 and time T 36 in synchronization with the fourth alignment data strobe signal ADQS 4 and may generate the second read flag RD_F 2 at time T 34 in synchronization with the second alignment data strobe signal ADQS 2.FIG. 7 is a block diagram illustrating a configuration of a stack system 20 according to an embodiment of the present disclosure. As shown in FIG. 7, the stack system 20 may include a stack device 201, a processor 203, an interposer 205, and a substrate 207.The interposer 205 may be disposed over the substrate 207, the stack memory device 201, and the processor 203 may be disposed over the interposer 205. The interposer 205 may be used to electrically connect the substrate 207, the stack device 201, and the processor 203. Since the differences in distance between the substrate 207, the stack device 201, and the processor 203 are large, the substrate 207, the stack device 201, and the processor 203 can be electrically connected using the interposer 205 including wires formed differently.The processor 203 may include a memory controller (MC) 221 and a processor interface circuit (PPHY) 223. The memory controller 221 may apply a control signal CNT including commands, addresses, and the like to the stack device 201 for controlling various internal operations of the stack device 201. The memory controller 221 may apply a clock signal CLK and a control signal CNT to the stack memory device 201 through the processor interface circuit 223.The stack memory device 201 may include a base chip 211 and memory chips 213, 215, 217, and 219. As shown in the figure, the memory chips 213, 215, 217 and 219 are vertically stacked one above the other. The "array" of these vertically stacked chips 213, 215, 217 and 219 is stacked on the base chip 211 as shown in the figure. A stack device 201 may thus be implemented with the stack chips 213, 215, 217 and 219 as shown in FIG. 7.As used herein, the term "sequentially stacked memory chips" and derivatives of that term should be construed to mean a set of memory chips that are vertically stacked one above the other such that each memory chip of the stack may be labeled with a number or identified by it. In other words, "sequential" NOT should be construed as requiring a particular ordered stacking of either identical, similar, or different memory chips on top of each other.The memory chip 213, 215, 217, and 219 may be sequentially stacked on the upper surface 211A of the base chip 211. Each stacked memory chip 213, 215, 217, and 219 may selectively and individually receive one or more signals output from conductive vias or simply "vias" 220 of the base chip 211. As FIG. 7 shows, the vias 220 (so-called vias) are aligned vertically relative to one another. In the embodiment shown in FIG. 7, each via extends completely through the memory chip in which it is formed.A complete or partial set of the memory chips, i.e., two or more of the memory chips 213, 215, 217 and 219, are vertically aligned. In other words, corresponding vertical surfaces of the memory chips lie in the same geometric vertical planes.In an alternative embodiment, a subset of the memory chips 213, 215, 217 and 219, i.e., fewer than four memory chips as shown in FIG. 7, may simultaneously or selectively receive one or more of the same signals output from the base chip 211.Referring back to FIG. 1, each memory chip 213, 215, 217, and 219 stacked on top of each other may receive, on the base chip 211, a first read flag signal RD_F 1, a second read flag signal RD_F 2, and an alignment data strobe signal ADQS from the base chip 211. Signals such as the first read flag signal RD_F 1, the second read flag signal RD_F 2, and the alignment data strobe signal ADQS may be sent to one or more memory chips 213, 215, 217, and 219 using electrically conductive vias 220 formed in and extending through each memory chip.When read operations are performed on the first pseudo channel and the second pseudo channel, the memory chips 213, 215, 217 and 219 may share and use the alignment data strobe signals ADQS to control the data output operation, i.e., a read operation, on each of a first pseudo channel and a second pseudo channel. Such a read operation occurs in response to the logic state of the first read flag signal RD_F 1 and the logic state of the second read flag signal RD_F 2. Accordingly, the number of conductive vias required to transmit the alignment data strobe signals ADQS from the base chip 101 to one or more of the memory chips may be reduced.The base chip 211 may include a core interface circuit (CPHY) 231 and an operation control circuit (OP CTR) 233. The core interface circuit 231 may be configured to enable and provide communication between it and the processor interface circuit 223. Such communication may include transmitting the clock signal signal CLK and the control signal CNT from the memory controller 221 to the operation control circuit 233 located in the base chip 211.The operation control circuit 233 may generate the first read flag RD_F 1 and the second read flag RD_F 2 generated in synchronization with the alignment data strobe signals ADQS in response to the clock signal CLK and the control signal CNT. The operation control circuit 233 may be implemented with the operation control circuit 111A shown in FIG. 2.FIG. 8 is a block diagram illustrating a configuration of a memory chip 213A according to an embodiment of the memory chip 213 shown in FIG. 7.As shown in FIG. 8, a memory chip 213A may include a first channel 243_ 1, a second channel 243_ 2, a third channel 243_ 3, a fourth channel 243_ 4, and a via formation region 241. In an embodiment, the first channel 243_ 1 and the second channel 243_ 2 may be arranged to be symmetrically opposed with respect to the via formation region 214. Similarly, the third channel 243_ 3 and the fourth channel 243_ 4 may be arranged symmetrically opposite with respect to the via formation region 214.Each channel, i.e., the first channel 243_ 1, the second channel 243_ 2, the third channel 243_ 3 and the fourth channel 243_ 4, may be arranged in the stack device 201 such that each channel includes a first pseudo channel PCH 1 and a second pseudo channel PCH 2.When a read operation is performed on the first channel 243_ 1, the second channel 243_ 2, the third channel 243_ 3, and the fourth channel 243_ 4, the read operation may be sequentially performed on the first pseudo channel PCH 1 and the second pseudo channel PCH 2. Sequentially performing a second read operation after a first operation improves channel data transfer rates, which increases the data transfer efficiency of the respective channels.A plurality of vias may be formed and arranged in the via formation region 241. In FIG. 7, such vias are identified by reference numeral 220. Alignment data strobe signals ADQS, a first read flag RD_F 1, and a second read flag RD_F 2 may be transmitted through corresponding ones of the three (3) conductive vias 220.The memory chip 213A may not receive the alignment data strobe signals ADQS for each read operation performed on the first pseudo channel PCH 1. The read operation on the second pseudo channel PCH 2 may share and use the alignment data strobe signals ADQS in response to the first read flag RD_F 1 and the second read flag RD_F 2, so that the number of vias may be reduced.Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure. Accordingly, the embodiments disclosed in the present specification should be considered not from a limiting aspect, but rather from an illustrative aspect. The true scope of the invention disclosed herein is therefore set forth in the appended claims.

Claims

A memory device, comprising: a base chip configured to generate a first read flag, a second read flag, and a plurality of alignment data strobe signals, each of which is generated in response to a clock signal and a control signal; and a memory chip configured to output data stored in a first pseudo channel in a memory core as pipe data, wherein data is output from the pseudo channel based on the first read flag and the alignment data strobe signals, wherein the memory chip is additionally configured to output data stored in a second pseudo channel in the memory core as the pipe data, wherein the pipe data is stored in the second pseudo channel based on the second read flag and the alignment data strobe signals.The memory device of claim 1, wherein the base chip is configured to receive the clock signal and the control signal from a memory controller configured to control internal operations of the first pseudo channel and control internal operations of the second pseudo channel.The memory device of claim 1, wherein the base chip is configured to: generate the first read flag when a read operation is performed on the first pseudo channel, and generate the second read flag when a read operation is performed on the second pseudo channel.The memory device of claim 1, wherein the base chip comprises an operation control circuit configured to generate the first read flag in synchronization with the alignment data strobe signals when a read operation is performed on the first pseudo channel.The memory device of claim 1, wherein the base chip comprises an operation control circuit configured to generate the second read flag in synchronization with the alignment data strobe signals when a read operation is performed on the second pseudo channel.The memory device according to claim 1, wherein the base chip comprises: an operation control circuit configured to generate an output control signal when a read operation is performed on the first pseudo channel or the second pseudo channel; and an output pipe configured to store the pipe data and output the stored pipe data as output data based on the output control signal.The memory device of claim 1, wherein the base chip comprises: a control signal decoder configured to decode the control signal based on the clock signal to generate a read command, a first pseudo read command, a second pseudo read command, and an identification signal; and an alignment control circuit configured to divide the clock signal to generate a data strobe signal, generate the alignment data strobe signals based on the data strobe signal, and generate the first read flag and the second read flag aligned with the alignment data strobe signals based on the read command, the first pseudo read command, and the second pseudo read command.The memory device of claim 7, wherein the alignment control circuit is configured to: store the identification signal in response to the read command and generate a first pseudo identification signal from the stored identification signal in response to the first pseudo read command, store the identification signal in response to the read command and generate a second pseudo identification signal from the stored identification signal in response to the first pseudo read command, and synthesize the first pseudo identification signal and the second pseudo identification signal to generate a synthetic identification signal.The memory device of claim 7, wherein the alignment control circuit is configured to: generate a first read command pulse in response to the first pseudo read command, generate a second read command in response to the second pseudo read command, and align the first read command pulse and the second read command pulse in synchronization with the alignment data strobe signals to generate both the first read flag and the second read flag.The memory device of claim 7, wherein the alignment control circuit comprises: a first pseudo identification signal generation circuit configured to: generate a first pseudo identification signal from the identification signal in response to the clock signal, the read command, and the first pseudo read command; and latch and delay the first pseudo read command in synchronization with the clock signal to generate a first inverted read command pulse; wherein the memory device additionally comprises: a second pseudo identification signal generation circuit configured to generate a second pseudo identification signal from the identification signal in response to the clock signal signal, the read command, and the second pseudo read command, and latch and delay the second pseudo read command in synchronization with the clock signal to generate a second inverted read command pulse; and an identification signal synthesis circuit configured to synthesize the first pseudo identification signal and the second pseudo identification signal to generate a synthetic identification signal.The memory device of claim 10, wherein the alignment control circuit further comprises a data strobe signal delay circuit configured to delay internal data strobe signals generated by dividing the clock signal to generate delayed data strobe signals.The memory device of claim 10, wherein the alignment control circuit further comprises an alignment circuit configured to generate alignment data strobe signals in response to delayed data strobe signals, and align the synthetic identification signal, the first read command pulse, and the second read command pulse in synchronization with the alignment data strobe signals to generate an alignment identification signal, the first read flag, and the second read flag.The memory device of claim 12, wherein the alignment data strobe signals comprise a first alignment data strobe signal, a second alignment data strobe signal, a third alignment data strobe signal, and a fourth alignment data strobe signal, and wherein the alignment control circuit is configured to: align the synthetic identification signal and the first read command pulse in synchronization with the fourth alignment data strobe signal to generate the alignment identification signal and the first read flag, and align the synthetic identification signal and the second read command pulse in synchronization with the second alignment data strobe signal to generate the alignment identification signal and the second read flag.A stack memory device comprising a plurality of memory chips stacked over a base chip, wherein the base chip comprises an operation control circuit configured to: generate a first read flag in synchronization with an alignment data strobe signal when a read operation is performed on a first pseudo channel, and generate a second read flag in synchronization with the alignment data strobe signal when a read operation is performed on a second pseudo channel, and wherein each of the plurality of memory chips comprises a memory core including the first pseudo channel and the second pseudo channel, and configured to output pipe data in response to the alignment data strobe signals, the first read flag, and the second read flag when a read operation is performed on the first pseudo channel or the second pseudo channel.The stack storage device of claim 14, wherein the base further comprises an output pipe configured to store the pipe data and output the stored pipe data as output data in response to an output control signal.The stack memory device of claim 14, wherein the operation control circuit comprises: a control signal decoder configured to decode a control signal in response to a clock signal to generate a read command, a first pseudo read command, a second pseudo read command, and an identification signal; and an alignment control circuit configured to divide the clock signal to generate a data strobe signal, generate the alignment data strobe signals in response to the data strobe signal, and generate the first read flag and the second read flag aligned with the alignment data strobe signals in response to the read command, the first pseudo read command, and the second pseudo read command.The stack memory device of claim 16, wherein the alignment control circuit is configured to: store the identification signal in response to the read command and generate a first pseudo identification signal from the stored identification signal in response to the first pseudo read command, store the identification signal in response to the read command and generate a second pseudo identification signal from the stored identification signal in response to the first pseudo read command, and synthesize the first pseudo identification signal and the second pseudo identification signal to generate a synthetic identification signal.The stack memory device of claim 16, wherein the alignment control circuit is configured to: generate a first read command pulse in response to the first pseudo read command; generate a second read command in response to the second pseudo read command; and align the first read command pulse and the second read command pulse in synchronization with the alignment data strobe signals to generate the first read flag and the second read flag.The stack memory device of claim 16, wherein the alignment control circuit comprises: a first pseudo identification signal generating circuit configured to generate a first pseudo identification signal from the identification signal in response to the clock signal, the read command, and the first pseudo read command, and latch and delay the first pseudo read command in synchronization with the clock signal to generate a first inverted read command pulse; a second pseudo identification signal generating circuit configured to generate a second pseudo identification signal from the identification signal in response to the clock signal, the read command, and the second pseudo read command, and latch and delay the second pseudo read command in synchronization with the clock signal to generate a second inverted read command pulse; and an identification signal synthesis circuit configured to synthesize the first pseudo identification signal and the second pseudo identification signal to generate a synthetic identification signal.The stack memory device of claim 19, wherein the alignment control circuit further comprises an alignment circuit configured to generate alignment data strobe signals in response to delayed data strobe signals, and align the synthetic identification signal, the first read command pulse, and the second read command pulse in synchronization with the alignment data strobe signals to generate an alignment identification signal, the first read flag, and the second read flag.

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