Semiconductor structure and manufacturing process thereof

Abstract

A semiconductor structure (10) comprises a storage element (100) with a floating gate (110), a dielectric tunnel layer (150), a control gate structure (200), an inter-gate oxide layer (130), an erase gate (120), and a word line (140). The control gate structure (200) is arranged on the floating gate (110). The control gate structure (200) includes a high dielectric layer (210, 410) and a metal gate (230), and the width of an upper section (200T) of the control gate structure (200) is greater than the width of a lower section (200B) of the control gate structure (200). The intermediate gate oxide layer (130) is located between the floating gate (110) and the control gate structure (200). The erase gate (120) is located on one side of the floating gate (110). The word line (140) is located on the other side of the floating gate (110).

Description

BACKGROUND Technical area

[0001] The disclosure relates to a semiconductor structure manufactured according to the manufacturing process of the invention, and a manufacturing process therefor, and in particular an embedded flash memory and a manufacturing process therefor. State of the art

[0002] In a conventional embedded flash (E-flash) manufacturing process, it is difficult to fabricate a control gate using a high-k metal gate (HKMG) process. Therefore, in the manufacturing process described above, a relatively large doped area is placed within a substrate to replace the function of the control gate. However, this results in the ultimately formed embedded flash memory exhibiting poor write efficiency.

[0003] US 2018 / 0151582A1 discloses a semiconductor device with a non-volatile memory. The non-volatile memory comprises a first dielectric layer arranged on a substrate, a floating gate and a control gate arranged on the dielectric layer, wherein a second dielectric layer is arranged between the floating gate and the control gate and consists of a silicon nitride layer, a silicon oxide layer, or a multiple layer thereof. A third dielectric layer is arranged between the second dielectric layer and the control gate and comprises a dielectric material with a dielectric constant higher than that of silicon nitride.

[0004] Furthermore, US 2017 / 0033000A1 describes a method for forming a gate cut-off area, which includes forming a tapered profile gate conductor trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask.

[0005] US 2017 / 0301683A1 discloses a semiconductor device with a split-gate flash memory cell structure, comprising a substrate with a first region and a second region, at least one first cell formed in the first region and at least one second cell formed in the second region.

[0006] US 7 517 746 B2 discloses a method for manufacturing a metal oxide semiconductor transistor with a metal gate.

[0007] US Patent 2005 / 0269644A1 describes a process for replacing a metal gate in which a stack of at least two polysilicon layers or other materials can be formed. Sidewall spacers can be formed on the stack. The stack can then be planarized. Next, the top layer of the stack can be selectively removed. Then, the exposed sections of the sidewall spacers can be selectively removed. Finally, the bottom section of the stack can be removed to form a T-shaped trench that can be filled with the metal replacement.

[0008] US Patent 2010 / 0044783A1 provides a method for forming a metal gate using a gate-load process. It also provides a semiconductor device that incorporates a gate structure with a greater width at the top of the gate than at the bottom.

[0009] US 2012 / 0049247A1 discloses a method for manufacturing a semiconductor device, wherein a modified profile opening is formed on a substrate. A metal-gate electrode is formed by filling the modified profile opening with a conductive material. Furthermore, a semiconductor device is also described, wherein the device has a metal-gate structure with a first width and a second, different width. SUMMARY

[0010] The disclosure provides a semiconductor structure, manufactured according to the manufacturing process of the disclosure, with relatively good writing efficiency.

[0011] Some embodiments of the disclosure provide a semiconductor structure, fabricated according to the manufacturing process of the disclosure, comprising a substrate and a storage element. The storage element is arranged on the substrate and includes a floating gate, a dielectric tunnel layer, a control gate structure, an intermediate gate oxide layer, an erase gate, and a word line. The floating gate is arranged on the substrate. The dielectric tunnel layer is arranged between the floating gate and the substrate. The control gate structure is arranged on the floating gate. The control gate structure includes a high-k dielectric layer and a metal gate, and the width of the upper part of the control gate structure is greater than the width of the lower part of the control gate structure. The intermediate gate oxide layer is arranged between the floating gate and the control gate structure. The erase gate is arranged on one side of the floating gate.The word line is located on the other side of the floating gate.

[0012] The disclosure provides a manufacturing process for a semiconductor structure, and the manufactured semiconductor structure exhibits relatively good writing efficiency.

[0013] Other embodiments of the disclosure provide a fabrication method for a semiconductor structure comprising the following steps. A memory material layer is formed on a substrate. The memory material layer contains, sequentially, a floating gate, an erase gate, a first nitride layer, a first oxide layer, a second nitride layer, and a second oxide layer. A first recess is formed in the memory material layer. The first recess exposes a portion of the first nitride layer. A second recess is formed in the memory material layer. The second recess overlaps the first recess to form an opening, and the second recess exposes a portion of the floating gate. An inter-gate oxide layer is formed in the opening.The opening contains a dummy gate structure with a dielectric layer having a high dielectric constant and a dummy gate (230). A control gate structure (200) is formed with a metal gate (230) to create a storage element (100) by replacing the dummy gate (230a) in the dummy gate structure (200a) with a metal gate (230). The width of an upper section of the control gate structure is greater than the width of a lower section of the control gate structure.

[0014] Based on the above, the disclosure provides a novel semiconductor structure, manufactured according to the manufacturing process of the disclosure, and a corresponding manufacturing process. By forming the control-gate structure with the dielectric layer having a high dielectric constant and the metal gate in the memory element, the write efficiency of the memory element in the disclosure can be increased compared to conventional embedded flash memory. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figures 1A to 1F are schematic views of a process flow for a manufacturing process for a semiconductor structure according to an embodiment of the disclosure. Fig. Figure 2A is a schematic partial cross-sectional view of a semiconductor structure, manufactured according to the manufacturing process of the disclosure, according to an embodiment of the disclosure. Fig. Figure 2B is a schematic partial cross-sectional view of a control gate structure according to an embodiment of the disclosure. DETAILED DESCRIPTION OF THE DISCLOSED FORM OF EXECUTION

[0015] The following examples, with reference to the accompanying drawings, are given to describe the revelation in detail, but these examples are not intended to limit the scope of the revelation. Furthermore, the drawings in the revelation are drawn for illustrative purposes only, and certain elements in the drawings are not drawn to scale. To aid the reader's understanding, identical elements in the following description are identified by the same reference symbols.

[0016] Fig. Figures 1A to 1F are schematic views of a process flow of a manufacturing process for a semiconductor structure according to the first embodiment of the disclosure.

[0017] With reference to the Fig. 1A to 1F, in this embodiment the following steps can be carried out to form a semiconductor structure 10, but the disclosure is not limited thereto.

[0018] Step (1) is performed. A storage material layer is formed on a substrate SB.

[0019] With reference to Fig. 1A In some embodiments, the substrate SB may be a semiconductor substrate, but the disclosure is not limited thereto. A material of the substrate SB may, for example, be an elementary semiconductor, a compound semiconductor, an alloy semiconductor, or other suitable materials. The material of the substrate SB may, for example, comprise silicon, germanium, indium antimonide, indium arsenide, indium phosphide, gallium nitride, gallium arsenide, gallium antimonide, lead telluride, or a combination thereof. In other embodiments, the substrate SB may be a silicon-on-insulator (SOI) substrate.

[0020] In this embodiment, the substrate SB comprises a storage element region A1, a high-voltage element region A2, and a logic element region A3. The storage material layer is formed in the storage element region A1 of the substrate SB. It is worth noting that, prior to the formation of the storage material layer on the substrate SB, a dielectric layer IL1, a local silicon oxidation (LOCOS) layer LO, and a shallow trench insulation structure STI can be formed on the substrate SB. In this embodiment, the dielectric layer IL1 located in the region of the storage element A1 can be formed into a tunnel dielectric layer after subsequent processes, and the dielectric layer IL1 located in the region of the high-voltage element A2 can be formed into a gate dielectric layer after subsequent processes, which are described in detail in the following embodiments.The local oxidation of silicon LO is, for example, located in the area of ​​the storage element A1 and adjacent to the dielectric layer IL1. In some embodiments, the local oxidation of silicon LO can be formed by a thermal oxidation process, but the disclosure is not limited to this. The flat trench insulation structure STI comprises, for example, a flat trench insulation structure STI1, a flat trench insulation structure STI2, and a flat trench insulation structure STI3. The flat trench insulation structure STI1 is used, for example, to separate the storage element area A1 and the high-voltage element area A2. The flat trench insulation structure STI2 is used, for example, to separate the high-voltage element area A2 and the logic element area A3.The shallow trench isolation structure STI3 is used, for example, to separate the logic element area A3 from another element area (not shown). In some embodiments, the shallow trench isolation structure STI can be formed by first performing an etching process to create multiple grooves in the substrate SB, and then performing a chemical vapor deposition process to form an insulating material in the grooves. However, the disclosure is not limited to this.

[0021] The storage material layer includes, for example, a floating gate 110, an erasure gate 120, a first oxide layer OL1, a first nitride layer NL1, a second oxide layer OL2, a second nitride layer NL2, and a third oxide layer OL3. However, the disclosure is not limited to this.

[0022] The floating gate 110 is, for example, arranged on the dielectric layer IL1. In some embodiments, the material of the floating gate 110 contains polysilicon. However, the disclosure is not limited to this.

[0023] The quenching gate 120 is, for example, arranged on one side of the floating gate 110. In some embodiments, the material of the quenching gate 120 contains polysilicon. However, the disclosure is not limited to this.

[0024] It is worth noting that the storage material layer may, for example, contain a conductive material layer CL located in the region of the storage element A1 and in the region of the high-voltage element A2. The conductive material layer CL is, for example, arranged on the dielectric layer IL1. The conductive material layer CL located in the region of the storage element A1 can be formed into a word-line material layer after subsequent processes, and the conductive material layer CL located in the region of the high-voltage element A2 can be formed into a gate material layer after subsequent processes. In some embodiments, the material of the conductive material layer CL comprises polysilicon, but the disclosure is not limited thereto. In other embodiments, the conductive material layer CL, the floating gate 110, and the erase gate 120 may belong to the same layer.

[0025] The first oxide layer OL1 is, for example, arranged on the floating gate 110. In this embodiment, the first oxide layer OL1 covers the floating gate 110. In some embodiments, the material of the first oxide layer OL1 contains silicon oxide, but the disclosure is not limited thereto.

[0026] The first nitride layer NL1 is arranged, for example, on the first oxide layer OL1. In some embodiments, the material of the first nitride layer NL1 contains silicon nitride, but the disclosure is not limited to this. It is worth noting that the first nitride layer NL1 is also arranged in the area of ​​the logic element A3 and covers the dielectric layer IL1, but the disclosure is not limited to this.

[0027] The second oxide layer OL2 is, for example, arranged on the first nitride layer NL1. In this embodiment, the second oxide layer OL2 covers the first nitride layer NL1 and the quenching gate 120. In some embodiments, the material of the second oxide layer OL2 contains silicon oxide, but the disclosure is not limited to this. It is worth noting that the second oxide layer OL2 is also arranged in the area of ​​the high-voltage element A2 and in the area of ​​the logic element A3, but the disclosure is not limited to this.

[0028] The second nitride layer NL2 is, for example, arranged on the second oxide layer OL2. In some embodiments, the material of the second nitride layer NL2 contains silicon nitride, but the disclosure is not limited to this. It is worth noting that the second nitride layer NL2 is also arranged in the area of ​​the high-voltage element A2 and in the area of ​​the logic element A3, but the disclosure is not limited to this.

[0029] The third oxide layer OL3 is, for example, arranged on the second nitride layer NL2. In some embodiments, the material of the third oxide layer OL3 contains silicon oxide, but the disclosure is not limited to this. It is worth noting that the third oxide layer OL3 is also arranged in the area of ​​the high-voltage element A2 and in the area of ​​the logic element A3, but the disclosure is not limited to this.

[0030] Step (2) is carried out. A first recess R1 is formed in the storage material layer.

[0031] As in Fig. As shown in Figure 1B, in some embodiments the etching process can be carried out to form the first recess R1 in the storage material layer. In this embodiment, the first recess R1 exposes a section of the first nitride layer NL1. Specifically, the above etching process can be carried out to successively remove a section of the third oxide layer OL3, the second nitride layer NL2, and the second oxide layer OL2. The material of the second oxide layer OL2 and the material of the first nitride layer NL1 have different etch selectivities, so the first nitride layer NL1 can be used as an etch stop layer in this etching process.

[0032] It is worth mentioning that in the step of forming the first recess R1, the third oxide layer OL3, the second nitride layer NL2 and the second oxide layer OL2, which are located in the area of ​​the logic element A3, can also be removed simultaneously, but the disclosure is not limited to this.

[0033] Step (3) is performed. A second recess R2 is formed in the storage material layer.

[0034] As in Fig. As shown in Figure 1B, in some embodiments the etching process can be performed to form the second recess R2 in the storage material layer. In this embodiment, the second recess R2 and the first recess R1 overlap in a normal direction Z of the substrate SB to form an opening OP. Specifically, the second recess R2 is formed by performing the etching process on the first nitride layer NL1, which is exposed by the first recess R1. In this embodiment, the width of the second recess R2 in a direction X is less than the width of the first recess R1 in direction X. In this embodiment, the second recess R2 exposes a section of the first oxide layer OL1. Specifically, the above etching process can be performed to remove the first nitride layer NL1.The material of the first nitride layer NL1 and the material of the first oxide layer OL1 have different etch selectivities, so that the first oxide layer OL1 can be used as an etch stop layer in this etching process.

[0035] Step (4) is performed. An intermediate gate oxide layer 130 is formed in the OP opening.

[0036] As in Fig. As shown in Figure 1C, the inter-gate oxide layer 130 can, in some embodiments, be formed on the floating gate 110 by a suitable deposition process, but the disclosure is not limited thereto. The inter-gate oxide layer 130 can, for example, have a composite structure. In this embodiment, the inter-gate oxide layer 130 comprises three dielectric layers stacked sequentially. The inter-gate oxide layer 130 can, for example, comprise an oxide-nitride-oxide (ONO) composite layer, but the disclosure is not limited thereto. In other embodiments, the inter-gate oxide layer 130 can have a single-layer structure, and one of the materials contained therein can be silicon oxide.

[0037] Step (5) is performed. A dummy gate structure 200a is formed in the OP opening.

[0038] In some embodiments, a method for forming the dummy gate structure 200a in the opening OP includes the following steps, although the disclosure is not limited thereto (see Fig. 1C).

[0039] First, a high dielectric layer 210 is formed on a side wall of the opening OP. In some embodiments, the high dielectric layer 210 can be formed by a suitable deposition process, but the disclosure is not limited thereto. A material of the high dielectric layer 210 can, for example, include hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), or other suitable materials with high dielectric constants. In this embodiment, the material of the high dielectric layer 210 is hafnium oxide, but the disclosure is not limited thereto.It is worth noting that in this embodiment, during the formation of the high dielectric layer 210, a high dielectric layer 410 is also formed in the logic element region A3, but the disclosure is not limited to this. Furthermore, prior to the formation of the high dielectric layer 410, a buffer layer (not shown) can first be formed in the logic element region A3 to buffer the high dielectric layer 410 and the substrate SB.

[0040] Next, a lower barrier layer 220 is formed on the high-dielectric-constant dielectric layer 210. In some embodiments, the lower barrier layer 220 can be formed by a suitable deposition method, but the disclosure is not limited thereto. A material of the lower barrier layer 220 can be, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. In this embodiment, the lower barrier layer 220 is a multilayer structure. Specifically, the lower barrier layer 220 can comprise a first lower barrier layer 222 and a second lower barrier layer 224. A material of the first lower barrier layer 222 is titanium nitride, and a material of the second lower barrier layer 224 is tantalum nitride. However, the disclosure is not limited thereto.It is worth noting that in this embodiment, during the step of forming the lower barrier layer 220, a lower barrier layer 420, which contains a first lower barrier layer 422 and a second lower barrier layer 424, is also formed simultaneously in the logic element area A3. However, the disclosure is not limited to this.

[0041] A dummy gate 230a is then formed on the lower barrier layer 220. In some embodiments, the dummy gate 230a can be formed by a suitable deposition method, but the disclosure is not limited to this. For example, the dummy gate 230a can be made of polysilicon. It is worth noting that in this embodiment, a dummy gate 430a is simultaneously formed in the logic element area A3 during the formation of the dummy gate 230a, but the disclosure is not limited to this.

[0042] In some embodiments, a section of the dummy gate 230a can also be removed to form a recess. The bottom of the recess is essentially in the same plane as the bottom of the second nitride layer NL2. Subsequently, a first sacrificial layer SA1 and a second sacrificial layer SA2 are formed successively in the recess. One material of the first sacrificial layer SA1 is silicon nitride, and one material of the second sacrificial layer SA2 is silicon oxide. It is worth noting that in this embodiment, the first sacrificial layer SA1 and the second sacrificial layer SA2 are also formed simultaneously in the region of the logic element A3, but the disclosure is not limited to this.

[0043] The fabrication of the dummy gate structure 200a has been completed. Although a fabrication method for the dummy gate structure 200a in this embodiment is described using the method above, the fabrication method for the dummy gate structure in the disclosure is not limited to this.

[0044] Step (6) is performed. A section of dummy gate structure 200a is removed to form dummy gate structure 200b.

[0045] Referring to Fig. In some embodiments, the etching process can be carried out to remove a section of the high dielectric constant dielectric layer 210, a section of the lower barrier layer 220, and the section of the dummy gate 230a to form the dummy gate structure 200b. It is worth noting that the first sacrificial layer SA1 and the second sacrificial layer SA2 are also removed in the etching process. Furthermore, in this embodiment, the remaining second nitride layer NL2 and the third oxide layer OL3 are also removed in the etching process, and a section of the second oxide layer OL2 is exposed.

[0046] It is worth noting that further steps are planned after the formation of the dummy gate structure in 200b.

[0047] First, a structuring process is performed on the second oxide layer OL2, the conductive material layer CL, and the dielectric layer IL1 to form a word line 140 and a dielectric tunnel layer 150 in the storage element area A1. The word line 140 is a section of the conductive material layer CL, and the dielectric tunnel layer 150 is part of the dielectric layer IL1. It is worth noting that a high-voltage element 300 is also formed in the high-voltage element area A2 during the above structuring process. Specifically, the high-voltage element 300 includes, for example, a gate 302, a gate oxide layer 304, and a spacer 306. The gate 302 is a section of the conductive material layer CL. The gate oxide layer 304 is a section of the dielectric layer IL1. The spacer 306 is a section of the dielectric layer IL2.Furthermore, the second oxide layer OL2 can be formed into a dielectric layer 310 after the structuring process described above.

[0048] Next, a side wall 440 can be formed in the area of ​​logic element A3 by carrying out a suitable deposition process. The side wall 440 is located on both sides of the high dielectric constant dielectric layer 410, the lower barrier layer 420, and the dummy gate 430a.

[0049] Subsequently, the conformal dielectric layer IL2 is formed in the area of ​​the storage element A1, in the area of ​​the high-voltage element A2, and in the area of ​​the logic element A3 by a suitable deposition process. In some embodiments, the material of the dielectric layer IL2 contains silicon nitride, but the disclosure is not limited thereto. The dielectric layer IL2 can, for example, serve as a spacer for subsequent elements, which are described in detail in the following embodiments.

[0050] Then, a dielectric layer IL3 is formed by performing a suitable deposition or spin-coating process. In this embodiment, the dielectric layer IL3 exposes a portion of the dielectric layer IL2 located in the region of the storage element A1, the high-voltage element A2, or the logic element A3, and has an upper surface that is substantially flush with the dielectric layer IL2. In some embodiments, the material of the dielectric layer IL3 contains silicon oxide, but the disclosure is not limited thereto.

[0051] Step (7) is executed. The dummy gate structure 200b is replaced by a control gate structure 200 to form a memory element 100.

[0052] With reference to Fig. 1E contains a method for replacing the dummy gate structure 200b with the control gate structure 200 in some embodiments the following steps, but the disclosure is not limited thereto.

[0053] First, a planarization process is performed to remove a section of the dielectric layer IL3 and a section of the dielectric layer IL2, exposing the dummy gate 230a.

[0054] Subsequently, a replacement metal gate (RMG) process is performed to replace the dummy gate 230a with a metal gate 230. In this embodiment, the metal gate 230 successively comprises a metal layer for adjusting the work function 232, an upper barrier layer 234, and a low-resistance material layer 236, but the disclosure is not limited thereto. For example, the material of the metal layer for adjusting the work function 232 comprises a binary composite metal. For example, the material of the metal layer for adjusting the work function 232 may comprise titanium-aluminum (TiAl), zirconium-aluminum (ZrAl), tungsten-aluminum (WAl), tantalum-aluminum (TaAl), hafnium-aluminum (HfAl), or another suitable composite metal. In this embodiment, the material of the metal layer for adjusting the work function 232 is titanium-aluminum, but the disclosure is not limited thereto. The material of the upper barrier layer 234 can be, for example,The material of the upper barrier layer 234 may be titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. In this embodiment, the material of the upper barrier layer 234 is a combination of titanium and titanium nitride, but the disclosure is not limited thereto. A material of the low-resistance material layer 236 may, for example, be aluminum (Al), tungsten (W), copper (Cu), or a combination thereof. In this embodiment, the material of the low-resistance material layer 236 is aluminum, but the disclosure is not limited thereto.

[0055] The manufacturing process for replacing the dummy gate structure 200b with the control gate structure 200 has been completed. Although a manufacturing process for replacing the dummy gate structure 200b with the control gate structure 200 in this embodiment is described using the method above, the manufacturing process for replacing the dummy gate structure with the control gate structure in the disclosure is not limited to this.

[0056] It is worth noting that the dummy gate 430a, located in the area of ​​logic element A3, is also replaced by a metal gate 430, while the metal gate exchange procedure described above is carried out to form a logic element 400. Specifically, the metal gate 430 may, for example, comprise a metal layer for adjusting the work function 432, an upper barrier layer 434, and a layer of a low-resistance material 436, but the disclosure is not limited thereto.

[0057] Step (8) is performed. An intermediate connection structure 500 is formed on the substrate SB. The intermediate connection structure 500 is electrically connected to the storage element 100, the high-voltage element 300, and the logic element 400.

[0058] As in Fig. As shown in Figure 1F, the interconnect structure 500 in this embodiment contains a dielectric layer IL4 and several conductive vias V.

[0059] In some embodiments, the dielectric layer IL4 can be formed by chemical vapor deposition, spin coating, or other suitable methods, the disclosure of which is not limited thereto. A material of the dielectric layer IL4 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, polyimide, or another suitable material, the disclosure of which is not limited thereto.

[0060] The conductive vias V are arranged, for example, in and penetrate the dielectric layer IL4. In some embodiments, the conductive vias V can be formed by a physical vapor deposition process, a chemical vapor deposition process, an electroplating process, or other suitable processes, but the disclosure is not limited thereto. In this embodiment, the conductive vias V comprise a conductive via V1, a conductive via V2, and a conductive via V3. One conductive via V1 is, for example, electrically connected to the control gate structure 200 of the storage element 100. The conductive via V2 penetrates, for example, the dielectric layer 310 and is, for example, electrically connected to the gate 302 of the high-voltage element 300.The conductive via V3 is, for example, electrically connected to the metal gate 430 of the logic element 400. Materials of the conductive via V can be, for example, suitable conductive materials. The materials of the conductive vias V can be, for example, copper, titanium, tungsten, tantalum, titanium nitride, tantalum nitride, polysilicon, or a combination thereof, but the disclosure is not limited thereto.

[0061] A manufacturing process for the semiconductor structure 10 in this embodiment has been completed, but the manufacturing process for the semiconductor structure 10 described in the disclosure is not limited to this. In this embodiment, the semiconductor structure 10 includes the memory element 100, which is an embedded flash memory (E-Flash). By forming the control gate structure 200, the write efficiency of the memory element 100 can be relatively increased.

[0062] Fig. Figure 2A is a schematic partial cross-sectional view of a semiconductor structure, manufactured according to the manufacturing process of the disclosure, according to an embodiment of the disclosure. Fig. Figure 2B is a schematic partial cross-sectional view of a control gate structure according to an embodiment of the disclosure. A structure of the semiconductor structure 10 in this embodiment is briefly described below with reference to the Fig. 1F, Fig. 2A and Fig. 2B was briefly introduced, but the revelation is not limited to it.

[0063] With reference to Fig. 1F and Fig. In this embodiment, the semiconductor structure 10 in 2A includes the substrate SB and the storage element 100.

[0064] The substrate SB is, for example, a silicon substrate, but the disclosure is not limited to this. In this embodiment, the substrate SB contains the storage element area A1, the high-voltage element area A2, and the logic element area A3, with the high-voltage element area A2 located between the storage element area A1 and the logic element area A3 in the X direction. However, the disclosure is not limited to this. For the remainder of the introduction concerning the substrate SB, reference may be made to the embodiment described above, which will not be repeated here.

[0065] The storage element 100 is, for example, arranged on the substrate SB and is located in the storage element area A1 of the substrate SB. The storage element 100 is, for example, the embedded flash memory (E-Flash). In this embodiment, the storage element 100 comprises the floating gate 110, the dielectric tunnel layer 150, the control gate structure 200, the inter-gate oxide layer 130, the erase gate 120, and the word line 140.

[0066] The floating gate 110 is, for example, arranged on the substrate SB. The floating gate 110 can be used, for example, to store hot electrons and can also have a data storage function. For the remainder of the introduction to the floating gate 110, reference can be made to the embodiment described above, which will not be repeated here.

[0067] The dielectric tunneling layer 150 is arranged, for example, on the substrate SB and is located, for example, between the floating gate 110 and the substrate SB. The dielectric tunneling layer 150 can, for example, serve to tunnel the hot electrons when a corresponding voltage is applied to the storage element 100. For the remainder of the introduction concerning the dielectric tunneling layer 150, reference can be made to the embodiment described above, which will not be repeated here.

[0068] The control gate structure 200 is, for example, arranged on the floating gate 110. The hot electrons can be tunneled to the floating gate 110 by, for example, applying a voltage to the control gate structure 200. Referring to the Fig. 2A and Fig. In this embodiment, the width WT of an upper section 200T of the control gate structure 200 in the X direction is greater than the width WB of a lower section 200B of the control gate structure 200 in the X direction. Since the control gate structure 200 is arranged in the opening OP formed by the first recess R1 and the second recess R2, the control gate structure 200 can have the upper section 200T and the lower section 200B with different widths.

[0069] As in the two Fig. 2A and Fig. As shown in Figure 2B, the control gate structure 200 in this embodiment includes the high dielectric constant dielectric layer 210, the lower barrier layer 220, the metal layer for adjusting the work function 232, the upper barrier layer 234 and the low resistance material layer 236.

[0070] The high dielectric layer 210 is, for example, conformally arranged on the side wall of the opening OP and has, for example, a collar shape. In this embodiment, the material of the high dielectric layer 210 is hafnium oxide, but the disclosure is not limited thereto. For the remainder of the introduction concerning the high dielectric layer 210, reference can be made to the embodiment described above, which is not repeated here.

[0071] The lower barrier layer 220 is, for example, conformally arranged on the high-dielectric-constant dielectric layer 210 and has, for example, a collar shape. In this embodiment, the lower barrier layer 220 comprises the first lower barrier layer 222 and the second lower barrier layer 224. The material of the first lower barrier layer 222 is titanium nitride, and the material of the second lower barrier layer 224 is tantalum nitride. However, the disclosure is not limited thereto. For the remainder of the introduction concerning the lower barrier layer 220, reference may be made to the above embodiment, which will not be repeated here.

[0072] The metal layer for adjusting the work function 232 is, for example, arranged on the lower barrier layer 220 and has, for example, a U-shaped form. In this embodiment, the material of the metal layer for adjusting the work function 232 is titanium-aluminum, but the disclosure is not limited thereto. For the remainder of the introduction concerning the metal layer for adjusting the work function 232, reference can be made to the embodiment above, which will not be repeated here.

[0073] The upper barrier layer 234 is, for example, arranged on the metal layer for adjusting the work function 232 and has, for example, a U-shaped form. In this embodiment, the material of the upper barrier layer 234 is a combination of titanium and titanium nitride, but the disclosure is not limited thereto. For the remainder of the introduction concerning the upper barrier layer 234, reference can be made to the embodiment described above, which will not be repeated here.

[0074] The low-resistance material layer 236 is, for example, arranged on the upper barrier layer 234 and is, for example, filled into the opening OP. In this embodiment, the material of the low-resistance material layer 236 is aluminum, but the disclosure is not limited thereto. For the remainder of the introduction concerning the low-resistance material layer 236, reference can be made to the embodiment described above, which is not repeated here.

[0075] In this embodiment, the metal layer for adjusting the work function 232, the upper barrier layer 234 and the low-resistance material layer 236 can be formed into the metal gate 230, but the disclosure is not limited thereto.

[0076] The intermediate-gate oxide layer 130 is arranged, for example, between the floating gate 110 and the control gate structure 200. The intermediate-gate oxide layer 130 can be used, for example, to electrically isolate the floating gate 110 and the control gate structure 200 from each other. In this embodiment, the intermediate-gate oxide layer 130 contains the oxide-nitride oxide (ONO) composite layer, but the disclosure is not limited thereto. For the remainder of the introduction concerning the intermediate-gate oxide layer 130, reference can be made to the embodiment described above, which will not be repeated here.

[0077] The erase gate 120 is, for example, arranged on one side of the floating gate 110. The erase gate 120 can, for example, have the function of erasing the hot electrons stored in the floating gate 110. For the remainder of the introduction concerning the erase gate 120, reference can be made to the embodiment described above, which will not be repeated here.

[0078] The word line 140 is, for example, arranged on the other side of the floating gate 110. A corresponding write or read operation can be performed on the storage element 100 by applying a write voltage or a read voltage to the word line 140, but the disclosure is not limited to this. For the remainder of the introduction concerning the word line 140, reference can be made to the embodiment described above, which will not be repeated here.

[0079] The spacer 160 is, for example, arranged on one side of the word line 140 away from the floating gate 110. In this embodiment, the spacer 160 is a section of the dielectric layer IL2, but the disclosure is not limited thereto.

[0080] In this embodiment, the semiconductor structure 10 also includes the high-voltage element 300 and the logic element 400.

[0081] The high-voltage element 300 is, for example, arranged in the region of the high-voltage element A2. In this embodiment, the high-voltage element 300 is a transistor. The high-voltage element 300 includes, for example, the gate 302, the gate oxide layer 304, and the spacer 306. The gate oxide layer 304 is arranged between the gate 302 and the substrate SB, and the spacer 306 is arranged on both sides of the gate 302. However, the disclosure is not limited to this. For the remainder of the introduction concerning the high-voltage element 300, reference may be made to the above embodiment, which will not be repeated here.

[0082] The logic element 400 is, for example, arranged in logic element region A3. In this embodiment, the logic element 400 is a transistor. The logic element 400 includes, for example, the high-dielectric-constant dielectric layer 410, the lower depletion layer 420, the metal gate 430, the side wall 440, and a spacer 450. The high-dielectric-constant dielectric layer 410 is arranged on the substrate SB. The lower depletion layer 420 is arranged on the high-dielectric-constant dielectric layer 410. The metal gate 430 is arranged on the lower depletion layer 420. However, the disclosure is not limited to this. The lower barrier layer 420, for example, contains the first lower barrier layer 422 and the second lower barrier layer 424. The metal gate 430, for example, contains the metal layer for adjusting the work function 432, the upper barrier layer 434, and the layer of low-resistance material 436.The side wall 440 is arranged, for example, on both sides of the high dielectric constant dielectric layer 410, the lower barrier layer 420, and the metal gate 430. The spacer 450 is arranged, for example, on one side of the side wall 440, away from the metal gate 430. For the remainder of the introduction concerning the logic element 400, reference can be made to the embodiment described above, which will not be repeated here.

[0083] In this embodiment, the semiconductor structure 10 can also include the interconnect structure 500.

[0084] Referring to the two Fig. 1F and Fig.In embodiment 2A, the interconnect structure 500 includes, for example, the dielectric layer IL4 and the conductive vias V. The conductive vias V are arranged, for example, in the dielectric layer IL4 and each penetrates, for example, the dielectric layer IL4. In this embodiment, the conductive vias V include conductive via V1, conductive via V2, conductive via V3, conductive via V4, and conductive via V5. Conductive via V1 is, for example, electrically connected to the control gate structure 200 of the storage element 100. Conductive via V2 is, for example, electrically connected to the gate 302 of the high-voltage element 300. Conductive via V3 is, for example, electrically connected to the metal gate 430 of the logic element 400.The conductive via V4 is, for example, electrically connected to the erase gate 120 of the memory element 100. The conductive via V5 is, for example, electrically connected to the word line 140 of the memory element 100.

[0085] Based on the above explanations, in the manufacturing process of a semiconductor structure provided in the disclosure, by forming the control-gate structure which contains the dielectric layer with high dielectric constant and the metal gate in the memory element, the write efficiency of the memory element in the disclosure can be increased compared to the conventional embedded flash.

[0086] Furthermore, in the manufacturing process for the semiconductor structure described in the disclosure, the high-dielectric-constant layer and the metal gate can be formed in the same process as the other film layers in the logic element region. That is, no additional processes are required to form the high-dielectric-constant layer and the metal gate. Therefore, the manufacturing process for the semiconductor structure in the disclosure does not require any additional manufacturing costs. REFERENCE MARK LIST 10 Semiconductor structure 100 storage element 110 Floating Gate 120 deletion gate 130 Inter-gate oxide layer 140 Word guidance 150 dielectric tunnel layer 160, 306, 450 spacers 200 Tax Gate Structure 200a Dummy Gate Structure 200B lower part 200T upper part 210 high dielectric layer 220 lower barrier layer 222 first lower barrier layer 224 second lower barrier layer 230 metal gates 230a Dummy Gate 232 Metal layer for adjusting the work function 234 upper barrier layer 236 Low-resistance material layer 300 high-voltage elements 302 Gate 304 Gate oxide layer 310 dielectric layer 400 Logical Element 440 side wall 500 Interconnect structure A1 storage element area A2 High-voltage element area A3 Logic element area CL conductive material layer IL1, IL2, IL3, IL4 dielectric layer NL1 first nitride layer NL2 second nitride layer OL1 first oxide layer OL2 second oxide layer OL3 third oxide layer Surgical opening R1 first recess R2 second recess SA1 first victim layer SA2 second victim layer SB Substrat STI, STI1, STI2, STI3 Shallow Trench Isolation Structure V, V1, V2, V3, V4, V5 conductive vias WB, WT width X direction Z normal direction

Claims

[1] Manufacturing process of a semiconductor structure (10), comprising: Forming a storage material layer on a substrate (SB), wherein the storage material layer comprises a floating gate (110), an quenching gate (120), a first oxide layer (OL1), a first nitride layer (NL1), a second oxide layer (OL2), a second nitride layer (NL2) and a third oxide layer (OL3); Forming a first recess (R1) in the storage material layer, wherein the first recess (R1) exposes a section of the first nitride layer (NL1); Forming a second recess (R2) in the storage material layer, wherein the second recess (R2) overlaps the first recess (R1) to form an opening (OP), and the second recess (R2) exposes a section of the floating gate (110); Formation of an inter-gate oxide layer (130) in the opening (OP); Forming a dummy gate structure (200a) with a dielectric layer with a high dielectric constant (210) and a dummy gate (230a) in the opening (OP); and Forming a control gate structure (200) with a metal gate (230) to form a storage element (100) by replacing the dummy gate (230a) in the dummy gate structure (200a) with a metal gate (230), where the width of an upper section (200T) of the control gate structure (200) is greater than the width of a lower section (200B) of the control gate structure (200). [2] Manufacturing method of a semiconductor structure (10) according to claim 1, wherein a step comprises forming the dummy gate structure (200a) in the opening (OP): Formation of the dielectric layer with high dielectric constant (210) on a side wall of the aperture (OP); Formation of a lower barrier layer (220) on the dielectric layer with high dielectric constant (210); and Forming the dummy gate (230a) on the lower barrier layer (220). [3] Manufacturing method of a semiconductor structure (10) according to claim 2, wherein the storage material layer further comprises a conductive material layer (CL), and after a step of forming the dummy gate (230a) on the lower barrier layer (220) the conductive material layer (CL) is structured to form a word line (140). [4] Manufacturing method of a semiconductor structure (10) according to claim 2, wherein a step comprises forming the lower barrier layer (220) on the high dielectric constant dielectric layer (210): Forming a first lower barrier layer (222) on the high dielectric layer (210), wherein a material of the first lower barrier layer (222) comprises titanium nitride and Forming a second lower barrier layer (224) on top of the first lower barrier layer (222), wherein a material of the second lower barrier layer (224) comprises tantalum nitride. [5] Manufacturing method of a semiconductor structure (10) according to claim 2, wherein a step comprises forming the control gate structure (200) with the metal gate (230): Removal of the dummy gate (230a); Forming a metal layer to adjust the work function (232) on the lower barrier layer (220); Forming an upper barrier layer (234) on the metal layer to adjust the work function (232); and Forming a low-resistance material layer (236) on the upper barrier layer (234).

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