ELECTRONIC SWITCHING WITH A LEVEL SHIFTER

Abstract

An electronic circuit and an integrated circuit are disclosed. The electronic circuit comprises: a level shifter (2) having a level shifter transistor (TL1) with a load path coupled between a low-side reference node (N11) and a high-side supply node (N13) of the electronic circuit (1). The electronic circuit further comprises a semiconductor body (100) having a base region (110) of a first doping type, a well (120) of a second doping type complementary to the first doping type, and a device region (130) of the first doping type, which is separated from the base region (110) by the well (120). The level shifter transistor (TL1) is at least partially integrated in the device region (130), and the well (120) is connected to the high-side supply node (N13) and the base region (110) is connected to the low-side reference node (N11).

Description

This disclosure relates generally to an electronic circuit having a level shifter.A level shifter is used to transfer signals from a first voltage domain to a second voltage domain different from the first voltage domain. In particular, a level shifter may be used to transmit control signals related to a first reference potential, such as ground potential, to a drive circuit of a high-side switch. The drive circuit usually receives a supply voltage related to a second reference potential that is different from the first reference potential, and is configured to generate a drive signal for the high-side switch that is related to the second reference potential.There is a need for an electronic circuit with a level shifter capable of quickly and reliably transmitting a signal.An example relates to an electronic circuit. The electronic circuit includes a level shifter having a level shifter transistor with a load path coupled between a low-side reference node and a high-side supply node of the electronic circuit. The electronic circuit further comprises a semiconductor body having a base region of a first doping type, a well of a second doping type complementary to the first doping type, and a device region of the first doping type separated from the base region by the well. The level shifter transistor is at least partially integrated in the device region. The well is connected to the high side supply node and the base region is connected to the low side reference node.Another example relates to an integrated circuit. The integrated circuit comprises a semiconductor body having a base region of a first doping type, a well of a second doping type complementary to the first doping type, and a device region of the first doping type separated from the base region by the well. The integrated circuit further comprises a transistor at least partially integrated in the device region, the transistor comprising a drift region of the second doping type, a drain region of the second doping type adjoining the drift region, a body region of the first doping type adjoining the drift region and spaced apart from the drain region, a source region of the second doping type separated from the drift region by the body region, and a gate electrode adjoining the body region and dielectrically insulated from the body region by a gate dielectric. The body region forms a closed loop around the drain region in a horizontal plane of the semiconductor body, and the drift region is spaced from the body region in a first and / or second edge region of the transistor.Examples will be explained below with reference to the drawings. The drawings are intended to illustrate certain principles, thus illustrating only aspects necessary to understand these principles. The drawings are not to scale. In the drawings, like reference numerals designate like features. FIG. 1 illustrates an example of an electronic circuit including a level shifter with a level shifter transistor; FIGS. 2A-2B illustrate an example of at least partially integrating the level shifter transistor in a semiconductor body; FIG. 3 illustrates a load circuit with a high side switch driven by the electronic circuit of FIG. 1 ; FIG. 4 shows a vertical cross-sectional view of a semiconductor body to illustrate an example for at least partially integrating the level shifter transistor in the semiconductor body; FIG. 5 shows a plan view of the semiconductor body according to FIG. 3 ; FIG. 6 is a vertical cross-sectional view of a portion of the semiconductor body to illustrate a modification of the level shifter transistor of FIG. 4 ; FIG. 7 is a plan view of a portion of the semiconductor body to illustrate a level shifter transistor according to another example; FIGS. 8A-8B illustrate a level shifter transistor according to another example; FIG. 9 illustrates a modification of the level shifter transistor of FIGS. 8A-8B; FIGS. 10A-10B illustrate a level shifter transistor according to another example, which is a modification of the level shifter transistor according to FIGS. 8A-8B ; FIG. 11 illustrates an example of a level shifter including a level shifter transistor and an evaluation circuit connected in series with the level shifter transistor; FIG. 12 illustrates an example of the evaluation circuit in further detail; FIG. 13 illustrates an example of a level shifter including two level shifter transistors; FIG. 14 illustrates an example for at least partially integrating the two level shifter transistors in a doped well of a semiconductor body; FIG. 15 illustrates an example of a high-side driver circuit included in the electronic circuit; FIG. 16 illustrates a modification of the electronic circuit of FIG. 1 additionally including a low-side driver circuit; and FIG. 17 illustrates an example of a well in detail in which active device regions of the level shifter transistor are integrated.In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the specification and, for purposes of illustration, show examples of how the invention may be used and implemented. It is understood that the features of the various embodiments described herein may be combined with each other, unless expressly stated otherwise.FIG. 1 schematically illustrates an example of an electronic circuit 1 comprising a level shifter 2. The level shifter 2 includes a level shifter transistor TL 1 including a load path coupled between a low-side reference node N 11 and a high-side supply node N 13 of the electronic circuit 1. The load path of the level shifter transistor TL 1 is a circuit path between a first and a second load path node D 1, S 1 of the level shifter transistor TL 1. The manner in which the load path of the level shifter transistor TL 1 is connected between the low-side reference node N 11 and the high-side supply node N 13 is not illustrated in detail in FIG. 1. Examples of connecting the load path of the level shifter transistor TL 1 between the low-side reference node N 11 and the high-side supply node N 13 are explained further below herein.The level shifter transistor TL 1 is at least partially integrated in a semiconductor body 100. In particular, the level shifter transistor TL 1 is at least partially integrated in a device region 130 of the semiconductor body 100. The semiconductor body 100 is not illustrated in the circuit diagram shown in FIG. 1.A vertical cross-sectional view and a plan view of the semiconductor body 100 comprising the device region 130 in which the level shifter transistor TL 1 is at least partially integrated are schematically illustrated in FIGS. 2A-2B. According to an example, the semiconductor body 100 comprises a monocrystalline semiconductor material, such as silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs) or gallium nitride (GaN).The level shifter transistor TL1 is represented in FIGS. 2A-2B only by its circuit symbol. For the purpose of illustration only, the level shifter transistor TL 1 according to FIGS. 1 and 2A- 2B is implemented as a MOSFET, in particular as an N-type enhancement MOSFET. However, this is only an example. Other types of transistor devices, such as other types of MOSFETs or bipolar junction transistors (BJTs), may also be used as the level shifter transistor TL 1. More detailed examples of the level shifter transistor TL 1 are explained hereinafter.Referring to FIGS. 2A and 2B, the semiconductor body 100 comprises a base region 110 of a first doping type, a well 120 of a second doping type complementary to the first doping type, and the device region 130. The device region 130 is of the first doping type and is separated from the base region 110 by the well 120. Further, the well 120 is connected to the high-side supply node N 13, and the base region 110 is connected to the low-side reference node N 11.According to an example, a polarity of a voltage between the high-side supply node N 13 and the low-side reference node N 11 and the first and second doping types are matched to each other such that the voltage between the high-side supply node N 13 and the low-side reference node N 11 reverse-biases a PN junction formed between the second doping type well 120 and the first doping type base region 110. According to an example, the voltage between the high side supply node N 13 and the low side reference node N 11 is positive, the first doping type is a P type and the second doping type is an N type. In this example, the PN junction between the well 120 and the base region 110 is reverse biased by the positive voltage between the high side supply node N 13 and the low side reference node N 11.According to one example, the electrical potential at the low-side reference node N 11 is ground GND. Thus, the low-side reference node N 11 may also be referred to as a ground node below.Referring to the above, the device region 130 is separated from the base region 110 of the semiconductor body 100 by the well 120. Referring to FIGS. 2A-2B, this may include that the well 120 completely surrounds the device region 130 in the semiconductor body 100. Examples of forming the well 120 are discussed further below herein.According to an example illustrated in FIG. 1, the electronic circuit 1 comprises, in addition to the level shifter 2, a high-side driver circuit 4. the level shifter 2 is configured to receive an input signal Sin at an input IN and to provide a level-shifted control signal Shs to the high-side driver circuit 4 based on the input signal Sin. The level-shifted control signal Shs, which is also referred to as a high-side control signal Shs below, contains information contained in the input signal Sin. The input signal Sin and the high-side control signal Shs are related to different potentials. The input signal Sin is referenced to ground GND, for example. According to an example, the input signal Sin switches the level shifter transistor TL 1 on or off, such that the high-side control signal Shs depends on the switching state (on or off) of the level shifter transistor TL 1. The high-side control signal Shs is related to, for example, a high-side supply voltage Vhs obtained at the high-side supply node N 13.The information included in the input signal Sin and therefore the high-side control signal Shs is, for example, switching information for an electronic switch. According to one example, the high-side drive circuit 4 is configured to provide a drive signal Sdrwh based on the high-side control signal Shs at an output N 14. The drive signal Sdrvh is also referred to below as a high-side drive signal Sdrvh. According to an example, the drive signal Sdrvh is a voltage related to a high-side reference node N 12.FIG. 3 illustrates an example of a load circuit 6 including an electronic switch 7 configured to receive the high-side drive signal Sdrwh from the high-side driver circuit 4. In this example, the electronic switch 7 is a high-side switch connected between a load supply node N 23 and a low-side circuit 8, and a series circuit including a load path of the high-side switch 7 and the low-side circuit 8 is connected between the load supply node N 23 and a load reference node N 21. According to an example, the load reference node N 21 and the low side reference node N 11 are connected to the same potential, such as ground potential, GND. The load supply node N 23 is configured to obtain a load supply voltage Vhv related to the load reference node N 21. According to an example, the load supply voltage Vhv is selected from between several 10 V and several 100 V. A withstand voltage of the high-side switch 7 is selected depending on the load supply voltage Vhv such that the high-side switch 7 is configured to withstand the load supply voltage Vhv when the high-side switch 7 is in a blocking state (off state).According to one example, the high-side switch 7 is configured to turn on or off depending on the high-side drive signal Sdrvl obtained from the high-side driver circuit 4. In the on state (on state) of the high-side switch 7, the load supply voltage Vhv substantially drops across the low-side circuit 8. In the off state of the high-side switch 7, the load supply voltage Vhv drops substantially across the high-side switch 7.The high-side switch 7 may be implemented as a conventional electronic switch. For the purpose of illustration only, the high-side switch 7 shown in FIG. 3 is a MOSFET, in particular an N-type MOSFET. As is well known, a MOSFET is a voltage controlled device that turns on or off depending on a driving voltage obtained at a driving input, the driving input being constituted by a gate node and a source node. Thus, in the example of FIG. 3, the high-side drive signal Sdrvl is a voltage applied between a gate node G and the source node S of the MOSFET constituting the high-side switch 7. For this purpose, the gate node G is connected to the output N 14 of the electronic circuit 1 having the level shifter 2 and the high-side drive circuit 4, and the source node S is connected to the high-side reference node N 12. The load path of the high-side switch 7 is a circuit path between the source node S and a drain node D of the MOSFET constituting the high-side switch 7.According to an example illustrated in FIG. 3, the high-side supply voltage Vhs obtained at the high-side supply node N 13 and related to the low-side reference node N 11 is provided by a voltage source 51 connected between the high-side supply node N 13 and the high-side reference node N 12. The electric potential at the high-side reference node N 12 depends on the switching state of the high-side switch 7 in the load circuit 6 as follows.When the high-side switch 7 is in the on state, the electric potential at the high-side reference node N 12 is substantially equal to the load supply voltage Vhv, so that the high-side supply potential Vhs is substantially given by the load supply voltage Vhv plus the supply voltage V 51 obtained between the high-side supply node N 13 and the high-side reference node N 12. When the high-side switch 7 is in the off state, the potential at the high-side reference node N 12 is substantially equal to the ground potential GND, so that the high-side supply voltage is substantially equal to the voltage V 51 provided by the voltage source 51 connected between the high-side supply node N 13 and the high-side reference node N 12.The voltage source 51 providing the supply voltage V 51 includes, for example, a bootstrap circuit (not illustrated). An example of a voltage source 51 with a bootstrap circuit is explained further below.FIG. 4 schematically illustrates an example of implementing the level shifter transistor TL 1 in the device region 130 of the semiconductor body 100. For the purpose of illustration only, the level shifter transistor TL1 shown in FIG. 4 is a MOSFET. In this example, the level shifter transistor TL 1 includes a drift region 31 of the second doping type, a drain region 34 of the second doping type adjoining the drift region 31, a body region 33 of the first doping type adjoining the drift region 31 and spaced apart from the drain region 34, and a source region 32 of the second doping type separated from the drift region 31 by the body region 33. Each of the drift region 31, the drain region 34, the body region 33 and the source region 32 is a doped region formed within the device region 130 of the semiconductor body 100.The drift region 31, the source region 32, the body region 33 and the drain region 34 are also referred to below as active device regions of the level shifter transistor TL 1. Forming the active device regions of the level shifter transistor TL 1 may include implanting dopant atoms into the device region 130, and may include a thermal process for activating the implanted dopant atoms. The device region 130 has a base doping of the second doping type. Referring to FIG. 4, portions of the device region 130 having the base doping concentration remain after forming the active device regions of the level shifter transistor TL 1. In the following, unless otherwise indicated, "active device region 130" also denotes those portions of the active device region 130 which have the basic doping concentration after the production of the active device regions of the level shifter transistor TL 1.According to an example, doping concentrations of the base region 110 and the device region 130 are selected from a range between 1E14cm-3and 1E16cm-3, for example. According to an example, the base region 110 and the device region 130 have substantially the same doping concentration. The doping concentration of the well 120 is selected from, for example, between 1E18cm -3 and 1E20cm -3. Doping concentrations of the source and drain regions 32, 34 are, for example, higher than 1E19cm -3 and lower than 1E21cm -3. The doping concentration of the drift region 31 is selected from between 1E16 cm -3 and 1E18 cm -3, and the doping concentration of the body region 33 is selected from between 1E17 cm -3 and 1E19 cm -3. for example.Referring to FIG. 4, the level shifter transistor TL 1 further includes a gate electrode 35 adjacent to the body region 33 and dielectrically insulated from the body region 33 by a gate dielectric 36. Conventionally, the gate electrode 35 serves to control a conductive channel in the body region 33 between the source region 32 and the drift region 31.The level shifter transistor TL 1 is in an on state (conductive state) in which there is a conductive channel in the body region 33 between the source region 32 and the drift region 31 when a voltage higher than a threshold voltage of the level shifter transistor TL 1 is applied between the gate electrode 35 and the source region 32. In an N-type MOSFET, for example, the threshold voltage is a positive voltage, so that the level shifter transistor TL 1 is in the on state whenever a drive voltage higher than the threshold voltage is applied between the gate electrode 35 and the source region 32. The level shifter transistor TL 1 is in an off state (off state) when the voltage between the gate electrode 35 and the source region 32 is below the threshold voltage. In this operating state, the conductive channel in the body region 33 is interrupted.According to an example, the level shifter transistor TL 1 further includes a source electrode 221 connected to the source region 32 and the body region 33, and a drain electrode 222 connected to the drain region 34. The source and drain electrodes 221, 222 may be spaced apart from the semiconductor body 100 and separated from the semiconductor body 100 by an insulating layer 210. For the purpose of illustration only, the source and drain electrodes 221, 222 are drawn to be formed on the insulating layer 210 in the example illustrated in FIG. 4. The source electrode 221 may form a source node S 1 of the level shifter transistor TL 1 or may be connected to the source node S 1. The drain electrode 222 may form a drain node D 1 of the level shifter transistor TL 1 or may be connected to the drain node D 1.Connections between the source electrode 221 and the source and body regions 32, 33 and a connection between the drain electrode 222 and the drain region 34 are only schematically illustrated in FIG. 4. These connections may be implemented in a conventional manner. According to an example, the connections comprise electrically conductive vias formed between the respective doped region 32, 33, 34 and the respective electrode 221, 222.In the example illustrated in FIG. 4, the gate electrode 35 is a planar electrode formed on a first surface 101 of the semiconductor body 100 and separated from the semiconductor body 100 by the gate dielectric 36. However, this is only an example. According to another example (not shown), the gate electrode 35 is a trench electrode formed in a trench extending in a vertical direction of the semiconductor body 100 from the first surface 101 into the semiconductor body 100 and extending in a lateral direction of the semiconductor body 100 from the source region 32 through the body region 33 to the drift region 31. The "vertical direction" is a direction substantially perpendicular to the first surface 101, and the "lateral direction" is a direction substantially parallel to the first surface 101.The arrangement illustrated in FIG. 4 with the semiconductor body 100 and the level shifter transistor TL 1, the active device regions of which are formed in the device region 130, which is separated from the base region 110 by the well 120, comprises a plurality of capacitances, which are illustrated in FIG. 4 by capacitor circuit symbols. Each of these capacitances is a junction capacitance, that is, a capacitance including a PN junction between a doped region of the first doping type and a doped region of the second doping type. Each of these capacitances is charged when a voltage is applied to the respective PN junction which reverse biases the respective PN junction, wherein the state of charge of the respective capacitance varies as the magnitude of the voltage which reverse biases the PN junction varies.Referring to FIG. 4, a first capacitance C 1 includes the well 120 and the base region 110 and the PN junction formed therebetween. By connecting the base region 110 to the low-side reference node N 11 and the well 120 to the high-side reference node N 13, the first capacitance C 1 is connected between the high-side reference node N 13 and the low-side reference node N 11. Referring to the above, the high-side power supply voltage Vhs varies depending on the switching state of the high-side switch 7 of the load circuit 6.A second capacitance C 2 includes the body region 33 connected to the source node S 1, the device region 130, the well 120, and the PN junction formed between the device region 130 and the well 120. According to an example, the source node S 1 is connected to the low-side reference node N 11. In this example, the second capacitance C 2, like the first capacitance C 1, is connected between the high-side supply node N 13 and the low-side reference node N 11, so that the state of charge of this capacitance varies depending on the switching state of the high-side switch 7.A third capacitance C 3, which may also be referred to as drain-source capacitance of the level shifter transistor TL 1, includes the drain region 34, the drift region 31, the body region 33 connected to the source node S 1, portions of the device region 130 adjacent to the drift region 31 and the body region 33, a PN junction formed between the body region 33 and the drift region 31, and a PN junction formed between the drift region 31 and the device region 130.Referring to the above, the high side control signal Shs depends on the switching state of the level shifter transistor TL 1, wherein the switching state of the level shifter transistor depends on the input signal Sin. The switching speed of the level shifter 2 indicates how fast a signal level of the high-side control signal Shs changes after the signal level of the input signal Sin changes. The shorter a delay time between a change in the signal level of the input signal Sin and a corresponding change in the signal level of the high-side control signal Shs, the higher a switching speed of the level shifter 2, the input signal Sin controls the operating state of the level shifter transistor TL 1, such that the switching speed of the level shifter transistor TL 1 substantially determines the switching speed of the level shifter 2. The switching speed of the level shifter transistor TL 1 indicates how fast the level shifter transistor TL 1 changes its operating state (switching state) depending on the input signal Sin.The level shifter transistor TL 1 may be operated in an on state (conductive state) or an off state (blocking state). When the level shifter transistor TL 1 switches from the on-state to the off-state, the conductive channel in the body region 33 is interrupted and the PN junction between the body region 33 and the drift region 31 and also the PN junction between the drift region 31 and the device region 130 is reverse biased so that the source-drain capacitance C 3 is charged. Equivalently, when the level shifter transistor TL 1 changes from the off state to the on state, a conductive channel is generated in the body region 33 and the voltage between the body region 33 and the drift region 31 decreases, so that the source-drain capacitance C 3 is discharged. The switching speed of the level shifter transistor TL 1 is substantially determined by how fast the source-drain capacitance C 3 is charged when the level shifter transistor TL 1 changes from the on state to the off state, or is discharged when the level shifter transistor TL 1 changes from the off state to the on state.Referring to the above, the source-drain capacitance C 3 includes the drift region 31 and portions of the device region 130 adjacent to the drift region 31. Further, the device region 130 is also part of the second capacitance C 2 formed between the body region 33 connected to the source node S 1 and the well region 120 connected to the high side supply node N 13. The PN junction formed between the device region 130 and the well 120 is always reverse biased, wherein the voltage reverse biasing the PN junction is either substantially equal to the supply voltage V 51 provided by the supply voltage source 51 or equal to the supply voltage V 51 plus the load supply voltage Vhv. Hereinafter, the first operation state is referred to as a low voltage state, and the second operation state is referred to as a high voltage state.In each of these operating states, the device region 130 is at least partially depleted of charge carriers, wherein such depletion of charge carriers of the device region 130 reduces a capacitance value of the source-drain capacitance C 3. Basically, the larger the portions of the device region 130 depleted of charge carriers, the lower the capacitance value of the source-drain capacitance C 3 so that in the high voltage state the source-drain capacitance C 3 is lower than in the low voltage state. Nevertheless, in both operating states, the high voltage state and the low voltage state, the partial depletion of the device region 130, which is due to the connection of the well 120 to the high side supply node N 13 and the coupling of the source node S 1 of the level shifter transistor TL 1 to the low side reference node N 11, results in a reduced capacitance value of the source-drain capacitance C 3, which results in a high switching speed of the level shifter transistor TL 1.The state of charge of each of the first and second capacitances C 1, C 2 is different in the high voltage state and the low voltage state, so that the state of charge of these capacitances C 1, C 2 changes as the high-side supply voltage Vhs changes. The first and second capacitances C 1, C 2 are charged or discharged by current provided or obtained from the load circuit 6. The load circuit 6 is usually capable of providing a high current for changing the states of charge of the first and second capacitances C 1, C 2, so that the charging or discharging of the first and second capacitances C 1, C 2 does not have a substantial influence on the switching speed of the level shifter 2.FIG. 5 illustrates a top view of a transistor device of the type illustrated in FIG. 4, according to an example. In particular, FIG. 5 illustrates a top view of the first surface 101 of the semiconductor body 100 in those regions in which the well 120 and the device region 130 are arranged with the active device regions of the level shifter transistor TL 1. The position of the gate electrode 35 relative to the positions of the source, body and drift regions 32, 33, 31 is illustrated in dashed lines in FIG. 5.FIG. 6 shows a modification of the transistor device of FIG. 4. the transistor device of FIG. 4 includes a field electrode 37 adjacent to the drift region 31 and dielectrically insulated from the drift region 31 by a field dielectric 38. According to an example, the gate electrode 35 and the field electrode 37 are formed by the same electrode, wherein a portion adjacent to the body region 33 forms the gate electrode 35 and a portion adjacent to the drift region 31 forms the field electrode 37. According to an example, the field dielectric 38 separating the field electrode from the drift region 31 is thicker than the gate dielectric 36. Both the gate dielectric 35 and the field dielectric 36 comprise an oxide, for example.According to an example, a dimension of the field electrode 37 in the direction in which the body region 33 and the drain region 34 are spaced apart from each other is about 30%, 50% or 70% of the distance between the body region 33 and the drain region 34.FIG. 7 illustrates a modification of a transistor device of the type illustrated in FIG. 5 or 6. In particular, FIG. 7 shows a top view of the device region 130 in which active device regions of the level shifter transistor TL 1 are integrated.In the example illustrated in FIG. 7, the body region 33 includes two body region portions, a first body region portion 331 and a second body region portion 332, each spaced apart from the drain region 34. Further, the first and second body region portions 33 are spaced apart from each other in 1, 332 such that the drain region 34 is arranged between the first and second body region portions 33 in 1, 332 manner. According to an example, distances between the drain region 34 and the first body region portion 33 1 on one side and between the drain region 34 and the second body region portion 33 2 on the other side are substantially equal, such that the first and the second body region portions 33 1, 332 are symmetrical to each other with respect to the drain region 34. The first and second body region portions 331, 332 are respectively connected to the source node S 1 of the level shifter transistor TL 1. However, connections between the first and second body region portions 331, 332 and the source node S 1 are not illustrated in FIG. 7.Referring to FIG. 7, in the transistor device according to FIG. 7, the source region 32 includes a first source region portion 32 1, which is separated from the drift region 31 by the first body region portion 33 1 and a second source region portion 32 2, which is separated from the drift region 31 by the second body region portion 33 2. The first and second source region portions 32 1, 322 are connected to the source node S 1, respectively. However, connections between the first and second source region portions 32 1, 322 and the source node S 1 are not illustrated in FIG. 7.Further, in the transistor device of FIG. 7, the gate electrode 35 comprises two gate electrode portions, a first gate electrode portion 35 1 and a second gate electrode portion 35 2. The first gate electrode portion 35 1 is adjacent to the first body region portion 33 1 and serves to control a first conductive channel in the first body region portion 33 1 between the first source region portion 32 1 and the drift region 31. The second gate electrode portion 35 2 is adjacent to the second body region portion 33 2 and serves to control a second conductive channel in the second body region portion 33 2 between the second source region portion 32 2 and the drift region 31. The first and second gate electrode portions 35 1, 352 are connected to the gate node G1, respectively, so that the first and second conductive channels are simultaneously controlled.Optionally, in the same manner as the transistor device of FIG. 6, the transistor device of FIG. 7 includes a field electrode 37. in this example, the field electrode 37 includes first field electrode portions 37 1, which are adjacent to the first gate electrode portion 35 1 and second field electrode portions 37 2, which are adjacent to the second gate electrode portion 35 2.FIGS. 8A-8B illustrate a modification of the transistor device of FIG. 7, wherein FIG. 8A shows a top view of the device region 130 in which the active device regions of the level shifter transistor TL 1 are integrated, and FIG. 8B shows a vertical cross-sectional view of a portion of the level shifter transistor TL 1 of FIG. 8A. The transistor device according to FIGS. 8A-8B differs from the transistor device according to FIG. 7 in that the body region 33 forms a ring in a horizontal plane of the semiconductor body 100 surrounding the drift region 31 and the drain region 34. According to one example, the body region 33 is formed such that at each position of the body region 33, a (shortest) distance between the body region 33 and the drain region 34 is substantially equal.Referring to FIG. 8A, the body region 33 comprises first and second body region portions 331, 332 of the type explained with reference to FIG. 7. That is, the first body region portion 33 1 separates a first source region portion 321 from the drift region 31, and the second body region portion 33 2 separates a second source region portion 32 2 from the drift region 31.Further, referring to FIG. 8A, the body region 33 includes a third body region portion 33 3, which is arranged in a first edge region ER 1 of the device region 130 between the first and second body region portions 33 1, 332 and a fourth body region portion 33 4, which is arranged in a second edge region ER 2 of the device region 130 between the first and second body region portions 33 1, 332. The third and fourth body region portions 33 3, 334 are free of source region portions. Further, the first, second, third and fourth body region portions 33 1, 332, 333, 334 form a closed loop of the body region 33 around the drift and drain regions 31, 34.According to an example illustrated in FIG. 8A, the gate electrode 35 is ring-shaped in a similar manner as the body region 33 and forms a closed loop over the first surface 101 around projections of the drift and drain regions 31, 34. in the first and second body region portions 33 1, 332 the gate electrode 35 is dielectrically insulated from the body region 33 by the gate dielectric 36 (not visible in FIG. 8A ). According to one example, in the edge regions ER 1, ER 2, the gate electrode 35 is separated from the semiconductor body 100 by a dielectric layer 39 that is thicker than the gate dielectric 36.FIG. 8B illustrates a vertical cross-sectional view of the level shifter transistor TL 1 in the first edge region ER 1. More specifically, FIG. 8B shows a vertical cross-sectional view of a portion of the body region 33, the drift region 31, the gate electrode 35 and the field dielectric 39. the field dielectric 39 is, for example, a shallow trench isolation (STI) and may extend from the first surface 101 into the semiconductor body 100.According to a further example illustrated in FIG. 9, the field dielectric 39 is formed on the first surface 101 of the semiconductor body 100.The thickness of the field dielectric 39 is, for example, at least 5 times the thickness of the gate dielectric 36. in one example, the thickness of the field dielectric 39 is less than 100 times the thickness of the gate dielectric 36. in one example, the thickness of the field dielectric 39 is between 5 times and 30 times the thickness of the gate dielectric 36.FIGS. 10A-10B show a modification of the level shifter transistor TL1 of FIGS. 9A-9B. FIG. 10A shows a top view of the device region 130 and the active device regions of the level shifter transistor TL 1, and FIG. 10B shows a vertical cross-sectional view of the level shifter transistor TL 1 in a portion of the first edge region ER 1.In the level shifter transistor TL 1 according to FIGS. 10A-10B, the drift region 31 is spaced apart from the third and fourth body region portions 33 in 3, 334 fashion. According to an example, a doped region of the first doping type is arranged between the body region 33 and the drift region 31 and extends from the drift region 31 to the body region 33.According to an example, the doped region of the first doping type arranged between the body region 33 and the drift region 31 has a doping concentration different from the doping concentration of the body region 33. According to an example, the doping concentration is lower than the doping concentration of the body region 33, such as less than 50% or less than 10% of the doping concentration of the body region 33.According to an example, the doped region of the first doping type arranged between the body region 33 and the drift region 31 has a doping concentration equal to or lower than the doping concentration of the drift region 31. According to an example, the doping concentration is lower than the doping concentration of the drift region 31, such as lower than 50% or lower than 10% of the doping concentration of the drift region 31.According to another example (illustrated in FIG. 10A ), the doped region of the first doping type arranged between the body region 33 and the drift region 31 is formed by the device region 130, such that portions of the device region 130 are respectively arranged between the third and fourth body region portions 33 3, 334 and the drift region 31.In the transistor device according to FIGS. 10A-10B, a total size of the drift region 31 in a lateral plane of the semiconductor body 100 is smaller than in the transistor device according to FIGS. 8A-8B. Consequently, an area of the PN junction formed between the drift region 31 and the device region 130 is smaller in the transistor device according to FIGS. 10A-10B compared to the transistor device according to FIGS. 8A-8B. Thus, the level shifter transistor TL 1 according to FIGS. 10A-10B has a lower source-drain capacitance C 3 than the level shifter transistor according to FIGS. 8A-8B, such that the level shifter transistor TL 1 according to FIGS. 10A-10B, in particular in the low-voltage state, has a higher switching speed than the level shifter transistor TL 1 according to FIGS. 8A-8B.Referring to the above, the level shifter 2 includes the level shifter transistor TL 1 whose load path is coupled between the high-side supply node N 13 and the low-side reference node N 11. An example of coupling the load path of the level shifter transistor TL 1 between the high-side supply node N 13 and the low-side reference node N 11 is illustrated in FIG. 11. In this example, the level shifter 2 comprises an evaluation circuit 21 connected in series with the load path of the level shifter transistor TL 1, wherein the series circuit comprising the level shifter transistor TL 1 and the evaluation circuit 21 is connected between the high-side supply node N 13 and the low-side reference node N 11.According to one example, a voltage limiting element 22 is connected in parallel with the evaluation circuit 21. The voltage limiting circuit 22 is designed to limit (clamp) a voltage at the evaluation circuit 21, so that the voltage at the evaluation circuit does not exceed a predefined voltage threshold. The voltage limiting circuit 22 includes, for example, a Zener diode or a series circuit including a plurality of Zener diodes connected in series. The voltage threshold (clamping voltage) is selected from between several volts, such as 3V and 20V.The evaluation circuit 21 is designed to detect the operating state (switching state) of the level shifter transistor TL 1 and to generate the high-side control signal Shs as a function of the detected switching state of the level shifter transistor TL 1. According to one example, the evaluation circuit 21 is designed to monitor a transistor current IL 1 through the level shifter transistor TL 1 and to generate the high-side control signal Shs as a function of a detected current level of the transistor current IL 1. According to one example, the evaluation circuit 21 is configured to generate the high-side control signal Shs such that the high-side control signal Shs has a first signal level when the monitored current IL 1 indicates that the level shifter transistor TL 1 is in the on state and a second signal level when the monitored current IL 1 indicates that the level shifter transistor TL 1 is in the off state.An example of an evaluation circuit 21 configured to monitor the transistor current IL 1 and to generate the high-side control signal Shs depending on the monitored transistor current IL 1 is illustrated in FIG. 12. In the example illustrated in FIG. 12, the evaluation circuit 21 comprises a resistor 211 which is connected in series with the load path of the level shifter transistor TL 1. A comparator 212 compares a voltage V 211 across the resistor 211 with a reference voltage Vref provided from a reference voltage source 213, and generates the high-side control signal Shs depending on a relationship between the voltage V 211 across the resistor 211 and the reference voltage Vref. According to an example, the comparator 212 generates the high-side control signal Shs to have a first signal level when the voltage V 211 across the resistor 211 is higher than the reference voltage Vref and a second signal level when the voltage V 211 across the resistor 211 is lower than the reference voltage. According to one example, the first signal level is a high signal level and the second signal level is a low signal level.The voltage V 211 across the resistor 211 is given by a resistance value R 211 of the resistor 211 multiplied by a current level of the transistor current IL 1, where R 211 denotes the resistance value of the resistor 211 and IL 1 denotes the current level of the transistor current. Thus, the comparator 212 switches the high-side control signal Shs from the first signal level to the second signal level when the monitored current IL 1 falls below a current threshold IL 1th that depends on the resistance value R 211 and the reference voltage Vref as follows:Equivalently, the comparator switches the high-side control signal Shs from the second signal level to the first signal level when the monitored current IL 1 increases above the current threshold IL 1thaccording to equation (2).FIG. 13 shows a modification of the level shifter 2 according to FIG. 11 In the example illustrated in FIG. 13, the level shifter 2 comprises, in addition to the level shifter transistor TL 1, a further level shifter transistor TL 2 having a load path coupled between the high-side supply node N 13 and the low-side reference node N 11. In the following, the level shifter transistor TL 1 is referred to as a first level shifter transistor and the further level shifter transistor TL 2 is referred to as a second level shifter transistor.Referring to FIG. 13, the first and second level shifter transistors TL 1, TL 2 are each connected in series with the evaluation circuit 21. For the purpose of illustration only, the first and second level shifter transistors TL 1, TL 2 are each implemented as a MOSFET, in particular as an N-type MOSFET. Source nodes S 1, S 2 of the two level shifter transistors are connected to the low-side reference node N 11 and drain nodes D 1, D 2 of the level shifter transistors TL 1, TL 2 are connected to the evaluation circuit 21. Hereinafter, the level shifter transistor TL 1 is referred to as a first level shifter transistor, and the level shifter transistor TL 2 is referred to as a second level shifter transistor. Equivalently, hereinafter, an input signal Sin configured to control the operation state of the first level shifter transistor TL 1 is referred to as a first input signal, and an input signal Sin 2 configured to control the operation state of the second level shifter transistor TL 2 is referred to as a second input signal. The first and second input signals Sin, Sin 2 are each designed to switch the respective level shifter transistor TL 1, TL 2 on or off.The evaluation circuit 21 is designed to detect the operating state of the first and second level shifter transistors TL 1, TL 2 and to generate the high-side control signal Shs as a function of the operating states of the first and second level shifter transistors TL 1, TL 2. According to an example, the first and second level shifter transistors TL1, TL2 are operated in a complementary (differential) manner such that at any time one of the first and second level shifter transistors TL1, TL2 is in the on state and the other of the first and second level shifter transistors TL1, TL2 is in the off state. In this example, the evaluation circuit 21 is designed to generate the signal level of the high-side control signal Shs as a function of which of the first and second level shifter transistors TL 1, TL 2 is in the on state and which of the first and second level shifter transistors TL 1, TL 2 is in the off state.According to an example, active device regions of the first and second level shifter transistors TL 1, TL 2 are integrated in the same device region 130. This is illustrated in FIG. 14, which shows a top view of the device region 130 in which active device regions of the first and second level shifter transistors TL 1, TL 2 are integrated.In the example illustrated in FIG. 14, each of the first and second level shifter transistors is implemented according to the example illustrated in FIG. 8A. However, this is only an example. According to another example (not shown), each of the first and second level shifter transistors is implemented according to the example shown in FIG. 10A.In the example shown in FIG. 14, the individual parts (features) of the first and second level shifter transistors TL 1, TL 2 have the same reference numerals as in the example shown in FIG. 8A, wherein the index "TL 1" has been added to the reference numerals of the first level shifter transistor TL 1 and the index "TL 2" has been added to the reference numerals of the second level shifter transistor TL 2.Referring to FIG. 14, the ring-shaped body regions 33 TL1, 33TL2 of the first and second level shifter transistors TL 1, TL 2 may be adjacent to each other or may be partially merged together such that the body region body regions 33 TL1, 33TL2 form a contiguous doped semiconductor region. The source regions 32 TL1, 32TL2 may be formed by the same doped semiconductor region and may be connected to a common source node that simultaneously forms the source node S 1 of the first level shifter transistor TL 1 and the source node S 2 of the second level shifter transistor TL 2.Note that the level shifter 2 is not limited to be implemented with one or two level shifter transistors. According to another example (not shown), the level shifter 2 comprises at least one further level shifter transistor, the load path of which is coupled between the high-side reference node N 13 and the low-side reference node N 11. The operating state of the further level shifter transistor is controlled by a further input signal. The at least one further level shifter transistor can be used to transmit further information from a control circuit which generates the further input signal to the evaluation circuit, wherein this further information can be transmitted from the evaluation circuit 21 to the high-side driver circuit 4.FIG. 15 illustrates an example of the high-side control circuit 4. in this example, the high-side control circuit 4 includes a control circuit 41 configured to obtain the high-side control signal Shs and a half bridge. The half bridge comprises a first switch 42 connected between the high-side supply node N 13 and the output 14 of the high-side drive circuit 4, and a second switch 43 connected between the output 14 and the high-side reference node N 12. Each of the first and second switches 42, 43 is controlled by the control circuit 41 depending on the high-side control signal Shs.The control circuit 41 is configured to control the operation of the first and second switches 42, 43 in a complementary manner such that only one of the first and second switches 42, 43 is turned on at any time. In order to turn on the high-side switch 7, the control circuit 41 turns on the first switch 42 depending on the high-side control signal Shs so that the drive voltage (gate-source voltage) of the high-side switch 7 is substantially equal to the supply voltage V 51 capable of turning on the high-side switch 7. To turn off the high-side switch 7, the control circuit 41 turns on the second switch 43 so that the driving voltage of the high-side switch 7 is substantially zero, turning off the high-side switch 7.FIG. 16 illustrates an example of the low-side circuit 8 and a driving circuit configured to control the operation of the low-side circuit 8. In the example illustrated in FIG. 16, the low-side circuit 8 includes a low-side switch 81 connected in series with the high-side switch 7. More specifically, a load path of the low-side switch 81 is connected in series with the load path of the high-side switch 7. According to one example, an electronic circuit 82 is connected in parallel with the low-side switch 81. This circuit 82 may be implemented in various ways. According to an example, the electronic circuit 82 includes circuit elements, such as inductors or capacitors, that in combination with the high-side switch 7 and the low-side switch 81 form a power converter, such as a buck converter, a boost converter, or the like.The operation state of the low-side switch 81 is controlled by a low-side driving circuit 9 that is part of the electronic circuit 1. For the purpose of illustration only, the low-side switch 81 of FIG. 16 is a MOSFET, in particular an N-type MOSFET. The low-side switch 81 turns on or off depending on a drive signal Sdrvl generated by the low-side drive circuit 9. The low-side drive circuit 9 is designed to generate the low-side drive signal Sdrvl as a function of a respective input signal Sinl obtained by the low-side drive circuit 9.The low-side driving circuit 9 may be implemented similarly to the high-side driving circuit illustrated in FIG. 15. To generate the low-side drive signal Sdrvl, the low-side drive circuit 9 receives a low-side supply voltage V 52 from a low-side voltage source 52.According to an example illustrated in FIG. 16, the voltage source 51 that provides the supply voltage V 51 to the high-side driving circuit 4 includes a bootstrap circuit that is coupled to the low-side voltage source 52 and that includes a capacitor 511 connected between the high-side supply node N 13 and the high-side reference node N 12. Furthermore, the bootstrap circuit comprises a diode 512 which is connected between the capacitor 511 and the low-side voltage source 52. In this example, the capacitor 511 is charged by the low-side voltage source 52 each time the low-side switch 81 is in the on state. The low-side supply voltage V 52 is referenced to ground, so that the capacitor 511 is charged each time the high-side reference node N 12 is substantially equal to ground GND because the low-side switch 8 is in the on state.FIG. 17 illustrates an example of the tub 120 in detail. The level shifter transistor is not shown in FIG. 17. Referring to FIG. 17, the well 120 includes a bottom portion 121 and sidewall portions 122 extending from the bottom portion 121 to the first surface 101 of the semiconductor body 100 such that the bottom portion 121 and the sidewall portions 122 surround the device region 120 within the semiconductor body 100.Forming a well 120 of the type illustrated in FIG. 17 may include providing a first layer 140 of the semiconductor body 100 and implanting dopant atoms into a surface of the first layer 142 to form the bottom region 121. The first layer 140 may include a semiconductor substrate having a base doping of the base region 110, or may include a substrate and an epitaxial layer formed on the substrate.Forming the well 120 may further include forming a second layer 150 on the first layer 140 of the semiconductor body 100 and forming the sidewall portions 122 in the second layer 150. Forming the sidewall portions 120 may include implanting dopant atoms via the first surface 101 of the semiconductor body 100 into those regions in which the sidewall portions 122 are to be formed.According to another example, the second layer 150 comprises a plurality of sub-layers, wherein after forming each of these sub-layers dopant atoms are implanted into the respective sub-layer to form doped regions. The doped regions in the sublayers together form the sidewall portions 122 of the top side 120.According to another example, which is illustrated in dashed lines in FIG. 17, after forming the second layer 150, trenches are formed in the first surface 101 and the trenches are filled with a material comprising dopant atoms and serving as dopant source. The dopant source is, for example, a silicate glass. The method further includes diffusing dopant atoms from the dopant source into surrounding semiconductor regions to form the doped regions forming the sidewall portions 122. The dopant source may be removed from the trenches after the diffusion process and replaced with a fill material or may remain in the trenches.It should be noted that, in addition to the level shifter 2 with the one or more level shifter transistors TL 1, TL 2, further portions of the electronic circuit 1 may be integrated in the semiconductor body 100. According to an example, the high-side driving circuit 4 is also integrated in the semiconductor body 100. According to a further example, the high-side drive circuit 4 and the low-side drive circuit 9 are integrated in the semiconductor body 100.Some of the examples discussed above are briefly summarized below with reference to numbered examples.Example 1. electronic circuit comprising: a level shifter comprising a level shifter transistor having a load path coupled between a low-side reference node and a high-side supply node of the electronic circuit, wherein the electronic circuit further comprises a semiconductor body comprising a base region of a first doping type, a well of a second doping type complementary to the first doping type, and a device region of the first doping type separated from the base region by the well, wherein the level shifter transistor is at least partially integrated in the device region, and wherein the well is connected to the high-side supply node and the base region is connected to the low-side reference node.Example 2. the electronic circuit of example 1, wherein the level shifter transistor comprises: a drift region of the second doping type; a drain region of the second doping type adjoining the drift region; a body region of the first doping type adjoining the drift region and spaced apart from the drain region; a source region of the second doping type separated from the drift region by the body region; and a gate electrode adjoining the body region and dielectrically insulated from the body region by a gate dielectric.Example 3. The electronic circuit of example 2, wherein the drain region is embedded in the drift region, wherein the body region comprises a first body region portion spaced apart from the drain region in a first lateral direction of the semiconductor body and a second body region portion spaced apart from the drain region in a second lateral direction opposite to the first lateral direction, and wherein the source region comprises a first source region portion arranged in the first body region portion and a second source region portion arranged in the second body region portion.Example 4. the electronic circuit of example 3, wherein the first and second source region portions are spaced apart from each other, and wherein the body region forms a closed loop around the drain region in a horizontal plane of the semiconductor body.Example 5. the electronic circuit of example 4, wherein the body region comprises a third body region portion arranged in a first edge region of the level shifter transistor between the first and second body region portions, wherein the body region comprises a fourth body region portion arranged in a second edge region of the level shifter transistor between the first and second body region portions, and wherein the drift region adjoins both the third and fourth body region portions.Example 6. The electronic circuit of example 4, wherein the body region comprises a third body region portion arranged in a first edge region of the level shifter transistor between the first and second body region portions, wherein the body region comprises a fourth body region portion arranged in a second edge region of the level shifter transistor between the first and second body region portions, and wherein the drift region is spaced apart from the third and / or fourth body region portions.Example 7. the electronic circuit of examples 5 and 6, wherein the gate electrode is arranged on the third and fourth body region portions and is dielectrically insulated from the third and fourth body region portions by a field dielectric.Example 8. the electronic circuit of any of examples 2 to 7, wherein the drift region is separated from the well by the device region.Example 9. The electronic circuit of any of examples 1 to 8, wherein the level shifter transistor is a first level shifter transistor, and wherein the level shifter comprises at least one further level shifter transistor having a load path coupled between the low-side reference node and the high-side supply node of the electronic circuit, and wherein the at least one further level shifter transistor is at least partially integrated in the device region.Example 10. The electronic circuit of any of Examples 1 to 9, wherein the level shifter further comprises: an evaluation circuit connected in series with the level shifter transistor and connected between the level shifter transistor and the high-side supply node.Example 11: The electronic circuit of example 10, wherein the level shifter further comprises: a voltage clamping element connected in parallel with the evaluation circuit.Example 12: Electronic circuit according to Example 10 or 11, wherein the evaluation circuit is at least partially integrated in the semiconductor body.Example 13 The electronic circuit of any of Examples 10 to 12, further comprising: a high-side driver circuit connected to the evaluation circuit and configured to receive a high-side control signal from the evaluation circuit and drive a high-side transistor device depending on the high-side control signal.Example 14. The electronic circuit of example 13, wherein the high-side driver circuit is at least partially integrated in the semiconductor body.Example 15. An integrated circuit comprising: a semiconductor body having a base region of a first doping type, a well of a second doping type complementary to the first doping type, and a device region of the first doping type separated from the base region by the well; and a transistor at least partially integrated in the device region, the transistor comprising: a drift region of the second doping type; a drain region of the second doping type adjoining the drift region; a body region of the first doping type adjoining the drift region and spaced apart from the drain region; a source region of the second doping type separated from the drift region by the body region; and a gate electrode that is adjacent to the body region and is dielectrically insulated from the body region by a gate dielectric, and wherein the body region forms a closed loop around the drain region in a horizontal plane of the semiconductor body, and wherein the drift region is spaced apart from the body region in a first and / or second edge region of the transistor.Example 16. The integrated circuit of example 15, wherein a doped region of the first doping type is arranged in the first and / or second edge region of the transistor between the drift region and the body region.Example 17. the integrated circuit of example 16, wherein a doping concentration of the doped region of the first doping type is different from the doping concentration of the body region.Example 18. The integrated circuit of example 17, wherein a doping concentration of the doped region of the first doping type is lower than the doping concentration of the body region.Example 19. The integrated circuit of example 15, wherein a portion of the device region is disposed in the first and / or second edge region of the transistor between the drift region and the body region.Example 20. The integrated circuit of example 15, wherein a doped region of the second doping type having a doping concentration equal to or lower than the doping concentration of the drift region is arranged in the first and / or second edge region of the transistor between the drift region and the body region.Example 21: The integrated circuit according to any one of examples 15 to 20, wherein the body region comprises a first body region portion spaced apart from the drain region in a first lateral direction of the semiconductor body and a second body region portion spaced apart from the drain region in a second lateral direction opposite to the first lateral direction, and wherein the source region comprises a first source region portion arranged in the first body region portion and a second source region portion arranged in the second body region portion, wherein the body region further comprises a third body region portion arranged in the first edge region of the transistor between the first and the second body region portions, and wherein the body region comprises a fourth body region portion arranged in a second edge region of the transistor between the first and the second body region portions.Example 22. the electronic circuit of any of Examples 15 to 21, wherein the drift region is separated from the well by the device region.Example 23. An electronic circuit comprising the integrated circuit of any of Examples 15 to 22; and a level shifter comprising a level shifter transistor formed by the transistor of the integrated circuit and having a load path coupled between a low-side reference node and a high-side supply node of the electronic circuit, wherein the well of the integrated circuit is connected to the high-side supply node and the base region of the integrated circuit is connected to the low-side reference node.

Claims

An electronic circuit comprising: a level shifter (2) comprising a level shifter transistor (TL1) having a load path coupled between a low side reference node (N11) and a high side supply node (N13) of the electronic circuit (1), the electronic circuit further comprising a semiconductor body (100) comprising a base region (110) of a first doping type, a well (120) of a second doping type complementary to the first doping type, and a device region (130) of the first doping type separated from the base region (110) by the well (120), wherein the level shifter transistor (TL1) is at least partially integrated in the device region (130), and wherein the well (120) is connected to the high side supply node (N13) and the base region (110) is connected to the low side reference node (N11).The electronic circuit of claim 1, wherein the level shifter transistor (TL1) comprises: a drift region (31) of the second doping type; a drain region (34) of the second doping type adjoining the drift region (31); a body region (33) of the first doping type adjoining the drift region (31) and spaced apart from the drain region (34); a source region (32) of the second doping type separated from the drift region (31) by the body region (33); and a gate electrode (35) adjoining the body region (33) and dielectrically insulated from the body region (33) by a gate dielectric (36).The electronic circuit of claim 2, wherein the drain region (34) is embedded in the drift region (31), wherein the body region (33) comprises a first body region portion (33 1), spaced apart from the drain region (34) in a first lateral direction of the semiconductor body (100), and a second body region portion (33 2), spaced apart from the drain region (34) in a second lateral direction opposite to the first lateral direction, and wherein the source region (32) comprises a first source region portion (32 1), arranged in the first body region portion (33 1) and a second source region portion (32 2), arranged in the second body region portion (33 2).The electronic circuit of claim 3, wherein the first and second source region portions (32 are spaced apart in 1, 322) from each other, and wherein the body region (33) forms a closed loop around the drain region (34) in a horizontal plane of the semiconductor body (100).Electronic circuit according to claim 4, wherein the body region (33) comprises a third body region portion (33 3) arranged in a first edge region (ER1) of the level shifter transistor (TL1) between the first and second body region portions (33 1, 332) wherein the body region (33) comprises a fourth body region portion (33 4) arranged in a second edge region (ER2) of the level shifter transistor (TL1) between the first and second body region portions (33 1, 332), and wherein the drift region (21) adjoins both the third and the fourth body region portion (33 3, 334).Electronic circuit according to claim 4, wherein the body region (33) comprises a third body region portion (33 3) arranged in a first edge region (ER1) of the level shifter transistor (TL1) between the first and second body region portions (33 1, 332) wherein the body region (33) comprises a fourth body region portion (33 4) arranged in a second edge region (ER2) of the level shifter transistor (TL1) between the first and second body region portions (33 1, 332), and wherein the drift region (21) is spaced apart from the third and / or the fourth body region portion (33 in 3, 334).The electronic circuit of any of claims 2 to 6, wherein the drift region (21) is separated from the well (120) by the device region (130).The electronic circuit of any of the preceding claims, wherein the level shifter transistor (TL1) is a first level shifter transistor, and wherein the level shifter (2) comprises at least one further level shifter transistor (TL2) having a load path coupled between the low-side reference node (N11) and the high-side supply node (N13) of the electronic circuit (1), and wherein the at least one further level shifter transistor (TL2) is at least partially integrated in the device region (130).Electronic circuit according to one of the preceding claims, wherein the level shifter (2) further comprises: an evaluation circuit which is connected in series with the level shifter transistor (TL1) and is connected between the level shifter transistor (TL1) and the high-side supply node (N13).Electronic circuit according to Claim 9, wherein the level shifter (2) furthermore has: a voltage clamping element (22) which is connected in parallel with the evaluation circuit.Electronic circuit according to one of Claims 9 to 10, which furthermore has: a high-side drive circuit (4) which is connected to the evaluation circuit (21) and is designed to receive a high-side control signal (Shs) from the evaluation circuit (21) and to drive a high-side transistor component (7) on the basis of the high-side control signal (Shs).An integrated circuit comprising: a semiconductor body (100) having a base region (110) of a first doping type, a well (120) of a second doping type complementary to the first doping type, and a device region (130) of the first doping type separated from the base region (110) by the well (120); and a transistor (TL1) at least partially integrated in the device region (130), wherein the transistor (TL1) comprises: a drift region (31) of the second doping type; a drain region (34) of the second doping type adjoining the drift region (31); a body region (33) of the first doping type adjoining the drift region (31) and spaced apart from the drain region (34); a source region (32) of the second doping type separated from the drift region (31) by the body region (33); and a gate electrode adjacent to the body region (33) and dielectrically insulated from the body region (33) by a gate dielectric (36), and wherein the body region (33) forms a closed loop around the drain region (34) in a horizontal plane of the semiconductor body (100), and wherein the drift region (21) is spaced apart from the body region (33) in a first and / or second edge region (ER1, ER2) of the transistor (TL1).The integrated circuit of claim 12, wherein the device region (130) is arranged in the first and / or second edge region (ER1, ER2) of the transistor (TL1) between the drift region (21) and the body region (33).Integrated circuit according to claim 12, wherein a doped region of the second doping type having a doping concentration equal to or lower than the doping concentration of the drift region (21) is arranged in the first and / or second edge region (ER1, ER2) of the transistor (TL1) between the drift region (21) and the body region (33).The integrated circuit according to claim 12, wherein a doped region of the second doping type having a doping concentration different from the doping concentration of the body region (33) is arranged in the first and / or second edge region (ER1, ER2) of the transistor (TL1) between the drift region (21) and the body region (33).The integrated circuit according to any of claims 12 to 15, wherein the body region (33) comprises a first body region portion (33 1), spaced apart from the drain region (34) in a first lateral direction of the semiconductor body (100), and a second body region portion (33 2), spaced apart from the drain region (34) in a second lateral direction opposite to the first lateral direction, and wherein the source region (32) comprises a first source region portion (32 1), arranged in the first body region portion (33 1) and a second source region portion (32 2), arranged in the second body region portion (33 2), wherein the body region (33) further comprises a third body region portion (33 3) arranged in the first edge region (ER1) of the transistor (TL1) between the first and the second body region portion (33 1, 332) and wherein the body region (33) comprises a fourth body region portion (33 4) arranged in a second edge region (ER2) of the transistor (TL1) between the first and the second body region portion (33 1, 332).

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