STRIP CELLS IN SEMICONDUCTOR MEMORY COMPONENTS

Abstract

A memory device includes a first memory array disposed over a substrate, a second memory array disposed over the substrate and separated from the first memory array along a first direction, and a stripe cell defined in the substrate and located between the first memory array and the second memory array. The stripe cell includes a first boundary adjacent to the first memory array, a second boundary adjacent to the second memory array, a p-well stripe located between the first boundary and the second boundary along the first direction, and an n-well stripe spaced from the p-well stripe along the second direction. The first boundary and the second boundary extend along a second direction perpendicular to the first direction. The p-well stripe is coupled to a first power supply voltage, and the n-well stripe is coupled to a second power supply voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to and benefit from U.S. Provisional Patent Application No. 63 / 616,932, filed January 2, 2024, entitled "Memory Devices with Tap Cells," which is incorporated by reference into this application. BACKGROUND

[0002] With the advancement of integrated circuit (IC) technologies to smaller technology nodes, memory or data storage cells, such as static random access memory (SRAM) cells, often incorporate transition cells, such as stripe cells and filler cells, into their designs to improve device performance, where each memory cell can store one bit of data. In one such example, stripe cells were implemented to stabilize a well potential, thereby facilitating uniform charge distribution across the memory cells and achieving uniform performance within an array of memory cells. While existing designs of stripe cells and filler cells have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 illustrates a top view of an example block diagram of a memory block in accordance with some embodiments. Fig. 2 illustrates an example layout design according to the example block diagram of Fig. 1 in accordance with some embodiments. Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E, Fig. 4A, Fig. 4B, Fig. 4C, Fig. 4D, Fig. 5, Fig. 6A, Fig. 6B, Fig. 6C, Fig. 7, Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 14, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 16, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B, Fig. 23C and Fig. 24 each illustrate a top view of an example block diagram of a memory device that includes the memory block of Fig. 1 and / or 2, in accordance with some embodiments. Fig. 25 illustrates a flow diagram of a method of manufacturing a semiconductor device in accordance with some embodiments. Fig. 26 illustrates a block diagram of a system for generating an IC layout design in accordance with some embodiments. Fig. 27 illustrates a block diagram of an IC manufacturing system and an associated IC manufacturing flow in accordance with some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "underlying," "beneath," "under," "overlying," "upper," "above," "below," and the like may be used herein for ease of description to describe the relationship of one element or structural element to another element(s) or structural element(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0006] The terms "couple" and "connect," as used herein, refer to an electrical or other operative connection between two components, with or without any intervening layers or components formed therebetween. Therefore, unless explicitly stated, the terms "coupled," "connected," "electrically coupled," and "operatively coupled" are used interchangeably in the present disclosure.

[0007] Over the past several technology generations (or nodes), the size of transistors has been progressively reduced to provide improvements in power, performance, and area density (PPA). Along with this trend, design-technology co-optimization (TDCO) combined with intrinsic scaling has been adopted to achieve the desired logic density and die cost / area reduction. As its name suggests, DTCO refers to optimizing design and process technology while improving power, power efficiency, transistor density, and cost. With DTCO, the result is a solid 1.7x increase in logic density and a substantial 35-40% per generation of size reduction for the same design, even when excluding the "less scalable" areas of the chip, such as analog and I / O.

[0008] DTCO for a new technology node typically involves significant architectural innovation rather than offering the exact same architecture as the previous generation, only smaller. As technology nodes continue to shrink, the contribution of DTCO can become increasingly significant. For example, the technology impacts static random access memory (SRAM) design considerations such as manufacturability, reliability, performance, operating power, and area. Scaling SRAM is one of the most fundamental and challenging issues. SRAM loss, operating power, and density are of paramount importance and often pose conflicting requirements.

[0009] With cell arrays implemented in advanced technology nodes, it has become challenging to further reduce the area of memory cell arrays to a significant extent (e.g., more than 5%). Transition cells, such as stripe cells, edge cells, and / or filler cells, have been incorporated into memory devices to improve the performance of cell arrays and / or maintain device dimensions to comply with Design Rule Check (DRC) guidelines. The present disclosure provides various memory device structures including such transition cells at the periphery of memory cell arrays for improved scalability (e.g., increased chip density) of the memory devices.

[0010] Fig. 1 illustrates an example block diagram of a semiconductor memory block 10 (hereinafter referred to as a memory block 10) in accordance with various embodiments. In some embodiments, the memory block 10 is incorporated as a portion of a semiconductor memory device or macro (e.g., semiconductor memory device 100 provided herein). In the present embodiments, the memory block 10 is formed over a substrate (e.g., substrate 12) and includes at least one memory array 18 and a plurality of transition cells (or peripheral cells) adjacent to or surrounding the memory array 18.

[0011] The memory block 10 may be included in a microprocessor, a memory cell and / or another IC device. In some embodiments, the memory block 10 is a portion of an IC chip, a system on a chip (SoC), or a portion thereof that includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS), bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0012] The memory array 18 is a hardware component that stores data. In one aspect, the memory array 18 is configured as a semiconductor memory device. The memory array 18 includes a plurality of memory cells (or data storage units) 11. The memory array 18 includes a number of rows R1, R2, R3...R M , each extending in a first direction (e.g. X-direction), and a number of columns C1, C2, C3...C Nthat extend in a second direction (e.g., Y-direction). Each of the rows / columns may include one or more conductive structures. In some embodiments, each memory cell 11 is arranged at the intersection of a corresponding row and a corresponding column and may be operated according to voltages or currents through the respective conductive structures of the column and row. In the present embodiments, the memory array 18 extends a width W1 along the first direction and a height H along the second direction. The width W1 is defined between a first boundary B1 and a second boundary B2, each extending along the second direction.

[0013] In the present embodiments, the memory cells 11 are configured as SRAM cells, although the present disclosure is also applicable to other types of circuits. In addition, for purposes of discussion, the memory cells 11 are each configured to include one or more transistors, such as fin field-effect transistors (FinFETs). However, in some examples, the memory cells 11 may additionally or alternatively include other types of FETs, such as nanolayer FETs, nanowire FETs, gate-all-around FETs (GAA-FETs), complementary FETs (CFETs), or the like.

[0014] The transition cells, comprising a first stripe cell 17, a second stripe cell 19, and an edge cell 21, are aligned with the memory array 18 along the first direction. The first stripe cell 17 and the second stripe cell 19 are generally arranged along boundaries of the memory block 10 and are therefore alternatively referred to as boundary stripe cells 17 and 19, respectively. Unlike the memory array 18, which includes active transistors that participate in storing data for the memory device, the transition cells of the memory block 10 occupy dummy areas of the substrate that separate the memory array 18 from peripheral circuitry of a memory device (or macro; such as semiconductor memory device 100 described above).In the present embodiments, the first stripe cell 17 abuts the memory array 18 along the first boundary B1, while the second stripe cell 19 abuts the memory array 18 along the second boundary B2, such that the memory array 18 lies between the first stripe cell 17 and the second stripe cell 19. Furthermore, the edge cell 21 abuts the first stripe cell 17 along a boundary of the first stripe cell 17. In some embodiments, the edge cell 21 does not include front-end device features, such as the fins 20-26, the epitaxial source / drain features 40A-40D, the gate structures 30A-30C, or the like.

[0015] In some embodiments, the transition cells are configured to improve the performance of the memory array 18 and / or the peripheral circuitry of the memory device. For example, one or both of the first stripe cell 17 and the second stripe cell 19 include well stripes (e.g., an n-well stripe and a p-well stripe) configured to provide protection against latch-up forming in the circuitry of the memory array 18. In general, latch-up refers to an inadvertently induced short circuit between a first power supply line carrying a first power supply voltage (e.g., a power supply voltage V DD ), and a second power supply line providing a second power supply voltage (e.g. a power supply voltage V SS). By coupling a potential well (e.g., a p-well for n-FETs or NFETs and an n-well for p-FETs or PFETs) of some of the FETs in the memory array 18 to a corresponding power supply rail using a well strip, the latch-up phenomenon associated with the FETs can be mitigated.

[0016] For example, an n-well stripe (or an n-well tap, NTAP; e.g. an n-well stripe 17A of Fig. 2) to couple an n-well provided in the first stripe cell 17 to the first power supply voltage can help reduce latch-up of p-FETs (PFETs) in the memory array 18. Similarly, a p-well stripe (or a p-well plug, PTAP; e.g., a p-well stripe 17B of Fig. 2) to couple a p-well provided in the first stripe cell 18 to the second power supply voltage, helping to reduce latch-up of n-FETs (NFETs) in the memory array 18. In some embodiments, each of the first stripe cell 17 and the second stripe cell 19 further comprises a plurality of dummy FETs (as opposed to active transistors in the memory array 18) configured to stabilize well potential near the first boundary B1 and the second boundary B2, which may help to facilitate uniform charge distribution across the memory array 18 (e.g., between edge memory cells and inner memory cells) and thereby achieve uniform performance among the memory cells 11 of the memory array. In some embodiments, only one of the first stripe cell 17 and the second stripe cell 19 comprises the n-well stripes and the p-well stripes, i.e.is coupled to the first power supply voltage and the second power supply voltage. For example, in the illustrated embodiments, only the first stripe cell 17 is electrically coupled to the first supply voltage and the second supply voltage via the n-well stripes and the p-well stripes, respectively, and the second stripe cell 19 is electrically isolated from the first supply voltage and the second supply voltage.

[0017] In some embodiments, the transition cells are configured to maintain a certain width-to-height ratio of the memory block 10 according to DRC constraints for a given memory device. For example, the edge cell 21 is generally arranged at an outer edge of the memory device along the second direction and configured with a dimension (e.g., a width along the first direction) to ensure a consistent width-to-height ratio of the memory block 10 according to DRC constraints at a given technology node. The edge cell 21 generally does not include any active or dummy devices (e.g., FETs), but may include a doped region, such as the n-doped region 14B. In some embodiments, dimensions (e.g.,Widths along the first direction) of one or both of the first stripe cell 17 and the second stripe cell 19 are also configured to maintain a given width-to-height ratio for the memory block 10 in accordance with certain DRC constraints.

[0018] As depicted herein, nor in relation to Fig. 1, the memory block 10 extends by a width W along the first direction (e.g., X-direction), which includes a width W1 of the memory array 19, a width W2 of the first stripe cell 17, a width W3 of the second stripe cell 19, and width W4 of the edge cell 21. In the present embodiments, the width W1 is greater than each of the widths W2, W3, and W4, and the width W4 is less than each of the widths W1, W2, and W3. For embodiments in which the first stripe cell 17 includes the n-well stripes and the p-well stripes, and the second stripe cell 19 is free of any of the n-well stripes and the p-well stripes, the width W2 is greater than the width W3. Using center-poly pitch (CPP) as a unit of measurement, the widths W1, W2, W3, and W4 can each be measured as a multiple of CPPs. For example, width W2 can be 10 CPP, width W3 can be 4 CPP, and width W4 can be 1.5 CPP.

[0019] While DTCO techniques exist to improve the manufacturability, reliability, performance, operating capacity, and storage area of (e.g., SRAM) devices, they have generally been adequate but have not been entirely satisfactory in all aspects. The present disclosure provides various embodiments directed to structures and arrangement of the transition cells in the periphery of the memory array 18 for improved scalability of the memory devices. In various embodiments, the present disclosure contemplates placement of two adjacent memory blocks 10, as well as memory devices incorporating such memory blocks 10, to combine one or more of the first stripe cell 17, the second stripe cell 19, and the edge cell 21 between the memory blocks 10, resulting in a reduction in the width (e.g., the width W) of the memory blocks 10 for improved scalability.

[0020] Fig. Figure 2 illustrates an example layout of the memory block 10, in part or in whole, according to various embodiments of the present disclosure. The components of the memory block 10 are arranged in a configuration substantially similar to that shown in Fig. 1. For example, the edge cell 21, the first stripe cell 17, the memory array 18, and the second stripe cell 19 are arranged along the first direction and disposed over a substrate 12. The substrate 12 may include any suitable semiconductor material, such as an elemental semiconductor (e.g., silicon and / or germanium), a compound semiconductor (e.g., silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (e.g., SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP). Alternatively, the substrate 12 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate 12 comprises a p-type dopant, such as boron (e.g., BF2), indium, other p-type dopants, or combinations thereof, and is therefore considered a p-type substrate.

[0021] In the present embodiments, the substrate 12 includes various doped regions configured according to the design requirements of memory block 10. In the depicted embodiment, the substrate 12 includes a plurality of n-doped regions 14A and 14B, collectively referred to as n-doped regions 14 (also referred to as n-wells 14), and a p-doped region 16 (also referred to as a p-well 16). In the depicted embodiment, the n-doped regions 14A extend across the first stripe cell 17, the memory array 18, and the second stripe cell 19, respectively, while the n-doped region 14B is disposed (or defined) within the edge cell 21. In some embodiments, the p-doped region 16 surrounds the n-doped regions 14.N-doped regions 14 are configured for a plurality of p-type metal-oxide-semiconductor FinFETs (PMOS FinFETs) 18A, such as pull-up FinFETs (PU FinFETs), and doped p-type region 16 is defined for a plurality of n-MOS FinFETs (NMOS FinFETs) 18B, such as pull-down FinFETs (PD FinFETs), so that the memory array 18 comprises a plurality of CMOS FinFETs. The PMOS FinFETs 18A and the NMOS FinFETs 18B are spaced apart from each other along the second direction.

[0022] N-doped regions, such as n-doped region 14, are doped with n-type dopants such as phosphorus, arsenic, another n-type dopant, or combinations thereof. P-doped regions, such as doped p-type region 16, are doped with p-type dopants such as boron (e.g., BF2), indium, another p-type dopant, or combinations thereof. In some embodiments, substrate 12 includes doped regions formed with a combination of p-type dopants and n-type dopants. The various doped regions may be formed directly on and / or within substrate 12, providing, for example, a p-well structure, an n-well structure, a double-well structure, a raised structure, or combinations thereof. An ion implantation process, a diffusion process, and / or another suitable doping process may be performed to form the various doped regions.

[0023] In the depicted embodiment, the n-well stripe 17A is disposed over (and electrically coupled to) each of the n-doped regions 14A. The n-well stripe 17A is configured to electrically connect each of the n-doped regions 14A to the first power supply voltage, such as a power supply voltage V DD , to couple. The p-well stripe 17B is arranged over (and electrically coupled to) the p-doped region 16. The p-well stripe 17B is configured to electrically couple the p-doped region 16 to a second power supply voltage, such as power supply voltage V SS , to couple. In some embodiments, the power supply voltage V DD a positive power supply voltage and the power supply voltage V SS is an electrical mass.

[0024] Memory block 10 includes various fins disposed over substrate 12, such as fins 20, 22, 24, and 26 disposed over substrate 12. Fins 20-26 each extend longitudinally along the first direction (e.g., X-direction) over at least a portion of memory block 10 and are spaced apart from each other (e.g., parallel to each other) along the second direction (e.g., Y-direction). In some embodiments, the PMOS FinFETs 18A have fins 20 over (and electrically coupled to) the n-doped regions 14A, the NMOS FinFETs 18B have fins 22 over (and electrically coupled to) the p-doped region 16, the n-well stripes 17A each have a fin 24 over (and electrically coupled to) the n-doped region 14A, and the p-well stripe 19B has a fin 26 over (and electrically coupled to) the p-doped region 16.The present disclosure contemplates embodiments where the PMOS FinFET 18A, the NMOS FinFET 18B, the n-well stripe 17A, and / or the p-well stripe 17B each have more or fewer fins. In some embodiments, to improve performance of memory block 10, a dopant concentration of the FinFET fins, i.e., fins 20 and 22, is lower than a dopant concentration of the well stripe fins, i.e., fins 24 and 26.

[0025] Although not shown, isolation features are formed over and / or within substrate 12 to isolate various regions, such as various device regions, of memory block 10. For example, the isolation features separate and isolate active device regions and / or passive device regions from each other, such as PMOS FinFET 18A, NMOS FinFET 18B, n-well stripe 17A, and p-well stripe 17B. The isolation features further separate and isolate fins, such as fins 20-26, from each other. In some embodiments, the isolation features surround a bottom portion of each of fins 20-26. The isolation features may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof.The isolation structure elements can have different structures, such as trench isolation structures (STI structures, Shallow Trench Isolation Structures), deep trench isolation structures (DTI structures, Deep Trench Isolation Structures) and / or local oxidation of silicon structures (LOCOS structures, Local Oxidation of Silicon Structures).

[0026] In the depicted embodiment, the first stripe cell 17 includes a plurality of PMOS dummy FETs 58A and a plurality of NMOS dummy FETs 58B. The PMOS dummy FETs 58A have end portions of the fins 20 above (and electrically coupled to) the n-doped regions 14A. The NMOS dummy FETs 58B have end portions of the fins 22 above (and electrically coupled to) the p-doped region 16. Consequently, the PMOS dummy FETs 58A are disposed between the n-well stripe 17A and the memory array 18 (including the PMOS FinFETs 18A), and the NMOS dummy FETs 58B are disposed between the p-well stripe 17B and the memory array 18 (including the NMOS FinFETs 18B). As previously described, the PMOS dummy FETs 59A and the NMOS dummy FETs 58B may be configured to stabilize a well potential near the first boundary B1, which may help facilitate uniform charge distribution across the memory array 18.Similarly, the second stripe cell 19 may also include PMOS dummy FETs 58C and NMOS dummy FETs 58D. In some embodiments, each PMOS dummy FET 58A and 58C has a gate terminal (e.g., provided by gate structures 30B and 30C, respectively) electrically connected to a power supply voltage (e.g., the first power supply voltage V. DD ) instead of a signal voltage. Similarly, each NMOS dummy FET 58B and 58D has a gate terminal that is electrically connected to a power supply voltage (e.g., the second power supply voltage V SS ) instead of a signal voltage.

[0027] The fins 20-26 each have at least one channel region, at least one source region, and at least one drain region defined longitudinally along the first direction, where a channel region is disposed between the source region and the drain region (generally referred to as source / drain regions). Channel regions have a cap portion defined between sidewall portions where the cap portion and the sidewall portions engage with a gate structure so that current can flow between the source / drain regions during operation. The source / drain regions may also have cap portions defined between sidewall portions. The fins 20 of the PMOS FinFETs 18A are aligned substantially parallel to each other, and the fins 22 of the NMOS FinFETs 18B are aligned substantially parallel to each other.

[0028] Various gate structures 30A, 30B, and 30C, collectively referred to as gate structures 30, are disposed over fins 22-26, where each gate structure 30 extends along the second direction, i.e., perpendicular to each of fins 22-26. In the depicted embodiment, gate structures 30A are each disposed over and intersect with the respective channel regions of fins 20 and 22 in memory array 18; gate structures 30B are each disposed over and intersect with the respective channel regions of fins 20-26 in first stripe cell 17; and gate structures 30C are each disposed over and intersect with the respective channel regions of fins 20 and 22 in second stripe cell 19.In some embodiments, gate structures 30A-30C each wrap around respective channel regions of fins 20-26, thereby interposing them between respective source / drain regions of fins 20-26 and allowing current to flow between them.

[0029] In some embodiments, gate structures 30A are active gate structures, whereas gate structures 30B and 30C are dummy gate structures. "Active gate structure" generally refers to an electrically functional gate structure, whereas "dummy gate structure" generally refers to an electrically non-functional gate structure. In some embodiments, a dummy gate structure mimics physical properties of an active gate structure, such as physical dimensions of the active gate structure, but is electrically inoperative in memory block 10 (in other words, does not allow current to flow between source / drain regions).In some embodiments, the gate structures 30B and 30C enable a substantially uniform processing environment, for example, enabling uniform epitaxial material growth in source / drain regions of the fins 20-26 (e.g., when forming epitaxial source / drain features), uniform etch rates in source / drain regions of the fins 20-26 (e.g., when forming source / drain recesses), and / or uniform, substantially planar surfaces (e.g., by reducing (or preventing) processing-induced (e.g., chemical mechanical polishing, or CMP-induced) dishing effects).

[0030] Epitaxial source features and epitaxial drain features, collectively referred to as epitaxial source / drain features, are disposed over the source / drain regions of fins 20-26. For example, semiconductor material is epitaxially grown on fins 20-26, forming epitaxial source / drain features 40A, 40B, 40C, and 40D, respectively. In the depicted embodiment, a fin recession process (e.g., an etch-back process) is performed in source / drain regions of fins 20-26 such that epitaxial source / drain features 40A-40D are grown from lower active fin regions of fins 20-26. In some embodiments, source / drain regions of fins 20-26 are not subjected to a fin recessing process, such that epitaxial source / drain features 40A-40D are grown from and wrap around at least a portion of upper active fin regions of fins 20-26.Continuing with the depicted embodiment, the epitaxial source / drain features 40A-40D extend (or grow) laterally along the first direction (in some embodiments substantially perpendicular to the fins 20-26) such that the epitaxial source / drain features 40A-40D are merged epitaxial source / drain features spanning more than one fin.

[0031] An epitaxial process may implement CVD deposition techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the fins 20-26. The epitaxial source / drain structure elements 40A-40D are doped with n-type dopants and / or p-type dopants.In the depicted embodiment, the epitaxial source / drain features 40A comprise a p-doped epitaxial material and form the PMOS FinFETs 18A, the epitaxial source / drain features 40B comprise an n-doped epitaxial material and form the NMOS FinFETs 18B, the epitaxial source / drain features 40C comprise an n-doped epitaxial material; and the epitaxial source / drain features 40D comprise a p-doped epitaxial material. As a result, the n-well stripe 17A and the NMOS FinFET 18B contain dopants of the same conductivity, the p-well stripe 17B and the PMOS FinFET 18A contain dopants of the same conductivity, and the n-well stripe 17A and the p-well stripe 17B contain dopants of different (or opposite) conductivities.

[0032] For example, for the PMOS FinFET 18A and the p-well stripe 17B, the epitaxial source / drain features 40A and 40D are epitaxial layers containing silicon and / or germanium, where the silicon-germanium-containing epitaxial layers are doped with boron, carbon, another p-dopant, or combinations thereof (e.g., forming a Si:Ge:B epitaxial layer or a Si:Ge:C epitaxial layer). Continuing the example, for the NMOS FinFET 18B and the n-well stripe 17A, the epitaxial source / drain features 40B and 40C are epitaxial layers containing silicon and / or carbon, where silicon-containing epitaxial layers or silicon-carbon-containing epitaxial layers are doped with phosphorus, arsenic, another n-dopant, or combinations thereof (e.g., forming a Si:P epitaxial layer, a Si:C epitaxial layer, or a Si:C:P epitaxial layer).

[0033] In some embodiments, the epitaxial source / drain features 40A-40D include materials and / or dopants that achieve a desired tensile strength and / or compressive strength in the channel region. In some embodiments, the epitaxial source / drain features 40A-40D are doped during deposition by adding impurities to a source material of the epitaxial process. In some embodiments, the epitaxial source / drain features 40A-40D are doped by an ion implantation process following a deposition process. In some embodiments, annealing processes are performed to activate dopants in epitaxial source / drain features 40A-40D and / or other source / drain regions in the memory block 10. In some embodiments, silicide layers are formed on epitaxial source / drain features 40A-40D by any suitable method.In some embodiments, the silicide layers include nickel silicide, titanium silicide, or cobalt silicide. In some embodiments, the silicide layers and epitaxial source / drain structures 40A-40D are collectively referred to as the epitaxial source / drain structures.

[0034] A multilayer interconnect (MLI) structure element comprising a combination of dielectric layers and electrically conductive layers (e.g., metal layers) configured to form various interconnect structures is disposed over the substrate 12, partially or completely covering the components of the memory block 10. The MLI structure element electrically couples various devices (for example, the PMOS FinFET 18A, the NMOS FinFET 18B, the n-well stripe 17A, the p-well stripe 17B, transistors, resistors, capacitors, and / or inductors) and / or components (for example, the gate structures 30A-30C) and / or source / drain structures (for example, epitaxial source / drain structures 40A-40D) so that the various devices and / or components can operate as specified by design requirements of the memory block 10.The conductive layers are configured to form vertical interconnect features, such as device-level contacts and / or vias, and / or horizontal interconnect features, such as conductive lines. Vertical interconnect features typically connect horizontal interconnect features in different layers (or different levels) from the MLI feature. During operation of the memory block 10, the interconnect features are configured to route signals between the devices and / or components of memory block 10 and / or to distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to the devices and / or components of memory block 10.

[0035] In order to map the various well stripes defined in the substrate 12, the components of the MLI structure element of the memory block 10 are largely Fig. 2 with the exception of vias 50, 52, 54, and 56. The vias 50-56 are disposed in one or more interlayer dielectric (ILD) layers (not shown) to form interconnect structures. In some embodiments, the vias 50-56 electrically and / or physically couple conductive features of the MLI feature as well as underlying device-level features (e.g., the gate structures 30A-30C and / or the epitaxial source / drain features 40A-40D). In the depicted embodiment, the vias 50 and 52 are each disposed on the device-level contacts (not shown) associated with the epitaxial source / drain features 40B (i.e.,the NMOS FinFETs 18B) are coupled such that, for example, the vias 50 and 52 physically (or directly) connect the device-level contacts (for example, gate contacts and source / drain contacts) to conductive lines (not shown) subsequently formed over the vias 50 and 52, respectively.

[0036] In the present embodiments, the vias 50 and 52 each electrically couple the epitaxial source / drain features 40B of the NMOS FinFETs 18B to a conductive line electrically connected to the second power supply voltage V SS In some embodiments, the power supply voltage V SSas ground and / or a negative supply voltage. Although not shown, the memory block 10 may include a plurality of additional vias electrically coupled to the device-level features (or contacts). For example, the memory block 10 may include vias electrically coupled to gate contacts of the gate structures 30A and / or to source / drain contacts of the epitaxial source / drain features 40A. In the present embodiments, the vias 54 electrically couple the epitaxial source / drain features 40C of the n-well stripe 17A to a conductive line (not shown) electrically coupled to the first power supply voltage V DDFurthermore, the vias 56 electrically couple the epitaxial source / drain structure element 40D of the p-well stripe 17B to a conductive line (not shown) electrically connected to the second power supply voltage V SS is connected.

[0037] The vias 50-56 contain any suitable electrically conductive material, such as Ta, Ti, Al, Cu, Co, W, TiN, TaN, other suitable conductive materials, or combinations thereof. Various conductive materials may be combined to provide the vias 50-56, such as a barrier layer, an adhesion layer, a liner layer, a bulk layer, another suitable layer, or combinations thereof. The vias 50-56 may be formed by any suitable method, such as patterning the respective ILD layers by lithography processes and / or etching processes to form openings (trenches) substantially filled with one or more conductive materials. The conductive material(s) may be deposited by PVD, CVD, ALD, electroplating, electroless plating, another suitable deposition process, or combinations thereof.Thereafter, any excess conductive material(s) may be removed by a planarization process, such as a CMP process, thereby planarizing top surfaces of ILD layers and the vias 50-56.

[0038] In some embodiments, the memory block 10 further includes a plurality of horizontal isolation structures 28 and vertical isolation structures 29, each extending at least across the first stripe cell 17, the memory array 18, and the second stripe cell 19. The horizontal isolation structures 28 and the vertical isolation structures 29 may each include a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. In some embodiments, two adjacent horizontal isolation structures 28 define half a height of the memory cell 11 (e.g., corresponding to an inverter), and two adjacent vertical isolation structures 29 define a width of each memory cell 11. For example, in the depicted embodiment, the width of each memory cell 11 defined by two adjacent vertical isolation structures 29 is equal to 2 CPP.

[0039] The present disclosure contemplates various embodiments directed to structures and arrangement of one or more transition cells (e.g., first stripe cell 17, second stripe cell 19, and / or edge cell 21) in the periphery of a memory array (e.g., memory array 18) of a memory device to improve the scalability of the memory devices. In various embodiments, the present disclosure contemplates placement of two adjacent memory blocks (e.g., memory block 10), as well as memory devices including such memory blocks, for reducing the width of two merged memory blocks (or devices) for improved scalability.For example, in existing implementations, multiple memory blocks 10 are arranged by abutting the edge cell 21 of a first memory block 10 against the edge cell 21 of a second memory block 10 such that the two edge cells 21 are positioned side by side along the first direction (e.g., X direction). As a result, a total width of the two adjacent memory blocks 10 is equal to 2*W, where the width W is the sum of the widths W2, W3, and W4, as shown in . Fig. 1 and Fig. 2. In the present embodiments, at least one of the transition cells described herein may be merged to reduce the width W of each memory block 10, resulting in a more compact layout design toward greater scalability.

[0040] In some embodiments, with respect to Fig. 3A-3C together, a first memory block 10A and a second memory block 10B, each equivalent to the first memory block 10 described herein, are interconnected (or coupled, merged, etc.) by placing two (e.g., first and second) edge cells 21 in a side-by-side configuration along the first direction and uniting (merging) the interconnected edge cells 21 and their respective adjacent (e.g., first and second) first stripe cells 17. The resulting interconnected memory block 10C includes a third stripe cell 60 located between the two (e.g., first and second) memory arrays 18, where the third stripe cell 60 has a width W5 spanning an area defined by a first boundary B3 and a second boundary B4, each extending along the second direction.As a result, the first boundary B3 abuts the memory array 18 of the first memory block 10A, and the second boundary B4 abuts the memory array 18 of the second memory block 10B. As depicted herein, the memory blocks 10A and 10B are arranged as mirror images of each other around the third stripe cell 60. In particular, the merged memory block 10C no longer has an edge cell 21 that is free of any FETs (e.g., front-end device features) and well stripes, as previously described with respect to FIG. Fig. 2. Instead, the combined memory block 10C includes the third stripe cell 60, which combines the structures and functions of two of the first stripe cells 17 of two combined memory blocks 10A and 10B.

[0041] More specifically, in relation to Fig. 3D, which illustrates details of one embodiment of the merged memory block 10C, comprises merging the two edge cells 21 and the two adjacent first stripe cells 17, forming each n-doped region 14A and each p-doped region 16 to extend laterally between at least the two memory arrays 18 (and the two second stripe cells 19 in the depicted embodiments) and across the third stripe cell 60 along the first direction. In the present embodiments, the third stripe cell 60 comprises an alternating arrangement of the n-doped region 14A and the p-doped region 16 along the second direction, where each doped region has a corresponding well stripe. For example, the n-doped region 14A comprises the n-well stripe 17A electrically connected to the first power supply voltage V DDand each p-doped region 16 has the p-well stripe 17B electrically connected to the second power supply voltage V SS is coupled, as in Fig. 2 and described in detail above. Accordingly, the n-well stripe 17A and the p-well stripe 17B are arranged together lying between the two memory arrays 18. Furthermore, the n-well stripe 17A and the p-well stripe 17B are also arranged in an alternating structure along the second direction in the third stripe cell 60, which lies between the two memory arrays 18 along the first direction. In some embodiments, the n-well stripe(s) 17A and the p-well stripe 17B are offset along the first direction, as shown in Fig. is depicted in 3D.

[0042] Alternatively, with regard to Fig. 3E, which illustrates details of another embodiment of the merged memory block 10C, the n-doped region 14A of each of the memory blocks extends partially into the third stripe cell 60 such that a portion of the p-doped region 16 extends continuously between portions of the n-doped region 14A in the third stripe cell 60. Therefore, each portion of the n-doped region 14A in the third stripe cell 60 includes the n-well stripe 17A, and the portion of the p-doped region 16 in the third stripe cell 60 includes a common p-well stripe 17B that electrically connects portions of the p-doped region 16 in the memory arrays 18 to the second power supply voltage V SS coupled.

[0043] Although not in Fig. 3A-3E, the combined memory block 10C includes structural elements similar (or the same) to those of the memory block 10, as described in detail above. For example, the combined memory block 10C further includes (e.g., a first and a second) second stripe cells 19 disposed adjacent to each memory array 18. Each memory array 18 (in each of the memory blocks 10A and 10B) includes a plurality of PMOS FinFETs 18A disposed in the n-doped region 14A and a plurality of NMOS FinFETs 18B disposed in the p-doped region 16. Furthermore, the third stripe cell 60 includes at least one first via configured to electrically connect each n-well stripe 17A to the first power supply voltage V DD and a second via configured to couple each p-well stripe 17B to the second power supply voltage V SS to pair.

[0044] In some embodiments, the third stripe cell 60 further includes a plurality of dummy FETs (as opposed to the active FETs in the memory array 18), similar to the first stripe cell 17 of the memory block 10 described above. For example, the third stripe cell 60 may each include the PMOS dummy FETs 58A disposed between the n-well stripe 17A and the PMOS FinFETs 18A in the n-doped region 14A, and a plurality of NMOS dummy FETs 58B disposed between the p-well stripe 17B and the NMOS FinFETs 18B in the p-doped region 16. Similarly, every second stripe cell 19 may include the PMOS dummy FETs 58C and the NMOS dummy FETs 58D, as described in detail above.

[0045] In existing implementations, joining the memory blocks 10A and 10B to form the depicted configuration would generally result in the width W5 of the third stripe cell 60 being equal to 2*(W2 + W4), where the width W2 is that of the first stripe cell 17 and the width W4 is that of the edge cell 21, and where the width W2 is greater than the width W3 of the second stripe cell 19, according to descriptions of Fig. 1 and Fig. 2. However, in the present embodiments (see Fig. 3A-3E), by removing the edge cell 21 of each memory block, which is generally provided as a means to adjust the overall width of the memory block in accordance with the DRC constraints, the width W5 can be reduced by at least 2*W4. Additionally, to form the third stripe cell 60, two merged first stripe cells 17 are combined, which can further reduce the width W5 to be in a range greater than or equal to W2 to less than 2*W2. For example, if the width W2 of the first stripe cell 17 is 10 CPP, the width W5 of the third stripe cell 60 is at least 10 CPP and less than 20 CPP, such as 10 CPP, 14 CPP, or 17 CPP, etc. In some embodiments, the specific value of the width W5 varies in the range from W2 to 2*W2 based on the specific width-to-height ratio in accordance with the DRC constraints of a given technology node.For example, a width-to-height ratio can be defined as a multiple of a CPP. Consequently, the overall dimension, such as a width W' of the aggregated memory block 10C, is defined as 2*(W1 + W3) + W5, which is less than 2*W as defined herein.

[0046] In some embodiments, with respect to Fig. 4A-4D together, the first memory block 10A and the second memory block 10B are interconnected (or coupled together) by placing the two (e.g., a first and a second) second stripe cells 19 in a side-by-side configuration along the first direction and combining (or merging) the interconnected second stripe cells 19. The resulting interconnected memory block 10D includes a fourth stripe cell 62 disposed between the two (e.g., a first and a second) memory arrays 18, where the fourth stripe cell 62 has a width W6 spanning an area defined by a first boundary B5 and a second boundary B6, each extending along the second direction. As a result, the first boundary B5 abuts the memory array 18 of the first memory block 10A, and the second boundary B6 abuts the memory array 18 of the second memory block 10B.Analogous to the merged memory block 10C, the merged memory block 10D includes the fourth stripe cell 62, which combines the structures and functions of two of the second stripe cells 19 of two adjacent memory blocks into a single stripe cell, i.e., the fourth stripe cell 62. In some embodiments, the merged memory block 10D includes the edge cells 21 as shown in FIG. Fig. 4C. Alternatively, the merged memory block 10D may be merged with another memory block, such as the first memory block 10A, by merging two first stripe cells 17 and one of the edge cells 21 in a similar manner to that described previously with respect to Fig. 3A-3E is removed.

[0047] Fig. 4D illustrates one embodiment of the merged memory block 10D. In some embodiments, merging the two stripe cells 19 includes forming each n-doped region 14A and each p-doped region 16 to extend laterally between at least the two memory arrays 18 and across the fourth stripe cell 62 along the first direction. Further, each n-doped region 14A extends partially into each first stripe cell 17, merging each memory array 18 along the first direction and opposing the fourth stripe cell 62. In the present embodiments, similar to the merged memory block 10C, the fourth stripe cell 62 comprises an alternating arrangement of the n-doped region 14A and the p-doped region 16 along the second direction.However, unlike the merged memory block 10C, the fourth stripe cell 62 is free of any well stripe electrically connected to any power supply voltage (V. DD or V SS ). Instead, the n-well strip(s) 17A, which are electrically connected to the first power supply voltage V DD and the p-well stripe 17B which is electrically connected to the second power supply voltage V SScoupled, is arranged in the first stripe cell 17 of each of the memory blocks 10A and 10B, such that the n-well stripe(s) 17A and the p-well stripe 17B are arranged along a side of the memory array 18 opposite the fourth stripe cell 62. Other aspects of the merged memory block 10D are similar (or substantially the same) to those of the memory block 10, and their description will therefore not be repeated here. Furthermore, due to their positions within the memory device, the third stripe cell 60 and the fourth stripe cell 62 may alternatively be referred to as merged (or center) stripe cells, as opposed to boundary stripe cells such as the first stripe cell 17 and the second stripe cell 19.

[0048] Similar to the merged memory block 10C, combining the memory blocks 10A and 10B to form the depicted configuration would generally result in the width W6 of the fourth stripe cell 62 being equal to 2*W3, where the width W3 is that of the second stripe cell 19, and where the width W3 is less than the width W2 of the first stripe cell 17, according to descriptions of Fig. 1 and Fig. 2. However, in the present embodiments (see Fig. 4A-4D), by combining (or merging) two second stripe cells 19 into the fourth stripe cell 62, the width W6 is reduced by at least an equivalent of the width W3. Therefore, the width W6 is greater than or equal to the width W3 and less than the width 2*W3. For example, if the width W3 of the second stripe cell 19 is 4 CPP, the width W6 of the fourth stripe cell 62 is at least 4 CPP and less than 8 CPP, such as 4 CPP, 5 CPP, or 6.5 CPP, etc. In some embodiments, the specific value of the width W6 varies in the range of W3 and w*W3 based on the specific width-to-height ratio in accordance with the DRC constraints of a given technology node, similar to the determination of the width W5. As a result, the overall dimension, such as a width W'' of the combined memory block 10D, is defined as w*(W1 + W2) + W6, which is less than 2*W as defined herein.

[0049] In some embodiments, the merged memory block 10C and the merged memory block 10D are each configured as a portion of a memory device that also includes a plurality of peripheral circuit components disposed above, below, or laterally adjacent to components of the merged memory block 10C and the merged memory block 10D. In some embodiments, additional memory blocks (e.g., memory block 10A / 10B) are merged with the merged memory block 10C or the merged memory block 10D in a manner similar to that described above with respect to forming the third stripe cell 60 and the fourth stripe cell 62, respectively.

[0050] Fig. 5 illustrates a schematic example diagram of a semiconductor memory device 100 (hereinafter referred to as memory device 100) in accordance with various embodiments. The memory device (or macro) 100 includes an input / output (I / O) circuit 110, a control logic circuit 120, a wordline driver 130, and the memory block 10 described herein, which includes at least the memory array 18. In the depicted embodiments, the I / O circuit 110 is located at a vertical boundary of the memory block 10 such that it is arranged adjacent to the memory block 10 along the first direction. In the present disclosure, the I / O circuit 110, the control logic circuit 120, and the wordline driver 130 may be collectively referred to as the peripheral circuitry of the memory device 100. Although not clearly shown in Fig. 5, the various components of the memory device 100 may be electrically (or operatively) coupled to each other and to the control logic circuit 120. For example, the I / O circuit 110, the control logic circuit 120, and the wordline driver 130 may be electrically coupled to the memory array 18. Although the components in Fig. 5 are shown as separate blocks for illustrative purposes, in some embodiments some or all of the components may be integrated together.

[0051] The word line driver (WL driver) 130, which may include a row decoder and a word line voltage supply unit, may be responsible for activating word lines within the memory array 18. When data is read from a row of the memory cells 11 (see Fig. 1) of the memory array 18 need to be read or written to, the wordline driver 130 can select the appropriate wordline by setting it to a higher voltage level. The selected row of cells can then be read or written to by sense amplifiers or write drivers connected to bitlines that run vertically and intersect the wordlines. The I / O circuit 110 is a hardware component that can access (e.g., read, program) each memory cell, which is confirmed by a range decoder, such as the row decoder and a column decoder. The control logic circuit 120 is a hardware component that can control various coupled components of the memory device 100 (e.g., components 18, 110, 120, and 130).

[0052] In some embodiments, with respect to Fig. 5, the memory device 100 further includes a peripheral transition cell 124 and a peripheral transition cell 134, each of which is configured to implement the design and function of peripheral logic circuit components, such as the control logic circuit 120 and / or the wordline driver 130. In some embodiments, the peripheral transition cell 124 is aligned with the second stripe cell 19 along the second direction, while the peripheral transition cell 134 is aligned with the first stripe cell 17 along the second direction. As depicted herein, the edge cell 21 of the memory block 10 may extend along the second direction to abut the peripheral transition cell 134.

[0053] In some examples, the peripheral junction cell 124 may be configured as a stripe cell having a well stripe configured to be coupled to a power supply voltage in a similar manner to the well stripe arranged in the first stripe cell 17. In a specific example, the peripheral junction cell 124 may include an n-doped region, similar to the n-doped region 14A, having an n-well stripe, similar to the n-well stripe 17A. Accordingly, the peripheral junction cell 124 electrically couples a portion of the substrate 12 (e.g., a portion of the substrate 12 providing PMOS devices) of the control logic circuit 120 to the first power supply voltage V DD. Similarly, the peripheral junction cell 134 may be configured as a stripe cell having a well stripe configured to electrically couple a portion of the substrate 12 to a power supply voltage. Alternatively, one or both of the peripheral junction cells 124 and 134 may be configured as an edge cell, similar to the edge cell 21 in both structure and function as described herein. In some embodiments, still with respect to Fig. 5, the memory device 100 further includes a lower edge cell 160 and an upper edge cell 210 separated from the lower edge cell 160 along the second direction. Each of the lower edge cell 160 and the upper edge cell 210 traverses a width (e.g., width DW) of the memory device 100 along the first direction.

[0054] The memory device 100 has a width DW along the first direction and a height DH along the second direction, where the width DW and the height DH are greater than the width W and the height H, respectively, of the memory block 10, as defined herein. The structures and functions of the lower edge cell 160 and the upper edge cell 210 are similar to those of the edge cell 21 of the memory block 10. For example, a height H1 of the lower edge cell 160 and / or a height H2 of the upper edge cell 210 can be adjusted such that a ratio of the width DW to the height DH satisfies specific DRC constraints at a given technology node. In the present embodiments, the lower edge cell 160 has a height H1 and the upper edge cell 210 has a height H2.The present disclosure does not limit the height H1 and the height H2 to any specific values, as long as the ratio of the width DW to the height DH satisfies specific DRC constraints. For example, the height H1 may be the same as or different from the height H2.

[0055] Analogous to the Fig. 3A-4D at the memory block level are directed in Fig. 6A-23C illustrate embodiments of structures and an arrangement of one or more transition cells at the memory device level to reduce the width DW and / or the height DH of the memory device 100.

[0056] In some embodiments, collectively with respect to Fig. 6A-6C, a first memory device 100A and a second memory device 100B, each equivalent to the memory device 100 described herein, are interconnected (or coupled, merged, etc.) by placing two (e.g., a first and a second) edge cells 21 in a side-by-side configuration along the first direction. As a result, a vertical boundary of the first memory device 100A abuts that of the second memory device 100B, and the memory devices are arranged as mirror images of each other.

[0057] In the present embodiments, with respect to Fig. 6C, interconnecting the edge cell 21 of memory block 10 (e.g., 10A or 10B) of each of the memory devices 100A and 100B results in a interconnected memory device 100C comprising the interconnected memory block 10C as described herein. For example, interconnecting the memory devices 100A and 100B at the edge cells 21 combines (or merges) the edge cells 21 and their respective adjacent (e.g., a first and a second) first stripe cells 17 to form the third stripe cell 60 as in the interconnected memory block 10C of Fig. 3A-3E. In some embodiments, after memory devices 100A and 100B have been merged, the peripheral circuitry of each memory device retains control of the operations of its respective memory blocks 10, i.e., each peripheral circuitry is configured to control its corresponding memory array(s) 18.

[0058] Furthermore, merging the memory devices 100A and 100B at the edge cells 21 also merges the two peripheral transition cells 134 of the respective memory devices to form a peripheral transition cell 136. The resulting merged memory device 100C includes the third stripe cell 60 and the peripheral transition cell 136 between the two (e.g., a first and a second) memory arrays 18 of the respective memory devices, where the third stripe cell 60 and the peripheral transition cell 136 are aligned along the second direction. As a result, the third stripe cell 60 and the peripheral transition cell 136 have the same width as the width W5 defined in the merged memory block 10C. It goes even further to connect the memory devices 100A and 100B at the edge cells 21, the two (e.g. a first and a second) lower edge cells 160 and the two (e.g.a first and a second) upper edge cells 210 together.

[0059] In the present embodiments, the peripheral transition cell 136 serves substantially the same function as the peripheral transition cell 134. For example, if the peripheral transition cell 134 is configured as an edge cell, the peripheral transition cell 136 is also configured as an edge cell. Alternatively, if the peripheral transition cell 134 is configured as a stripe cell having a well stripe, as previously described in detail, the peripheral transition cell 136 is also configured to have the well stripe. In particular, the width of the peripheral transition cell 134 corresponds to the width W5 of the third stripe cell 60, previously described in detail with respect to the merged memory block 10C.

[0060] Furthermore, analogous to the description of reducing the width of the merged memory block 10C, merging the memory devices 100A and device 100B reduces the overall width W' of the memory blocks in the merged memory device 100C because the width W5 of the third stripe cell 60 is less than the sum of the widths W2 (i.e., less than 2*W2) of the two merged first stripe cells 17 (with the two edge cells 21 removed). This, in turn, reduces the overall dimension DW' of the merged memory device 100C to less than 2*DW, where the width DW is the width W of the memory block 10 in each of the memory devices 100A and 100B.

[0061] Fig. 7 forms a memory device 200 similar to the memory device 100 of Fig. 5. For example, memory device 200 includes I / O circuitry 110, control logic circuitry 120, wordline driver 130, and memory block 10. Memory device 200 further includes peripheral transition cells 124 and 134 disposed adjacent to control logic circuitry and wordline driver 130, respectively. Memory device 200 further includes lower edge cell 160 and upper edge cell 210, each traversing the width DW of memory device 200, which is also defined by height DH along the second direction. Unlike the memory device 100, the I / O circuit 110 of the memory device 200 is located at a vertical boundary of the memory block 10 at the first stripe cell 17, while the I / O circuit 110 of the memory device 100 is located at a vertical boundary of the memory block 10 at the second stripe cell 19.Descriptions of the structural elements common to both memory devices 100 and 200 are omitted here for the sake of brevity.

[0062] In relation to Fig. 8A-8C together, a first memory device 200A and a second memory device 200B, each equivalent to the memory device 200 described herein, are interconnected (or coupled, merged, etc.) by placing two (e.g., a first and a second) second stripe cells 19 in a side-by-side configuration along the first direction such that the vertical boundary of the first memory device 200A abuts that of the second memory device 200B, and the memory devices are depicted as mirror images of each other. In some embodiments, after the memory devices 200A and 200B are merged, the peripheral circuitry of each memory device retains control of the operations of its respective memory blocks 10, i.e., each peripheral circuitry is configured to control its corresponding memory array(s) 18.

[0063] In the present embodiments, with respect to Fig. 8C, combining the second stripe cell 19 of the memory block 10 of each of the memory devices 200A and 200B results in a combined memory device 200 having the combined memory block 10D as described herein. For example, combining the memory devices 200A and 200B at the second stripe cell 19 combines the second stripe cells 19 to form the fourth stripe cell 62 as in the combined memory block 10D of Fig. 4A-4D shown and described.

[0064] Combining memory devices 200A and 200B at the second stripe cell 19 also combines the two peripheral transition cells 124 of the respective memory devices to form a peripheral transition cell 126. The resulting combined memory device 200C includes the fourth stripe cell 62 and the peripheral transition cell 126 disposed between the two (e.g., first and second) memory arrays 18 of the respective memory devices, where the fourth stripe cell 62 and the peripheral transition cell 126 are aligned along the second direction. As a result, the third stripe cell 60 and the peripheral transition cell 126 have the same width as the width W6 defined in the combined memory block 10D.Similar to the relationship between peripheral transition cell 134 and peripheral transition cell 136, peripheral transition cell 126 serves substantially the same function as peripheral transition cell 124. Still further, interconnecting memory devices 200A and 200B at second stripe cell 19 interconnects the two (e.g., first and second) lower edge cells 160 and the two (e.g., first and second) upper edge cells 210 in a similar manner to interconnecting memory devices 200A and 200B.

[0065] Analogous to the description of reducing the width of the merged memory block 10D, merging the memory devices 200A and 200B reduces the overall width W'' of the memory blocks in the merged memory device 100C due to the width W6 of the fourth stripe cell 62 being less than the sum of the widths W3 (i.e., less than 2*W3) of the two merged second stripe cells 19. This, in turn, reduces the overall dimension DW' of the merged memory device 200C to less than 2*DW, where the width DW is the width W of the memory block 10 in each of the memory devices 200A and 200B.

[0066] In some embodiments, with respect to Fig. 9A-9C together, the memory devices 200A and 200B are interconnected by placing the lower edge cell 160 of the memory device 200A and the upper edge cell 210 of the memory device 200B in a top-down configuration along the second direction such that a horizontal boundary of the first memory device 200A abuts that of the second memory device 200B. In the present embodiments, with respect to Fig. 9C, combining memory devices 200A and 200B in this configuration results in a combined memory device 200D having a single middle edge cell 182 disposed between two vertically stacked memory blocks 10d of memory devices 200A and 200B. In the depicted embodiments, middle edge cell 182 abuts one of the memory arrays 18, such as memory array 18 in lower memory block 10 (i.e., memory device 200B) that is located between middle edge cell 182 and lower edge cell 160. In some embodiments, after the memory devices 200A and 200B have been merged along the second direction, the peripheral circuitry of each memory device retains control of the operations of its respective memory blocks 10, i.e., each peripheral circuitry is configured to control its corresponding memory array(s) 18.

[0067] In a similar manner to the merging of two first stripe cells 17 or two second stripe cells 19, the merged middle edge cell 182 has a height H3 that is less than a sum of the height H1 of the lower edge cell 160 and the height H2 of the upper edge cell 210. Therefore, the total height DH' of the merged memory device 200D is less than a sum of the height DH (i.e., less than 2*DH) of each of the memory devices 200A and 200B. The present disclosure does not limit the height H3 to any specific value within this range, as long as the ratio of the width DW to the height DH' satisfies the specific DRC constraints.

[0068] In some embodiments, with respect to Fig. 10A-10C together, the memory devices 200A and 200B are joined by placing the lower edge cell 160 of the memory device 200A and the lower edge cell 160 of the memory device 200B in a top-down configuration along the second direction such that a horizontal boundary of the first memory device 200A abuts that of the second memory device 200B. In the present embodiments, with respect to Fig. 10C, combining memory devices 200A and 200B in this configuration results in a combined memory device 200E having a single center edge cell 184 sandwiched between two vertically stacked memory blocks 10 of memory devices 200A and 200B. The two memory devices 200A and 200B are therefore arranged as mirror images around the center edge cell 184. In the depicted embodiments, the center edge cell 184 interfaces with the peripheral circuitry (e.g., control logic circuitry 120 and wordline driver 130, etc.) of memory devices 200A and 200B, but is separated from each of the memory arrays 18 along the second direction.

[0069] Similar to the merged middle edge cell 182, the merged middle edge cell 184 has a height H4 that is less than a sum of the height H1 of each of the lower edge cells 160 (i.e., less than 2*H1). The total height DH' of the merged memory device 200E is similarly less than the sum of the height DH (i.e., less than 2*DH) of each of the memory devices 200A and 200B. The present disclosure does not limit the height H4 to any specific value within this range, as long as the ratio of the width DW to the height DH' satisfies the specific DRC constraints.

[0070] In some embodiments, with respect to Fig. 11A-11C together, the memory devices 200A and 200B are connected together by placing the upper edge cell 210 of the memory device 200A and the upper edge cell 210 of the memory device 200B in a top-down configuration along the second direction such that a horizontal boundary of the first memory device 200A abuts that of the second memory device 200B. In the present embodiments, with respect to Fig. 11C, combining memory devices 200A and 200B in this configuration results in a combined memory device 200F having a single center edge cell 186 sandwiched between two vertically stacked memory blocks 10 of memory devices 200A and 200B. The two memory devices 200A and 200B are therefore arranged as mirror images around the center edge cell 186. In the depicted embodiments, the center edge cell 186 abuts each memory array 18 of the upper and lower memory blocks 10 (i.e., memory devices 200A and 200B).

[0071] The combined middle edge cell 186 has a height H5 that is less than a sum of the height H2 of each of the top edge cells 210 (i.e., less than 2*H2). The total height DH' of the combined memory device 200F is similarly less than the sum of the height DH (i.e., less than 2*DH) of each of the memory devices 200A and 200B. The present disclosure does not limit the height H5 to any specific value within this range, as long as the ratio of the width DW to the height DH' satisfies the specific DRC constraints.

[0072] In some embodiments, with respect to Fig. 12A-12C together, the memory devices 200A and 200B are joined by placing the upper edge cell 210 of the memory device 200A and the lower edge cell 160 of the memory device 200B in a top-down configuration along the second direction such that a horizontal boundary of the first memory device 200A abuts that of the second memory device 200B. In the present embodiments, with respect to Fig. 12C, combining memory devices 200A and 200B in this configuration results in a combined memory device 200G having a single middle edge cell 188 sandwiched between two vertically stacked memory blocks 10 of memory devices 200A and 200B. In the depicted embodiments, middle edge cell 188 abuts one of the memory arrays 18, such as memory array 18 in upper memory block 10 (i.e., memory device 200A), sandwiched between middle edge cell 188 and lower edge cell 160.

[0073] The merged middle edge cell 188 has a height H6 that is less than a sum of the height H1 of the lower edge cell 160 and the height H2 of the upper edge cell 210. The total height DH' of the merged memory device 200G is similarly less than the sum of the height DH (i.e., less than 2*DH) of each of the memory devices 200A and 200B. The present disclosure does not limit the height H6 to any specific value within this range, as long as the ratio of the width DW to the height DH' satisfies the specific DRC constraints.

[0074] Various arrangements of the memory devices 200A and 200B shown in Fig. 9A-12C may also be applicable to the memory devices 100A and 200B. For example, with respect to Fig. 13A-13C together, the memory devices 100A and 100B are connected together by placing the lower edge cell 160 of the memory device 100A and the upper edge cell 210 of the memory device 100B in a top-down configuration along the second direction such that a horizontal boundary of the first memory device 100A abuts that of the second memory device 100B. In the present embodiments, with respect to Fig. 13C, combining the memory devices 100A and 100B in this configuration results in a combined memory device 100D having a single middle edge cell 190 sandwiched between two vertically stacked memory blocks 10 of the memory devices 100A and 100B. The combined middle edge cell 190 has a height H7 that is less than a sum of the height H1 of the lower edge cell 160 and the height H2 of the upper edge cell 210. Therefore, the total height DH' of the combined memory device 100D is less than a sum of the height DH (i.e., less than 2*DH) of each of the memory devices 200A and 200B.

[0075] In some embodiments, as in Fig. 5-13C, the I / O circuit 110 of each of the memory devices 100 (e.g., 100A and 100B) and 200 (e.g., 200A and 200B) is located at the vertical boundary (e.g., along the second direction) of the memory block 10, where the I / O circuit 110 provides single-sided control for the memory array 18. In other words, each peripheral circuit is configured to control a memory block 10 (or a bank comprising a single memory block 10). In some embodiments, as in Fig. 14-17C, analog memory devices 300 and 400 each include the I / O circuit 110 (and the control logic circuit 120) sandwiched between two memory blocks 10 (or two banks of memory blocks 10, each bank including one memory block 10) such that the two memory arrays 18 are symmetrically disposed about and operatively controlled by the I / O circuit 110 along the first direction.

[0076] For example, with regard to Fig. 14, memory device 300 has a structure similar to memory devices 100 and 200, except that the I / O circuit 110 of memory device 300 is flanked by two memory blocks 10 along the first direction, where the I / O circuit 110 abuts the second stripe cell 19 of each of the memory blocks 10, and the first stripe cells 17 are arranged along an outer boundary of memory device 300. As a result, the I / O circuit 110 of memory device 300 provides control of the two symmetrically arranged memory blocks 10 along the first direction.

[0077] In some embodiments, various arrangements of the memory device 100 are also applicable to the memory device 300. For example, with respect to Fig. 15A-15C, a first memory device 300A and a second memory device 300B, each equivalent to the memory device 300 described herein, are interconnected by placing two (e.g., a first and a second) edge cells 21 in a side-by-side configuration along the first direction to form an interconnected memory device 300C.

[0078] Similar to the combined memory device 100C, with respect to Fig. 15C, the merged memory device 300C includes the merged memory block 10C, which merges the edge cells 21 and their respective adjacent (e.g., a first and a second) first stripe cells 17 to form the third stripe cell 60. As a result, the memory devices 300A and 300B are arranged as mirror images of each other around the third stripe cell 60. Furthermore, merging the memory devices 300A and 300B at the edge cells 21 also forms the peripheral transition cell 136. As a result, the third stripe cell 60 and the peripheral transition cell 136 have the same width as the width W5 defined in the merged memory block 10C.

[0079] In some embodiments, with respect to Fig. 16, the memory device 400 has a structure similar to that of the memory device 300, except that the I / O circuit 110 is adjacent to the first stripe cell 17 of each of the memory blocks 10 and the second stripe cells 19 are arranged along an outer boundary of the memory device 400.

[0080] In some embodiments, various arrangements of the memory device 200 are also applicable to the memory device 400. For example, with respect to Fig. 17A-17C, a first memory device 400A and a second memory device 400B, each of which is equivalent to the memory device 300 described herein, are interconnected by placing two (e.g., a first and a second) second stripe cells 19 in a side-by-side configuration along the first direction to form an interconnected memory device 400C. Similar to the interconnected memory device 200C, with respect to Fig. 16C, the merged memory device 400C includes the merged memory block 10D that merges the second stripe cells 19 to form the fourth stripe cell 62. As a result, the memory devices 400A and 400B are arranged as mirror images of each other around the fourth stripe cell 62. Furthermore, merging the memory devices 400A and 400B at the second stripe cell 19 also forms the peripheral transition cell 126, which has the same width as the width W6 of the fourth stripe cell 62.

[0081] In some embodiments, as in Fig. 18-19C, an analog memory device 500 includes two I / O circuits 110, each coupled to a common control logic circuit 120 along the second direction and coupled to the vertical boundary of each memory block 10 along the first direction where two such memory blocks 10 are stacked along the second direction and separated by the wordline driver 130 and the peripheral transition cells 124 and 134. The I / O circuits 110 are each configured to control the adjacent memory block 10. The memory device 500 further includes the lower edge cell 160 coupled to a boundary of the lower memory block 10 and the upper edge cell 210 coupled to a boundary of the upper memory block 10.

[0082] In some embodiments, various arrangements of the memory device 100 are also applicable to the memory device 500. For example, with respect to Fig. 19A-19C, a first memory device 500A and a second memory device 500B, each of which is equivalent to the memory device 500 described herein, are joined by placing two (e.g., a first and a second) edge cells 21 in a side-by-side configuration along the first direction to form a joined memory device 500C. Similar to the joined memory device 100C, with respect to Fig. 19C, the merged memory device 500C includes the merged memory block 10C from each pair of upper and lower memory blocks 10, where each merged memory block 10C merges the adjacent edge cells 21 and their respective adjacent (e.g., a first and a second) first stripe cells 17 to form the third stripe cell 60. The adjacent peripheral transition cells 134 are also merged to form the peripheral transition cell 136, such that the merged memory blocks 10C in the upper and lower portions of the memory device 500C are separated by the peripheral transition cell 136. As a result, the memory devices 500A and 500B are arranged as mirror images of each other around the third stripe cell 60.In addition, connecting the memory devices 500A and 500B at the edge cells 21 also forms the peripheral transition cell 136, which has the same width as the width W5 of the third stripe cell 60.

[0083] In some embodiments, as in Fig. 5-19C, the I / O circuit 110 operatively controls each of the memory devices 100 (e.g., 100A and 100B), 200 (e.g., 200A and 200B), 300 (e.g., 300A and 300B), 400 (e.g., 400A and 400B), and 500 (e.g., 500A and 500B) to control a single bank comprising a memory array 18 of a memory block 10. In some embodiments, as shown in Fig. 20A-23C, analog memory devices 600A, 600B, 700A, 700B, 800A, 800B, 900A, and 900B each include I / O circuitry 110 (and control logic circuitry 120) configured to control the operations of more than one bank of memory arrays 18, where each bank includes more than one memory array 18 of its respective memory blocks 10, such as two memory blocks 10 stacked along the second direction.

[0084] In some embodiments, with respect to Fig. 20A-21C, the memory device has an even number of banks flanking the I / O circuit 110. For example, each of the memory devices 600A, 600B, 700A, and 700B has one bank on each side of the I / O circuit 110, and each bank has two memory arrays 18 (i.e., two memory blocks 10) stacked along the second direction. In some embodiments, with respect to Fig. 22A-23C, the memory device has an odd number of banks flanking the I / O circuit 110. For example, each of the memory devices 800A, 800B, 900A, and 900B has one bank on one side of the I / O circuit 110 near a vertical boundary B7 and two banks on the opposite side of the I / O circuit 110 near a vertical boundary B8, and each bank has two memory arrays 18 (i.e., two memory blocks 10) stacked along the second direction.

[0085] In some embodiments, with respect to Fig. 20A-20C, the memory devices 600A and 600B are connected together at two (e.g., a first and a second) edge cells 21 in the side-by-side configuration along the first direction, thereby uniting the edge cells 21 and their respective adjacent first stripe cells 17 to form the third stripe cell 60 (see Fig. 20C). The adjacent peripheral transition cells 134 are also merged to form the peripheral transition cell 136, such that the merged memory blocks 10C in the upper portion and the lower portion of the memory device 600C are separated by the peripheral transition cell 136. In some embodiments, after the memory devices 600A and 600B have been merged along the first direction, the peripheral circuitry of each memory device retains control of the operations of its respective memory blocks 10, i.e., each peripheral circuitry is configured to control its corresponding banks of the memory arrays 18. A similar arrangement is implemented for the memory devices 800A and 800B, as shown in Fig. 22A-22C.

[0086] In some embodiments, with respect to Fig. 21A-21C, the memory devices 700A and 700B are connected together at two (e.g., a first and a second) second stripe cells 19 in the side-by-side configuration along the first direction, thereby uniting the second stripe cells 19 to form the fourth stripe cell 62 (see Fig. 21C). The adjacent peripheral transition cells 134 are also combined to form the peripheral transition cell 136 in a similar manner to that shown in Fig. 20C. A similar arrangement is implemented for memory devices 900A and 900B, as shown in Fig. 23A-23C.

[0087] In some embodiments, the various memory devices provided herein each include mergeable stripe cells arranged along both of the memory device's vertical outer boundaries B7 and B8, which are separated along the first direction. The mergeable stripe cells, i.e., the first stripe cell 17 and the second stripe cell 19, may be of the same type as those depicted in memory devices 600A / B, 700A / B, and 800A / B. Alternatively, the mergeable stripe cells may be of different types, such as those depicted in memory devices 900A / B. Different placements of the mergeable stripe cells allow different merged (or center) stripe cells, i.e., the third stripe cell 60 and the fourth stripe cell 62, to be formed in the memory devices, providing greater design flexibility with improved scalability.

[0088] Fig. Figure 24 illustrates a schematic diagram of the memory component of an exemplary memory device 1000 according to some embodiments of the present disclosure. For simplicity, the peripheral circuit components (e.g., I / O circuitry, control logic circuitry, wordline drivers, etc.) of the memory device 1000 are shown in Fig. 24 omitted. The memory component includes a plurality of memory blocks 1001, each analogous to (i.e., having a similar or substantially the same structure) memory block 10 and arranged in a grid having M columns and N rows, where M and N are both greater than or equal to one. Memory device 1000 includes an upper edge cell 1020 and a lower edge cell 1010, which are analogous to upper edge cell 210 and lower edge cell 160, respectively. Two adjacent memory blocks 1001 along the first direction are separated by a merged stripe cell 1050, which is analogous to third stripe cell 60 or fourth stripe cell 62. Additionally, two adjacent memory blocks 1001 along the second direction are separated by a middle edge cell 1030, which is analogous to any one of middle edge cells 182-188.In the present embodiments, one or more of the combined stripe cells 1050 and the middle edge cells 1030 are configured to reduce a width GDH' and a height GDW' of the memory device 1000, respectively, thereby achieving a higher chip density in the memory devices (e.g., SRAM devices).

[0089] Fig. 25 is a flow diagram of a method 1400 for forming or manufacturing a semiconductor device, such as any of the memory block 10 or any of the memory devices 100-1000, in accordance with some embodiments. It should be understood that additional operations may be performed before, during, and / or after the Fig. 25 procedures shown can be carried out 1400 times.

[0090] In operation 1410 of method 1400, a layout design of a semiconductor device is generated. Operation 1410 is performed by a processing device (e.g., processor 1502 of Fig. 26) configured to execute instructions for generating a layout design. In one approach, the layout design is generated by placing layout designs of one or more standard cells via a user interface. In one approach, the layout design is automatically generated by a processor executing a synthesis tool that converts a logic design (e.g., Verilog) into a corresponding layout design. In some embodiments, the layout design is rendered in a graphical database system (GDSII) file format. In some embodiments, the layout design includes a file format that corresponds to the file format in Fig. 2, which is an embodiment of the memory block 10 described herein.

[0091] In operation 1420 of method 1400, a semiconductor device is fabricated based on the layout design. In some embodiments, operation 1420 of method 1400 includes fabricating at least one mask based on the layout design and fabricating a semiconductor device based on the at least one mask. Example manufacturing operations of operation 1420 may include patterning, implantation, deposition, etching, planarization, the like, or combinations thereof to form a plurality of front-end-of-line features (e.g., n-doped region 14, p-doped region 16, n-well stripe 17A, p-well stripe 17B, fins 20-26, epitaxial source / drain features 40A-40D, gate structures 30A-30C, etc.), device-level contacts, and interconnect features including vias (e.g., vias 50-56) and conductive lines.

[0092] In some embodiments, method 1400 is implemented as a stand-alone software application for execution by a processor. In some embodiments, method 1400 is implemented as a software application that is a part of an additional software application. In some embodiments, method 1400 is implemented as a plug-in to a software application. In some embodiments, method 1400 is implemented as a software application that is a portion of an EDA tool. In some embodiments, method 1400 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design of the IC device. In some embodiments, the layout design is stored on a non-transitory computer-readable medium.In some embodiments, the layout design is generated based on a netlist created based on the schematic design.

[0093] Fig. 26 is a schematic view of a system 1500 for designing and manufacturing an IC layout design in accordance with some embodiments. The system 1500 creates or places one or more IC layout designs as described herein. In some embodiments, the system 1500 manufactures one or more semiconductor devices based on the one or more IC layout designs as described herein. The system 1500 includes a (e.g., hardware) processor 1502 and a non-transitory, computer-readable storage medium 1504 encoded with, e.g., storing, computer program code 1506, e.g., a set of executable instructions. The computer-readable storage medium 1504 is configured to interface with manufacturing machines for producing the semiconductor device. The processor 1502 is electrically coupled to the computer-readable storage medium 1504 by a bus bar 1508.The processor 1502 is also electrically coupled to an I / O interface 1510 through bus bar 1508. A network interface 1512 is also electrically connected to the processor 1502 through bus bar 1508. Network interface 1512 is connected to a network 1514 such that the processor 1502 and the computer-readable storage medium 1504 can connect to external elements via network 1514. The processor 1502 is configured to execute the computer program code 1506 encoded in the computer-readable storage medium 1504 to cause the system 1500 to be operable to perform some or all of the operations described in method 1400.

[0094] In some embodiments, processor 1502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or any suitable processing unit.

[0095] In some embodiments, the computer-readable storage medium 1504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or component). For example, the computer-readable storage medium 1504 comprises a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random-access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In some embodiments using optical disks, the computer-readable storage medium 1504 comprises a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0096] In some embodiments, computer-readable storage medium 1504 stores computer program code 1506 configured to cause system 1500 to perform method 1400. In some embodiments, computer-readable storage medium 1504 also stores information required to perform method 1400, as well as information generated during performance of method 1400, such as layout design 1516, user interface 1518, manufacturing unit 1520, and / or a set of executable instructions to perform the operation of method 1400.

[0097] In some embodiments, computer-readable storage medium 1504 stores instructions (e.g., computer program code 1506) for interfacing with manufacturing machines. The instructions (e.g., computer program code 1506) enable processor 1502 to generate manufacturing instructions readable by the manufacturing machines to effectively implement method 1400 during a manufacturing process.

[0098] System 1500 includes I / O interface 1510. I / O interface 1510 is coupled to external circuitry. In some embodiments, I / O interface 1510 includes a keyboard, keypad, mouse, control ball, input pad, and / or arrow keys to communicate information and commands to processor 1502.

[0099] System 1500 also includes network interface 1512 coupled to processor 1502. Network interface 1512 allows system 1500 to communicate with network 1514 to which one or more other computer systems are connected. Network interface 1512 includes wireless network interfaces, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces, such as ETHERNET, USB, or IEEE-13154. In some embodiments, method 1400 is implemented in two or more systems 1500, and information such as layout design, user interface, and manufacturing unit is exchanged between different systems 1500 through network 1514.

[0100] The system 1500 is configured to receive information regarding a layout design through the I / O interface 1510 or network interface 1512. The information is transmitted to the processor 1502 through the bus 1508 to determine a layout design for manufacturing an IC. The layout design is then stored in the computer-readable storage medium 1504 as the layout design 1516. The system 1500 is configured to receive information regarding a user interface through the I / O interface 1510 or network interface 1512. The information is stored in the computer-readable storage medium 1504 as the user interface 1518. The system 1500 is configured to receive information regarding a manufacturing unit through the I / O interface 1510 or network interface 1512. The information is stored in the computer-readable storage medium 1504 as the manufacturing unit 1520.In some embodiments, the manufacturing unit 1520 contains manufacturing information used by the system 1500.

[0101] In some embodiments, the method 1400 is implemented by a manufacturing device to manufacture an IC using a set of masks manufactured based on one or more layout designs generated by the system 1500. In some embodiments, the system 1500 includes a manufacturing device (e.g., manufacturing tool 1522) to manufacture an IC using a set of masks manufactured based on one or more layout designs of the present disclosure. In some embodiments, the system 1500 generates Fig. 26 layout designs of an IC that is smaller than other approaches. In some embodiments, the system generates 1500 of Fig. 26 layout designs of a semiconductor device that occupy less area than other approaches.

[0102] Fig. 27 is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system 1600 and an associated IC manufacturing flow in accordance with at least one embodiment of the present disclosure.

[0103] In Fig. 27, the IC manufacturing system 1600 includes entities such as a design house 1620, a mask house 1630, and an IC manufacturer / fabricator (“fab”) 1640 that interact with each other in services related to the design, development, and manufacturing cycles and / or fabrication of an IC (semiconductor) device 1660 (e.g., corresponding to the memory block 10 or the memory devices 100-1000). The entities in the IC manufacturing system 1600 are interconnected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communications channels. Each entity interacts with one or more of the other entities and provides and / or receives services to one or more of the other entities.In some embodiments, a single company owns two or more of design house 1620, mask house 1630, and IC fab 1640. In some embodiments, two or more of design house 1620, mask house 1630, and IC fab 1640 exist in a common facility and use common resources.

[0104] The design house (or design team) 1620 creates an IC design layout 1622. The IC design layout 1622 includes various geometric structures designed for the IC device 1660. The geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 1660 to be manufactured. The various layers combine to form various IC structural elements. For example, a portion of the IC design layout 1622 includes various IC structural elements, such as an active area, gate structures, source / drain regions, interconnect structures, and openings for bond pads to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house 1620 implements a suitable design procedure to form the IC design layout 1622.The design procedure includes one or more of logic design, physical design, or placement and routing. The IC design layout 1622 is represented in one or more data files that include information about the geometric structures. For example, the IC design layout 1622 can be expressed in a GDSII file format or DFII file format.

[0105] The mask house 1630 includes mask data preparation 1632 and mask fabrication 1634. The mask house 1630 uses the IC design layout 1622 to create one or more masks to be used to fabricate the various layers of the IC device 1660 according to the IC design layout 1622. The mask house 1630 performs mask data preparation 1632, where the IC design layout 1622 is translated into a representative data file ("RDF"). The mask data preparation 1632 provides the RDF to the mask fabrication 1634. The mask fabrication 1634 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by the mask data preparation 1632 to conform to certain properties of the mask writer and / or requirements of the IC-fab 1640. In Fig.27, mask data preparation 1632 and mask fabrication 1634 are illustrated as separate elements. In some embodiments, mask data preparation 1632 and mask fabrication 1634 may be collectively referred to as mask data preparation.

[0106] In some embodiments, mask data preparation 1632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those that may arise from refraction, interference, other process effects, and the like. OPC adjusts the IC design layout 1622. In some embodiments, mask data preparation 1632 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0107] In some embodiments, mask data preparation 1632 includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in OPC against a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margin, account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to accommodate constraints during mask fabrication 1634, which may offset some of the modifications performed by OPC to satisfy mask creation rules.

[0108] In some embodiments, mask data preparation 1632 includes lithography process checking (LPC), which simulates processing implemented by IC fab 1640 to fabricate IC device 1660. LPC simulates this processing based on IC design layout 1622 to create a simulated fabricated device, such as IC device 1660. The processing parameters in LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to fabricate the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like, or combinations thereof.In some embodiments, after a simulated fabricated device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and / or MRC may be repeated to further refine the IC design layout 1622.

[0109] It should be understood that the above description of mask data preparation 1632 has been simplified for clarity. In some embodiments, mask data preparation 1632 includes additional functions, such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to IC design layout 1622 during mask data preparation 1632 can be performed in a variety of different orders.

[0110] After mask data preparation 1632 and during mask fabrication 1634, a mask or a group of masks is fabricated based on the modified IC design layout. In some embodiments, an electron beam (e-beam) or a multiple e-beam mechanism is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask can be formed using various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transmissive regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (e.g., photoresist) deposited on a wafer is blocked by the opaque region and passes through the transmissive regions.In one example, a binary mask comprises a transmissive substrate (e.g., fused silica) and an opaque material (e.g., chromium) layered in the opaque regions of the mask. In another example, the mask is formed using a phase shift technology. In the phase shift mask (PSM), various features in the structure formed on the mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or alternating PSM. The mask(s) produced by mask fabrication 1634 is / are used in a variety of processes. For example, such a mask(s) is / are used in an ion implantation process to create various doped regions in the semiconductor wafer (e.g.,the n-doped regions 14 and the p-doped region 16), in an etching process to form various etched regions in the semiconductor wafer, and / or in other suitable processes.

[0111] The IC fab 1640 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, the IC fab 1640 is a semiconductor foundry. For example, there may be a first manufacturing facility for the front-end manufacturing of multiple IC products (e.g., the epitaxial source / drain features 40A-40C, the gate structures 30A-30C), a second manufacturing facility may provide middle-end manufacturing for interconnecting the IC products (e.g., the vias 50-56, contact features, gate contacts, etc.), a third manufacturing facility may provide back-end manufacturing for interconnecting and packaging the IC products (e.g., front-side metallization layers, back-side metallization layers, etc.), and a fourth manufacturing facility may provide other services to the foundry entity.

[0112] The IC fab 1640 uses the mask (or masks) fabricated by the mask house 1630 to fabricate the IC device 1660. Therefore, the IC fab 1640 at least indirectly uses the IC design layout 1622 to fabricate the IC device 1660. In some embodiments, a semiconductor wafer 1642 is fabricated by the IC fab 1640 using the mask (or masks) to form the IC device 1660. The semiconductor wafer 1642 comprises a silicon substrate or other suitable substrate having layers of material formed thereon. The semiconductor wafer further comprises one or more various doped regions, dielectric features, multilevel interconnects, and the like (formed during subsequent manufacturing steps).

[0113] The IC manufacturing system 1600 is shown to include the design house 1620, mask house 1630, and the IC fab 1640 as separate components or entities. However, it should be understood that one or more of the design house 1620, mask house 1630, and the IC fab 1640 are part of the same component or entity.

[0114] In one aspect of the present disclosure, a memory device includes a first memory array disposed over a substrate, a second memory array disposed over the substrate and separated from the first memory array along a first direction, and a stripe cell defined in the substrate and disposed between the first memory array and the second memory array. The stripe cell includes a first boundary adjacent to the first memory array, a second boundary adjacent to the second memory array, a p-well stripe disposed between the first boundary and the second boundary along the first direction, and an n-well stripe spaced from the p-well stripe along the second direction. The first boundary and the second boundary extend along a second direction perpendicular to the first direction.The p-well stripe is coupled to a first power supply voltage and the n-well stripe is coupled to a second power supply voltage.

[0115] In another aspect of the present disclosure, a memory device includes a first bank of memory arrays disposed over a substrate. The memory device includes a second bank of memory arrays disposed over the substrate and separated from the first bank along a first direction. The memory device includes a first stripe cell located between the first bank and the second bank, where the first stripe cell is directly interconnected with the first bank and the second bank. The memory device includes a second stripe cell interconnected with the first bank, opposite the first stripe cell along the first direction. The memory device includes a third stripe cell interconnected with the second bank, opposite the second stripe cell along the first direction. The first stripe cell has a first width along the first direction.The second stripe cell and the third stripe cell each have a second width along the first direction. The second width differs from the first width.

[0116] In yet another aspect of the present disclosure, a memory device includes a first memory device over a substrate and a second memory device over the substrate, a middle edge cell adjacent to each of the first memory device and the second memory device, an upper edge cell adjacent to the first memory device opposite the middle edge cell, and a lower edge cell adjacent to the second memory device opposite the middle edge cell. The first memory device includes a first memory array and a first stripe cell adjacent to the first memory array, where the first stripe cell and the first memory array are arranged along a first direction.The first stripe cell has a first well stripe electrically coupled to a first power supply voltage and a second well stripe electrically coupled to a second power supply voltage. The second memory device is aligned with the first memory device along a second direction perpendicular to the first direction. The second memory device has a second memory array aligned with the first memory array along the second direction. The middle edge cell has a first height along the second direction, the top edge cell has a second height along the second direction, and the bottom edge cell has a third height along the second direction where the first height is less than a sum of the second height and the third height.

[0117] As used herein, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0118] The foregoing outlines features of some embodiments so that those skilled in the art will better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can already use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 616,932

[0001]

Claims

[1] Storage device comprising: a first memory array disposed over a substrate; a second memory array disposed over the substrate and separated from the first memory array along a first direction; and a stripe cell defined in the substrate and located between the first memory array and the second memory array, the stripe cell comprising: a first boundary adjacent to the first memory array, a second boundary adjacent to the second memory array, the first boundary and the second boundary extending along a second direction perpendicular to the first direction, a p-well stripe disposed between the first boundary and the second boundary along the first direction, and an n-well stripe spaced from the p-well stripe along the second direction, wherein: the p-well strip is coupled to a first power supply voltage, and the n-well strip is coupled to a second power supply voltage. [2] The memory device of claim 1, wherein the first power supply voltage is electrical ground and wherein the second power supply voltage is a positive power supply voltage. [3] The memory device according to claim 1 or 2, wherein the stripe cell further comprises: an n-type transistor arranged adjacent to the p-well stripe along the first direction, the n-type transistor having a first gate terminal, and a p-type transistor disposed adjacent to the n-well stripe along the first direction, the p-well transistor having a second gate terminal, the first gate terminal and the second gate terminal being coupled to the first power supply voltage and the second power supply voltage, respectively. [4] A storage device according to any one of claims 1 to 3, further comprising: a p-doped region defined in the substrate and extending across the first memory array, the stripe cell, and the second memory array along the first direction, wherein the p-well stripe is disposed in the p-doped region; and an n-doped region defined in the substrate and extending across the first memory array, the stripe cell, and the second memory array along the first direction, wherein the n-well stripe is disposed in the n-doped region. [5] The memory device of claim 4, wherein the stripe cell further comprises: a first via coupling the p-well stripe to the first power supply voltage, and a second via coupling the n-well stripe to the second power supply voltage. [6] A storage device according to any one of claims 1 to 5, further comprising: a first peripheral circuit configured to control the first memory array; and a second peripheral circuit configured to control the second memory array, wherein the first peripheral circuit and the second peripheral circuit are arranged on opposite sides of the stripe cell. [7] Storage device comprising: a first bank of memory arrays disposed over a substrate; a second bank of memory arrays disposed above the substrate and separated from the first bank along a first direction; a first strip cell located between the first bank and the second bank, the first strip cell directly connecting the first bank and the second bank; a second strip cell connected to the first bank opposite to the first strip cell along the first direction; and a third strip cell connected to the second bank opposite to the second strip cell along the first direction, wherein: the first strip cell has a first width along the first direction, the second stripe cell and the third stripe cell each have a second width along the first direction, and the second width differs from the first width. [8] A storage device according to claim 7, wherein: the second width is less than the first width, and the first stripe cell has a p-well stripe and an n-well stripe spaced from the p-well stripe along a second direction perpendicular to the first direction, wherein: the p-well strip is coupled to a first power supply voltage, and the n-well strip is coupled to a second power supply voltage. [9] The memory device of claim 8, wherein the second stripe cell and the third stripe cell are electrically isolated from each of the first power supply voltage and the second power supply voltage. [10] A storage device according to claim 7, wherein: the second width is greater than the first width, the second stripe cell comprises a first p-well stripe and a first n-well stripe spaced from the first p-well stripe along a second direction perpendicular to the first direction, wherein: the first p-well stripe is coupled to a first power supply voltage, and the first n-well stripe is coupled to a second power supply voltage; and the third stripe cell has a second p-well stripe and a second n-well stripe spaced from the second p-well stripe along the second direction, wherein: the second p-well stripe is coupled to the first power supply voltage; and the second n-well strip is coupled to the second power supply voltage. [11] The memory device of claim 10, wherein the first stripe cell is electrically isolated from each of the first power supply voltage and the second power supply voltage. [12] The memory device of any one of claims 7 to 11, wherein the first bank comprises a first number of memory arrays arranged along a second direction perpendicular to the first direction, and wherein the second bank comprises a second number of memory arrays arranged along the second direction, the first number and the second number being greater than or equal to 1. [13] A storage device according to any one of claims 7 to 12, further comprising: a first peripheral circuit configured to control the first bank; and a second peripheral circuit configured to control the second bank, wherein the first peripheral circuit and the second peripheral circuit are arranged on opposite sides of the first stripe cell. [14] The memory device of any one of claims 7 to 13, further comprising a transition cell with the first stripe cell aligned along a second direction perpendicular to the first direction, the transition cell having a fourth width along the first direction, the fourth width being the same as the first width. [15] Semiconductor structure, comprising: a first memory device over a substrate, the first memory device comprising: a first memory array, and a first stripe cell adjacent to the first memory array, the first stripe cell and the first memory array being arranged along a first direction, the first stripe cell having a first well stripe electrically coupled to the first power supply voltage and a second well stripe electrically coupled to a second power supply voltage; a second memory device over the substrate and aligned with the first memory device along a second direction perpendicular to the first direction, the second memory device comprising a second memory array aligned with the first memory array along the second direction; a central edge cell adjacent to each of the first storage device and the second storage device, the central edge cell having a first height along the second direction, an upper edge cell adjacent to the first storage device opposite the middle edge cell, the upper edge cell having a second height along the second direction; and a lower edge cell adjacent to the second memory device opposite the middle edge cell, the lower edge cell having a third height along the second direction, the first height being less than a sum of the second height and the third height. [16] The semiconductor structure of claim 15, wherein the second memory device further comprises a second stripe cell adjacent to the second memory array along the first direction and aligned with the first stripe cell along the second direction, the second stripe cell having a third well stripe electrically coupled to the first power supply voltage and a fourth well stripe electrically coupled to the second power supply voltage. [17] The semiconductor structure of claim 16, wherein the middle edge cell is adjacent to one of the first memory array and the second memory array. [18] The semiconductor structure of claim 17, wherein the middle edge cell is adjacent to both the first memory array and the second memory array. [19] A semiconductor structure according to any one of claims 15 to 18, wherein: the first memory device further comprises a second stripe cell adjacent to the first memory array, the second stripe cell being opposite the first stripe cell along the first direction, the first strip cell has a first width along the first direction, the second stripe cell has a second width along the first direction, the second width being different from the first width, and the second strip cell is electrically isolated from the first power supply voltage and the second power supply voltage. [20] The semiconductor structure of claim 19, further comprising: a third memory array adjacent to the first memory array along the first direction, the third memory array adjacent to the first stripe cell; and a third stripe cell adjacent to the third memory array along the first direction, the third stripe cell being opposite the first stripe cell along the first direction, wherein: the third stripe cell has a third width along the first direction, the third width being the same as the second width, and the third strip cell is electrically isolated from the first power supply voltage and the second power supply voltage.

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