STORAGE DEVICE AND METHOD FOR OPERATING THE SAME

Abstract

An integrated circuit chip includes first and second memory cell arrays and first and second sets of bitlines. The first memory cell array has a first width in a first direction and a first height in a second direction. The second memory cell array has a second width in the first direction and a second height in the second direction. The first set of bitlines extends in the first direction, is coupled to the first memory cell array, overlaps the first memory cell array, and is located on a first metal layer. The second set of bitlines extends in the first direction, is coupled to the second memory cell array, overlaps the second memory cell array, and is located on the first metal layer. At least one of the first width and the second height is different from the second width.

Description

PRIORITY CLAIM

[0001] This application claims priority to U.S. Provisional Application No. 63 / 617,295, filed January 3, 2024, which is incorporated herein by reference in its entirety. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has developed a wide variety of digital devices to address problems in a number of different areas. Some of these digital devices, such as memory macros, are designed to store data. As ICs become smaller and more complex, the resistance of conductive lines within these digital devices also changes, affecting the operating voltages of these digital devices and overall IC performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 is a block diagram of a memory circuit, according to some embodiments. Fig. 2A is a circuit diagram of a memory circuit, according to some embodiments. Fig. 2B is a circuit diagram of a memory circuit, according to some embodiments. Fig. 3A-3B are corresponding circuit diagrams of corresponding memory cells 300A and 300B shown in Fig. 1 and 2A-2B may be used, according to some embodiments. Fig. 4A to 4C are respective schematic diagrams of a respective memory circuit 400A to 400C, according to some embodiments. Fig. 5A is a corresponding schematic diagram of a corresponding memory circuit 500A, according to some embodiments. Fig. 5B is a corresponding schematic diagram of a corresponding memory circuit 500B, according to some embodiments. Fig. Figure 5C is a cross-sectional view of an integrated circuit cut through the plane A-A'. Fig. Figure 5D is a cross-sectional view of an integrated circuit cut through the plane B-B'. Fig. Figure 5E is a cross-sectional view of an integrated circuit cut through the plane C-C'. Fig. Figure 5F is a cross-sectional view of an integrated circuit cut through the plane D-D'. Fig. 6 is a corresponding schematic diagram of a corresponding memory circuit 600, according to some embodiments. Fig. 7A-7B are respective schematic diagrams of a respective memory circuit 700A-700B, according to some embodiments. Fig. 8 is a corresponding schematic diagram of a corresponding memory circuit, according to some embodiments. Fig. 9 is a corresponding schematic diagram of a corresponding memory circuit, according to some embodiments. Fig. 10 is a schematic diagram of a memory circuit, according to some embodiments. Fig. 11 is a schematic diagram of a memory circuit, according to some embodiments. Fig. 12 is a schematic diagram of a memory circuit, according to some embodiments. Fig. 13 is a schematic diagram of a memory circuit, according to some embodiments. Fig. 14 is a schematic diagram of a memory circuit, according to some embodiments. Fig. 15 is a functional flow diagram of a method of manufacturing an integrated circuit, according to some embodiments. Fig. 16 is a flow diagram of a method of manufacturing an integrated circuit, according to some embodiments. Fig. 17 is a flow diagram of a method for generating a layout design of an integrated circuit, according to some embodiments. Fig. Fig. 18 is a schematic view of a system for designing an IC layout design and manufacturing an IC circuit, according to some embodiments. Fig. 19 is a block diagram of an IC manufacturing system and an associated IC manufacturing flow, according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides various embodiments, or examples, for implementing features of the present subject matter. Specific examples of components, materials, values, steps, arrangements, or the like are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like are contemplated. For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact.Furthermore, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is done for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] In addition, terms relating to spatial relativity, such as "beneath," "under," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0006] According to some embodiments, an integrated circuit chip includes a first memory cell array. In some embodiments, the first memory cell array has a first width in a first direction and a first height in a second direction. In some embodiments, the second direction is different from the first direction.

[0007] In some embodiments, the integrated circuit chip further includes a second memory cell array. In some embodiments, the second memory cell array has a second width in the first direction and a second height in the second direction.

[0008] In some embodiments, the integrated circuit chip further includes a first set of bit lines extending in the first direction. In some embodiments, the first set of bit lines is coupled to the first memory cell array. In some embodiments, the first set of bit lines overlaps the first memory cell array.

[0009] In some embodiments, the first set of bit lines is located on at least a first metal layer over a front surface of a substrate.

[0010] In some embodiments, the integrated circuit chip further includes a second set of bitlines extending in the first direction. In some embodiments, the second set of bitlines is coupled to the second memory cell array. In some embodiments, the second set of bitlines overlaps the second memory cell array. In some embodiments, the second set of bitlines is located on at least the first metal layer.

[0011] In some embodiments, at least the first width is different from the second width, or the first height is different from the second height.

[0012] In some embodiments, the integrated circuit chip further includes a first set of wordlines extending in the second direction. In some embodiments, the first set of wordlines extends in the second direction. In some embodiments, the first set of wordlines is coupled to the first memory cell array. In some embodiments, the first set of wordlines overlaps the first memory cell array. In some embodiments, the first set of wordlines is located on at least a second metal layer. In some embodiments, the second metal layer is different from the first metal layer.

[0013] In some embodiments, the integrated circuit chip further includes a second set of wordlines extending in the second direction.

[0014] In some embodiments, the second set of wordlines extends in the second direction. In some embodiments, the second set of wordlines is coupled to the second memory cell array. In some embodiments, the second set of wordlines overlaps the second memory cell array. In some embodiments, the second set of wordlines is located on at least the second metal layer.

[0015] In some embodiments, at least the first width is different from the second width, or the first height is different from the second height. Because at least the first width is different from the second width, or the first height is different from the second height, in some embodiments, the first memory cell array and the second memory cell array have different corresponding electrical characteristics.

[0016] In some embodiments, incorporating the first memory cell array and the second memory cell array with different corresponding electrical characteristics in the integrated circuit chip causes the integrated circuit chip to have a more flexible design than other approaches with the same cell type with the same type of electrical characteristics, resulting in improved performance than other approaches.

[0017] In some embodiments, the different corresponding electrical characteristics comprise one or more of a resistance / capacitance of the first set of bitlines, a resistance / capacitance of the second set of bitlines, a resistance / capacitance of the first set of wordlines, or a resistance / capacitance of the second set of wordlines.

[0018] Fig. 1 is a block diagram of a memory circuit 100, according to some embodiments.

[0019] Fig. 1 is simplified for illustrative purposes. In some embodiments, the memory circuit 100 includes various elements in addition to those shown in Fig. 1, or it is arranged in another manner to perform the operations discussed below.

[0020] The memory circuit 100 is an IC that includes memory partitions 102A to 102D, a global control circuit 100GC, and global input / output (GIO) circuits 100BL.

[0021] Each memory partition 102A to 102D includes memory banks 110U and 110L adjacent to a word line driver (WL driver) circuit 110AC and a local control circuit 110LC. Each memory bank 110U and 110L includes a memory cell array 110AR and a local input / output (LIO) circuit 110BS.

[0022] A memory partition, e.g., a memory partition 102A to 102D, represents a portion of the memory circuit 100 that contains a subset of memory devices (in Fig. 1 not shown) and adjacent circuits configured to selectively access the subset of memory devices during programming and reading operations. In the embodiment of Fig. 1, the memory circuit 100 has a total of four partitions. In some embodiments, the memory circuit 100 has a total number of partitions that is greater or less than four.

[0023] GIO circuitry 100BL is configured to control access to one or more electrical paths, e.g., bit lines, to each memory device of the corresponding memory bank 110U or 110L of each memory partition 102A to 102D, e.g., by generating one or more bit line signals. In some embodiments, GIO circuitry 100BL includes a global bit line driver circuit. In some embodiments, GIO circuitry 100BL is coupled to each memory bank 110U and 110L by a corresponding global bit line (not shown).

[0024] The global control circuit 100GC is configured to control some or all of the programming and reading operations on each memory partition 102A to 102D, e.g., by generating and / or issuing one or more control and / or enable signals.

[0025] In some embodiments, global control circuit 100GC includes one or more analog circuits configured to interface with memory partitions 102A-102D, cause data to be programmed into one or more memory devices, and / or use data received from one or more memory devices in one or more circuit operations. In some embodiments, global control circuit 100GC includes one or more global address decode or predecode circuits configured to output one or more address signals to WL driver circuit 110AC of each memory partition 102A-102D.

[0026] Each WL driver circuit 110AC is configured to generate wordline signals on corresponding wordlines WL. In some embodiments, each WL driver circuit 110AC is configured to output wordline signals on corresponding wordlines WL to the adjacent memory banks 110U and 110L of the respective memory partition 102A to 102D.

[0027] Each local control circuit 110LC represents an electronic circuit configured to receive one or more address signals. Each local control circuit 110LC is configured to generate signals corresponding to adjacent subgroups of memory devices identified by the one or more address signals. In some embodiments, the adjacent subgroups of memory devices correspond to columns of memory devices. In some embodiments, each local control circuit 110LC is configured to generate each signal as a complementary pair of signals. In some embodiments, each local control circuit 110LC is configured to output the signals to corresponding word power driver circuits within the adjacent WL driver circuit 110AC of the respective memory partition 102A-102D.In some embodiments, the local control circuit 110LC includes a bank decoder circuit.

[0028] Each LIO circuit 110BS is configured to access one or more bit lines (shown in Fig. 2A-2B) coupled to adjacent subgroups of memory devices of the respective memory cell array 110AR, in response to the GIO circuit 110BL, e.g., based on one or more BL control signals. In some embodiments, the adjacent subgroups of memory devices correspond to rows of memory devices. In some embodiments, the LIO circuit 110BS includes a bit line selection circuit.

[0029] Each LIO circuit 110BS includes one or more circuits 114. For ease of illustration, circuitry 114 in memory bank 110U and 110L of memory partitions 102B, 102C, and 102D is not shown. In some embodiments, each circuit 114 includes at least one sense amplifier circuit. In some embodiments, during a read operation, according to some embodiments, the sense amplifier circuit is configured to read data from at least one memory cell 112 in a corresponding column of memory cells in the respective memory cell array 110AR. In some embodiments, each circuit 114 in the LIO circuit 110BS is coupled to a corresponding column of memory devices 112 in the memory cell array 110AR.

[0030] Each memory bank 110U and 110L includes the corresponding memory cell array 110AR, which includes memory cells or memory devices 112 configured to be accessed in programming and reading operations by the adjacent LIO circuit 110BS and the adjacent WL driver circuit 110AC.

[0031] Each memory cell array 110AR includes an array of memory devices 112 having N rows and M columns, where M and N are positive integers. The rows of cells in the memory cell array 110AR are arranged in a first direction X. The columns of cells in the memory cell array 110AR are arranged in a second direction Y. The second direction is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array 110AR is divided into an upper region and a lower region (not shown). In some embodiments, each column of memory devices 112 in the memory cell array 110AR is coupled to a corresponding circuit 114 in the LIO circuit 110BS.

[0032] The storage device 112 is shown in memory bank 110U and 110L of memory partition 102A. For simplicity of illustration, the storage device 112 is not shown in memory bank 110U and 110L of memory partitions 102B, 102C, and 102D.

[0033] The memory device 112 is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by logical states. At least one logical state of the memory device 112 can be programmed in a write operation and detected in a read operation. In some embodiments, a logical state corresponds to a voltage level of an electrical charge stored in a given memory device 112. In some embodiments, a logical state corresponds to a physical property, e.g., a voltage, a current, a resistance, or a magnetic orientation, of a component of a given memory device 112.

[0034] In some embodiments, the memory device 112 includes one or more single-port static random access memory (SP-SRAM) cells. In some embodiments, the memory device 112 includes one or more dual-port SRAM (DP-SRAM) cells. In some embodiments, the memory device 112 includes one or more multi-port SRAM (multi-port SRAM) cells. Various types of memory cells in the memory device 112 are within the contemplated scope of the present disclosure. In some embodiments, the memory device 112 includes one or more dynamic random access memory (DRAM) cells. In some embodiments, the memory device 112 includes one or more one-time programmable (OTP) memory devices, such asElectronic fuse or antifuse devices (e-fuse or antifuse devices), flash memory devices, random access memory (RAM) devices, resistive RAM devices, ferroelectric RAM devices, magnetoresistive RAM devices, erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, or the like. In some embodiments, memory device 112 is an OTP memory device having one or more OTP memory cells.

[0035] Other embodiments of the memory circuit 100 are within the scope of the present disclosure.

[0036] Fig. 2A is a circuit diagram of a memory circuit 200A according to some embodiments.

[0037] The memory circuit 200A is an embodiment of the memory cell array 110AR of Fig. 1, and a similar detailed description is therefore omitted.

[0038] Components that are identical to those in one or more of Fig. 1 to 19 are the same or similar, are designated by the same reference numerals and a detailed description thereof is therefore omitted.

[0039] The memory circuit 200A includes a memory cell array 202 having M rows and N columns of memory cells MCB, where N is a positive integer corresponding to the number of columns in the memory cell array 202, and M is a positive integer corresponding to the number of rows in the memory cell array 202. The rows of cells in the memory cell array 202 are arranged in the first direction X. The columns of cells in the memory cell array 202 are arranged in the second direction Y.

[0040] In some embodiments, each memory cell MCB in memory cell array 202 is configured to store one bit of data. In some embodiments, memory circuit 200A is a logic-based memory.

[0041] The number of rows M in the memory cell array 202 is equal to or greater than 1. The number of columns N in the memory cell array 202 is equal to or greater than 1. Various types of memory cells MCB in the memory cell array 202 are within the contemplated scope of the present disclosure.

[0042] Memory circuit 200A also includes N bit lines BL[1], ... BL[N] (collectively referred to as "bit line BL"). Each column 1, ..., N in memory cell array 202 is overlapped and coupled to a corresponding bit line BL[1], ..., BL[N]. Each bit line BL extends in the second direction Y and across a column of cells (e.g., column 1, ..., N).

[0043] The memory circuit 200A also includes N bitline bars BLB[1], ..., BLB[N] (collectively referred to as a "bitline bar BLB"). Each column 1, ..., N in the memory cell array 202 is overlapped and coupled to a corresponding bitline bar BLB[1], ..., BLB[N]. Each bitline bar BLB extends in the second direction Y and across a column of cells (e.g., column 1, ..., N).

[0044] Memory circuit 200A also includes M word lines WL[1], ... WL[M] (collectively referred to as "word line WL"). Each row 1, ..., M in memory cell array 202 is overlapped and coupled to a corresponding word line WL[1], ..., WL[M]. Each word line WL extends in the first direction X and across a row of cells (e.g., row 1, ..., M).

[0045] The memory circuit 200A includes a region 201a. The region 201a includes two rows of memory cells MCB and two columns of memory cells MCB. The region 201a includes rows 1 and 2 of the memory circuit 200A and columns 1 and 2 of the memory circuit 200A. Other numbers of rows or columns of the region 201a are within the scope of the present disclosure. In some embodiments, the region 201a is arranged in other rows or columns of the memory circuit 200A.

[0046] Other configurations of memory circuit 200A are within the scope of the present disclosure. In some embodiments, one or more of the bit lines BL, the bit line bars BLB, or the word lines WL are not included in memory circuit 200A. In some embodiments, one or more of the bit lines BL, the bit line bars BLB, or the word lines WL are replaced by a corresponding source line SL. In some embodiments, one or more source lines SL are added.

[0047] Fig. 2B is a circuit diagram of a memory circuit 200B, according to some embodiments.

[0048] The memory circuit 200B represents a modification of the memory circuit 200A of Fig. 2A and a similar detailed description is therefore omitted. In comparison with the memory circuit 200A of Fig. 2A are word lines WL of Fig. 2A by write word lines WWL of Fig. 2B, and a similar detailed description is therefore omitted. In comparison with the memory circuit 200A of Fig. 2A are the M word lines WL[1], ... WL[M] of Fig. 2A through M corresponding write word lines WWL[1], ... WWL[M] (collectively referred to as “write word line WWL”) of Fig. 2B, and a similar detailed description is therefore omitted.

[0049] Compared with the 200A storage circuit from Fig. 2A, the memory circuit 200B further includes N read bit lines RBL[1], ... RBL[N] and M read word lines RWL[1], ... RWL[M], and a similar detailed description is therefore omitted.

[0050] The memory circuit 200B represents an embodiment of the memory cell array of Fig. 1, and a similar detailed description is therefore omitted.

[0051] The memory circuit 200A includes the memory cell array 202, the bit line BL, the bit line bar BLB, and the write word line WWL.

[0052] Memory circuit 200B also includes N read bit lines RBL[1], ..., RBL[N] (collectively referred to as "read bit line RBL"). Each column 1, ..., N in memory cell array 202 is overlapped and coupled to a corresponding read bit line RBL[1], ..., RBL[N]. Each read bit line RBL extends in the second direction Y and across a column of cells (e.g., column 1, ..., N).

[0053] Memory circuit 200B also includes M read word lines RWL[1], ..., RWL[M] (collectively referred to as "read word line RWL"). Each row 1, ..., M in memory cell array 202 is overlapped and coupled to a corresponding read word line RWL[1], ..., RWL[M]. Each read word line RWL extends in the first direction X and across a row of cells (e.g., row 1, ..., M).

[0054] Memory circuit 200B includes a region 201b. Region 201b includes two rows of memory cells MCB and two columns of memory cells MCB. Region 201b includes rows 1 and 2 of memory circuit 200B and columns 1 and 2 of memory circuit 200B. Other numbers of rows or columns of region 201b are within the scope of the present disclosure. In some embodiments, region 201b is arranged in other rows or columns of memory circuit 200B.

[0055] Other configurations of memory circuit 200B are within the scope of the present disclosure. In some embodiments, one or more of the bit lines BL, the bit line bars BLB, the read bit lines RBL, the write word lines WWL, or the read word lines RWL are not included in memory circuit 200B. In some embodiments, one or more of the bit lines BL, the bit line bars BLB, the read bit lines RBL, the write word lines WWL, or the read word lines RWL are replaced by a corresponding source line SL. In some embodiments, one or more source lines SL are added.

[0056] Fig. 3A-3B are corresponding circuit diagrams of corresponding memory cells 300A and 300B shown in Fig. 1 and 2A-2B may be used, according to some embodiments.

[0057] Fig. 3A is a circuit diagram of a memory cell 300A used in Fig. 1 and 2A-2B, according to some embodiments.

[0058] At least one of the memory cells 300A or 300B may be configured as one or more memory cells MCB in at least one of the memory cell array 110AR of Fig. 1 or the storage device 112 of Fig. 1 can be used.

[0059] At least one of the memory cells 300A or 300B may be configured as one or more memory cells MCB in at least one of the memory circuit 200A of Fig. 2A or the storage circuit 200A of Fig. 2B can be used.

[0060] Memory cell 300A is a six-transistor (6T) single-port SRAM (SP-SRAM) memory cell used for illustration purposes. In some embodiments, memory cell 300A uses a number of transistors other than eight. Other memory types are within the scope of various embodiments.

[0061] Memory cell 300A includes two P-type field-effect transistors (PFET transistors) P2-1 and P2-2, and four NFET transistors N2-1, N2-2, N2-3, and N2-4. PFET transistors P2-1 and P2-2 and NFET transistors N2-1 and N2-2 form a cross-latch or a pair of cross-coupled inverters. For example, PFET transistor P2-1 and NFET transistor N2-1 form a first inverter, while PFET transistor P2-2 and NFET transistor N2-2 form a second inverter.

[0062] A source terminal of each of the PFET transistors P2-1 and P2-2 is configured as a power supply node NODE_1. Each power supply node NODE_1 is coupled to a first power supply VDDI.

[0063] All of a drain terminal of the PFET transistor P2-1, a drain terminal of the NFET transistor N2-1, a gate terminal of the PFET transistor P2-2, a gate terminal of the NFET transistor N2-2, and a source terminal of the NFET transistor N2-3 are coupled together and are configured as a storage node ND.

[0064] All of a drain terminal of the PFET transistor P2-2, a drain terminal of the NFET transistor N2-2, a gate terminal of the PFET transistor P2-1, a gate terminal of the NFET transistor N2-1, and a source terminal of the NFET transistor N2-4 are coupled together and are configured as a storage node NDB.

[0065] A source terminal of each of the NFET transistors N2-1 and N2-2 is configured as a supply reference voltage node (not labeled) having a supply reference voltage VSS. The source terminal of each of the NFET transistors N2-1 and N2-2 is also coupled to the supply reference voltage VSS.

[0066] A word line WL is coupled to a gate terminal of each of the NFET transistors N2-3 and N2-4. The word line WL is also referred to as a write control line because the NFET transistors N2-3 and N2-4 are configured to be controlled by a signal on the word line WL to transfer data between bit lines BL, BLB and corresponding nodes ND, NDB.

[0067] A drain terminal of the NFET transistor N2-3 is coupled to a bit line BL. A drain terminal of the NFET transistor N2-4 is coupled to a bit line BLB.

[0068] The bit lines BL and the bit line bars BLB are configured as both data input and output for the memory cell 200A. In some embodiments, during a write operation, applying a logic value to a bit line BL and the opposite logic value to the bit line bar BLB enables the logic values on the bit lines and the bit line bars to be written to the memory cell 200A. Each of the bit lines BL and the bit line bar BLB is referred to as a data line because the data carried on the bit lines BL and the bit line bar BLB is written to and read from the corresponding nodes ND and NDB.

[0069] Other configurations of the memory cell 300A are within the scope of the present disclosure.

[0070] Fig. 3B is a circuit diagram of a memory cell 300B used in Fig. 1 and 2A-2B, according to some embodiments.

[0071] The memory cell 300B represents a modification of the memory cell 300A of Fig. 3A and a similar detailed description is therefore omitted. In comparison with the memory cell 300A of Fig. 3A, the memory cell 300B also includes NFET transistors N2-5 and N2-6, and a similar detailed description is therefore omitted.

[0072] Memory cell 300B is an eight-transistor (8T), one-read / one-write (1R / 1W), two-terminal (2P) SRAM memory cell used for illustration purposes. In some embodiments, memory cell 300B uses a number of transistors other than eight. Other types of memory cells are within the scope of various embodiments.

[0073] Compared with the 300A storage cell from Fig. 3A, the word line rod WLB replaces the word line WL, and a similar detailed description is therefore omitted.

[0074] The memory cell 300B includes the PFET transistors P2-1 and P2-2, and the NFET transistors N2-1, N2-2, N2-3, N2-4, N2-5, and N2-6.

[0075] All of a drain terminal of the PFET transistor P2-1, a drain terminal of the NFET transistor N2-1, a gate terminal of the PFET transistor P2-2, a gate terminal of the NFET transistor N2-2, a source terminal of the NFET transistor N2-4, and a gate terminal of the NFET transistor N2-5 are coupled together and are configured as a storage node ND.

[0076] All of a drain terminal of the PFET transistor P2-2, a drain terminal of the NFET transistor N2-2, a gate terminal of the PFET transistor P2-1, a gate terminal of the NFET transistor N2-1, and a source terminal of the NFET transistor N2-3 are coupled together and are configured as a storage node NDB.

[0077] A drain terminal of the NFET transistor N2-3 is coupled to a write bit line WBL. A drain terminal of the NFET transistor N2-4 is coupled to a write bit line bar WBLB.

[0078] A source terminal of NFET transistor N2-5 is configured as a supply reference voltage node (not labeled) having a supply reference voltage VSS. The source terminal of NFET transistor N2-5 is also coupled to the supply reference voltage VSS.

[0079] All of a drain terminal of the NFET transistor N2-5 and a source terminal of the NFET transistor N2-6 are coupled together.

[0080] A drain terminal of the NFET transistor N2-6 is coupled to a read bit line RBL.

[0081] A write word line WWL is coupled to a gate terminal of each of the NFET transistors N2-3 and N2-4. The write word line WWL is also referred to as a write control line because the NFET transistors N2-3 and N2-4 are configured to be controlled by a signal on the write word line WWL to transfer data between write bit lines WBL, WBLB and corresponding nodes ND, NDB.

[0082] A read word line RWL is coupled to a gate terminal of the NFET transistor N2-6. The read word line RWL is also referred to as a read control line because the NFET transistor N2-6 is configured to be controlled by a signal on the read word line RWL to transmit data to the read bit line RBL.

[0083] In some embodiments, NFET transistor N2-5 is referred to as a read pull-down (RPD) transistor. In some embodiments, NFET transistor N2-6 is referred to as a read pass-gate (read RPG) transistor.

[0084] Other configurations of the memory cell 300B are within the scope of the present disclosure.

[0085] Fig. 4A to 4C are respective schematic diagrams of a respective memory circuit 400A to 400C, according to some embodiments.

[0086] Fig. 4A is a schematic diagram of a memory circuit 400A, according to some embodiments.

[0087] The memory circuit 400A is associated with the memory cell array 202 of Fig. 2A. The memory circuit 400A represents an embodiment of the region 201a of the memory circuit 200A of Fig. 2A and a similar detailed description is therefore omitted. In some embodiments, memory circuit 400A is an embodiment of the portions of memory circuit 200A separated from portion 201a of memory circuit 200A of Fig. 2A are different.

[0088] The memory circuit 400A includes a memory cell array 401. The memory circuit 400A is a schematic representation of two adjacent columns and two adjacent rows of a memory cell array 401. In some embodiments, the memory circuit 400 is a schematic representation of columns 1 and 2 of the memory cell array 202 of Fig. 2A and rows 1 and 2 of the memory cell array 202 of Fig. 2A, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 400 is a schematic representation of other columns or other rows of the memory cell array 202 of Fig. 2A, and not columns 1 and 2 or rows 1 and 2 of the memory cell array 202 of Fig. 2A, and a similar detailed description is therefore omitted.

[0089] The memory circuits 400A to 400C are manufactured by a corresponding layout design similar to the memory circuits 400A to 400C. For the sake of brevity, Fig. 4A, 4B, 4C, 5A-5B, 6, 7A, 7B, 8, 9, 10, 11, 12, 13, 14 and 15 are described as a corresponding integrated circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400 and 1500, but in some embodiments, each of Fig. 4A, Fig. 4B, Fig. 4C, Fig. 5, Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 and Fig. 15 also represents a corresponding layout design, and each structural element of the integrated circuit 400A, 400B, 400C, 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400 and 1500 is a corresponding layout structure, and structural relationships having orientation, lengths and widths, as well as configurations and layers of a corresponding layout design of the integrated circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400 and 1500 are the structural relationships and configurations and layers of the integrated circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400 and 1500 are similar, and a similar detailed description is not described for the sake of brevity.

[0090] The memory cell array 401 is similar to the memory cell array 202 of Fig. 2A, and a similar detailed description is therefore omitted.

[0091] The memory cell array 401 includes memory cells 401a, 401b, 401c and 401d.

[0092] The memory cell 401a is located in row 1 and column 1 of the memory cell array 401, and is in Fig. 4A as “r1c1”. The memory cell 401b is located in row 1 and column 2 of the memory cell array 401, and is in Fig. 4A as “r1c2”. The memory cell 401c is located in row 2 and column 1 of the memory cell array 401, and is in Fig. 4A as “r2c1”. The memory cell 401d is located in row 2 and column 2 of the memory cell array 401, and is in Fig. 4A is marked as “r2c2”.

[0093] The memory cell array 401 is in Fig. 4A as a 2 x 2 memory cell array. Other numbers of rows and columns are within the scope of the present disclosure.

[0094] The memory cell array 401 has a height H1a in the first direction X. In some embodiments, the height H1a is equal to 2CH, where CH is a scaled cell height in the first direction X of at least one of the memory cells 401a, 401b, 401c, or 401d in the memory cell array 401. In some embodiments, the cell height of the memory cells in one of the memory cell array 401, 411, 421, 701 or 721 or the memory circuit 500A-500B, 600, 800 or 900 is scaled (e.g., scaled cell height) with a corresponding cell height of another memory cell in the memory cell array 401, 411, 421, 701 or 721 or the memory circuit 500A-500B, 600, 800 or 900.

[0095] The memory cell array 401 has a width W1a in the second direction Y. In some embodiments, the width W1a is equal to 2CW, where CW is a scaled cell width in the second direction Y of at least one of the memory cells 401a, 401b, 401c, or 401d in the memory cell array 401. In some embodiments, the cell width of the memory cells in one of the memory cell array 401, 411, 421, 701 or 721 or the memory circuit 500A-500B, 600, 800 or 900 is scaled (e.g., scaled cell width) with a corresponding cell width of another memory cell in the memory cell array 401, 411, 421, 701 or 721 or the memory circuit 500A-500B, 600, 800 or 900.

[0096] In some embodiments, the memory cell array 401 has a width in the second direction Y that is equal to 2 contacted polysilicon pitches (e.g., 2CPP).

[0097] In some embodiments, the memory cell array 401 has an aspect ratio AR1a that is equal to 1:1 (e.g., W1a / H1a).

[0098] The memory circuit 400A also includes bit lines BL[1] and BL[2] (collectively referred to as a “set of bit lines BL”), bit line bars BLB[1] and BLB[2] (collectively referred to as a “set of bit line bars BLB”), and word lines WL[1] and WL[2] (collectively referred to as a “set of word lines WL”).

[0099] In some embodiments, the memory cells 401a, 401b, 401c and 401d corresponding to memory cells MCB in the same corresponding rows and the same corresponding columns of the area 201a of Fig. 2A, and a similar detailed description is therefore omitted. In some embodiments, each of the memory cells 401a, 401b, 401c, and 401d is the memory cell 300A of FIG. 3A, and a similar detailed description is therefore omitted.

[0100] In some embodiments, the bit lines BL[1] and BL[2] are corresponding to bit lines BL[1] and BL[2] of Fig. 2A, and a similar detailed description is therefore omitted.

[0101] In some embodiments, the bitline bars BLB[1] and BLB[2] are corresponding bitline bars BLB[1] and BLB[2] of Fig. 2A, and a similar detailed description is therefore omitted.

[0102] In some embodiments, the word lines WL[1] and WL[2] are corresponding word lines WL[1] and WL[2] of Fig. 2A, and a similar detailed description is therefore omitted.

[0103] The set of bit lines BL and the set of bit line bars BLB extend in the second direction Y.

[0104] Bitline BL[1] and bitline bar BLB[1] overlap memory cells 401a and 401c. Bitline BL[1] is electrically coupled to memory cells 401a and 401c by a via 404a. Bitline bar BLB[1] is electrically coupled to memory cell 401a by a via 404a and to memory cell 401c by a via 404e.

[0105] Bitline BL[2] and bitline bar BLB[2] overlap memory cells 401b and 401d. Bitline BL[2] is electrically coupled to memory cells 401b and 401d via a via 404d. Bitline bar BLB[2] is electrically coupled to memory cell 401b via a via 404c and to memory cell 401d via a via 404f.

[0106] In some embodiments, the set of bitlines BL is located in a metal two layer (M2 layer) of at least one of the memory circuit 400A, 400B, 400C, 700A, or 700B. In some embodiments, the set of bitlines BL is located in a metal one layer (M1 layer) of at least one of the memory circuit 400A, 400B, 400C, 700A, or 700B. Other metal layers for the set of bitlines BL are within the scope of the present disclosure.

[0107] In some embodiments, the set of bitline bars BLB is located in the M2 layer of at least one of the memory circuit 400A, 400B, 400C, 700A, or 700B. In some embodiments, the set of bitline bars BLB is located in the M1 layer of at least one of the memory circuit 400A, 400B, 400C, 700A, or 700B. Other metal layers for the set of bitline bars BLB are within the scope of the present disclosure.

[0108] Other configurations, arrangements on other metal layers or numbers of bit lines in the set of bit lines BL are within the scope of the present disclosure.

[0109] Other configurations, arrangements on other metal layers or numbers of bit line bars in the set of bit line bars BLB are within the scope of the present disclosure.

[0110] The set of word lines WL extends in the first direction X.

[0111] The word line WL[1] overlaps the memory cells 401a and 401b. The word line WL[1] is electrically coupled to the memory cell 401a via vias 402a and 402b. The word line WL[1] is electrically coupled to the memory cell 401b via vias 402b and 402c.

[0112] The word line WL[2] overlaps the memory cells 401c and 401d. The word line WL[2] is electrically coupled to the memory cell 401c via vias 402d and 402e. The word line WL[2] is electrically coupled to the memory cell 401d via vias 402e and 402f.

[0113] In some embodiments, the set of word lines WL is located in an M1 layer of at least one of the memory circuit 400A, 400B, 400C, 700A, or 700B. In some embodiments, the set of word lines WL is located in a metal zero (Mo) layer of at least one of the memory circuit 400A, 400B, 400C, 700A, or 700B. In some embodiments, the set of word lines WL is located in an M2 layer of at least one of the memory circuit 400A, 400B, 400C, 700A, or 700B. Other metal layers for the set of word lines WL are within the scope of the present disclosure.

[0114] In some embodiments, the set of word lines WL is located in a polysilicon (POLY) layer of at least one of the memory circuits 400A, 400B, 400C, 700A, or 700B.

[0115] In some embodiments, the POLY layer is located beneath the Mo layer and the M1 layer. In some embodiments, the Mo layer is located beneath the M1 layer and the M2 layer. In some embodiments, the M1 layer is located beneath the M2 layer. In some embodiments, the term "layer(s)" and the term "level(s)" are used interchangeably.

[0116] Other configurations, arrangements on other metal layers or numbers of word lines in the set of word lines WL are within the scope of the present disclosure.

[0117] The memory circuit 400A also includes one or more vias 402a, 402b, 402c, 402d, 402e, or 402f (collectively referred to as a “set of vias 402”).

[0118] In some embodiments, the set of vias 402 is formed by a corresponding set of via structures (not shown) of a corresponding layout design of the memory circuit 400A to 400C or 700A-700B. In some embodiments, the vias 402a, 402b, 402c, 402d of the set of vias 402 are formed by corresponding via structures (not shown) of the set of via structures (not shown) of a corresponding layout design of the memory circuit 400A to 400C or 700A-700B.

[0119] The set of vias 402 is located between the set of word lines WL and underlying layers (e.g. in Fig. 5, Fig. 6, Fig. 8 or Fig. 9) of the memory cell array 401. In some embodiments, the set of vias 402 is located between the set of word lines WL and at least one memory cell 401a, 401b, 401c, or 401d of the memory cell array 401.

[0120] In some embodiments, vias 402a and 402b are located between wordline WL[1] and memory cell 401a. In some embodiments, vias 402b and 402c are located between wordline WL[1] and memory cell 401b.

[0121] In some embodiments, vias 402d and 402e are located between wordline WL[2] and memory cell 401c. In some embodiments, vias 402e and 402f are located between wordline WL[2] and memory cell 401d.

[0122] The set of vias 402 is arranged on one or more of a VD level (via via diffusion), a VG level (via via gate), a V0 level (via via M0), or a V1 level (via via M1) of the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700C, 800, or 900.

[0123] In some embodiments, the VD plane is located above at least one of an oxide diffusion (OD) plane, the POLY plane, or the MD (metal over diffusion) plane. In some embodiments, the VG plane is located above at least one of the OD plane, the POLY plane, or the MD plane. In some embodiments, the V0 plane is located above at least one of the OD plane, the POLY plane, the MD plane, or the M0 plane. In some embodiments, the V1 plane is located above at least one of the OD plane, the POLY plane, the MD plane, the M0 plane, or the M1 plane.

[0124] In some embodiments, the VD plane is located below at least one of the Mo plane, the M1 plane, or the M2 plane. In some embodiments, the VG plane is located below at least one of the Mo plane, the M1 plane, or the M2 plane. In some embodiments, the V0 plane is located below at least one of the M1 plane or the M2 plane. In some embodiments, the V1 plane is located below at least the M2 plane. Other planes are within the scope of the present disclosure.

[0125] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 402 are within the scope of the present disclosure.

[0126] The memory circuit 400A also includes one or more vias 404a, 404b, 404C, 404d, 404e, or 404f (collectively referred to as a “set of vias 404”).

[0127] In some embodiments, the set of vias 404 is formed by a corresponding set of via structures (not shown) of a corresponding layout design of the memory circuit 400A to 400C or 700A-700B. In some embodiments, the set of vias 404a, 404b, 404c, 404d of the set of vias 404 is formed by corresponding via structures (not shown) of the set of via structures (not shown) of a corresponding layout design of the memory circuit 400A to 400C or 700A-700B.

[0128] The set of vias 404 is located between at least one of the set of bit lines BL or the set of bit power bars BLB and underlying layers (e.g., in Fig. 5, Fig. 6, Fig. 8 or Fig. 9) of the memory cell array 401. In some embodiments, the set of vias 404 is located between at least one of the set of bit lines BL or the set of bit line bars BLB and at least one memory cell 401a, 401b, 401c, or 401d of the memory cell array 401.

[0129] In some embodiments, the via 404a is located between the bit line BL[1] and the memory cells 401a and 401c.

[0130] In some embodiments, the via 404b is located between the bitline bar BLB[1] and the memory cell 401a, and the via 404e is located between the bitline bar BLB[1] and the memory cell 401c.

[0131] In some embodiments, the via 404d is located between the bit line BL[2] and the memory cells 401b and 401d.

[0132] In some embodiments, the via 404c is located between the bitline bar BLB[2] and the memory cell 401b, and the via 404f is located between the bitline bar BLB[2] and the memory cell 401d.

[0133] The set of vias 404 is disposed on one or more of the VD level, the VG level, the V0 level, or the V1 level of the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700C, 800, or 900. In some embodiments, the V1 level is located above at least one of the OD level, the POLY level, the MD level, the M0 level, or the M1 level.

[0134] In some embodiments, the V1 plane is located below the M2 plane.

[0135] Other levels for at least one of the set of vias 402 or 404 are within the scope of the present disclosure.

[0136] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 404 are within the scope of the present disclosure.

[0137] Other embodiments of the memory circuit 400A are within the scope of the present disclosure.

[0138] Fig. 4B is a schematic diagram of a memory circuit 400B, according to some embodiments.

[0139] The memory circuit 400B is associated with the memory cell array 202 of Fig. 2A. The memory circuit 400B represents an embodiment of the region 201a of the memory circuit 200A of Fig. 2A, and a similar detailed description is therefore omitted. In some embodiments, memory circuit 400B is an embodiment of the portions of memory circuit 200A separated from portion 201a of memory circuit 200A of Fig. 2A are different.

[0140] The memory circuit 400B represents a modification of the memory circuit 400A of Fig. 4A, and a similar detailed description is therefore omitted. In comparison with the memory circuit 400A of Fig. 4A replaces a memory cell array 411 of Fig. 4B the memory cell array 401 of Fig. 4A, and a similar detailed description is therefore omitted.

[0141] The memory circuit 400B has a memory cell array 411. The memory cell array 411 is similar to the memory cell array 202 of Fig. 2A or the memory cell array 401 of Fig. 4A, and a similar detailed description is therefore omitted.

[0142] The memory cell array 411 includes memory cells 411a, 411b, 411c, and 411d. In some embodiments, at least one of the memory cells 411a, 411b, 411c, or 411d is at least one of the memory cells 401a, 401b, 401c, or 401d of the memory cell array 401 of Fig. 4A, and a similar detailed description is therefore omitted.

[0143] The memory cell 411a is located in row 1 and column 1 of the memory cell array 411, and is in Fig. 4B as “r1c1”. The memory cell 411b is located in row 1 and column 2 of the memory cell array 411, and is in Fig. 4B as “r1c2”. The memory cell 411c is located in row 2 and column 1 of the memory cell array 411, and is in Fig. 4B as “r2c1”. The memory cell 411d is located in row 2 and column 2 of the memory cell array 411, and is in Fig. 4B is marked as “r2c2”.

[0144] The memory cell array 411 is in Fig. 4B as a 2 x 2 memory cell array. Other numbers of rows and columns are within the scope of the present disclosure.

[0145] The memory cell array 411 has a height H1b in the first direction X. In some embodiments, the height H1b is equal to 1CH, where 0.5CH is the scaled cell height in the first direction X of at least one of the memory cells 411a, 411b, 411c, or 411d in the memory cell array 411.

[0146] The memory cell array 411 has a width W1b in the second direction Y. In some embodiments, the width W1b is equal to 4CW, where 2CW is the scaled cell width in the second direction Y of at least one of the memory cells 411a, 411b, 411c, or 411d in the memory cell array 411.

[0147] In some embodiments, the memory cell array 411 has a width in the second direction Y that is equal to 4 contacted polysilicon pitches (e.g., 4CPP).

[0148] In some embodiments, the memory cell array 411 has an aspect ratio AR1b equal to 4:1 (e.g., W1b / H1b).

[0149] The memory circuit 400B also includes the set of bit lines BL, the set of bit line bars BLB, and the set of word lines WL.

[0150] In some embodiments, the memory cells 411a, 411b, 411c and 411d corresponding to memory cells MCB in the same corresponding rows and the same corresponding columns of the area 201a of Fig. 2A, and a similar detailed description is therefore omitted. In some embodiments, each of the memory cells 411a, 411b, 411c, and 411d is the memory cell 300A of FIG. 3A, and a similar detailed description is therefore omitted.

[0151] The set of bit lines BL and the set of bit line bars BLB extend in the second direction Y.

[0152] Bitline BL[1] and bitline bar BLB[1] overlap memory cells 411a and 411c. Bitline bar BLB[1] is electrically coupled to memory cells 411a and 411c via a via 414b. Bitline BL[1] is electrically coupled to memory cell 411a via a via 414b and to memory cell 411c via a via 414e.

[0153] Bitline BL[2] and bitline bar BLB[2] overlap memory cells 411b and 411d. Bitline bar BLB[2] is electrically coupled to memory cells 411b and 411d via a via 414d. Bitline BL[2] is electrically coupled to memory cell 411b via a via 414c and to memory cell 411d via a via 414f.

[0154] Other configurations, arrangements on other metal layers or numbers of bit lines in the set of bit lines BL are within the scope of the present disclosure.

[0155] Other configurations, arrangements on other metal layers or numbers of bit line bars in the set of bit line bars BLB are within the scope of the present disclosure.

[0156] The set of word lines WL extends in the first direction X.

[0157] The word line WL[1] overlaps the memory cells 411a and 411b. The word line WL[1] is electrically coupled to the memory cell 411a via a via 412a. The word line WL[1] is electrically coupled to the memory cell 411b via a via 412b.

[0158] The word line WL[2] overlaps the memory cells 411c and 411d. The word line WL[2] is electrically coupled to the memory cell 411c via a via 412c. The word line WL[2] is electrically coupled to the memory cell 411d via a via 412d.

[0159] Other configurations, arrangements on other metal layers or numbers of word lines in the set of word lines WL are within the scope of the present disclosure.

[0160] The memory circuit 400B also includes one or more vias 412a, 412b, 412c, or 412d (collectively referred to as a “set of vias 412”).

[0161] In some embodiments, the set of vias 412 is the same as the set of vias 402 of Fig. 4A, and a similar detailed description is therefore omitted. In some embodiments, at least one of the vias 412a, 412b, 412c, or 412d is at least one or more of the vias 402a, 402b, 402c, 402d, 402e, or 402f of the set of vias 402 of Fig. 4A, and a similar detailed description is therefore omitted.

[0162] In some embodiments, via 412a is located between wordline WL[1] and memory cell 411a. In some embodiments, via 412b is located between wordline WL[1] and memory cell 411b.

[0163] In some embodiments, via 412c is located between wordline WL[2] and memory cell 411c. In some embodiments, via 412b is located between wordline WL[2] and memory cell 411d.

[0164] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 412 are within the scope of the present disclosure.

[0165] The memory circuit 400B also includes one or more vias 414a, 414b, 414c, 414d, 414e, or 414f (collectively referred to as a “set of vias 414”).

[0166] In some embodiments, the set of vias 414 is the same as the set of vias 404 of Fig. 4A, and a similar detailed description is therefore omitted. In some embodiments, at least one of the vias 414a, 414b, 414c, 414d, 414e, or 414f is at least one or more of the vias 404a, 404b, 404c, 404d, 404e, or 404f of the set of vias 404 of Fig. 4A, and a similar detailed description is therefore omitted.

[0167] In some embodiments, via 414b is located between bitline bar BLB[1] and memory cells 411a and 411c. In some embodiments, via 414a is located between bitline BL[1] and memory cell 411a, and via 414e is located between bitline BL[1] and memory cell 411c.

[0168] In some embodiments, via 414d is located between bitline bar BLB[2] and memory cells 411b and 411d. In some embodiments, via 414c is located between bitline BL[2] and memory cell 411b, and via 414f is located between bitline BL[2] and memory cell 411d.

[0169] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 414 are within the scope of the present disclosure.

[0170] Other embodiments of the memory circuit 400B are within the scope of the present disclosure.

[0171] Fig. 4C is a schematic diagram of a memory circuit 400C, according to some embodiments.

[0172] The memory circuit 400C is associated with the memory cell array 202 of Fig. 2A. The memory circuit 400C is an embodiment of the portion 201a of the memory circuit 200A of Fig. 2A, and a similar detailed description is therefore omitted. In some embodiments, memory circuit 400C is an embodiment of the portions of memory circuit 200A separated from portion 201 of memory circuit 200A of Fig. 2A are different.

[0173] The memory circuit 400C is a modification of the memory circuit 400A of Fig. 4A or the memory circuit 200B of Fig. 4B, and a similar detailed description is therefore omitted. In comparison with the memory circuit 400A of Fig. 4A replaces a memory cell array 421 of Fig. 4B the memory cell array 401 of Fig. 4A, and a similar detailed description is therefore omitted.

[0174] The memory circuit 400C has a memory cell array 421. The memory cell array 421 is similar to the memory cell array 202 of Fig. 2A, the memory cell array 401 of Fig. 4A or the memory cell array 411 of Fig. 4B, and a similar detailed description is therefore omitted.

[0175] The memory cell array 421 includes memory cells 421a, 421b, 421c, and 421d. In some embodiments, at least one of the memory cells 421a, 421b, 421c, or 421d is at least one of the memory cells 401a, 401b, 401c, or 401d of the memory cell array 401 of Fig. 4A or at least one of the memory cells 411a, 411b, 411c or 411d of the memory cell array 411 of Fig. 4B, and a similar detailed description is therefore omitted.

[0176] The memory cell 421a is located in row 1 and column 1 of the memory cell array 421, and is in Fig. 4C as “r1c1”. The memory cell 421b is located in row 2 and column 1 of the memory cell array 421, and is in Fig. 4C is labeled “r2c1”. The memory cell 421c is located in row 1 and column 2 of the memory cell array 421, and is in Fig. 4C as “r1c2”. The memory cell 411d is located in row 2 and column 2 of the memory cell array 421, and is in Fig. 4C is marked as “r2c2”.

[0177] The memory cell array 421 is in Fig. 4C as a 2 x 2 memory cell array. Other numbers of rows and columns are within the scope of the present disclosure.

[0178] The memory cell array 421 has a height H1c in the first direction X. In some embodiments, the height H1c is equal to 2CH, where CH is the scaled cell height in the first direction X of at least one of the memory cells 421a, 421b, 421c, or 421d in the memory cell array 421.

[0179] The memory cell array 421 has a width W1c in the second direction Y. In some embodiments, the width W1c is equal to 2CW, where 2CW is the scaled cell width in the second direction Y of at least one of the memory cells 421a, 421b, 421c, or 421d in the memory cell array 421.

[0180] In some embodiments, the memory cell array 421 has a width in the second direction Y that is equal to 4 contacted polysilicon pitches (e.g., 4CPP).

[0181] In some embodiments, the memory cell array 421 has an aspect ratio AR1c that is equal to 1:1 (e.g., W1c / H1c).

[0182] The memory circuit 400C also includes the set of bit lines BL, the set of bit line bars BLB, and the set of word lines WL.

[0183] In some embodiments, the memory cells 421a, 421b, 421c and 421d corresponding to memory cells MCB in the same corresponding rows and the same corresponding columns of the area 201a of Fig. 2A, and a similar detailed description is therefore omitted. In some embodiments, each of the memory cells 421a, 421b, 421c, and 421d is the memory cell 300A of FIG. 3A, and a similar detailed description is therefore omitted.

[0184] The set of bit lines BL and the set of bit line bars BLB extend in the second direction Y.

[0185] Bitline BL[1] overlaps memory cell 421a. Bitline BL[1] is electrically coupled to memory cell 421a via a via 424a. In some embodiments, bitline BL[1] is electrically coupled to memory cell 421a and memory cell 421b (not shown), and bitline BL[1] is shared between memory cell 421a and memory cell 421b. In other words, adjacent memory cells (e.g., memory cells 421b and 421a) in memory circuit 400C are configured to share BLs.

[0186] Bitline bar BLB[1] overlaps memory cell 421b. Bitline bar BLB[1] is electrically coupled to memory cell 421b via a via 424b. In some embodiments, bitline bar BLB[1] is electrically coupled to memory cell 421b and memory cell 421a (not shown), and bitline bar BLB[1] is shared between memory cell 421b and memory cell 421a. In other words, adjacent memory cells (e.g., memory cells 421b and 421a) in memory circuit 400C are configured to share BLBs.

[0187] Bitline bar BLB[2] overlaps memory cell 421c. Bitline bar BLB[2] is electrically coupled to memory cell 421c via a via 424c. In some embodiments, bitline bar BLB[2] is electrically coupled to memory cell 421c and memory cell 421d (not shown), and bitline bar BLB[2] is shared between memory cell 421c and memory cell 421d. In other words, adjacent memory cells (e.g., memory cells 421d and 421c) in memory circuit 400C are configured to share BLBs.

[0188] Bitline BL[2] overlaps memory cell 421d. Bitline BL[2] is electrically coupled to memory cell 421d via a via 424d. In some embodiments, bitline BL[2] is electrically coupled to memory cell 421d and memory cell 421c (not shown), and bitline BL[2] is shared between memory cell 421d and memory cell 421c. In other words, adjacent memory cells (e.g., memory cells 421d and 421c) in memory circuit 400C are configured to share BLs.

[0189] Other configurations, arrangements on other metal layers or numbers of bit lines in the set of bit lines BL are within the scope of the present disclosure.

[0190] Other configurations, arrangements on other metal layers or numbers of bit line bars in the set of bit line bars BLB are within the scope of the present disclosure.

[0191] The set of word lines WL extends in the first direction X.

[0192] The word line WL[1] overlaps the memory cells 421a, 421b, 421c and 421d. The word line WL[1] is connected to the memory cell 421b (which is shown in Fig. 4C is also labeled as “Cell2”). The word line WL[1] is connected via a via 422d to the memory cell 421d (which is Fig. 4C is also marked as “Cell4”).

[0193] The word line WL[2] overlaps the memory cells 421a, 421b, 421c and 421d. The word line WL[2] is connected to the memory cell 421a (which is shown in Fig. 4C is also labeled as “Cell1”). The word line WL[2] is connected via a via 422c to the memory cell 421c (which is Fig. 4C is also marked as “Cell3”).

[0194] As in Fig. 4C, the word line WL[1] is electrically coupled to the memory cells 421b and 421d, and is therefore shared between the memory cells 421b and 421d, and is referred to as an “interleaved or alternating word line.” As shown in Fig. As shown in Figure 4C, wordline WL[1] is electrically coupled to memory cells 421a and 421c, and is therefore shared between memory cells 421a and 421c, and is referred to as an "interleaved or alternating wordline." In some embodiments, interleaving the set of WLs and sharing BLs or BLBs between adjacent memory cells causes memory circuit 400C to have a similar aspect ratio (1:1) to memory circuit 400A, resulting in a more flexible cell compared to other approaches.

[0195] Other configurations, arrangements on other metal layers or numbers of word lines in the set of word lines WL are within the scope of the present disclosure.

[0196] The memory circuit 400C also includes one or more of the vias 422a, 422b, 422c, or 422d (collectively referred to as a “set of vias 422”).

[0197] In some embodiments, the set of vias 422 is the same as the set of vias 402 of Fig. 4A or the set of vias 412 in Fig. 4B, and a similar detailed description is therefore omitted. In some embodiments, at least one of the vias 422a, 422b, 422c, or 422d is at least one or more of the vias 402a, 402b, 402c, 402d, 402e, or 402f of the set of vias 402 of Fig. 4A or at least one or more of the vias 412a, 412b, 412c or 412d of the set of vias 412 of Fig. 4B, and a similar detailed description is therefore omitted.

[0198] In some embodiments, via 422b is located between wordline WL[1] and memory cell 421b. In some embodiments, via 422d is located between wordline WL[1] and memory cell 421d.

[0199] In some embodiments, via 422a is located between wordline WL[2] and memory cell 421a. In some embodiments, via 422c is located between wordline WL[2] and memory cell 421c.

[0200] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 422 are within the scope of the present disclosure.

[0201] The memory circuit 400C also includes one or more vias 424a, 424b, 424c, or 424d (collectively referred to as a “set of vias 424”).

[0202] In some embodiments, the set of vias 424 is the same as the set of vias 404 of Fig. 4A or the set of vias 414 in Fig. 4B, and a similar detailed description is therefore omitted. In some embodiments, at least one of the vias 424a, 424b, 424c, or 424d is at least one or more of the vias 404a, 404b, 404c, 404d, 404e, or 404f of the set of vias 404 of Fig. 4A or at least one or more of the vias 414a, 414b, 414c, 414d, 414e or 414f of the set of vias 414 of Fig. 4A, and a similar detailed description is therefore omitted.

[0203] In some embodiments, the via 424a is located between the bit line BL[1] and the memory cell 421a.

[0204] In some embodiments, the via 424b is located between the bitline bar BLB[1] and the memory cell 421b.

[0205] In some embodiments, the via 424c is located between the bitline bar BLB[2] and the memory cell 421c.

[0206] In some embodiments, the via 424d is located between the bit line BL[2] and the memory cell 421d.

[0207] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 424 are within the scope of the present disclosure.

[0208] Other embodiments of the memory circuit 400C are within the scope of the present disclosure.

[0209] Fig. 5A is a corresponding schematic diagram of a corresponding memory circuit 500A, according to some embodiments.

[0210] The memory circuit 500A is associated with the memory cell array 202 of Fig. 2A. The memory circuit 500A is an embodiment of a memory cell (e.g., memory cell 401a, 401b, 401c, or 401d) of the memory cell array 401 of Fig. 4A, and a similar detailed description is therefore omitted.

[0211] The memory circuit 500A is manufactured by a corresponding layout design similar to the memory circuit 500A.

[0212] The memory circuit 500A has a height H2a in the first direction X. In some embodiments, the height H2a is equal to CH, where CH is a scaled cell height in the first direction X of at least the circuit 500A.

[0213] The memory circuit 500A has a width W2a in the second direction Y. In some embodiments, the width W2a is equal to CW, where CW is a scaled cell width in the second direction Y of at least the memory circuit 500A.

[0214] In some embodiments, the memory circuit 500A has a width in the second direction Y that is equal to 2 contacted polysilicon pitches (e.g., 2CPP).

[0215] In some embodiments, the memory circuit 500A may be configured as at least one memory cell 401a, 401b, 401c, or 401d of the memory cell array 401 of Fig. 4A, and a similar detailed description is therefore omitted.

[0216] The memory circuit 500A includes one or more active regions 502a, 502b, 502c, or 502d (collectively referred to as a “set of active regions 502”) extending in the second direction Y. The set of active regions 502 is embedded in a well 501a, 501b, 501c, or 501d (collectively referred to as a “set of wells 501”). The set of wells 501 is located in a substrate 490. In some embodiments, at least one of the wells 501a or 501d is a P-well, and at least one of the wells 501b or 501c is an N-well. In some embodiments, the wells 501b and 501c are a continuous well. In some embodiments, at least the well 501a or 501d comprises dopants of a first type, and at least the well 501a or 501d comprises dopants of a second type that is different from the first type. In some embodiments, the first type is an N-type dopant and the second type is a P-type dopant.In this embodiment, the first type is a P-dopant and the second type is an N-dopant.

[0217] In some embodiments, the set of active regions 502 is formed by a corresponding set of active region patterns (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900. In some embodiments, the active regions 502a, 502b, 502c, or 502d of the set of active regions 502 are formed by corresponding active region patterns (not shown) of the set of active region patterns (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900.

[0218] All of the active regions 502a, 502b, 502c and 502d of the set of active regions 502 are separated from each other in the first direction X.

[0219] In some embodiments, at least one of the set of active regions 502 is disposed on a front side 490a of the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500. In some embodiments, the front side 490a is part of a substrate 490.

[0220] In some embodiments, at least one of the set of active regions 502 corresponds to the source and drain regions of one or more complementary FET (CFET) transistors. In some embodiments, at least one of the set of active regions 502 corresponds to the source and drain regions of one or more nanofoil or nanowire transistors. Other transistor types are within the scope of the present disclosure. In some embodiments, at least one of the set of active regions 502 corresponds to the source and drain regions of one or more FinFET transistors.

[0221] In some embodiments, the set of active regions 502 is referred to as an oxide diffusion (OD) region that defines the source or drain diffusion regions of at least one of the memory cell 300A or 300B or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0222] In some embodiments, the active regions 502a or 502d are source and drain regions of NFET transistors of at least one of the memory cell 300A or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500, and the active regions 502b or 502c are source and drain regions of PFET transistors of at least one of the memory cell 300A or 300B or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400 or 1500.

[0223] In some embodiments, the active regions 502a or 502d are source and drain regions of PFET transistors of at least one of the memory cell 300A or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500, and the active regions 502b or 502c are source and drain regions of NFET transistors of at least one of the memory cell 300A or 300B or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400 or 1500.

[0224] In some embodiments, the set of active regions 502 is arranged on a first level. In some embodiments, the first level corresponds to an active level or an OD level of at least one of the memory cell 300A or 300B or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0225] Other configurations, arrangements at other levels, or numbers of regions in the set of active regions 502 are within the scope of the present disclosure.

[0226] The memory circuit 500A also includes one or more gates 504a, 504b, 504c, or 504d (collectively referred to as a “set of gates 504”) extending in the first direction X.

[0227] The set of gates 504 is located above the set of active regions 502.

[0228] The gates 504a and 504c are separated from each other in the first direction X.

[0229] The gates 504b and 504d are separated from each other in the first direction X.

[0230] The gates 504a and 504b are separated from each other in the second direction Y.

[0231] The gates 504c and 504d are separated from each other in the second direction Y.

[0232] In some embodiments, the set of gates 504 is formed by a corresponding set of gate structures (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900. In some embodiments, the gates 504a, 504b, 504c, or 504d of the set of gates 504 are formed by corresponding gate structures (not shown) of the set of gate structures (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900.

[0233] In some embodiments, at least one of the set of gates 504 is disposed on the front side of the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0234] In some embodiments, each of the gates in the set of gates 504 is Fig. 5, Fig. 6, Fig. 8 and Fig. 9 with markings “N2-1, P2-1, N2-2, P2-2, N2-3, N2-4”, the corresponding transistors of Fig. 3A, Fig. 4A, Fig. 4B and Fig. 4C, and they are omitted for brevity.

[0235] In some embodiments, one of the gates from the set of gates 504, 604, 804, or 904 is a gate of a dummy transistor. In some embodiments, a dummy transistor is a non-functional transistor.

[0236] In some embodiments, the set of gates 504 is located above the set of active regions 502.

[0237] In some embodiments, the set of gates 504 encapsulates the set of active region structures 502 and 304.

[0238] The set of gates 504 is arranged on a second level. In some embodiments, the second level is different from the first level. In some embodiments, the second level corresponds to the POLY level of one or more of the memory cell 300A or 300B or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500. In some embodiments, the POLY level is located above the OD level.

[0239] Other configurations, arrangements at other levels, or numbers of gates in the set of gates 504 are within the scope of the present disclosure.

[0240] In some embodiments, at least one via from the set of vias 402 is electrically coupled to at least one gate from the set of gates 504. In some embodiments, at least one via from the set of vias 404 is electrically coupled to at least one gate from the set of gates 504.

[0241] In some embodiments, at least one via from the set of vias 402 is electrically coupled to at least one active region from the set of active regions 502. In some embodiments, at least one via from the set of vias 404 is electrically coupled to at least one active region from the set of active regions 502.

[0242] Other embodiments of the memory circuit 500A are within the scope of the present disclosure.

[0243] Fig. 5B is a corresponding schematic diagram of a corresponding memory circuit 500B, according to some embodiments.

[0244] Fig. 5C is a cross-sectional view of integrated circuit 500B taken through plane A-A', according to some embodiments.

[0245] Fig. 5D is a cross-sectional view of integrated circuit 500B cut through plane B-B', according to some embodiments.

[0246] Fig. 5E is a cross-sectional view of integrated circuit 500B cut through plane C-C', according to some embodiments.

[0247] Fig. 5F is a cross-sectional view of integrated circuit 500B taken through plane F-F', according to some embodiments.

[0248] The memory circuit 500B is associated with the memory cell array 202 of Fig. 2A. The memory circuit 500B is an embodiment of the memory cell 401d of the memory cell array 401 of Fig. 4A, and a similar detailed description is therefore omitted. In some embodiments, memory circuit 500B is an embodiment of memory cell 401a, 401b, or 401c of memory cell array 401 of Fig. 4A, and a similar detailed description is therefore omitted.

[0249] The memory circuit 500B is manufactured by a corresponding layout design similar to the memory circuit 500B.

[0250] In some embodiments, memory circuit 500B combines elements of memory circuit 500A of Fig. 5A, which refers to the memory cell 401d of the memory cell array 401 of Fig. 4A, and a similar detailed description is therefore omitted. In some embodiments, the elements of memory circuit 500B may be applied to at least one of memory circuits 400B, 400C, 600, 700A, 700B, 800, or 900, and a similar detailed description is therefore omitted.

[0251] The memory circuit 500B is a modification of the memory circuit 400A of Fig. 4A and the storage circuit 500A of Fig. 5A, and a similar detailed description is therefore omitted. In comparison with the memory circuit 500A of Fig. 5A, the memory circuit 500B of Fig. 5B, the memory circuit 500A of FIG. 1 includes a set of contacts 506, a set of vias 512, a set of vias 514, a set of conductors 520, and a set of conductors 530.

[0252] Compared with the 400A memory circuit from Fig. 4A, the memory circuit 500B of Fig. 5B also shows the memory circuit 500A of Fig. 5A, the set of contacts 506, the set of vias 512, the set of vias 514, the set of conductors 520, and the set of conductors 530.

[0253] The memory circuit 500B is an embodiment of the memory cell 401d of the memory cell array 401 of Fig. 4A, and a similar detailed description is therefore omitted.

[0254] The memory circuit 500B includes the bit line BL[2], the bit line bar BLB[2], the word line WL[2], vias 402e and 402f and vias 404d and 404f, the set of active regions 502, the set of gates 504, the set of contacts 506, the set of vias 512, the set of vias 514, the set of conductors 520, and the set of conductors 530.

[0255] In some embodiments, the bit line BL[2], the bit line bar BLB[2], the word line WL[2], the vias 402e and 402f, and the vias 404d and 404f are part of the memory cell 401d of Fig. 4A.

[0256] The set of contacts 506 includes one or more of contacts 506a, 506b, 506c, or 506d. The set of contacts 506 extends in the first direction X. The set of contacts 506 is located above the set of active regions 502.

[0257] The set of contacts 506 is electrically coupled to the set of active regions 502. In some embodiments, the set of contacts 506 electrically couples the set of active regions 502 to upper levels (e.g., Mo, M1, or M2).

[0258] Contact 506a is electrically coupled to active regions 502a and 502b. Contact 506a electrically couples active regions 502a and 502b together. In some embodiments, contact 506a electrically couples the drain of NFET transistor N2-2, the drain of PFET transistor P2-2, and the source of NFET transistor N2-4 together.

[0259] Contact 506b is electrically coupled to active region 502a. In some embodiments, contact 506b is electrically coupled to the drain of NFET transistor N2-4.

[0260] Contact 506c is electrically coupled to active regions 502c and 502d. Contact 506c electrically couples active regions 502c and 502d together. In some embodiments, contact 506c electrically couples the drain of NFET transistor N2-1, the drain of PFET transistor P2-1, and the source of NFET transistor N2-3 together.

[0261] Contact 506d is electrically coupled to active region 502d. In some embodiments, contact 506d is electrically coupled to the drain of NFET transistor N2-3.

[0262] The set of contacts 506 is arranged at a third level. In some embodiments, the third level is different from the first level. In some embodiments, the third level corresponds to the MD (metal over diffusion) level of one or more of the memory cell 300A or 300B or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500. In some embodiments, the MD level is located above the OD level.

[0263] Other numbers, configurations, arrangements at other levels, or numbers of contacts in the set of contacts 506 are within the scope of the present disclosure.

[0264] The set of vias 512 includes one or more of vias 512a, 512b, or 512c.

[0265] In some embodiments, the set of vias 512 is formed by a corresponding set of via structures (not shown) of a corresponding layout design of the memory circuit 500B. In some embodiments, the vias 512a, 512b, or 512c of the set of vias 512 are formed by corresponding via structures (not shown) of the set of via structures (not shown) of a corresponding layout design of the memory circuit 500B.

[0266] The set of vias 512 is located between the set of gates 504 and the set of conductors 520.

[0267] In some embodiments, via 512a is located between gate 504b and conductor 520a. In some embodiments, via 512a electrically couples gate 504b and conductor 520a.

[0268] In some embodiments, via 512b is located between gate 504d and conductor 520d. In some embodiments, via 512b electrically couples gate 504d and conductor 520d.

[0269] In some embodiments, via 512c is located between gate 504c and conductor 520d. In some embodiments, via 512c electrically couples gate 504c and conductor 520d.

[0270] The set of vias 512 is arranged at the VG level of the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700C, 800, or 900. Other levels are within the scope of the present disclosure.

[0271] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 512 are within the scope of the present disclosure.

[0272] The set of vias 514 includes one or more of the vias 514a or 514b.

[0273] In some embodiments, the set of vias 514 is formed by a corresponding set of via structures (not shown) of a corresponding layout design of the memory circuit 500B. In some embodiments, the vias 514a or 514b of the set of vias 514 are formed by corresponding via structures (not shown) of the set of via structures (not shown) of a corresponding layout design of the memory circuit 500B.

[0274] The set of vias 514 is located between the set of contacts 506 and the set of conductors 520.

[0275] In some embodiments, via 514a is located between contact 506d and conductor 520c. In some embodiments, via 514a electrically couples contact 506d and conductor 520c.

[0276] In some embodiments, via 514b is located between contact 506b and conductor 520b. In some embodiments, via 514b electrically couples contact 506b and conductor 520b.

[0277] The set of vias 514 is arranged at the VD level of the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700C, 800, or 900. Other levels are within the scope of the present disclosure.

[0278] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 514 are within the scope of the present disclosure.

[0279] The set of conductors 520 includes one or more of conductors 520a, 520b, 520c, or 520d.

[0280] The set of conductors 520 extends in the second direction Y.

[0281] The set of conductors 520 is located above the set of contacts 506, the set of gates 504 and the set of active regions 502.

[0282] The set of conductors 520 is located below the set of conductors 530, the set of bit lines BL, the set of bit line bars BLB and the set of word lines WL.

[0283] The set of conductors 520 electrically couples the set of contacts 506 or the set of gates 504 to upper levels (e.g., M1 or M2).

[0284] The conductor 520a is electrically coupled to the gate 504b via the via 512a.

[0285] The conductor 520b is electrically coupled to the contact 506b via the via 514b.

[0286] The conductor 520c is electrically coupled to the contact 506d via the via 514a.

[0287] Conductor 520d is electrically coupled to gate 504d and gate 504c via respective vias 512b and 512c. Conductor 520d electrically couples gate 504d and gate 504c through respective vias 512b and 512c.

[0288] The set of conductors 520 is arranged on a fourth level. The fourth level is located above the first level, the second level, and the third level. In some embodiments, the fourth level is referred to as the metal zero (Mo) level. Other levels are within the scope of the present disclosure.

[0289] Other numbers or configurations of the set of conductors 520 are within the scope of the present disclosure.

[0290] The set of conductors 530 includes one or more of the conductors 530a or 530b.

[0291] The set of conductors 530 extends in the first direction X.

[0292] The set of conductors 530 is located above the set of conductors 530, the set of contacts 506, the set of gates 504 and the set of active regions 502.

[0293] The set of conductors 530 is located below the set of bit lines BL and the set of bit line bars BLB.

[0294] The set of conductors 530 electrically couples the set of contacts 506 or the set of gates 504 to upper levels (e.g., M2).

[0295] The conductor 530a is electrically coupled to the conductor 520c via the via 522a.

[0296] The conductor 530b is electrically coupled to the conductor 520b via the via 522b.

[0297] The set of conductors 530 is arranged on a fifth level. The fifth level is located above the first level, the second level, the third level, and the fourth level. In some embodiments, the fifth level is referred to as the metal one (M1) level. Other levels are within the scope of the present disclosure.

[0298] In some embodiments, wordline WL[2] is located on the fifth level. Wordline WL[2] is electrically coupled to conductor 520a via via 402e. Wordline WL[2] is electrically coupled to conductor 520d via via 402f.

[0299] In some embodiments, vias 402e and 402f are located in the V0 plane. In some embodiments, set of vias 402 is located in the V0 plane. Other planes are within the scope of the present disclosure.

[0300] Other numbers or configurations of the set of conductors 530 are within the scope of the present disclosure.

[0301] The set of vias 522 includes one or more of the vias 522a or 522b.

[0302] In some embodiments, the set of vias 522 is formed by a corresponding set of via structures (not shown) of a corresponding layout design of the memory circuit 500B. In some embodiments, the vias 522a or 522b of the set of vias 522 are formed by corresponding via structures (not shown) of the set of via structures (not shown) of a corresponding layout design of the memory circuit 500B.

[0303] The set of vias 522 is located between the set of conductors 520 and the set of conductors 530.

[0304] In some embodiments, via 522a is located between conductor 520c and conductor 530a. In some embodiments, via 522a electrically couples conductor 520c and conductor 530a.

[0305] In some embodiments, via 522b is located between conductor 520b and conductor 530b. In some embodiments, via 522b electrically couples conductor 520b and conductor 530b.

[0306] The set of vias 522 is arranged at the V1 level of the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700C, 800, or 900. Other levels are within the scope of the present disclosure.

[0307] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 522 are within the scope of the present disclosure.

[0308] In some embodiments, the set of bit lines BL and the set of bit line bars BLB are arranged on a sixth level. The sixth level is located above the first level, the second level, the third level, the fourth level, and the fifth level. In some embodiments, the sixth level is referred to as the metal two (M2) level. Other levels are within the scope of the present disclosure.

[0309] The bit line BL[2] is electrically coupled to the conductor 530a via the via 404d.

[0310] The bit line bar BLB[2] is electrically coupled to the conductor 530b via the via 404f.

[0311] In some embodiments, vias 404d and 404f are located in the V1 plane. In some embodiments, set of vias 404 is located in the V1 plane. Other planes are within the scope of the present disclosure.

[0312] Other numbers or configurations of the set of conductors 530 are within the scope of the present disclosure.

[0313] Other embodiments of the memory circuit 500B are within the scope of the present disclosure.

[0314] Fig. 6 is a corresponding schematic diagram of a corresponding memory circuit 600, according to some embodiments.

[0315] The memory circuit 600 is associated with the memory cell array 202 of Fig. 2A. The memory circuit 600 is an embodiment of a memory cell (e.g., memory cell 411a, 411b, 411c, or 411d) of the memory cell array 411 of Fig. 4B, and a similar detailed description is therefore omitted.

[0316] In some embodiments, the memory circuit 600 is an embodiment of a memory cell (e.g., memory cell 421a, 421b, 421c, or 421d) of the memory cell array 421 of Fig. 4C, and a similar detailed description is therefore omitted.

[0317] The memory circuit 600 is manufactured by a corresponding layout design similar to the memory circuit 600.

[0318] The memory circuit 600 has a height H2b in the first direction X. In some embodiments, the height H2b is equal to 0.5CH, where CH is a scaled cell height in the first direction X of at least the circuit 600.

[0319] The memory circuit 600 has a width W2b in the second direction Y. In some embodiments, the width W2b is equal to 2CW, where CW is a scaled cell width in the second direction Y of at least the memory circuit 600.

[0320] In some embodiments, the memory circuit 600 has a width in the second direction Y that is equal to 4 contacted polysilicon pitches (e.g., 4CPP).

[0321] In some embodiments, the memory circuit 600 may be implemented as at least one memory cell 411a, 411b, 411c, or 411d of the memory cell array 411 of Fig. 4B, and a similar detailed description is therefore omitted.

[0322] In some embodiments, the memory circuit 600 may be implemented as at least one memory cell 421a, 421b, 421c or 421d of the memory cell array 421 of Fig. 4C, and a similar detailed description is therefore omitted.

[0323] The memory circuit 600 includes one or more active regions 602a or 602b (collectively referred to as a “set of active regions 602”) extending in the second direction Y.

[0324] In some embodiments, the set of active regions 602 is the same as the set of active regions 502 of Fig. 5A, and a similar detailed description is therefore omitted. In some embodiments, one or more of the active regions 602a or 602b is one or more of the active regions 502a, 502b, 502c, or 502d of the set of active regions 502 of Fig. 5A, and a similar detailed description is therefore omitted.

[0325] In some embodiments, the set of active regions 602 is formed by a corresponding set of active region patterns (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900. In some embodiments, the active regions 602a or 602b of the set of active regions 602 are formed by corresponding active region patterns (not shown) of the set of active region patterns (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900.

[0326] In some embodiments, the active region 602a represents source and drain regions of PFET transistors of at least one of the memory cell 300A or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1600, and the active region 602b represents source and drain regions of NFET transistors of at least one of the memory cell 300A or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400 or 1500.

[0327] In some embodiments, the active region 602a represents source and drain regions of NFET transistors of at least one of the memory cell 300A or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1600, and the active region 602b represents source and drain regions of PFET transistors of at least one of the memory cell 300A or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400 or 1500.

[0328] Other configurations, arrangements at other levels, or numbers of regions in the set of active regions 602 are within the scope of the present disclosure.

[0329] The memory circuit 600 also includes one or more gates 604a, 604b, 604c, or 604d (collectively referred to as a “set of gates 604”) extending in the first direction X.

[0330] In some embodiments, the set of gates 604 is similar to the set of gates 504 of Fig. 5A, and a similar detailed description is therefore omitted. In some embodiments, one or more of the gates 604a, 604b, 604c, or 604d is associated with one or more of the gates 504a, 504b, 504c, or 504d of the set of gates 504 of Fig. 5A, and a similar detailed description is therefore omitted.

[0331] Each of the gates in the set of gates 604 is separated from another gate in the set of gates 604 in the second direction Y.

[0332] In some embodiments, the set of gates 604 is formed by a corresponding set of gate structures (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900. In some embodiments, the gates 604a, 604b, 604c, or 604d of the set of gates 604 are formed by corresponding gate structures (not shown) of the set of gate structures (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900.

[0333] In some embodiments, each of the gates in the set of gates 604 is Fig. 5, Fig. 6, Fig. 8 and Fig. 9 with markings “N2-1, P2-1, N2-2, P2-2, N2-3, N2-4”, the corresponding transistors of Fig. 3A, Fig. 4A, Fig. 4B and Fig. 4C, and they are omitted for brevity.

[0334] Other configurations, arrangements at other levels, or numbers of gates in the set of gates 604 are within the scope of the present disclosure.

[0335] In some embodiments, at least one via from the set of vias 402 is electrically coupled to at least one gate from the set of gates 604. In some embodiments, at least one via from the set of vias 404 is electrically coupled to at least one gate from the set of gates 604.

[0336] In some embodiments, at least one via from the set of vias 402 is electrically coupled to at least one active region from the set of active regions 602. In some embodiments, at least one via from the set of vias 404 is electrically coupled to at least one active region from the set of active regions 602.

[0337] Other embodiments of the memory circuit 600 are within the scope of the present disclosure.

[0338] Fig. 7A-7B are respective schematic diagrams of a respective memory circuit 700A-700B, according to some embodiments.

[0339] Fig. 7A is a schematic diagram of a memory circuit 700A, according to some embodiments.

[0340] The memory circuit 700A is associated with the memory cell array 202 of Fig. 2B. The memory circuit 700A is an embodiment of the portion 201b of the memory circuit 200B of Fig. 2B, and a similar detailed description is therefore omitted. In some embodiments, memory circuit 700A is an embodiment of the portions of memory circuit 200B separated from portion 201b of memory circuit 200B of Fig. 2B are different.

[0341] The memory circuit 700A is a modification of the memory circuit 400A of Fig. 4A, and a similar detailed description is therefore omitted. In comparison with the memory circuit 400A of Fig. 4A replaces a memory cell array 701 of Fig. 7A the memory cell array 401 of Fig. 4A, the read word lines RWL of Fig. 7A or the write word lines WWL of Fig. 7A replace the word lines WL of Fig. 4A, and a similar detailed description is therefore omitted. In comparison with the memory circuit 400A of Fig. 4A, the memory cell 700A also includes read bit lines RBL, and a similar detailed description is therefore omitted.

[0342] The memory circuit 700A includes a memory cell array 701. The memory circuit 700A is a schematic representation of two adjacent columns and two adjacent rows of a memory cell array 701. In some embodiments, the memory circuit 700 is a schematic representation of columns 1 and 2 of the memory cell array 202 of Fig. 2B and rows 1 and 2 of the memory cell array 202 of Fig. 2B, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 700 is a schematic representation of other columns or other rows of the memory cell array 202 of Fig. 2A, and not columns 1 and 2 or rows 1 and 2 of the memory cell array 202 of Fig. 2B, and a similar detailed description is therefore omitted.

[0343] The memory circuits 700A-700B are manufactured by a corresponding layout design similar to the memory circuits 700A-700B.

[0344] The memory cell array 701 is similar to the memory cell array 202 of Fig. 2B, and a similar detailed description is therefore omitted.

[0345] The memory cell array 701 includes memory cells 701a, 701b, 701c and 701d.

[0346] The memory cell 701a is located in row 1 and column 1 of the memory cell array 701, and is in Fig. 7A as “r1c1”. The memory cell 701b is located in row 1 and column 2 of the memory cell array 701, and is in Fig. 7A as “r1c2”. The memory cell 701c is located in row 2 and column 1 of the memory cell array 701, and is in Fig. 7A as “r2c1”. The memory cell 701d is located in row 2 and column 2 of the memory cell array 701, and is in Fig. 7A marked as “r2c2”.

[0347] The memory cell array 701 is in Fig. 7A as a 2 x 2 memory cell array. Other numbers of rows and columns are within the scope of the present disclosure.

[0348] The memory cell array 701 has a height H3a in the first direction X. In some embodiments, the height H3a is equal to 2CH + 2RP, where CH is a scaled cell height in the first direction X of at least one of the memory cells 701a, 701b, 701c, or 701d in the memory cell array 401, and where RP is a cell height in the first direction X of at least one region 810 in Fig. 8 is.

[0349] The memory cell array 701 has a width W3a in the second direction Y. In some embodiments, the width W3a is equal to 2CW, where CW is a scaled cell width in the second direction Y of at least one of the memory cells 701a, 701b, 701c, or 701d in the memory cell array 701.

[0350] In some embodiments, the memory cell array 701 has a width in the second direction Y that is equal to 2 contacted polysilicon pitches (e.g., 2CPP).

[0351] In some embodiments, the memory cell array 701 has an aspect ratio AR1a equal to ((CH + RP) / CW) (e.g., W1a / H1a).

[0352] The memory circuit 700A also includes the set of bit lines BL and the set of bit line bars BLB.

[0353] In some embodiments, the memory cells 701a, 701b, 701c and 701d corresponding to memory cells MCB in the same corresponding rows and the same corresponding columns of the area 201b of Fig. 2B, and a similar detailed description is therefore omitted. In some embodiments, each of the memory cells 701a, 701b, 701c, and 701d is the memory cell 300B of FIG. 3B, and a similar detailed description is therefore omitted.

[0354] The bit line BL[1] and the bit line bar BLB[1] overlap the memory cells 701a and 701c. The bit line bar BLB[1] is electrically coupled to the memory cells 701a and 701c via a via 704a. The bit line BL[1] is electrically coupled to the memory cell 701a via a via 704b and to the memory cell 701c via a via 704e.

[0355] Bitline BL[2] and bitline bar BLB[2] overlap memory cells 701b and 701d. Bitline BL[2] is electrically coupled to memory cells 701b and 701d via via 404d. Bitline bar BLB[2] is electrically coupled to memory cell 701b via via 404c and to memory cell 701d via via 404f.

[0356] Other configurations, arrangements on other metal layers or numbers of bit lines in the set of bit lines BL are within the scope of the present disclosure.

[0357] Other configurations, arrangements on other metal layers or numbers of bit line bars in the set of bit line bars BLB are within the scope of the present disclosure.

[0358] The memory circuit 700A also includes read word lines RWL[1] and RWL[2] (collectively referred to as a “set of read word lines RWL”) or write word lines WWL[1] and WWL[2] (collectively referred to as a “set of write word lines WL”).

[0359] The set of write word lines WWL or the set of read word lines RWL extend in the first direction X. In some embodiments, at least one of the set of read word lines RWL or the set of read word lines RWL is similar to the set of word lines WL, and a similar description is therefore omitted.

[0360] In some embodiments, the write word lines WWL[1] and WWL[2] are corresponding write word lines WWL[1] and WWL[2] of Fig. 2B, and a similar detailed description is therefore omitted. In some embodiments, the read word lines RWL[1] and RWL[2] are corresponding read word lines RWL[1] and RWL[2] of Fig. 2B, and a similar detailed description is therefore omitted.

[0361] The write word line WWL[1] or the read word line RWL[1] overlaps the memory cells 701a and 701b. The write word line WWL[1] or the read word line RWL[1] is electrically coupled to the memory cell 701a via vias 402a and 402b. The write word line WWL[1] or the read word line RWL[1] is electrically coupled to the memory cell 701b via vias 402b and 402c.

[0362] The write word line WWL[2] or the read word line RWL[2] overlaps the memory cells 701c and 701d. The write word line WWL[2] or the read word line RWL[2] is electrically coupled to the memory cell 701c via vias 402d and 402e. The write word line WWL[2] or the read word line RWL[2] is electrically coupled to the memory cell 701d via vias 402e and 402f.

[0363] In some embodiments, at least one of the set of write word lines WWL or the set of read word lines RWL is located in the M1 layer of at least one of the memory circuit 700A, 700B, 700C, 700A, or 700B. In some embodiments, at least one of the set of write word lines WWL or the set of read word lines RWL is located in a Mo layer of at least one of the memory circuit 700A, 700B, 700C, 700A, or 700B. Other metal layers for at least one of the set of write word lines WWL or the set of read word lines RWL are within the scope of the present disclosure.

[0364] In some embodiments, at least one of the set of write word lines WWL or the set of read word lines RWL is located in the POLY layer of at least one of the memory circuit 700A or 700B.

[0365] Other configurations, arrangements on other metal layers, or numbers of read word lines or write word lines in at least one of the set of write word lines WWL or the set of read word lines RWL are within the scope of the present disclosure.

[0366] The memory circuit 700A also includes read bit lines RBL[1] and RBL[2] (collectively referred to as a “set of read bit lines RBL”).

[0367] The set of read bit lines RBL extends in the second direction Y. In some embodiments, the set of read bit lines RBL is similar to the set of bit lines BL, and a similar detailed description is therefore omitted.

[0368] In some embodiments, the read bit lines RBL[1] and RBL[2] are corresponding read bit lines RBL[1] and RBL[2] of Fig. 2B, and a similar detailed description is therefore omitted.

[0369] The read bit line RBL[1] overlaps the memory cells 701a and 701c. The read bit line RBL[1] is electrically coupled to the memory cell 701a via a via 704g. The read bit line RBL[1] is electrically coupled to the memory cell 701c via a via 704i.

[0370] The read bit line RBL[2] overlaps the memory cells 701b and 701d. The read bit line RBL[2] is electrically coupled to the memory cell 701b via a via 704h. The read bit line RBL[2] is electrically coupled to the memory cell 701d via a via 704j.

[0371] In some embodiments, the set of read bit lines RBL is located in the M2 layer of at least one of the memory circuit 700A or 700B. In some embodiments, the set of read bit lines RBL is located in an M1 layer of at least one of the memory circuit 700A or 700B. Other metal layers for the set of read bit lines RBL are within the scope of the present disclosure.

[0372] Other configurations, arrangements on other metal layers, or numbers of read bit lines or write word lines in the set of read bit lines RBL are within the scope of the present disclosure.

[0373] The memory circuit 700A also includes one or more vias 402a, 402b, 402c, 402d, 402e, or 402f (collectively referred to as a “set of vias 702”).

[0374] In some embodiments, the set of vias 702 is the same as the set of vias 402 of Fig. 4A, and a similar detailed description is therefore omitted.

[0375] The set of vias 702 is located between one of the set of write word lines WWL or the set of read word lines RWL and underlying layers (e.g. in Fig. 5, Fig. 6, Fig. 8 or Fig. 9) of the memory cell array 701. In some embodiments, the set of vias 702 is located between one of the set of write word lines WWL or the set of read word lines RWL and at least one memory cell 701a, 701b, 701c, or 701d of the memory cell array 701.

[0376] In some embodiments, vias 402a and 402b are located between write word line WWL[1] or read word line RWL[1] and memory cell 701a. In some embodiments, vias 402b and 402c are located between write word line WWL[1] or read word line RWL[1] and memory cell 701b.

[0377] In some embodiments, vias 402d and 402e are located between write word line WWL[2] or read word line RWL[2] and memory cell 701c. In some embodiments, vias 402e and 402f are located between write word line WWL[2] or read word line RWL[2] and memory cell 701d.

[0378] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 702 are within the scope of the present disclosure.

[0379] The memory circuit 700A also includes one or more vias 704a, 704b, 704c, 704d, 704e, 704f, 704g, 704h, 704i, or 704j (collectively referred to as a “set of vias 704”).

[0380] In some embodiments, the set of vias 704 is the same as the set of vias 404 of Fig. 4A, and a similar detailed description is therefore omitted. In some embodiments, at least one of the vias 704a, 704b, 704e, 704g, 704h, 704i, or 704j is at least one or more of the vias 404a, 404b, 404c, 404d, 404e, or 404f of the set of vias 404 of Fig. 4A, and a similar detailed description is therefore omitted.

[0381] The set of vias 704 is located between at least one of the set of bit lines BL, the set of bit power bars BLB or the set of read bit lines RBL and underlying layers (e.g. in Fig. 5, Fig. 6, Fig. 8 or Fig. 9) of the memory cell array 701. In some embodiments, the set of vias 704 is located between at least one of the set of bit lines BL, the set of bit line bars BLB, or the set of read bit lines RBL and at least one memory cell 701a, 701b, 701c, or 701d of the memory cell array 701.

[0382] In some embodiments, the via 704a is located between the bitline bar BLB[1] and the memory cells 701a and 701c.

[0383] In some embodiments, via 704b is located between bitline BL[1] and memory cell 701a, and via 704e is located between bitline BL[1] and memory cell 701c.

[0384] In some embodiments, via 704g is located between read bit line RBL[1] and memory cell 701a, and via 704i is located between read bit line RBL[1] and memory cell 701c.

[0385] In some embodiments, via 704h is located between read bit line RBL[2] and memory cell 701b, and via 704j is located between read bit line RBL[2] and memory cell 701d.

[0386] In some embodiments, the via 404d is located between the bit line BL[2] and the memory cells 701b and 701d.

[0387] In some embodiments, the via 404c is located between the bitline bar BLB[2] and the memory cell 701b, and the via 404f is located between the bitline bar BLB[2] and the memory cell 701d.

[0388] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 704 are within the scope of the present disclosure.

[0389] Other embodiments of the memory circuit 700A are within the scope of the present disclosure.

[0390] Fig. 7B is a schematic diagram of a memory circuit 700B, according to some embodiments.

[0391] The memory circuit 700B is associated with the memory cell array 202 of Fig. 2B. The memory circuit 700B is an embodiment of the portion 201b of the memory circuit 200B of Fig. 2B, and a similar detailed description is therefore omitted. In some embodiments, memory circuit 700B is an embodiment of the portions of memory circuit 200B separated from portion 201b of memory circuit 200B of Fig. 2B are different.

[0392] The memory circuit 700B is a modification of the memory circuit 400C of Fig. 4C or the memory circuit 700A of Fig. 7A, and a similar detailed description is therefore omitted. In comparison with the memory circuit 400C of Fig. 4C replaces a memory cell array 721 of Fig. 7B the memory cell array 421 of Fig. 4C, and a similar detailed description is therefore omitted.

[0393] The memory circuit 700B has a memory cell array 721. The memory cell array 721 is similar to the memory cell array 202 of Fig. 2B, the memory cell array 421 of Fig. 4C or the memory cell array 701 of Fig. 7A, and a similar detailed description is therefore omitted.

[0394] The memory cell array 721 includes memory cells 721a, 721b, 721c, and 721d. In some embodiments, at least one of the memory cells 721a, 721b, 721c, or 721d is at least one of the memory cells 401a, 401b, 401c, or 401d of the memory cell array 401 of Fig. 4A or at least one of the memory cells 411a, 411b, 411c or 411d of the memory cell array 411 of Fig. 4B, and a similar detailed description is therefore omitted.

[0395] The memory cell 721a (also known as “Cell1” in Fig. 7B) is located in row 1 and column 1 of the memory cell array 721, and is in Fig. 7B as “r1c1”. The memory cell 721b (also known as “Cell2” in Fig. 7B) is located in row 2 and column 1 of the memory cell array 721, and is in Fig. 7B as “r2c1”. The memory cell 721c (also known as “Cell3” in Fig. 7B) is located in row 1 and column 2 of the memory cell array 721, and is in Fig. 7B as “r1c2”. The memory cell 721d (also known as “Cell4” in Fig. 7B) is located in row 2 and column 2 of the memory cell array 721, and is in Fig. 7B as "r2c2." In some embodiments, a portion (e.g., a memory cell portion 721b2) of memory cell 721b is located in r1c1. In some embodiments, a portion (e.g., a memory cell portion 721d2) of memory cell 721d is located in r1c2.

[0396] The memory cell array 721 is in Fig. 7B as a 2 x 2 memory cell array. Other numbers of rows and columns are within the scope of the present disclosure.

[0397] The memory cell array 721 has a height H3b in the first direction X. In some embodiments, the height H3b is equal to 2CH + 2RP, where 0.5CH is the scaled cell height in the first direction X of at least one of the memory cells 721b or 721d in the memory cell array 721, and where RP is a cell height in the first direction X of at least one region 901b in Fig. 9 is.

[0398] The memory cell array 721 has a width W3b in the second direction Y. In some embodiments, the width W3b is equal to 2CW, where 2CW is a scaled cell width in the second direction Y of at least one of the memory cells 721a, 721b, 721c, or 721d in the memory cell array 721.

[0399] In some embodiments, the memory cell array 721 has a width in the second direction Y that is equal to 4 contacted polysilicon pitches (e.g., 4CPP).

[0400] In some embodiments, the memory cell array 721 has an aspect ratio AR1a equal to ((CH + RP) / CW) (e.g., W3b / H3b).

[0401] In some embodiments, the memory cells 721a, 721b, 721c and 721d corresponding to memory cells MCB in the same corresponding rows and the same corresponding columns of the area 201b of Fig. 2B, and a similar detailed description is therefore omitted. In some embodiments, each of the memory cells 721a, 721b, 721c, and 721d is the memory cell 300B of FIG. 3B, and a similar detailed description is therefore omitted.

[0402] In some embodiments, the memory cell 721b is divided into a memory cell section 721b1 and a memory cell section 721b2. In some embodiments, the memory cell section 721b2 is arranged in a corner of a region 750. In some embodiments, the memory cell section 721b1 corresponds to the memory circuit 600 in Fig. 9 and area 901a in Fig. 9. In some embodiments, the memory cell portion 721b2 corresponds to the area 910a or 910b in Fig. 9.

[0403] In some embodiments, the memory cell 721d is divided into a memory cell 721d1 and a memory cell 721d2. In some embodiments, the memory cell section 721d2 is arranged in a corner of a region 752. In some embodiments, the memory cell section 721d1 corresponds to the memory circuit 600 in Fig. 9 and area 901a in Fig. 9. In some embodiments, the memory cell portion 721d2 corresponds to the area 910a or 910b in Fig. 9.

[0404] The memory circuit 700B also includes the set of bit lines BL, the set of bit line bars BLB, the set of read bit lines RBL, and at least one of the set of write word lines WWL or the set of read word lines RWL.

[0405] Bitline BL[1] overlaps memory cell 721a. Bitline BL[1] is electrically coupled to memory cell 721a via a via 724a. In some embodiments, bitline BL[1] is electrically coupled to memory cell 721a and memory cell 721b (not shown), and bitline BL[1] is shared between memory cell 721a and memory cell 721b. In other words, adjacent memory cells (e.g., memory cells 721b and 721a) in memory circuit 700B are configured to share BLs.

[0406] The bit line bar BLB[1] overlaps the memory cell 721b.

[0407] The bitline bar BLB[1] is electrically coupled to the memory cell 721b via a via 724c. In some embodiments, the bitline bar BLB[1] is electrically coupled to the memory cell 721b and the memory cell 721a (not shown), and the bitline bar BLB[1] is shared between the memory cell 721b and the memory cell 721a. In other words, adjacent memory cells (e.g., the memory cells 721b and 721a) in the memory circuit 700B are configured to share BLBs.

[0408] The bitline bar BLB[2] overlaps the memory cell 721d. The bitline bar BLB[2] is electrically coupled to the memory cell 721d via a via 724g. In some embodiments, the bitline bar BLB[2] is electrically coupled to the memory cell 721d and the memory cell 721c (not shown), and the bitline bar BLB[2] is shared between the memory cell 721d and the memory cell 721c. In other words, adjacent memory cells (e.g., the memory cells 721d and 721c) in the memory circuit 700B are configured to share BLBs.

[0409] Bitline BL[2] overlaps memory cell 721c. Bitline BL[2] is electrically coupled to memory cell 721c via a via 724e. In some embodiments, bitline BL[2] is electrically coupled to memory cell 721c and memory cell 721d (not shown), and bitline BL[2] is shared between memory cell 721c and memory cell 721d. In other words, adjacent memory cells (e.g., memory cells 721d and 721c) in memory circuit 700B are configured to share BLs.

[0410] Other configurations, arrangements on other metal layers or numbers of bit lines in the set of bit lines BL are within the scope of the present disclosure.

[0411] Other configurations, arrangements on other metal layers or numbers of bit line bars in the set of bit line bars BLB are within the scope of the present disclosure.

[0412] The read bit line RBL[1] overlaps the memory cell 721a and the memory cell section 721b2. The read bit line RBL[1] is electrically coupled to the memory cell 721a via a via 724b. The read bit line BL[1] is electrically coupled to the memory cell section 721b2 of the memory cell 721b via a via 724d.

[0413] In some embodiments, the read bit line RBL[1] is electrically coupled to the memory cell 721a and the memory cell 721b, and the read bit line RBL[1] is shared between the memory cell 721a and the memory cell 721b. In other words, adjacent memory cells (e.g., the memory cells 721b and 721a) in the memory circuit 700B are configured to share RLBs.

[0414] The read bit line RBL[2] overlaps the memory cell 721c and the memory cell section 721d2. The read bit line RBL[2] is electrically coupled to the memory cell 721c via a via 724f. The read bit line BL[2] is electrically coupled to the memory cell section 721d2 of the memory cell 721d via a via 724h.

[0415] In some embodiments, the read bit line RBL[2] is electrically coupled to the memory cell 721c and the memory cell 721d, and the read bit line RBL[2] is shared between the memory cell 721c and the memory cell 721d. In other words, adjacent memory cells (e.g., the memory cells 721c and 721d) in the memory circuit 700B are configured to share RLBs.

[0416] Other configurations, arrangements on other metal layers or numbers of read bit lines in the set of read bit lines RBL are within the scope of the present disclosure.

[0417] The write word line WWL[1] or the read word line RWL[1] overlaps the memory cells 721a, 721b, 721c, and 721d. The write word line WWL[1] or the read word line RWL[1] is electrically coupled to the memory cell 721b via a via 722b. The write word line WWL[1] or the read word line RWL[1] is electrically coupled to the memory cell 721c via a via 722d. The write word line WWL[1] or the read word line RWL[1] is electrically coupled to the memory cell 721d via a via 722f.

[0418] The write word line WWL[1] or the read word line RWL[1] overlaps the memory cells 721a, 721b, 721c, and 721d. The write word line WWL[2] or the read word line RWL[2] is electrically coupled to the memory cell 721a via a via 722a. The write word line WWL[2] or the read word line RWL[2] is electrically coupled to the memory cell 721c via a via 722c. The write word line WWL[2] or the read word line RWL[2] is electrically coupled to the memory cell 721d via a via 722e.

[0419] In some embodiments, interleaving the set of WWLs / RWLs and sharing BLs or BLBs between adjacent memory cells causes memory circuit 700B to have a same aspect ratio ((CH + RP) / CW) as memory circuit 700A, resulting in a more flexible cell compared to other approaches.

[0420] Other configurations, arrangements on other metal layers or numbers of word lines in the set of word lines WL are within the scope of the present disclosure.

[0421] The memory circuit 700B also includes one or more vias 722a, 722b, 722c, 722d, 722e, or 722f (collectively referred to as a “set of vias 722”).

[0422] In some embodiments, the set of vias 722 is the same as the set of vias 702 of Fig. 7A, and a similar detailed description is therefore omitted. In some embodiments, at least one of the vias 722a, 722b, 722c, 722d, 722e, or 722f is similar to at least one of the vias 402a, 402b, 402c, 402d, 402e, or 402f, and a similar detailed description is therefore omitted.

[0423] In some embodiments, via 722b is located between write word line WWL[1] or read word line RWL[1] and memory cell 721b. In some embodiments, via 722d is located between write word line WWL[1] or read word line RWL[1] and memory cell 721c. In some embodiments, via 722f is located between write word line WWL[1] or read word line RWL[1] and memory cell 721d.

[0424] In some embodiments, via 722a is located between write word line WWL[2] or read word line RWL[2] and memory cell 721a. In some embodiments, via 722c is located between write word line WWL[2] or read word line RWL[2] and memory cell 721c. In some embodiments, via 722e is located between write word line WWL[2] or read word line RWL[2] and memory cell 721d.

[0425] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 722 are within the scope of the present disclosure.

[0426] The memory circuit 700B also includes one or more vias 724a, 724b, 724c, 724d, 724e, 724f, 724g, or 724h (collectively referred to as a “set of vias 724”).

[0427] In some embodiments, the set of vias 724 is the same as the set of vias 404 of Fig. 4A or the set of vias 704 in Fig. 7A, and a similar detailed description is therefore omitted. In some embodiments, at least one of the vias 724a, 724b, 724c, 724d, 724e, 724f, 724g, or 724h is at least one or more of the vias 404a, 404b, 404c, 404d, 404e, or 404f of the set of vias 404 of Fig. 4A or at least one or more of the vias 704a, 704b, 404c, 404d, 704e, 404f, 704g, 704h, 704i or 704j of the set of vias 704 of Fig. 7A, and a similar detailed description is therefore omitted.

[0428] In some embodiments, the via 724a is located between the bit line BL[1] and the memory cell 721a.

[0429] In some embodiments, the via 724c is located between the bitline bar BLB[1] and the memory cell 721b.

[0430] In some embodiments, via 424b is located between read bit line RBL[1] and memory cell 721a.

[0431] In some embodiments, the via 724d is located between the read bit line RBL[1] and the memory cell portion 721b2 of the memory cell 721b.

[0432] In some embodiments, the via 724f is located between the read bit line RBL[2] and the memory cell 721c.

[0433] In some embodiments, the via 724h is located between the read bit line RBL[2] and the memory cell portion 721d2 of the memory cell 721d.

[0434] In some embodiments, the via 724e is located between the bit line BL[2] and the memory cell 721c.

[0435] In some embodiments, the via 724g is located between the bitline bar BLB[2] and the memory cells 721d.

[0436] Other configurations, arrangements at other levels, or numbers of vias in at least the set of vias 724 are within the scope of the present disclosure.

[0437] Other embodiments of the memory circuit 700B are within the scope of the present disclosure.

[0438] Fig. 8 is a corresponding schematic diagram of a corresponding memory circuit 800, according to some embodiments.

[0439] The memory circuit 800 is associated with the memory cell array 202 of Fig. 2B. The memory circuit 800 is an embodiment of a memory cell (e.g., memory cell 701a, 701b, 701c, or 701d) of the memory cell array 701 of Fig. 7A, and a similar detailed description is therefore omitted.

[0440] The memory circuit 800 is a modification of the memory circuit 500A of Fig. 5A, and a similar detailed description is therefore omitted. In comparison with the memory circuit 500A of Fig. 5A, the memory cell 800 also includes a region 810, and a similar detailed description is therefore omitted.

[0441] The memory circuit 800 is manufactured by a corresponding layout design similar to the memory circuit 800.

[0442] The memory circuit 800 has a height H4a in the first direction X. In some embodiments, the height H4a is equal to CH + RP, where CH is a scaled cell height in the first direction X of at least the memory circuit 800, and where RP is a cell height in the first direction X of at least the region 810.

[0443] The memory circuit 800 has a width W4a in the second direction Y. In some embodiments, the width W4a is equal to CW, where CW is a scaled cell width in the second direction Y of at least the memory circuit 800.

[0444] In some embodiments, the memory circuit 800 has a width in the second direction Y that is equal to 2 contacted polysilicon pitches (e.g., 2CPP).

[0445] In some embodiments, the memory circuit 800 may be implemented as at least one memory cell 701a, 701b, 701c or 701d of the memory cell array 701 of Fig. 7A, and a similar detailed description is therefore omitted.

[0446] The memory circuit 800 includes the memory circuit 500A and the region 810. The memory circuit 500A is located adjacent to or directly next to the region 810.

[0447] The area 810 has a height RP in the first direction X.

[0448] Area 810 has an active area 802e.

[0449] The set of active regions 802 includes one or more of the active regions 502a, 502b, 502c, 502d, or 802e.

[0450] In some embodiments, the set of active regions 802 is the same as the set of active regions 502 of Fig. 5A, and a similar detailed description is therefore omitted. In some embodiments, the active region 802e is one or more of the active regions 502a, 502b, 502c, or 502d of the set of active regions 502 of Fig. 5A, and a similar detailed description is therefore omitted.

[0451] In some embodiments, the set of active regions 802 is formed by a corresponding set of active region patterns (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900. In some embodiments, the active region 802e of the set of active regions 802 is formed by corresponding active region patterns (not shown) of the set of active region patterns (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900.

[0452] In some embodiments, the active region 802e represents source and drain regions of NFET transistors of at least one of the memory cell 300B or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0453] In some embodiments, the active region 802e represents source and drain regions of PFET transistors of at least one of the memory cell 300B or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0454] Other configurations, arrangements at other levels, or numbers of regions in the set of active regions 802 are within the scope of the present disclosure.

[0455] Region 810 also includes at least one of gates 804e or 804f.

[0456] The set of gates 804 includes one or more of the gates 504a, 504b, 504c, 504d, 804e, or 804f.

[0457] In some embodiments, the set of gates 804 is similar to the set of gates 504 of Fig. 5A, and a similar detailed description is therefore omitted. In some embodiments, at least one or more of the gates 804e or 804f is associated with one or more of the gates 504a, 504b, 504c, or 504d of the set of gates 504 of Fig. 5A, and a similar detailed description is therefore omitted.

[0458] In some embodiments, the set of gates 804 is formed by a corresponding set of gate structures (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900. In some embodiments, the gates 804e or 804f of the set of gates 804 are formed by corresponding gate structures (not shown) of the set of gate structures (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900.

[0459] In some embodiments, each of the gates in the set of gates 804 is Fig. 5, Fig. 6, Fig. 8 and Fig. 9 with markings “N2-1, P2-1, N2-2, P2-2, N2-3, N2-4, N2-5, N2-6”, which are corresponding transistors of Fig. 3B, Fig. 7A and Fig. 7B, and they are omitted for brevity.

[0460] Other configurations, arrangements at other levels, or numbers of gates in the set of gates 804 are within the scope of the present disclosure.

[0461] In some embodiments, at least one via from the set of vias 702 is electrically coupled to at least one gate from the set of gates 804. In some embodiments, at least one via from the set of vias 704 is electrically coupled to at least one gate from the set of gates 804.

[0462] In some embodiments, at least one via from the set of vias 702 is electrically coupled to at least one active region from the set of active regions 802. In some embodiments, at least one via from the set of vias 704 is electrically coupled to at least one active region from the set of active regions 802.

[0463] Other embodiments of the memory circuit 800 are within the scope of the present disclosure.

[0464] Fig. 9 is a corresponding schematic diagram of a corresponding memory circuit 900, according to some embodiments.

[0465] The memory circuit 900 is associated with the memory cell array 202 of Fig. 2B. The memory circuit 900 is an embodiment of the memory cells 721b and 721a of the memory cell array 721 of Fig. 7B, and a similar detailed description is therefore omitted.

[0466] The memory circuit 900 is a modification of the memory circuit 600 of Fig. 6, and a similar detailed description is therefore omitted. In comparison with the memory circuit 600 of Fig. 6, the memory circuit 900 further includes a region 901a and a region 901b, and a similar detailed description is therefore omitted.

[0467] The memory circuit 900 is manufactured by a corresponding layout design similar to the memory circuit 900.

[0468] The memory circuit 900 has a height H4b in the first direction X. In some embodiments, the height H4b is equal to CH + RP, where CH is a scaled cell height in the first direction X of at least the memory circuit 900, and where RP is a cell height in the first direction X of at least the region 901b.

[0469] The memory circuit 900 has a width W4b in the second direction Y. In some embodiments, the width W4b is equal to 2CW, where CW is a scaled cell width in the second direction Y of at least the memory circuit 900.

[0470] In some embodiments, the memory circuit 900 has a width in the second direction Y that is equal to 4 contacted polysilicon pitches (e.g., 4CPP).

[0471] In some embodiments, the memory circuit 900 may be configured as the memory cell 721a and 721b of the memory cell array 721 of Fig. 7B, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 900 may be used as the memory cells 721c and 721d of the memory cell array 721 of Fig. 7B, and a similar detailed description is therefore omitted.

[0472] Memory circuit 900 includes memory circuit 600, region 901a, and region 901b. Memory circuit 600 is located adjacent to or directly next to region 901a. Region 901a is adjacent to region 901b. Region 901a is located between memory circuit 600 and region 901b.

[0473] In some embodiments, the region 901a is a mirror image of the memory circuit 600 with respect to a raster line 950 in the second direction Y, and a similar detailed description is therefore omitted. The raster line 950 extends in the second direction Y.

[0474] The region 901b has a height RP in the first direction X.

[0475] The region 901b has a region 910a and a region 910b.

[0476] Each of the region 910a and the region 910b has a width CW in the second direction Y.

[0477] Area 910a has an active area 902a.

[0478] The set of active regions 902 includes the active region 902a.

[0479] In some embodiments, the set of active regions 902 is the same as the set of active regions 602 of Fig. 6, and a similar detailed description is therefore omitted. In some embodiments, the active region 902a is one or more of the active regions 602a, 602b, 602c, or 602d of the set of active regions 602 of Fig. 6, and a similar detailed description is therefore omitted.

[0480] In some embodiments, the set of active regions 902 is formed by a corresponding set of active region patterns (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900. In some embodiments, the active region 902a of the set of active regions 902 is formed by corresponding active region patterns (not shown) of the set of active region patterns (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900.

[0481] In some embodiments, the active region 902a represents source and drain regions of NFET transistors of at least one of the memory cell 300B or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0482] In some embodiments, the active region 902a represents source and drain regions of PFET transistors of at least one of the memory cell 300B or the memory circuit 400A, 400B, 400C, 500A-500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0483] Other configurations, arrangements at other levels, or numbers of regions in the set of active regions 902 are within the scope of the present disclosure.

[0484] The region 910a also includes at least one of the gates 904a or 904b.

[0485] The set of gates 904 includes one or more of the gates 904a, 904b, 904c, or 904d.

[0486] In some embodiments, the set of gates 904 is similar to the set of gates 604 of Fig. 6, and a similar detailed description is therefore omitted. In some embodiments, at least one or more of the gates 904a, 904b, 904c, or 904d is associated with one or more of the gates 604a, 604b, 604c, or 604d of the set of gates 604 of Fig. 6, and a similar detailed description is therefore omitted.

[0487] In some embodiments, the set of gates 904 is formed by a corresponding set of gate structures (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900. In some embodiments, the gates 904a, 904b, 904c, or 904d of the set of gates 904 are formed by corresponding gate structures (not shown) of the set of gate structures (not shown) of a corresponding layout design of the memory circuit 500A-500B, 600, 800, or 900.

[0488] In some embodiments, each of the gates in the set of gates 904 is Fig. 5, Fig. 6, Fig. 8 and Fig. 9 with markings “N2-1, P2-1, N2-2, P2-2, N2-3, N2-4, N2-5, N2-6”, which are corresponding transistors of Fig. 3B, Fig. 7A and Fig. 7B, and they are omitted for brevity.

[0489] Other configurations, arrangements at other levels, or numbers of gates in the set of gates 904 are within the scope of the present disclosure.

[0490] Region 910b includes a portion of active region 902a and at least one of gates 904c or 904d. In some embodiments, at least one of gates 904c or 904d is a gate of a dummy transistor. In some embodiments, a portion of active region 902a disposed in region 910b is part of the dummy transistor.

[0491] In some embodiments, at least one via from the set of vias 722 is electrically coupled to at least one gate from the set of gates 904. In some embodiments, at least one via from the set of vias 724 is electrically coupled to at least one gate from the set of gates 904.

[0492] In some embodiments, at least one via from the set of vias 722 is electrically coupled to at least one active region from the set of active regions 902. In some embodiments, at least one via from the set of vias 724 is electrically coupled to at least one active region from the set of active regions 902.

[0493] Other embodiments of the memory circuit 900 are within the scope of the present disclosure.

[0494] Fig. 10 is a schematic diagram of a memory circuit 1000, according to some embodiments.

[0495] In some embodiments, the memory circuit 1000 is an integrated circuit chip. In some embodiments, the memory circuit 1000 is an embodiment of the memory circuit 100 of Fig. 1, and a similar detailed description is therefore omitted.

[0496] The memory circuit 1000 includes a memory circuit 1002 and a memory circuit 1004.

[0497] In some embodiments, the memory circuit 1000 includes memory circuits of different types, and therefore the memory circuit 1000 is referred to as a “mixed cell.”

[0498] In some embodiments, the memory circuit 1002 is the memory circuit 400B of Fig. 4B, and a similar detailed description is therefore omitted. In these embodiments, the memory circuit 1002 is the memory circuit 400B of Fig. 4B, has one or more copies of the memory circuit 600 of Fig. 6, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 1002 is the memory circuit 200A of Fig. 2A, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 1002 comprises one or more portions of the memory circuit 200A of Fig. 2A, which are similar to area 201a, and a similar detailed description is therefore omitted.

[0499] In some embodiments, the memory circuit 1004 is the memory circuit 400C of Fig. 4C, and a similar detailed description is therefore omitted. In these embodiments, the memory circuit 1004 comprises one or more copies of the memory circuit 600 of Fig. 6, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 1004 is the memory circuit 200A of Fig. 2A, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 1004 comprises one or more portions of the memory circuit 200A of Fig. 2A, which are similar to area 201a, and a similar detailed description is therefore omitted.

[0500] The memory circuit 1000 is illustrated as including a memory circuit 1002 and a memory circuit 1004. In some embodiments, the memory circuit 1000 includes at least two or more of the memory circuit 1002. In some embodiments, the memory circuit 1000 includes at least two or more of the memory circuit 1004. Other locations in the memory circuit 1000 for at least one of the memory circuit 1002 or the memory circuit 1004 are within the scope of the present disclosure.

[0501] In some embodiments, memory circuit 1002 is generated by a first memory compiler. In some embodiments, memory circuit 1002 is generated by an SRAM memory compiler. Other types of memory compilers are within the scope of the present disclosure.

[0502] In some embodiments, memory circuit 1004 is generated by a second memory compiler. In some embodiments, memory circuit 1004 is generated by an SRAM memory compiler. Other types of memory compilers are within the scope of the present disclosure.

[0503] The memory circuit 1002 has a height H5a in the second direction Y. In some embodiments, the height H5a is equal to the height H1b of the memory circuit 400B of Fig. 4B.

[0504] The memory circuit 1002 has a width W5a in the first direction X. In some embodiments, the width W5a is equal to the width W1b of the memory circuit 400B of Fig. 4B.

[0505] The memory circuit 1004 has a height H5b in the second direction Y. In some embodiments, the height H5b is equal to the height H1c of the memory circuit 400C of Fig. 4C.

[0506] The memory circuit 1004 has a width W5b in the first direction X. In some embodiments, the width W5b is equal to the width W1c of the memory circuit 400C of Fig. 4C.

[0507] In some embodiments, the height H5a is different from the height H5b. In some embodiments, the height H5a is equal to the height H5b.

[0508] In some embodiments, the width W5a is different from the width W5b. In some embodiments, the width W5a is equal to the width W5b.

[0509] The memory circuit 1002 includes a memory cell 1002a, a memory cell 1002b, a set of bit lines BL1, a set of bit line bars BLB1, and a set of word lines WL1.

[0510] In some embodiments, memory cell 1002a is at least one of memory cells 411a, 411b, 411c, or 411d in one of columns 1 or 2, and memory cell 1002b is at least another of memory cells 411a, 411b, 411c, or 411d in the other of columns 1 or 2. For ease of illustration, memory circuit 1002 is illustrated as having two memory cells (memory cells 1002a and 1002b). However, other numbers of memory cells in memory circuit 1002 are within the scope of the present disclosure.

[0511] For ease of illustration, memory circuit 1002 is illustrated as having two columns of memory cells and two rows of memory cells. However, other numbers of rows or columns of memory cells in memory circuit 1002 are within the scope of the present disclosure.

[0512] The memory circuit 1004 includes a memory cell 1004a, a memory cell 1004b, a set of bit lines BL2, a set of bit line bars BLB2, and a set of word lines WL2.

[0513] In some embodiments, memory cell 1004a is at least one of memory cells 421a, 421b, 421c, or 421d in one of columns 1 or 2, and memory cell 1004b is at least another of memory cells 421a, 421b, 421c, or 421d in the other of columns 1 or 2. For ease of illustration, memory circuit 1004 is illustrated as having two memory cells (memory cells 1004a and 1004b). However, other numbers of memory cells in memory circuit 1004 are within the scope of the present disclosure.

[0514] For ease of illustration, memory circuit 1004 is illustrated as having two columns of memory cells and two rows of memory cells. However, other numbers of rows or columns of memory cells in memory circuit 1004 are within the scope of the present disclosure.

[0515] In some embodiments, the set of bit lines BL1 or BL2 is connected to one or more of Fig. 10, Fig. 11 or Fig. 12 similar to the set of bit lines BL of Fig. 4A to 4C, 6, 7A-7B, 8 and 9, and a similar detailed description is therefore omitted.

[0516] In some embodiments, the set of bit line bars BLB1 or BLB2 is comprised of one or more of Fig. 10, Fig. 11 or Fig. 12 similar to the set of bit line bars BLB of Fig. 4A to 4C, 6, 7A-7B, 8 and 9, and a similar detailed description is therefore omitted.

[0517] In some embodiments, the set of word lines WL1 or WL2 is formed by one or more of Fig. 10, Fig. 11 or Fig. 12 similar to the set of word lines WL of Fig. 4A to 4C, 6, 7A-7B, 8 and 9, and a similar detailed description is therefore omitted.

[0518] The set of word lines WL1 has a length L1a in the second direction Y.

[0519] The set of bit lines BL1 and the set of bit line bars BLB1 have a length L1b in the first direction X.

[0520] In some embodiments, the length L1a of the set of word lines WL1 is greater than the length L1b of the set of bit lines BL1 and the length L1b of the set of bit line bars BLB1. In some embodiments, memory circuits such as memory circuit 1002 are referred to as having a "tall cell" (and also having a "tall footprint") because the length L1a of the set of word lines WL1 is greater than the length L1b of the set of bit lines BL1 and the length L1b of the set of bit line bars BLB1. In some embodiments, the set of word lines WL1 is referred to as "long" because the length L1a of the set of word lines WL1 is greater than the length L1b of the set of bit lines BL1 and the length L1b of the set of bit line bars BLB1.

[0521] The set of word lines WL2 has a length L2a in the second direction Y.

[0522] The set of bit lines BL2 and the set of bit line bars BLB2 have a length L2b in the first direction X.

[0523] In some embodiments, the length L2a of the set of word lines WL2 is less than the length L2b of the set of bit lines BL2 and the length L2b of the set of bit line bars BLB2. In some embodiments, memory circuits, such as memory circuit 1004, are referred to as "a long cell" (and also having a "long footprint") because the length L2a of the set of word lines WL2 is less than the length L2b of the set of bit lines BL2 and the length L2b of the set of bit line bars BLB2. In some embodiments, the set of bit lines BL2 or the set of bit line bars BLB2 is referred to as "long" because the length L2a of the set of word lines WL2 is less than the length L2b of the set of bit lines BL2 and the length L2b of the set of bit line bars BLB2.

[0524] In some embodiments, the length L1a of the set of word lines WL1 is greater than the length L2a of the set of word lines WL2.

[0525] In some embodiments, at least one of the length L1b of the set of bitlines BL1 or the length L1b of the set of bitline bars BLB2 is smaller than at least one of the length L2b of the set of bitlines BL2 or the length L2b of the set of bitline bars BLB2.

[0526] In some embodiments, memory circuit 1000 includes different memory circuits (e.g., memory circuit 1002 and memory circuit 1004) with different corresponding dimensions (e.g., tall cells and long cells) in the same direction, and therefore, memory circuit 1000 is referred to as a "mixed cell array." In some embodiments, memory circuits (e.g., memory circuit 1002 and memory circuit 1004) with different corresponding dimensions in the same direction have different corresponding resistance and capacitance characteristics (e.g., as shown in Table 1 below). In some embodiments, the different characteristics of memory circuit 1000 include one or more of a resistance of the bit line or bit line bar, a resistance of the word line, a capacitance of the bit line or bit line bar, or a capacitance of the word line.

[0527] In some embodiments, by using the memory circuit 1002 and the memory circuit 1004 with different corresponding characteristics (e.g., the resistance of the bit line or bit line bar, the resistance of the word line, the capacitance of the bit line or bit line bar, the capacitance of the word line), a design of the memory circuit 1000 becomes more flexible than other approaches with the same type of cells with the same type of characteristics, and the performance of the memory circuit 1000 is greater than other approaches. In some embodiments, memory circuits (e.g.,the memory circuit 1002 and the memory circuit 1004) with different respective dimensions in the same direction have optimized respective resistance and capacitance characteristics compared to other approaches with the same type of cells with the same type of characteristics, and result in better performance than other approaches.

[0528] In some embodiments, a wordline resistance (WL-R), a wordline capacitance (WL-C), a bitline or bitline bar resistance (BL-R), a bitline or bitline bar capacitance (BL-C) are each provided by the memory circuit 1002 (e.g., marked as "4CCP"), the memory circuit 1004 (e.g., marked as "Pseudo-4CPP"), and the memory circuit 1102 (e.g., marked as "2CPP" and in Fig. 11) are shown in Table 1.

[0529] Table 1 is a table of various cells and parameters of the memory circuit 1002 (e.g., marked as “4CPP”), the memory circuit 1004 (e.g., marked as “Pseudo-4CPP”) and the memory circuit 1102 (e.g., marked as “2CPP” and in Fig. 11). Table 1 Zelle 2CPP 4CPP Pseudo-4CPP Zellenhöhe (äquivalent) Referenz 0,5x 1X Zellenbreite (äquivalent) Referenz 2X 1x BL-R Referenz Referenz 1x 0,5x BL-C Referenz Referenz 2X 1X WL-R Referenz Referenz 0,5x 1,2X WL-C Referenz Referenz 0,5x 1,2X

[0530] Table 1 has 7 rows and 4 columns. Row 1 has different cell types. Row 2 has an equivalent cell height for the corresponding cells. Row 3 has an equivalent cell width for the corresponding cells. Row 4 has a bitline or bitline bar resistance (BL-R) for the corresponding cells with respect to the 2CPP cell. Row 5 has a bitline or bitline bar capacitance (BL-C) for the corresponding cells with respect to the 2CPP cell. Row 6 has a wordline resistance (WL-R) for the corresponding cells with respect to the 2CPP cell. Row 7 has a wordline capacitance (WL-C) for the corresponding cells with respect to the 2CPP cell. Other numbers of columns or rows in Table 1 are within the scope of the present disclosure.

[0531] In some embodiments, the cell entry marked “2CPP” in Table 1 comprises one or more memory circuits from the memory circuit 400A of Fig. 4A, the memory circuit 500B of Fig. 5A, the memory circuit 700A of Fig. 7A or the memory circuit 800 of Fig. 8, and a similar detailed description is therefore omitted.

[0532] In some embodiments, the cell entry marked “4CPP” in Table 1 includes one or more memory circuits from the memory circuit 400B of Fig. 4B or the memory circuit 600 of Fig. 6, and a similar detailed description is therefore omitted.

[0533] In some embodiments, the cell entry in Table 1 labeled “Pesudo-4CPP” includes one or more memory circuits from the memory circuit 400C of Fig. 4C, the memory circuit 600 of Fig. 6, the memory circuit 700B of Fig. 7B or the memory circuit 900 of Fig. 9, and a similar detailed description is therefore omitted.

[0534] As shown in Table 1, the memory circuit 1002 (e.g., labeled "4CPP") has reduced WL-R or WL-C characteristics compared to the memory circuit 1004 (e.g., labeled "Pseudo-4CPP").

[0535] As shown in Table 1, the memory circuit 1004 (e.g., labeled "Pseudo-4CPP") has reduced BL-R or BL-C characteristics compared to the memory circuit 1002 (e.g., labeled "4CPP").

[0536] In some embodiments, memory circuit 1002 may be used for a high-cell or high-footprint SRAM compiler, and the set of word lines WL1 of memory circuit 1002 is also referred to as "long," as discussed above. For example, in some embodiments, since memory circuit 1002 may be used for a high-cell or high-footprint SRAM compiler (e.g., long word lines WL1), a memory circuit design with reduced WL-R or WL-C characteristics (e.g., 4CPP cell in Table 1) is used instead of a memory circuit design with reduced BL-R characteristics (e.g., pseudo-4CPP cell in Table 1). Therefore, although the memory circuit 1002 has a high footprint (e.g., long word lines WL1), the reduced WL-R or WL-C characteristics of the memory circuit 1002 compensate for the longer word lines WL1.

[0537] In some embodiments, the memory circuit 1004 may be used for an SRAM compiler with long cells or a long footprint, and the set of bitlines BL2 or the set of bitlines BLB2 of the memory circuit 1002 is also referred to as "long," as discussed above. For example, in some embodiments, since the memory circuit 1004 may be used for an SRAM compiler with long cells or a long footprint (e.g., long bitlines BL2 or long bitline bars BLB2), a memory circuit design (e.g., pseudo-4CPP cell in Table 1) with reduced BL-R characteristics is used instead of a memory circuit design with reduced WL-R or WL-C characteristics (e.g., 4CPP cell in Table 1). Although the memory circuit 1004 has a long footprint (e.g.,long bit lines BL2 or long bit line bars BLB2), the reduced BL-R characteristic of the memory circuit 1004 therefore compensates for the longer bit lines BL2 or bit line bars BLB2.

[0538] In some embodiments, technical compromises are made to balance the WL-R, WL-C, BL-R, and BL-C characteristics for cell type selection in memory circuit 1000. In some embodiments, combining cells of the memory circuits with different corresponding characteristics enables memory circuit 1000 to have better overall performance than a memory circuit having only a single memory cell type with the same corresponding characteristics. For example, according to some embodiments, memory circuit 1002 is combined with memory circuit 1004 such that memory circuit 1000 has the reduced WL-R or WL-C characteristics of memory circuit 1002 from Table 1 and the reduced BL-R characteristics of memory circuit 1004 from Table 1.In some embodiments, combining different cells of the memory circuits (e.g., memory circuits 1002 and 1004) with different corresponding characteristics into a single memory circuit, such as memory circuit 1000, results in more manufacturing steps during the manufacture of the memory circuit.

[0539] In some embodiments, by combining memory circuit 1002 with memory circuit 1004 into a single memory circuit 1000, the design of memory circuit 1000 is more flexible than other approaches using the same type of cells with the same type of characteristics, and the performance of memory circuit 1000 is better than other approaches. In some embodiments, by combining memory circuit 1002 with memory circuit 1004 into a single memory circuit 1000, the resistance and capacitance characteristics of memory circuit 1000 are optimized compared to other approaches using the same type of cells with the same type of characteristics, and it results in better performance than other approaches.

[0540] Other embodiments of the memory circuit 1000 are within the scope of the present disclosure.

[0541] Fig. 11 is a schematic diagram of a memory circuit 1100, according to some embodiments.

[0542] The memory circuit 1100 is a modification of the memory circuit 1000 of Fig. 10, and a similar detailed description is therefore omitted. In comparison with the memory circuit 1000 of Fig. 10, the memory circuit 1002 of Fig. 10 by a memory circuit 1102 of Fig. 11, and a similar detailed description is therefore omitted.

[0543] In some embodiments, the memory circuit 1100 is an integrated circuit chip.

[0544] The memory circuit 1100 includes the memory circuit 1102 and a memory circuit 1004.

[0545] In some embodiments, the memory circuit 1100 includes memory circuits of different types, and therefore the memory circuit 1100 is referred to as a “mixed cell.”

[0546] In some embodiments, the memory circuit 1102 is the memory circuit 400A of Fig. 4A, and a similar detailed description is therefore omitted. In these embodiments, the memory circuit 1102 is the memory circuit 400A of Fig. 4A, has one or more copies of the memory circuit 500A of Fig. 5A, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 1102 is the memory circuit 200A of Fig. 2A, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 1102 comprises one or more portions of the memory circuit 200A of Fig. 2, which are similar to area 201a, and a similar detailed description is therefore omitted.

[0547] Memory circuit 1100 is illustrated as including memory circuit 1102 and memory circuit 1104. In some embodiments, memory circuit 1100 includes at least two or more of memory circuit 1102. In some embodiments, memory circuit 1100 includes at least two or more of memory circuit 1104. Other locations in memory circuit 1100 for at least one of memory circuit 1104 or memory circuit 1102 are within the scope of the present disclosure.

[0548] In some embodiments, memory circuit 1102 is generated by a third memory compiler. In some embodiments, memory circuit 1102 is generated by an SRAM memory compiler. Other types of memory compilers are within the scope of the present disclosure.

[0549] The memory circuit 1102 has a height H5c in the second direction Y. In some embodiments, the height H5c is equal to the height H1a of the memory circuit 400A of Fig. 4A.

[0550] The memory circuit 1102 has a width W5c in the first direction X. In some embodiments, the width W5c is equal to the width W1a of the memory circuit 400A of Fig. 4A.

[0551] In some embodiments, the height H5c is different from the height H5b. In some embodiments, the height H5c is equal to the height H5b.

[0552] In some embodiments, the width W5c is different from the width W5b. In some embodiments, the width W5c is equal to the width W5b.

[0553] The memory circuit 1102 includes a memory cell 1102a, a memory cell 1102b, a set of bit lines BL3, a set of bit line bars BLB3, and a set of word lines WL3.

[0554] In some embodiments, memory cell 1102a is at least one of memory cells 401a, 401b, 401c, or 401d in one of columns 1 or 2, and memory cell 1102b is at least another of memory cells 401a, 401b, 401c, or 401d in the other of columns 1 or 2. For ease of illustration, memory circuit 1102 is illustrated as having two memory cells (memory cells 1102a and 1102b). However, other numbers of memory cells in memory circuit 1102 are within the scope of the present disclosure.

[0555] For ease of illustration, memory circuit 1102 is illustrated as having two columns of memory cells and two rows of memory cells. However, other numbers of rows or columns of memory cells in memory circuit 1102 are within the scope of the present disclosure.

[0556] In some embodiments, the set of bit lines BL3 is comprised of one or more of Fig. 11 or Fig. 12 similar to the set of bit lines BL of Fig. 4A to 4C, 6, 7A-7B, 8 and 9, and a similar detailed description is therefore omitted.

[0557] In some embodiments, the set of bit line bars BLB3 is comprised of one or more of Fig. 11 or Fig. 12 similar to the set of bit line bars BLB of Fig. 4A to 4C, 6, 7A-7B, 8 and 9, and a similar detailed description is therefore omitted.

[0558] In some embodiments, the set of word lines WL3 is comprised of one or more of Fig. 11 or Fig. 12 similar to the set of word lines WL of Fig. 4A to 4C, 6, 7A-7B, 8 and 9, and a similar detailed description is therefore omitted.

[0559] The set of word lines WL3 has a length L3a in the second direction Y.

[0560] The set of bit lines BL3 and the set of bit line bars BLB3 have a length L3b in the first direction X.

[0561] In some embodiments, the length L3a of the set of word lines WL3 is greater than the length L3b of the set of bit lines BL3 and the length L3b of the set of bit line bars BLB3. In some embodiments, memory circuits such as memory circuit 1102 are referred to as having a "tall cell" (and also having a "tall footprint") because the length L3a of the set of word lines WL3 is greater than the length L3b of the set of bit lines BL3 and the length L3b of the set of bit line bars BLB3. In some embodiments, the set of word lines WL3 is referred to as "long" because the length L3a of the set of word lines WL3 is greater than the length L3b of the set of bit lines BL3 and the length L3b of the set of bit line bars BLB3.

[0562] In some embodiments, the length L3a of the set of word lines WL3 is greater than the length L2a of the set of word lines WL2.

[0563] In some embodiments, at least one of the length L3b of the set of bitlines BL3 or the length L3b of the set of bitline bars BLB2 is smaller than at least one of the length L2b of the set of bitlines BL2 or the length L2b of the set of bitline bars BLB2.

[0564] In some embodiments, memory circuit 1100 includes various memory circuits (e.g., memory circuit 1102 and memory circuit 1104) with different corresponding dimensions (e.g., tall cells and long cells) in the same direction, and therefore, memory circuit 1100 is referred to as a "mixed cell array." In some embodiments, memory circuits (e.g., memory circuit 1102 and memory circuit 1104) with different corresponding dimensions in the same direction have different corresponding resistance and capacitance characteristics (e.g., as shown above in Table 1).

[0565] In some embodiments, by using the memory circuit 1102 and the memory circuit 1104 with different corresponding characteristics (e.g., the resistance of the bit line or bit line bar, the resistance of the word line, the capacitance of the bit line or bit line bar, the capacitance of the word line), a design of the memory circuit 1100 becomes more flexible than other approaches with the same type of cells with the same type of characteristics, and the performance of the memory circuit 1100 is greater than other approaches. In some embodiments, memory circuits (e.g.,the memory circuit 1102 and the memory circuit 1004) with different respective dimensions in the same direction have optimized respective resistance and capacitance characteristics compared to other approaches with the same type of cells with the same type of characteristics, and result in better performance than other approaches.

[0566] As shown above in Table 1, the memory circuit 1102 (e.g., labeled "2CPP") has reduced WL-R or WL-C characteristics compared to the memory circuit 1004 (e.g., labeled "pseudo-4CPP").

[0567] As shown in Table 1, the memory circuit 1004 (e.g., labeled "Pseudo-4CPP") has a reduced BL-R characteristic compared to the memory circuit 1102 (e.g., labeled "2CPP").

[0568] As shown in Table 1, the memory circuit 1004 (e.g., labeled “Pseudo-4CPP”) has a similar BL-C characteristic compared to the memory circuit 1102 (e.g., labeled “2CPP”).

[0569] In some embodiments, memory circuit 1102 may be used for a high-cell or high-footprint SRAM compiler, and the set of word lines WL3 of memory circuit 1102 is also referred to as "long," as discussed above. For example, in some embodiments, since memory circuit 1102 may be used for a high-cell or high-footprint SRAM compiler (e.g., long word lines WL3), a memory circuit design with reduced WL-R or WL-C characteristics (e.g., 4CPP cell in Table 1) is used instead of a memory circuit design with reduced BL-R characteristics (e.g., pseudo-4CPP cell in Table 1). Therefore, although the memory circuit 1102 has a high footprint (e.g., long word lines WL3), the reduced WL-R or WL-C characteristics of the memory circuit 1102 compensate for the longer word lines WL3.

[0570] In some embodiments, combining cells of the memory circuits with different corresponding characteristics enables the memory circuit 1100 to have better overall performance than a memory circuit that only has a single memory cell type with the same corresponding characteristics. For example, the memory circuit 1102 is combined with the memory circuit 1004 such that, according to some embodiments, the memory circuit 1100 has the reduced WL-R or WL-C characteristics of the memory circuit 1102 from Table 1 and the reduced BL-R characteristics of the memory circuit 1004 from Table 1. In some embodiments, combining different cells of the memory circuits (e.g., the memory circuits 1102 and 1004) with different corresponding characteristics results in a single circuit, such asthe memory circuit 1100, to more manufacturing steps during the manufacture of the memory circuit.

[0571] In some embodiments, by combining memory circuit 1102 with memory circuit 1004 into a single memory circuit 1100, the design of memory circuit 1100 is more flexible than other approaches using the same type of cells with the same type of characteristics, and the performance of memory circuit 1100 is better than other approaches. In some embodiments, by combining memory circuit 1102 with memory circuit 1004 into a single memory circuit 1100, the resistance and capacitance characteristics of memory circuit 1100 are optimized compared to other approaches using the same type of cells with the same type of characteristics, and it results in better performance than other approaches.

[0572] Other embodiments of the memory circuit 1100 are within the scope of the present disclosure.

[0573] Fig. 12 is a schematic diagram of a memory circuit 1200, according to some embodiments.

[0574] The memory circuit 1200 is a modification of the memory circuit 1000 of Fig. 10 and the memory circuit 1100 of Fig. 11, and a similar detailed description is therefore omitted. In comparison with the memory circuit 1000 of Fig. 10, the memory circuit 1200 of Fig. 12 also the memory circuit 1102 of Fig. 11, and a similar detailed description is therefore omitted. In comparison with the memory circuit 1100 of Fig. 11, the memory circuit 1200 of Fig. 12 also the memory circuit 1002 of Fig. 10, and a similar detailed description is therefore omitted.

[0575] In some embodiments, the memory circuit 1200 is an integrated circuit chip.

[0576] The memory circuit 1200 includes the memory circuit 1002, the memory circuit 1004 and the memory circuit 1102.

[0577] Memory circuit 1200 is illustrated as including memory circuit 1002, memory circuit 1004, and memory circuit 1102. In some embodiments, memory circuit 1200 includes at least two or more of memory circuit 1002. In some embodiments, memory circuit 1200 includes at least two or more of memory circuit 1004. In some embodiments, memory circuit 1200 includes at least two or more of memory circuit 1102. Other locations in memory circuit 1200 for at least one of memory circuit 1002, memory circuit 1004, or memory circuit 1102 are within the scope of the present disclosure.

[0578] In some embodiments, at least one of the heights H5a, H5b, or H5c is different from at least one other of the heights H5a, H5b, or H5c. In some embodiments, at least one of the heights H5a, H5b, or H5c is equal to at least one other of the heights H5a, H5b, or H5c.

[0579] In some embodiments, at least one of the widths W5a, W5b, or W5c is different from at least one other of the widths W5a, W5b, or W5c. In some embodiments, at least one of the widths W5a, W5b, or W5c is equal to at least one other of the widths W5a, W5b, or W5c.

[0580] In some embodiments, at least one of the lengths L1a, L2a, or L3a is different from at least one other of the lengths L1a, L2a, or L3a. In some embodiments, at least one of the lengths L1a, L2a, or L3a is equal to at least one other of the lengths L1a, L2a, or L3a.

[0581] In some embodiments, at least one of the lengths L1b, L2b, or L3b is different from at least one other of the lengths L1b, L2b, or L3b. In some embodiments, at least one of the lengths L1b, L2b, or L3b is equal to at least one other of the lengths L1b, L2b, or L3b.

[0582] The memory circuit 1200 achieves one or more of the advantages discussed herein.

[0583] Other embodiments of the memory circuit 1200 are within the scope of the present disclosure.

[0584] Fig. 13 is a schematic diagram of a memory circuit 1300, according to some embodiments.

[0585] The memory circuit 1300 is a modification of the memory circuit 1100 of Fig. 11, and a similar detailed description is therefore omitted. In comparison with the memory circuit 1100 of Fig. 11 is the memory circuit 1102 of Fig. 11 by a memory circuit 1302 of Fig. 13, the memory circuit 1004 of Fig. 11 is represented by a memory circuit 1304 of Fig. 13, and a similar detailed description is therefore omitted.

[0586] In some embodiments, the memory circuit 1300 is an integrated circuit chip.

[0587] The memory circuit 1300 includes the memory circuit 1302 and the memory circuit 1304.

[0588] In some embodiments, the memory circuit 1300 includes memory circuits of different types, and therefore the memory circuit 1300 is referred to as a “mixed cell.”

[0589] In some embodiments, the memory circuit 1302 is the memory circuit 700A of Fig. 7A, and a similar detailed description is therefore omitted. In these embodiments, the memory circuit 1302 is the memory circuit 700A of Fig. 7A, has one or more copies of the memory circuit 800 of Fig. 8, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 1302 is the memory circuit 200B of Fig. 2B, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 1302 comprises one or more portions of the memory circuit 200B of Fig. 2B, which are similar to area 201b, and a similar detailed description is therefore omitted.

[0590] In some embodiments, the memory circuit 1304 is the memory circuit 700B of Fig. 7B, and a similar detailed description is therefore omitted. In these embodiments, the memory circuit 1304 comprises one or more copies of the memory circuit 900 of Fig. 9, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 1304 is the memory circuit 200B of Fig. 2B, and a similar detailed description is therefore omitted. In some embodiments, the memory circuit 1304 comprises one or more portions of the memory circuit 200B of Fig. 2B, which are similar to area 201b, and a similar detailed description is therefore omitted.

[0591] Memory circuit 1300 is illustrated as including memory circuit 1302 and memory circuit 1304. In some embodiments, memory circuit 1300 includes at least two or more of memory circuit 1302. In some embodiments, memory circuit 1300 includes at least two or more of memory circuit 1304. Other locations in memory circuit 1300 for at least one of memory circuit 1302 or memory circuit 1304 are within the scope of the present disclosure.

[0592] In some embodiments, memory circuit 1302 is generated by a fourth memory compiler. In some embodiments, memory circuit 1302 is generated by an SRAM memory compiler. Other types of memory compilers are within the scope of the present disclosure.

[0593] In some embodiments, memory circuit 1304 is generated by a fifth memory compiler. In some embodiments, memory circuit 1304 is generated by an SRAM memory compiler. Other types of memory compilers are within the scope of the present disclosure.

[0594] The memory circuit 1302 has a height H6a in the second direction Y. In some embodiments, the height H6a is equal to the height H3a of the memory circuit 700A of Fig. 7A.

[0595] The memory circuit 1302 has a width W6a in the first direction X. In some embodiments, the width W6a is equal to the width W3a of the memory circuit 700A of Fig. 7A.

[0596] The memory circuit 1304 has a height H6b in the second direction Y. In some embodiments, the height H6b is equal to the height H3b of the memory circuit 700B of Fig. 7B.

[0597] The memory circuit 1304 has a width W6b in the first direction X. In some embodiments, the width W6b is equal to the width W3b of the memory circuit 700B of Fig. 7B.

[0598] In some embodiments, the height H6a is different from the height H6b. In some embodiments, the height H6a is equal to the height H6b.

[0599] In some embodiments, the width W6a is different from the width W6b. In some embodiments, the width W6a is equal to the width W6b.

[0600] The memory circuit 1302 includes a memory cell 1302a, a memory cell 1302b, a set of bit lines BL4, a set of bit line bars BLB4, and a set of word lines WL4.

[0601] In some embodiments, memory cell 1302a is at least one of memory cells 701a, 701b, 701c, or 701d in one of columns 1 or 2, and memory cell 1302b is at least another of memory cells 701a, 701b, 701c, or 701d in the other of columns 1 or 2. For ease of illustration, memory circuit 1302 is illustrated as having two memory cells (memory cells 1302a and 1302b). However, other numbers of memory cells in memory circuit 1302 are within the scope of the present disclosure.

[0602] For ease of illustration, memory circuit 1302 is illustrated as having two columns of memory cells and two rows of memory cells. However, other numbers of rows or columns of memory cells in memory circuit 1302 are within the scope of the present disclosure.

[0603] The memory circuit 1304 includes a memory cell 1304a, a memory cell 1304b, a set of bit lines BLS, a set of bit line bars BLB5, and a set of word lines WL5.

[0604] In some embodiments, memory cell 1304a is at least one of memory cells 721a, 721b, 721c, or 721d in one of columns 1 or 2, and memory cell 1304b is at least another of memory cells 721a, 721b, 721c, or 721d in the other of columns 1 or 2. For ease of illustration, memory circuit 1304 is illustrated as having two memory cells (memory cells 1304a and 1304b). However, other numbers of memory cells in memory circuit 1304 are within the scope of the present disclosure.

[0605] For ease of illustration, memory circuit 1304 is illustrated as having two columns of memory cells and two rows of memory cells. However, other numbers of rows or columns of memory cells in memory circuit 1304 are within the scope of the present disclosure.

[0606] In some embodiments, the set of bit lines BL4 or BL5 is connected to one or more of Fig. 13 or Fig. 14 similar to the set of bit lines BL of Fig. 7A-7B, 8 and 9, and a similar detailed description is therefore omitted.

[0607] In some embodiments, the set of bit line bars BLB4 or BLB5 is comprised of one or more of Fig. 13 or Fig. 14 similar to the set of bit line bars BLB of Fig. 7A-7B, 8 and 9, and a similar detailed description is therefore omitted.

[0608] In some embodiments, the set of word lines WL4 or WL5 is formed by one or more of Fig. 13 or Fig. 14 similar to the set of word lines WL of Fig. 7A-7B, 8 and 9, and a similar detailed description is therefore omitted.

[0609] The set of word lines WL4 has a length L4a in the second direction Y.

[0610] The set of bit lines BL4 and the set of bit line bars BLB4 have a length L4b in the first direction X.

[0611] In some embodiments, the length L4a of the set of word lines WL4 is greater than the length L4b of the set of bit lines BL4 and the length L4b of the set of bit line bars BLB4. In some embodiments, memory circuits such as memory circuit 1302 are referred to as having a "tall cell" (and also having a "tall footprint") because the length L4a of the set of word lines WL4 is greater than the length L4b of the set of bit lines BL4 and the length L4b of the set of bit line bars BLB4. In some embodiments, the set of word lines WL4 is referred to as "long" because the length L4a of the set of word lines WL4 is greater than the length L4b of the set of bit lines BL4 and the length L4b of the set of bit line bars BLB4.

[0612] The set of word lines WL5 has a length L5a in the second direction Y.

[0613] The set of bit lines BL5 and the set of bit line bars BLB5 have a length L5b in the first direction X.

[0614] In some embodiments, the length L5a of the set of word lines WL5 is less than the length L5b of the set of bit lines BL5 and the length L5b of the set of bit line bars BLB5. In some embodiments, memory circuits, such as memory circuit 1304, are referred to as "a long cell" (and also having a "long footprint") because the length L5a of the set of word lines WL5 is less than the length L5b of the set of bit lines BL5 and the length L5b of the set of bit line bars BLB5. In some embodiments, the set of bit lines BL5 or the set of bit line bars BLB5 is referred to as "long" because the length L5a of the set of word lines WL5 is less than the length L5b of the set of bit lines BL5 and the length L5b of the set of bit line bars BLB5.

[0615] In some embodiments, the length L4a of the set of word lines WL4 is greater than the length L5a of the set of word lines WL5.

[0616] In some embodiments, at least one of the length L4b of the set of bitlines BL4 or the length L4b of the set of bitline bars BLB5 is smaller than at least one of the length L5b of the set of bitlines BL5 or the length L5b of the set of bitline bars BLB5.

[0617] In some embodiments, memory circuit 1300 includes different memory circuits (e.g., memory circuit 1302 and memory circuit 1304) with different corresponding dimensions (e.g., tall cells and long cells) in the same direction, and therefore, memory circuit 1300 is referred to as a "mixed cell array." In some embodiments, memory circuits (e.g., memory circuit 1302 and memory circuit 1304) with different corresponding dimensions in the same direction have different corresponding resistance and capacitance characteristics (e.g., as discussed above in Table 1). In some embodiments, the different characteristics of memory circuit 1300 include one or more of a bitline or bitline bar resistance, a wordline resistance, a bitline or bitline bar capacitance, or a wordline capacitance.

[0618] The memory circuit 1300 achieves one or more of the advantages discussed herein.

[0619] In some embodiments, a wordline resistance (WL-R), a wordline capacitance (WL-C), a bitline or bitline bar resistance (BL-R), a bitline or bitline bar capacitance (BL-C) of each of memory circuit 1302 (e.g., marked as "2CCP") and memory circuit 1304 (e.g., marked as "Pseudo-4CPP") are shown in Table 1. In some embodiments, Table 1 is also a table of various cells and parameters of memory circuit 1302 (e.g., marked as "2CPP") and memory circuit 1304 (e.g., marked as "Pseudo-4CPP").

[0620] As shown in Table 1, the memory circuit 1302 has similar characteristics to the memory circuit 1102, and a similar detailed description is therefore omitted.

[0621] As shown in Table 1, the memory circuit 1304 has similar characteristics to the memory circuit 1004, and a similar detailed description is therefore omitted.

[0622] Other embodiments of the memory circuit 1300 are within the scope of the present disclosure.

[0623] Fig. 14 is a schematic diagram of a memory circuit 1400, according to some embodiments.

[0624] The memory circuit 1400 is a modification of the memory circuit 1000 of Fig. 10, the memory circuit 1100 of Fig. 11, the memory circuit 1200 of Fig. 12 and the memory circuit 1300 of Fig. 13, and a similar detailed description is therefore omitted. In comparison with the memory circuit 1300 of Fig. 13 is the memory circuit 1302 of Fig. 13 by a memory circuit 1402 of Fig. 14, and the circuit 1304 of Fig. 13 is through a memory circuit 1404 of Fig. 14, and a similar detailed description is therefore omitted.

[0625] The memory circuit 1400 includes the memory circuit 1402 and the memory circuit 1404.

[0626] The memory circuit 1400 is illustrated as including a memory circuit 1402 and a memory circuit 1404. In some embodiments, the memory circuit 1400 includes at least two or more of the memory circuit 1402. In some embodiments, the memory circuit 1400 includes at least two or more of the memory circuit 1404. Other locations in the memory circuit 1400 for at least one of the memory circuit 1402 or the memory circuit 1404 are within the scope of the present disclosure.

[0627] In some embodiments, the memory circuit 1402 is a memory circuit different from the memory circuit 1002 of Fig. 10, the memory circuit 1102 of Fig. 11 or the memory circuit 1302 of Fig. 13, and the memory circuit 1404 is a memory circuit 1104 of Fig. 10 or the memory circuit 1304 of Fig. 13, and a similar detailed description is therefore omitted.

[0628] In some embodiments, at least one of the heights H5a, H5b, H5c, H6a, or H6b is different from at least one other of the heights H5a, H5b, H5c, H6a, or H6b. In some embodiments, at least one of the heights H5a, H5b, H5c, H6a, or H6b is equal to at least one other of the heights H5a, H5b, H5c, H6a, or H6b.

[0629] In some embodiments, at least one of the widths W5a, W5b, W5c, W6a, or W6b is different from at least one other of the widths W5a, W5b, W5c, W6a, or W6b. In some embodiments, at least one of the widths W5a, W5b, W5c, W6a, or W6b is equal to at least one other of the widths W5a, W5b, W5c, W6a, or W6b.

[0630] In some embodiments, at least one of the lengths L1a, L2a, L3a, L4a, or L5a is different from at least one other of the lengths L1a, L2a, L3a, L4a, or L5a. In some embodiments, at least one of the lengths L1a, L2a, L3a, L4a, or L5a is equal to at least one other of the lengths L1a, L2a, L3a, L4a, or L5a.

[0631] In some embodiments, at least one of the lengths L1b, L2b, L3b, L4b, or L5b is different from at least one other of the lengths L1b, L2b, L3b, L4b, or L5b. In some embodiments, at least one of the lengths L1b, L2b, L3b, L4b, or L5b is equal to at least one other of the lengths L1b, L2b, L3b, L4b, or L5b.

[0632] The memory circuit 1400 achieves one or more of the advantages discussed herein.

[0633] Other embodiments of the memory circuit 1400 are within the scope of the present disclosure.

[0634] Fig. 15 is a functional flow diagram of a method 1500 for manufacturing an IC device, according to some embodiments. It should be understood that additional operations may occur before, during, and / or after the Fig. 15 may be performed, and that some other processes may only be briefly described here.

[0635] In some embodiments, a different order of operations of method 1500-1700 is within the scope of the present disclosure. Method 1500-1700 includes example operations, but the operations are not necessarily performed in the order presented. Operations may be added, substituted, changed in order, and / or eliminated as appropriate, consistent with the spirit and scope of disclosed embodiments. In some embodiments, one or more of the operations of at least method 1500, 1600, or 1700 are not performed.

[0636] In some embodiments, method 1500 is an embodiment of operation 804 of method 1600. In some embodiments, methods 1500-1700 may be used to fabricate at least memory circuit 100, 200A-200B, 400A-400C, 500A-500B, 600, 700A-700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or memory cells 300A-300B.

[0637] In operation 1502 of method 1500, a first set of transistors is fabricated in a first memory cell array. In some embodiments, the first memory cell array of method 1500 comprises at least one of memory cell array 1102, 1102, 1302, or 1402. In some embodiments, a first memory cell array has a first width in the first direction X and a first height in the second direction.

[0638] In some embodiments, the first width of the method 1500 is at least one of the widths W5a, W5c, or W6a. In some embodiments, the first height of the method 1500 is at least one of the heights H5a, H5c, or H6a.

[0639] In some embodiments, each memory cell in the first memory cell array includes a first set of transistors in the front side 490a of the substrate 490. In some embodiments, the first set of transistors of method 1500 includes the transistors of at least one of the memory cell array 1102, 1102, 1302, or 1402.

[0640] In some embodiments, the first set of transistors of method 1500 includes one or more transistors in at least the set of active regions 502, 602, 802, or 902.

[0641] In some embodiments, the first set of transistors comprises a first number of transistors. In some embodiments, the first number of transistors of method 1500 is 6 or 8.

[0642] In operation 1504 of method 1500, a second set of transistors is fabricated in a second memory cell array. In some embodiments, the second memory cell array of method 1500 comprises at least one of memory cell array 1004, 1304, or 1404. In some embodiments, the second memory cell array has a second width in the second direction X and a second height in the second direction.

[0643] In some embodiments, the second width of the method 1500 is at least one of the widths W5b or W6b. In some embodiments, the second height of the method 1500 is at least one of the heights H5b or H6b.

[0644] In some embodiments, each memory cell in the second memory cell array includes a second set of transistors in the front side 490a of the substrate 490. In some embodiments, the second set of transistors of method 1500 includes the transistors of at least one of the memory cell array 1102, 1102, 1302, or 1402.

[0645] In some embodiments, the second set of transistors of method 1500 includes one or more transistors in at least the set of active regions 502, 602, 802, or 902.

[0646] In some embodiments, the second set of transistors comprises a second number of transistors. In some embodiments, the second number of transistors of method 1500 is 6 or 8.

[0647] In some embodiments, the second set of transistors includes a second number of transistors. In some embodiments, the second number of transistors of method 1500 is equal to the first number of transistors of method 1500. In some embodiments, the second number of transistors of method 1500 is different from the first number of transistors of method 1500.

[0648] In operation 1506 of method 1500, a third set of transistors is fabricated in a third memory cell array. In some embodiments, the third memory cell array of method 1500 includes at least one of memory cell array 1002, 1004, 1102, 1302, 1304, 1402, or 1404.

[0649] In some embodiments, the third memory cell array has a third width in the third direction X and a third height in the third direction.

[0650] In some embodiments, the third width of the method 1500 is at least one of the widths W5a, W5b, W5c, W6a, or W6b. In some embodiments, the third height of the method 1500 is at least one of the heights H5a, H5b, H5c, H6a, or H6b.

[0651] In some embodiments, at least one of the first width, the second width, or the third width is different from at least one other of the first width, the second width, or the third width.

[0652] In some embodiments, at least one of the first width, the second width, or the third width is equal to at least one other of the first width, the second width, or the third width.

[0653] In some embodiments, at least one of the first height, the second height, or the third height is different from at least one other of the first height, the second height, or the third height.

[0654] In some embodiments, at least one of the first height, the second height, or the third height is equal to at least one other of the first height, the second height, or the third height.

[0655] In some embodiments, each memory cell in the third memory cell array includes a third set of transistors in the front side 490a of the substrate 490. In some embodiments, the third set of transistors of method 1500 includes the transistors of at least one of the memory cell arrays 1102, 1102, 1302, or 1402.

[0656] In some embodiments, the third set of transistors of method 1500 includes one or more transistors in at least the set of active regions 502, 602, 802, or 902.

[0657] In some embodiments, the third set of transistors comprises a third number of transistors. In some embodiments, the third number of transistors of method 1500 is 6 or 8.

[0658] In some embodiments, the third number of transistors of the method 1500 is equal to at least one of the first number of transistors of the method 1500 or the second number of transistors of the method 1500. In some embodiments, the third number of transistors of the method 1500 is different from at least one of the first number of transistors of the method 1500 or the second number of transistors of the method 1500.

[0659] In some embodiments, one or more of operations 1502, 1504, or 1506 are performed concurrently. In some embodiments, one or more portions of operations 1502, 1504, or 1506 are performed concurrently.

[0660] In some embodiments, at least one of operations 1502, 1504, or 1506 includes forming source and drain regions of the set of transistors in a first well. In some embodiments, the first well includes at least one of wells 501a, 501b, 501c, or 501d. In some embodiments, the first well includes p-type dopants. In some embodiments, the p-type dopants include boron, aluminum, or other suitable p-type dopants. In some embodiments, the first well includes an epi layer grown over a substrate. In some embodiments, the epi layer is doped by adding dopants during the epitaxial process. In some embodiments, the epi layer is doped by ion implantation after the epi layer is formed. In some embodiments, the first well is formed by doping the substrate.In some embodiments, the doping is performed by ion implantation. In some embodiments, the first well has a dopant concentration in a range of 1 × 10 12 Atoms / cm3 to 1 × 10 14 atoms / cm3.

[0661] In some embodiments, the first well comprises n-type dopants. In some embodiments, the n-type dopants comprise phosphorus, arsenic, or other suitable n-type dopants. In some embodiments, the n-type dopant concentration is in a range from approximately 1 × 1012 atoms / cm3 to approximately 1 × 1014 atoms / cm3.

[0662] In some embodiments, forming the source / drain elements comprises removing a portion of the substrate to form recesses at an edge of spacers, and then performing a filling process by filling the recesses in the substrate. In some embodiments, the recesses are etched after removing a pad oxide layer or a sacrificial oxide layer, for example, with a wet etch or a dry etch. In some embodiments, the etching process is performed to remove a top surface portion of the active region adjacent to an isolation region, such as an STI region. In some embodiments, the filling process is performed by an epitaxy or epitaxial process (Epi process).In some embodiments, the recesses are filled using a growth process concurrent with an etching process, wherein a growth rate of the growth process is greater than an etching rate of the etching process. In some embodiments, the recesses are filled using a combination of a growth process and an etching process. For example, a layer of material is grown in the recess, and then the grown material is subjected to an etching process to remove a portion of the material. Then, a subsequent growth process is performed on the etched material until a desired thickness of material in the recess is achieved. In some embodiments, the growth process continues until a top surface of the material is above the top surface of the substrate.In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first well is removed by an isotropic or an anisotropic etch process. The etch process selectively etches the first well without etching a gate structure and spacers. In some embodiments, the etch process is performed using a reactive ion etch (RIE), a wet etch, or another suitable technique. In some embodiments, a semiconductor material is deposited in the recesses to form the source / drain elements. In some embodiments, an epi-deposition process is performed to deposit the semiconductor material in the recesses.In some embodiments, the epi process comprises a selective epitaxial growth (SEG) process, a CVD process, molecular beam epitaxy (MBE), or other suitable processes and / or a combination thereof. The epi process uses gaseous and / or liquid precursors that interact with a composition of the substrate. In some embodiments, the source / drain elements comprise epitaxially grown silicon (epi-silicon), silicon carbide, or silicon germanium. The source / drain elements of the IC device associated with the gate structure are, in some cases, doped or undoped in-situ during the epi process. If source / drain elements are not doped during the epi process, source / drain elements are, in some cases, doped during a subsequent process.The subsequent doping process is achieved by ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes, and / or a combination thereof. In some embodiments, source / drain elements are further subjected to an annealing process after the formation of source / drain elements and / or after the subsequent doping process.

[0663] In some embodiments, at least one of operations 1502, 1504, or 1506 further comprises an operation 1502a (not shown). In some embodiments, operation 1502a comprises forming contacts of the first set of transistors, the second set of transistors, or the third set of transistors. In some embodiments, the contacts include at least one or more of contacts 506a, 506b, 506c, or 506d.

[0664] In some embodiments, at least one of operations 1502, 1504, or 1506 further comprises forming a gate region of the first set of transistors, the second set of transistors, the third set of transistors, or the fourth set of transistors. In some embodiments, the gate regions of method 1500 include the set of gates 504, 604, 804, or 904.

[0665] In some embodiments, the gate region is located between the drain region and the source region. In some embodiments, the gate region is located above the first well and the substrate. In some embodiments, forming the gate regions of at least one of operations 1502, 1504, or 1506 comprises performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, a deposition process comprises chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or another process suitable for depositing one or more material layers. In some embodiments, forming the gate regions comprises performing one or more deposition processes to form one or more conductive material layers.In some embodiments, forming the gate regions comprises forming gate electrodes or dummy gate electrodes. In some embodiments, forming the gate regions comprises depositing or growing at least one dielectric layer, e.g., a gate dielectric. In some embodiments, gate regions are formed using doped or undoped polycrystalline silicon (or polysilicon). In some embodiments, the gate regions comprise a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0666] In operation 1508 of method 1500, a first set of vias is formed on the front side 490a of the substrate 490. In some embodiments, the first set of vias of method 1500 includes at least one or more portions of at least the set of vias 514. In some embodiments, the first set of vias includes at least one or more vias in the VD plane.

[0667] In some embodiments, operations 1508 and 1510 are performed in a same operation.

[0668] In some embodiments, the first set of vias is electrically coupled to at least one of the first set of transistors or the second set of transistors.

[0669] In some embodiments, the first set of vias is electrically coupled to at least one of the first set of transistors, the second set of transistors, or the third set of transistors.

[0670] In some embodiments, operation 1508 includes forming a first set of self-aligned contacts (SACs) in the insulation layer over the front side 490a of the substrate or wafer.

[0671] In operation 1510 of method 1500, a second set of vias is formed on the front side 490a of the substrate 490. In some embodiments, the second set of vias of method 1500 includes at least one or more portions of at least the set of vias 512. In some embodiments, the second set of vias includes at least one or more vias in the VG plane.

[0672] In some embodiments, the second set of vias is electrically coupled to at least one of the first set of transistors or the second set of transistors.

[0673] In some embodiments, the second set of vias is electrically coupled to at least one of the first set of transistors, the second set of transistors, or the third set of transistors.

[0674] In some embodiments, operation 1510 includes forming a second set of SACs in the insulation layer over the front side 490a of the substrate or wafer.

[0675] In operation 1512 of method 1500, a first conductive material is deposited on the front side 403a of the substrate on a first metal level, thereby forming a first set of conductors.

[0676] In some embodiments, the first set of conductors of method 1500 includes at least one conductor from the set of conductors 520.

[0677] In some embodiments, the first metal level of the method 1500 includes at least one Mo-level conductor. In some embodiments, the first metal level of the method 1500 includes at least one M1-level or M2-level conductor.

[0678] In some embodiments, the first set of conductors overlaps the first memory cell array and extends in the first direction X.

[0679] In some embodiments, the first set of conductors is electrically coupled to the first set of transistors through the first set of vias or the second set of vias.

[0680] In some embodiments, the first set of conductors is electrically coupled to the second set of transistors through the first set of vias or the second set of vias.

[0681] In some embodiments, the first set of conductors is electrically coupled to the third set of transistors through the first set of vias or the second set of vias.

[0682] In operation 1514 of method 1500, a third set of vias is formed on the front side 490a of the substrate 490. In some embodiments, the third set of vias of method 1500 includes at least one or more portions of at least one of the set of vias 402, 412, 422, 702, 722, or 522. In some embodiments, the third set of vias includes at least one or more vias in the Vo plane.

[0683] In some embodiments, the third set of vias is electrically coupled to at least one of the first set of transistors, the second set of transistors, or the third set of transistors through at least the first set of conductors.

[0684] In some embodiments, operation 1514 includes forming a third set of SACs in the insulation layer over the front side 490a of the substrate or wafer.

[0685] In operation 1516 of method 1500, a second conductive material is deposited on the front side 403a of the substrate at a second level, thereby forming at least one of a first set of wordlines, a second set of wordlines, a third set of wordlines, or a second set of conductors.

[0686] In some embodiments, the first set of word lines of method 1500 comprises at least one of the set of word lines WL1, WL3, WL4, WL, WWL, or RWL.

[0687] In some embodiments, the second set of word lines of the method 1500 comprises at least one of the set of word lines WL2, WL5, WL, WWL or RWL

[0688] In some embodiments, the second set of wordlines of method 1500 comprises at least one of the set of wordlines WL1, WL2, WL3, WL4, WL5, WL, WWL, or RWL.

[0689] In some embodiments, the second set of conductors of the method 1500 comprises the set of conductors 530.

[0690] In some embodiments, the second metal level of the method 1500 comprises the M1 level. In some embodiments, the second metal level of the method 1500 comprises at least one of the M0 level or the M2 level.

[0691] In some embodiments, the first set of wordlines is electrically coupled to the first set of transistors through the second set of vias. In some embodiments, the first set of wordlines overlaps the first memory cell array and extends in the second direction Y.

[0692] In some embodiments, the second set of wordlines is electrically coupled to the second set of transistors through the second set of vias. In some embodiments, the second set of wordlines overlaps the second memory cell array and extends in the second direction Y.

[0693] In some embodiments, the third set of wordlines is electrically coupled to the third set of transistors through the second set of vias. In some embodiments, the third set of wordlines overlaps the third memory cell array and extends in the second direction Y.

[0694] In operation 1518 of method 1500, a fourth set of vias is formed on the front side 490a of the substrate 490. In some embodiments, the fourth set of vias of method 1500 includes at least one or more portions of at least one of the set of vias 404, 414, 424, 704, or 724. In some embodiments, the fourth set of vias includes at least one or more vias in the V1 plane.

[0695] In some embodiments, the fourth set of vias is electrically coupled to at least one of the first set of transistors, the second set of transistors, or the third set of transistors through at least the first set of conductors or the second set of conductors.

[0696] In some embodiments, operation 1518 includes forming a fourth set of SACs in the insulation layer over the front side 490a of the substrate or wafer.

[0697] In operation 1520 of method 1500, a third conductive material is deposited on the front side 403a of the substrate on a third metal level, thereby forming at least one of a first set of bitlines, a second set of bitlines, or a third set of bitlines.

[0698] In some embodiments, the first set of bitlines of method 1500 includes at least one of the set of bitlines BL1, BLB1, BL3, BLB3, BL4, BLB4, BL, BLB, or RBL.

[0699] In some embodiments, the second set of bitlines of method 1500 comprises at least one of the set of bitlines BL2, BLB2, BL5, BLB5, BL, BLB, or RBL.

[0700] In some embodiments, the third set of bitlines of method 1500 comprises at least one of the set of bitlines BL1, BLB1, BL2, BLB2, BL3, BLB3, BL4, BLB4, BL5, BLB5, BL, BLB, or RBL.

[0701] In some embodiments, the third metal level of the method 1500 is different from the first metal level and the second metal level. In some embodiments, the third metal level of the method 1500 comprises the M2 level. In some embodiments, the third metal level of the method 1500 comprises at least one of the Mo level, the M1 level, the M3 level, or the M4 level.

[0702] In some embodiments, the first set of bitlines is electrically coupled to the first set of transistors through the first set of vias. In some embodiments, the first set of bitlines overlaps the first memory cell array and extends in the first direction X.

[0703] In some embodiments, the second set of bitlines is electrically coupled to the second set of transistors through the first set of vias. In some embodiments, the second set of bitlines overlaps the second memory cell array and extends in the first direction X.

[0704] In some embodiments, the third set of bitlines is electrically coupled to the third set of transistors through the first set of vias. In some embodiments, the third set of bitlines overlaps the third memory cell array and extends in the first direction X.

[0705] In some embodiments, one or more of operations 1502, 1504, 1506, 1508, 1510, 1512, 1514, 1516, 1518, or 1520 of method 1500 comprise using a combination of photolithographic and material removal processes to form openings in an insulating layer (not shown) over the substrate. In some embodiments, the photolithographic process comprises patterning a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the photolithographic process comprises forming a hard mask, an anti-reflection structure, or other suitable photolithographic structure. In some embodiments, the material removal process comprises a wet etching process, a dry etching process, an RIE process, laser drilling, or other suitable etching process. The openings are then filled with conductive material, e.g.Copper, aluminum, titanium, nickel, tungsten, or another suitable conductive material. In some embodiments, the openings are filled using CVD, PVD, sputtering, ALD, or another suitable formation process.

[0706] In some embodiments, at least one or more acts of method 1500 are performed by a system 1900 of Fig. 19. In some embodiments, at least one method, such as the method 1500 discussed above, is performed in whole or in part by at least one manufacturing system including the system 1900. One or more of the operations of the method 1500 are performed by an IC microchip fabrication plant 1940 ( Fig. 19) to fabricate an IC device 1960. In some embodiments, one or more of the operations of method 1500 are performed by fabrication tools 1952 to fabricate a wafer 1942.

[0707] In some embodiments, the conductive material includes copper, aluminum, titanium, nickel, tungsten, or another suitable conductive material. In some embodiments, the openings and trench are filled using CVD, PVD, sputtering, ALD, or another suitable formation process. After the conductive material is deposited in one or more of operations 1508, 1510, 1512, 1514, 1516, 1518, or 1520, in some embodiments, the conductive material is planarized to provide a flat surface for subsequent steps.

[0708] In some embodiments, one or more of the acts of method 1500, 1600, or 1700 are not performed.

[0709] One or more of the operations of methods 1600-1700 are performed by a processing device configured to execute instructions for fabricating an integrated circuit, such as at least one of memory circuits 100, 200A-200B, 400A-400C, 500A-500B, 600, 700A-700B, 800, 900, 1000, 1100, 1200, 1300, or 1400, or memory cells 300A-300B. In some embodiments, one or more operations of methods 1600-1700 are performed using a same processing device as that used in one or more other operations of methods 1600-1700. In some embodiments, a different processing device is used to perform one or more operations of methods 1600-1700 than the processing device used to perform another one or more other operations of methods 1600-1700.In some embodiments, a different order of operations of method 1500, 1600, or 1700 is within the scope of the present disclosure. At least one of method 1500, 1600, or 1700 includes example operations, but the operations are not necessarily performed in the order presented. Operations in method 1500, 1600, or 1700 may be added, replaced, changed in order, and / or eliminated as appropriate, consistent with the spirit and scope of disclosed embodiments.

[0710] Fig. 16 is a flow diagram of a method 1600 for forming or manufacturing an integrated circuit according to some embodiments. It should be understood that additional operations may occur before, during, and / or after the Fig. 16, and that some other operations may be described only briefly here. In some embodiments, the method 1600 may be used to fabricate integrated circuits, such as at least the memory circuit 100, 200A-200B, 400A-400C, 500A-500B, 600, 700A-700B, 800, 900, 1000, 1100, 1200, 1300, or 1400, or the memory cells 300A-300B.

[0711] In operation 1602 of method 1600, a layout design of an integrated circuit is generated. The operation 1602 is performed by a processing device (e.g., a processor 1802 ( Fig. 18)) configured to execute instructions for generating a layout design. In some embodiments, the layout design of method 1600 comprises one or more layout structures that are similar to one or more elements of at least the memory circuit 100, 200A-200B, 400A-400C, 500A-500B, 600, 700A-700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or the memory cells 300A-300B. In some embodiments, the layout design of the present application is in a graphical database system (GDSII) file format. In some embodiments, operation 1602 corresponds to method 1700 of Fig. 17.

[0712] In operation 1604 of method 1600, the integrated circuit is fabricated based on the layout design. In some embodiments, operation 1604 of method 1600 includes fabricating at least one mask based on the layout design and fabricating the integrated circuit based on the at least one mask. In some embodiments, operation 1604 corresponds to method 1500 of Fig. 15.

[0713] Fig. 17 is a flow diagram of a method 1700 for generating a layout design of an integrated circuit, according to some embodiments. It should be understood that additional operations may occur before, during, and / or after the Fig. 17, and that some other processes may only be briefly described here. In some embodiments, method 1700 is an embodiment of operation 1602 of method 1600. In some embodiments, method 1700 may be used to generate one or more layout structures similar to one or more elements of at least memory circuit 100, 200A-200B, 400A-400C, 500A-500B, 600, 700A-700B, 800, 900, 1000, 1100, 1200, 1300, or 1400, or memory cells 300A-300B.

[0714] In some embodiments, the method 1700 may be used to generate one or more layout structures having structural relationships, alignment, lengths and widths, as well as configurations and layers that are at least similar to the IC memory circuit 100, 100, 200A-200B, 400A-400C, 500A-500B, 600, 700A-700B, 800, 900, 1000, 1100, 1200, 1300 or 1400 or memory cells 300A-300B, and a similar detailed description is provided for brevity in Fig. 17 not described.

[0715] At operation 1702 of method 1700, a set of active region structures is generated or placed on the layout design. In some embodiments, the set of active region structures of method 1700 includes one or more regions similar to the set of active regions 602, 602, 802, or 902. In some embodiments, the set of active region structures of method 1700 includes one or more structures similar to elements in the OD layer.

[0716] In operation 1704 of method 1700, a set of gate structures is generated or placed on the layout design. In some embodiments, the set of gate structures of method 1700 includes one or more regions similar to the set of gates 504, 602, 804, or 902. In some embodiments, the set of gate structures of method 1700 includes at least portions of one or more structures from the set of isolation structures 394. In some embodiments, the set of gate structures of method 1700 includes one or more structures similar to elements in the POLY layer.

[0717] At operation 1706 of method 1700, a set of contact structures is generated or placed on the layout design. In some embodiments, the set of contact structures of method 1700 includes one or more regions similar to the set of contacts 506. In some embodiments, the set of contact structures of method 1700 includes one or more structures similar to elements in the MD layer.

[0718] At operation 1708 of method 1700, a first set of via structures is generated or placed on the layout design. In some embodiments, the first set of via structures of method 1700 includes one or more via structures that are at least similar to the set of vias 512 or 514. In some embodiments, the first set of via structures of method 1700 includes one or more structures or vias that are similar to elements in the VD layer or the VG layer.

[0719] At operation 1710 of method 1700, a first set of conductive element structures is generated or placed on the layout design. In some embodiments, the first set of conductive element structures of method 1700 includes one or more regions similar to the set of conductors 520. In some embodiments, the first set of conductive element structures of method 1700 includes one or more structures similar to elements in the Mo layer.

[0720] At operation 1712 of method 1700, a second set of via structures is generated or placed on the layout design. In some embodiments, the second set of via structures of method 1700 includes one or more via structures similar to at least one of the set of vias 402, 412, 422, 702, 722, or 522. In some embodiments, the second set of via structures of method 1700 includes one or more structures or vias similar to elements in the Vo layer.

[0721] In operation 1714 of method 1700, a first set of wordline structures is generated or placed on the layout design. In some embodiments, the first set of wordline structures of method 1700 includes one or more structures similar to the set of wordlines WL, WL1, WL2, WL3, WL4, WL5, WWL, or RWL. In some embodiments, the first set of wordline structures of method 1700 includes one or more structures similar to elements in the POLY, Mo layer, M1 layer, or M2 layer. In some embodiments, operation 1714 also includes generating or placing a second set of conductive element structures on the layout design. In some embodiments, the second set of conductive element structures of method 1700 includes one or more regions similar to the set of conductors 530.In some embodiments, the second set of conductive element structures of method 1700 includes one or more structures similar to elements in the M1 layer.

[0722] At operation 1716 of method 1700, a third set of via structures is generated or placed on the layout design. In some embodiments, the third set of via structures of method 1700 includes one or more via structures similar to at least one of the set of vias 404, 414, 424, 704, or 724. In some embodiments, the third set of via structures of method 1700 includes one or more structures or vias similar to elements in the V1 layer.

[0723] In operation 1718 of method 1700, a first set of bitline structures or a first set of bitline bar structures is generated or placed on the layout design. In some embodiments, the first set of bitline structures or the first set of bitline bar structures of method 1700 includes one or more structures similar to the set of bitlines or the set of bitline bars BL, BLB, BL1, BLB1, BL2, BLB2, BL3, BLB3, BL4, BLB4, BL5, or BLB5. In some embodiments, the second set of wordline structures of method 1700 includes one or more structures similar to elements in the Mo layer, M1 layer, or M2 layer.

[0724] At operation 1720 of method 1700, a second set of bitline structures or a second set of bitline bar structures is generated or placed on the layout design. In some embodiments, the second set of bitline structures or the second set of bitline bar structures of method 1700 includes one or more structures similar to the set of read bitlines RBL. In some embodiments, the second set of wordline structures of method 1700 includes one or more structures similar to elements in the Mo layer, M1 layer, or M2 layer.

[0725] Fig. 18 is a schematic view of a system 1800 for designing an IC layout design and manufacturing an IC circuit according to some embodiments.

[0726] In some embodiments, system 1800 generates or places one or more IC layout designs described herein. System 1800 includes a hardware processor 1802 and a non-transitory computer-readable storage medium 1804 (e.g., memory 1804) encoded with, i.e., storing, computer program code 1806, i.e., a set of executable instructions 1806. Computer-readable storage medium 1804 is configured to connect to manufacturing machines for fabricating the integrated circuit. Processor 1802 is electrically coupled to computer-readable storage medium 1804 via a bus 1808. Processor 1802 is also electrically coupled to an I / O interface 1810 through bus 1808. A network interface 1812 is also electrically connected to processor 1802 via bus 1808.The network interface 1812 is connected to a network 1814 such that the processor 1802 and the computer-readable storage medium 1804 are capable of connecting to external elements via the network 1814. The processor 1802 is configured to execute the computer program code 1806 (also referred to as "instructions" or "non-transitory instructions") encoded in the computer-readable storage medium 1804 to cause the system 1800 to be usable for performing some or all of the operations described in methods 1600-1700.

[0727] In some embodiments, processor 1802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or any suitable processing unit.

[0728] In some embodiments, computer-readable storage medium 1804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or component). For example, computer-readable storage medium 1804 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, random access memory (RAM), read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In some embodiments that utilize optical disks, computer-readable storage medium 1804 includes a CD-ROM (Compact Disc Read-Only Memory), a CD-R / W (Compact Disc Read / Write), and / or a DVD (Digital Video Disc).

[0729] In some embodiments, computer-readable storage medium 1804 stores computer program code 1806 configured to cause system 1800 to perform method 1600-1700. In some embodiments, computer-readable storage medium 1804 also stores information needed to perform method 1600-1700, as well as information generated during the performance of method 1600-1700, such as a layout design 1816, a user interface 1818, and a manufacturing unit 1820, and / or a set of executable instructions to perform the operation of method 1600-1700. In some embodiments, the layout design 1816 includes one or more layout structures that are similar to one or more elements of at least the memory circuit 100, 200A-200B, 400A-400C, 500A-500B, 600, 700A-700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or the memory cells 300A-300B.

[0730] In some embodiments, computer-readable storage medium 1804 stores instructions (e.g., computer program code 1806) for interfacing with manufacturing machines. The instructions (e.g., computer program code 1806) allow processor 1802 to generate manufacturing instructions readable by the manufacturing machines to efficiently implement method 1600-1700 during a manufacturing process.

[0731] System 1800 includes an I / O interface 1810. I / O interface 1810 is coupled to external circuitry. In some embodiments, I / O interface 1810 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys to communicate information and commands to processor 1802.

[0732] System 1800 also includes a network interface 1812 coupled to processor 1802. Network interface 1812 allows system 1800 to communicate with network 1814 to which one or more other computer systems are connected. Network interface 1812 includes wireless network interfaces, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface, such as ETHERNET, USB, or IEEE-2094. In some embodiments, method 1600-1700 is implemented in two or more systems 1800, and information, such as layout design and user interface, is exchanged between different systems 1800 through network 1814.

[0733] System 1800 is configured to receive information related to a layout design via I / O interface 1810 or network interface 1812. The information is transmitted to processor 1802 through bus 1808 to determine a layout design for fabricating at least memory circuit 100, 200A-200B, 400A-400C, 500A-500B, 600, 700A-700B, 800, 900, 1000, 1100, 1200, 1300, or 1400, or memory cells 300A-300B. The layout design is then stored in computer-readable storage medium 1804 as layout design 1816. The system 1800 is configured to receive information related to a user interface via the I / O interface 1810 or the network interface 1812. The information is then stored in the computer-readable medium 1804 as a user interface 1818.The system 1800 is configured to receive information relating to a manufacturing unit 1820 via the I / O interface 1810 or the network interface 1812. The information is stored in the computer-readable storage medium 1804 as a manufacturing unit 1820. In some embodiments, the manufacturing unit 1820 includes manufacturing information used by the system 1800. In some embodiments, the manufacturing unit 1820 corresponds to a mask factory 1934 of FIG. Fig. 19.

[0734] In some embodiments, method 1600-1700 is implemented as a stand-alone software application for execution by a processor. In some embodiments, method 1600-1700 is implemented as a software application that is part of an additional software application. In some embodiments, method 1600-1700 is implemented as a plug-in for a software application. In some embodiments, method 1600-1700 is implemented as a software application that is part of an EDA tool. In some embodiments, method 1600-1700 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of the integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer-readable medium.In some embodiments, the layout is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable tool for generating layouts. In some embodiments, the layout is generated based on a netlist generated based on the schematic design. In some embodiments, the method 1600-1700 is implemented by a manufacturing apparatus to manufacture an integrated circuit using a set of masks fabricated based on one or more layout designs generated by the system 1800. In some embodiments, the system 1800 is a manufacturing apparatus configured to manufacture an integrated circuit using a set of masks fabricated based on one or more layout designs of the present disclosure.In some embodiments, the system generates 1800 of . Fig. 18 integrated circuit layout designs that are smaller than other approaches. In some embodiments, the system generates 1800 of Fig. 18 layout designs of an integrated circuit structure that occupies less area and provides better routing resources than other approaches.

[0735] Fig. 19 is a block diagram of an IC manufacturing system 1900 and an associated IC manufacturing flow, according to at least one embodiment of the present disclosure. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is manufactured using the manufacturing system 1900.

[0736] In Fig. 19, the IC manufacturing system 1900 (hereinafter "system 1900") includes entities such as a design house 1920, a mask house 1930, and an IC manufacturer / fabrication plant (a "microchip fab") 1940 that cooperate with one another in the design, development, and manufacturing cycles and / or services associated with manufacturing an IC device 1960. The entities 1900 are interconnected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network represents a variety of different networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communications channels. Each entity interacts with one or more of the other entities and provides and / or receives services to one or more of the other entities.In some embodiments, one or more of the design house 1920, the mask house 1930, and the IC microchip factory 1940 are owned by a single large company. In some embodiments, one or more of the design house 1920, the mask house 1930, and the IC microchip factory 1940 coexist in a common facility and use common resources.

[0737] The design house (or design team) 1920 generates an IC design layout 1922. The IC design layout 1922 includes various geometric structures designed for an IC device 1960. The geometric structures correspond to structures of metal, oxide, or semiconductor layers that make up the various components of the IC device 1960 to be manufactured. The various layers are combined to form various IC elements. For example, a portion of the IC design layout 1922 includes various IC elements, such as an active region, a gate electrode, a source electrode, and a drain electrode, metal lines or vias of an interlayer interconnect, and openings for bond pads to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers disposed on the semiconductor substrate.The design house 1920 implements a suitable design process to create the IC design layout 1922. The design process includes one or more of a logic design, a physical design, or a place and route design. The IC design layout 1922 is represented in one or more data files containing information about the geometric structures. The IC design layout 1922 can be represented, for example, in a GDSII file format or a DFII file format.

[0738] The mask house 1930 includes a data preparation 1932 and a mask manufacturing 1934. The mask house 1930 uses the IC design layout 1922 to produce one or more masks 1945 to be used to manufacture the various layers of the IC device 1960 according to the IC design layout 1922. The mask house 1930 performs a mask data preparation 1932, in which the IC design layout 1922 is translated into an RDF (representative data file). The mask data preparation 1932 provides the RDF for the mask manufacturing 1934. The mask manufacturing 1934 has a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1945, or a semiconductor wafer 1942 (also referred to as a “wafer 1942”).The IC design layout 1922 is manipulated by the mask data conditioning 1932 (also referred to as “data conditioning 1932”) to conform to certain characteristics of the mask writer and / or requirements of the IC microchip factory 1940. In . Fig. 19, mask data preparation 1932 and mask manufacturing 1934 are shown as separate elements. In some embodiments, mask data preparation 1932 and mask manufacturing 1934 may be collectively referred to as mask data preparation.

[0739] In some embodiments, mask data preparation 1932 includes optical proximity correction (OPC) that uses lithographic enhancement techniques to compensate for image defects, such as those that may occur due to diffraction, interference, or other process effects, and the like. OPC adjusts the IC design layout 1922. In some embodiments, mask data preparation 1932 includes other resolution enhancement techniques (RET), such as off-axis illumination, resolution assist devices, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithographic technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0740] In some embodiments, mask data preparation 1932 includes a mask rule checker (MRC) that checks the IC design layout subjected to processes in OPC against a set of mask generation rules that include certain geometric and / or interconnect constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout to accommodate constraints during mask fabrication 1934, which may also undo some of the modifications performed by OPC to conform to mask generation rules.

[0741] In some embodiments, mask data preparation 1932 includes a lithographic process verification (LPC) that simulates processing that will be implemented by IC microchip fabrication 1940 to fabricate IC device 1960. LPC simulates this processing based on IC design layout 1922 to produce a simulated fabricated device, such as IC device 1960. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to fabricate the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of field (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, after a simulated fabricated device is generated by the LPC, if the simulated device does not have an approximately correct shape to conform to design rules, OPC and / or MRC are repeated to further refine the IC design layout 1922.

[0742] It should be understood that the above description of mask data preparation 1932 has been simplified for clarity. In some embodiments, data preparation 1932 includes additional functions, such as a logic operation (LOP), to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1922 during data preparation 1932 may be performed in a variety of different orders.

[0743] After mask data preparation 1932 and during mask fabrication 1934, a mask 1945 or a group of masks 1945 is fabricated based on the modified IC design layout 1922. In some embodiments, mask fabrication 1934 includes performing one or more lithographic exposures based on the IC design layout 1922. In some embodiments, an electron beam (e-beam) or a multiple e-beam mechanism is used to form a structure on a mask (photomask or reticle) 1945 based on the modified IC design layout 1922. The mask 1945 can be formed using various technologies. In some embodiments, the mask 1945 is formed using a binary technology. In some embodiments, a mask structure has opaque regions and transparent regions. A radiation beam, such asUltraviolet (UV) radiation used to expose the image-sensitive material layer (e.g., photoresist) deposited on a wafer is blocked by the opaque region and transmitted through the transparent regions. In one example, a binary version of the mask 1945 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) deposited in the opaque regions of the binary mask. In another example, the mask 1945 is formed using phase-shift technology. In the phase-shift mask (PSM) version of the mask 1945, various elements in the structure formed on the mask are arranged to have an appropriate phase difference to improve the resolution of the image quality. In various examples, the phase-shift mask may be an attenuated PSM or alternating PSM.The mask(s) generated by the mask fabrication 1934 are used in a variety of processes. For example, such a mask(s) are used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etch regions in the semiconductor wafer, and / or in other suitable processes.

[0744] The IC microchip fab 1940 is an IC manufacturing unit that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, the IC microchip fab 1940 is a semiconductor foundry. For example, one manufacturing facility may be provided for the front-end manufacturing of multiple IC products (front-end-of-line (FEOL)), while a second manufacturing facility may provide back-end manufacturing for interconnecting and packaging the IC products (back-end-of-line (BEOL)), and a third manufacturing facility may provide other services to the foundry unit.

[0745] The IC microchip fab 1940 includes manufacturing tools 1952 (hereinafter "manufacturing tools 1952") configured to perform various manufacturing operations on the semiconductor wafer 1942 such that the IC device 1960 is manufactured according to the mask(s), e.g., mask 1945. In various embodiments, the manufacturing tools 1952 include: a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or an LPCVD furnace, a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes, as discussed herein.

[0746] The IC microchip fabrication shop 1940 uses a mask(s) 1945 fabricated by the mask house 1930 to fabricate the IC device 1960. Therefore, the IC microchip fabrication shop 1940 at least indirectly uses the IC design layout 1922 to fabricate the IC device 1960. In some embodiments, a semiconductor wafer 1942 is fabricated by the IC microchip fabrication shop 1940 using the mask(s) 1945 to form the IC device 1960. In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design layout 1922. The semiconductor wafer 1942 comprises a silicon substrate or other suitable substrate having layers of material formed thereon.The semiconductor wafer 1942 further includes one or more of various doped regions, dielectric elements, multi-level interconnects, and the like (which are formed in subsequent manufacturing steps).

[0747] The system 1900 is shown as including a design house 1920, a mask house 1930, or an IC microchip factory 1940 as separate components or units. However, it is understood that one or more of the design house 1920, the mask house 1930, or the IC microchip factory 1940 are part of the same component or unit.

[0748] One aspect of this description relates to an integrated circuit chip. In some embodiments, the integrated circuit chip includes a first memory cell array having a first width in a first direction and a first height in a second direction different from the first direction. In some embodiments, the integrated circuit chip further includes a second memory cell array having a second width in the first direction and a second height in the second direction. In some embodiments, the integrated circuit chip further includes a first set of bitlines extending in the first direction, coupled to the first memory cell array, overlapping the first memory cell array, and located on at least a first metal layer over a front side of a substrate.In some embodiments, the integrated circuit chip further includes a second set of bit lines extending in the first direction, coupled to the second memory cell array, overlapping the second memory cell array, and located on at least the first metal layer. In some embodiments, at least the first width is different from the second width, or the first height is different from the second height.

[0749] Another aspect of this description relates to an integrated circuit chip. In some embodiments, the integrated circuit chip includes a first memory cell array having a first width in a first direction and a first height in a second direction different from the first direction, wherein each memory cell in the first memory cell array includes a first number of transistors. In some embodiments, the integrated circuit chip further includes a second memory cell array having a second width in the first direction and a second height in the second direction, wherein each memory cell in the second memory cell array includes a second number of transistors greater than the first number of transistors.In some embodiments, the integrated circuit chip further includes a first set of wordlines extending in the second direction, coupled to the first memory cell array, overlapping the first memory cell array, and located on at least a first metal layer over a front side of a substrate. In some embodiments, the integrated circuit chip further includes a second set of wordlines extending in the second direction, coupled to the second memory cell array, overlapping the second memory cell array, and located on at least the first metal layer. In some embodiments, at least the first width is different from the second width, or the first height is different from the second height.

[0750] Yet another aspect of this description relates to a method of manufacturing an integrated circuit chip. In some embodiments, the method comprises manufacturing a first set of memory cells in a first memory cell array. In some embodiments, the first memory cell array has a first width in a first direction and a first height in a second direction different from the first direction, wherein each memory cell in the first memory cell array comprises a first set of transistors in a front side of a substrate, the first set of transistors comprising a first number of transistors. In some embodiments, the method further comprises manufacturing a second set of memory cells in a second memory cell array.In some embodiments, the second memory cell array has a second width in the first direction and a second height in the second direction, wherein each memory cell in the second memory cell array has a second set of transistors in the front side of the substrate, the second set of transistors having a second number of transistors. In some embodiments, the method further comprises forming a first set of vias on the front side of the substrate. In some embodiments, the first set of vias is electrically coupled to at least one of the first set of transistors and the second set of transistors. In some embodiments, the method further comprises forming a second set of vias on the front side of the substrate.In some embodiments, the second set of vias is electrically coupled to at least one of the first set of transistors and the second set of transistors. In some embodiments, the method further comprises depositing a first conductive material on the front side of the substrate on a first metal layer, thereby forming a first set of wordlines and a second set of wordlines. In some embodiments, the first set of wordlines is electrically coupled to the first set of transistors through the second set of vias, overlaps the first memory cell array, and extends in the second direction. In some embodiments, the second set of wordlines is electrically coupled to the second set of transistors through the second set of vias, overlaps the second memory cell array, and extends in the second direction.In some embodiments, the method further comprises depositing a second conductive material on the front side of the substrate on a second metal layer, thereby forming a first set of bitlines and a second set of bitlines. In some embodiments, the first set of bitlines is electrically coupled to the first set of transistors by the first set of vias, overlaps the first memory cell array, and extends in the first direction. In some embodiments, the second set of bitlines is electrically coupled to the second set of transistors by the first set of vias, overlaps the second memory cell array, and extends in the first direction. In some embodiments, the second metal level is different from the first metal level.In some embodiments, at least the first width is different from the second width, or the first height is different from the second height.

[0751] The foregoing outlines features of several embodiments so that one skilled in the art can better understand aspects of the present disclosure. One skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same tasks and / or achieve the same advantages of the embodiments presented herein. One skilled in the art should also understand that such equivalent embodiments do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 617,295

[0001]

Claims

[1] Integrated circuit chip, comprising: a first memory cell array having a first width in a first direction and a first height in a second direction different from the first direction, a second memory cell array having a second width in the first direction and a second height in the second direction, a first set of bit lines extending in the first direction, coupled to the first memory cell array, overlapping the first memory cell array, and located on a first metal layer, the first metal layer being located over a front side of a substrate, and a second set of bit lines extending in the first direction, coupled to the second memory cell array, overlapping the second memory cell array, and located on the first metal layer, wherein at least the first width is different from the second width, or the first height is different from the second height. [2] The integrated circuit chip of claim 1, further comprising: a first set of word lines extending in the second direction, coupled to the first memory cell array, overlapping the first memory cell array, and located on a second metal layer different from the first metal layer, and a second set of word lines extending in the second direction, coupled to the second memory cell array, overlapping the second memory cell array, and located on the second metal layer. [3] Integrated circuit chip according to claim 2, wherein the first set of bit lines has a first length in the first direction, the first set of word lines has a second length in the second direction, the second set of bit lines has a third length in the first direction, and the second set of word lines has a fourth length in the second direction. [4] The integrated circuit chip of claim 3, wherein at least one of the following: the first length is smaller than the second length, or the third length is greater than the fourth length. [5] The integrated circuit chip of claim 3, wherein at least one of: the first length is smaller than the third length, or the second length is greater than the fourth length. [6] Integrated circuit chip according to claim 2, wherein the second memory cell array comprises a first set of rows of memory cells extending in the first direction and a first set of columns of memory cells extending in the second direction, and the second set of word lines has: a first word line of the second set of word lines overlaps each memory cell in a first column of the first set of columns of memory cells, and a second word line of the second set of word lines overlaps each memory cell in the first column of the first set of columns of memory cells, the second word line being adjacent to the first word line, and the first word line and the second word line are electrically coupled to interleaved memory cells in the first column of the first set of columns of memory cells. [7] Integrated circuit chip according to claim 6, wherein the first memory cell array has a second set of rows of memory cells extending in the first direction and a second set of columns of memory cells extending in the second direction, and each word line of the first set of word lines overlaps and is electrically coupled to each memory cell in a corresponding column of the second set of columns of memory cells. [8] Integrated circuit chip according to one of claims 1 to 7, wherein each memory cell in the first memory cell array is a memory cell with six transistors (6T memory cell), and each memory cell in the second memory cell array is a 6T memory cell. [9] Integrated circuit chip according to one of claims 1 to 7, wherein each memory cell in the first memory cell array is a memory cell with six transistors (6T memory cell), and each memory cell in the second memory cell array is an eight-transistor memory cell (8T memory cell). [10] The integrated circuit chip of claim 8, wherein the second set of bit lines is shared with adjacent rows of memory cells in the second memory cell array. [11] The integrated circuit chip of any one of claims 1 to 10, wherein the first memory cell array comprises a first number of memory cells, and the second memory cell array comprises the first number of memory cells. [12] Integrated circuit chip, comprising: a first memory cell array having a first width in a first direction and a first height in a second direction different from the first direction, each memory cell in the first memory cell array having a first number of transistors, a second memory cell array having a second width in the first direction and a second height in the second direction, each memory cell in the second memory cell array having a second number of transistors that is greater than the first number of transistors, a first set of word lines extending in the second direction, coupled to the first memory cell array, overlapping the first memory cell array, and located on a first metal layer, the first metal layer being located over a front side of a substrate, and a second set of word lines extending in the second direction, coupled to the second memory cell array, overlapping the second memory cell array, and located on the first metal layer, wherein at least the first width is different from the second width, or the first height is different from the second height. [13] The integrated circuit chip of claim 12, further comprising: a first set of bit lines extending in the first direction, coupled to the first memory cell array, overlapping the first memory cell array, and located on a second metal layer different from the first metal layer, a second set of bit lines extending in the first direction, coupled to the second memory cell array, overlapping the second memory cell array, and located on the second metal layer, and a third set of bit lines extending in the first direction, coupled to the second memory cell array, overlapping the second memory cell array, located on the second metal layer, and separated from the second set of bit lines in the second direction. [14] Integrated circuit chip according to claim 12 or 13, wherein the first number of transistors is six, and each memory cell in the first memory cell array is a memory cell with six transistors (6T memory cell), and the second number of transistors is eight, and each memory cell in the second memory cell array is an eight-transistor memory cell (8T memory cell). [15] Integrated circuit chip according to claim 13, wherein the second memory cell array comprises a first set of rows of memory cells extending in the first direction and a first set of columns of memory cells extending in the second direction, and the second set of word lines has: a first read word line overlaps each memory cell in a first column of the first set of columns of memory cells, and a second read word line overlaps each memory cell in the first column of the first set of columns of memory cells, and the second read word line is adjacent to the first read word line, and the first read word line and the second read word line are electrically coupled to interleaved memory cells in the first column of the first set of columns of memory cells. [16] Integrated circuit chip according to claim 15, wherein the first memory cell array has a second set of rows of memory cells extending in the first direction and a second set of columns of memory cells extending in the second direction, and the first set of word lines has: a third word line overlaps each memory cell in a first column of the first set of columns of memory cells and is electrically connected thereto, and a fourth word line overlaps and is electrically connected to each memory cell in a second column of the first set of columns of memory cells, the fourth word line being adjacent to the third word line, and the second column of the first set of columns of memory cells being adjacent to the first column of the first set of columns of memory cells. [17] The integrated circuit chip of claim 13, wherein the second memory cell array comprises: a first memory cell in at least a first row of the second memory cell array, a second memory cell in a second row of the second memory cell array, the second row being adjacent to the first row, a third memory cell in a third row of the second memory cell array, the third row being adjacent to the second row, and a fourth memory cell in at least a fourth row of the second memory cell array, the fourth row being adjacent to the third row, wherein the first memory cell, the second memory cell, the third memory cell and the fourth memory cell are located in a first column of the second memory cell array. [18] The integrated circuit chip of claim 17, wherein the first memory cell comprises: a first section in the first row of the second memory cell array, and a second section in the second row of the second memory cell array, and the fourth memory cell has: a first section in the fourth row of the second memory cell array, and a second section in the third row of the second memory cell array. [19] The integrated circuit chip of claim 18, wherein the third set of bit lines comprises: a first read bit line extending in the first direction, electrically coupled to the second memory cell and the second portion of the first memory cell, overlapping the second memory cell and the second portion of the first memory cell, and a second read bit line extending in the first direction, electrically coupled to the third memory cell and the second portion of the fourth memory cell, overlapping the third memory cell and the second portion of the fourth memory cell. [20] A method of manufacturing an integrated circuit chip, the method comprising: Producing a first set of memory cells in a first memory cell array, the first memory cell array having a first width in a first direction and a first height in a second direction different from the first direction, each memory cell in the first memory cell array having a first set of transistors in a front side of a substrate, the first set of transistors having a first number of transistors, Producing a second set of memory cells in a second memory cell array, the second memory cell array having a second width in the first direction and a second height in the second direction, each memory cell in the second memory cell array having a second set of transistors in the front side of the substrate, the second set of transistors having a second number of transistors, Forming (operations 1508 and 1510 - the description states that they could be formed in the same operation or in separate operations for the width) a first set of vias (VD) and a second set of vias (VG) on the front side of the substrate, wherein the first set of vias and the second set of vias are electrically coupled to at least the first set of transistors or the second set of transistors, Depositing (1516) a first conductive material on the front side of the substrate on a first metal level (M1), thereby forming a first set of word lines and a second set of word lines, wherein the first set of word lines is electrically coupled to the first set of transistors by the second set of vias, overlaps the first memory cell array, and extends in the second direction, wherein the second set of word lines is electrically coupled to the second set of transistors by the second set of vias, overlaps the second memory cell array, and extends in the second direction, Producing (1518) a third set of vias (V1) on the front side of the substrate, the third set of vias being electrically coupled to at least the first set of transistors or the second set of transistors, and Depositing (1520) a second conductive material on the front side of the substrate on a second metal level (M2), thereby forming a first set of bit lines and a second set of bit lines, wherein the first set of bit lines is electrically coupled to the first set of transistors by the first set of vias and the third set of vias, overlaps the first memory cell array, and extends in the first direction, wherein the second set of bit lines is electrically coupled to the second set of transistors by the first set of vias and the third set of vias, overlaps the second memory cell array, and extends in the first direction, wherein the second metal level is different from the first metal level, wherein at least the first width is different from the second width, or the first height is different from the second height.

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