Semiconductor structure with gate insulation layer and manufacturing method therefor

Abstract

A method includes: forming a lower semiconductor region; forming an upper semiconductor region overlapping the lower semiconductor region; forming a lower gate dielectric and an upper gate dielectric on the lower and upper semiconductor regions, respectively; forming a lower gate electrode on the lower and upper gate dielectrics; etching back the lower gate electrode; forming a gate insulation layer on the lower gate electrode that has been etched back; and forming an upper gate electrode over the gate insulation layer. The upper gate electrode is disposed on the upper gate dielectric.

Description

Priority claim and cross-reference

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 620,304, filed on January 12, 2024, entitled "Semiconductor Structure with Gate Isolation Layer and Manufacturing Method Thereof," which is incorporated by reference into this application. background

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate. The various material layers are patterned using lithography to create circuit components and elements on the substrate.

[0003] The semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, allowing more components to be integrated into a given area. However, reducing the minimum feature size creates additional problems that need to be addressed. Short description of the drawings

[0004] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not drawn to scale. Rather, the dimensions of various elements may be arbitrarily exaggerated or reduced for clarity of explanation. Fig. 1 shows a perspective view of exemplary complementary field effect transistors (CFETs) according to some embodiments. The Fig. 2 to 7A, 7B, 8A, 8B, 9 to 13, 14A, 14B and 14C are illustrations of intermediate stages in the fabrication of CFETs according to some embodiments. The Fig. 15 to 22 are illustrations of intermediate stages in the fabrication of CFETs according to some embodiments. Fig. 23 shows a perspective view of a CFET structure according to some embodiments. Fig. 24 shows a flow diagram for fabricating CFETs according to some embodiments. Detailed description

[0005] The present disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the fabrication of a first element over or on top of a second element may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numbers and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in another orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] A CFET (complementary field-effect transistor) structure and a method for fabricating the same are provided. Throughout this specification, the terms "FET" and "transistor" are used interchangeably. In some embodiments, a CFET structure includes a bottom FET and an top FET that overlaps the bottom FET. A gate dielectric insulation layer is formed over a gate electrode of the bottom FET and under a gate electrode of the top FET. This electrically isolates the gate electrode of the bottom FET from the gate electrode of the top FET.

[0008] While gate-all-around (GAA) transistors, such as nanostructure FETs, are discussed here as an example, it should be understood that the principle of the present disclosure may also be used to fabricate other types of transistors, such as planar transistors, fin field-effect transistors (FinFETs), or the like.

[0009] Fig. 1 shows an example of CFETs 10 according to some embodiments, including FETs (transistors) 10U and 10L. Fig. Figure 1 is a three-dimensional diagram in which some structural elements of the CFETs are omitted for clarity of discussion.

[0010] A CFET 10 includes a bottom nanostructure FET 10L of a first device type (e.g., n / p) and an top nanostructure FET 10U of a second device type (e.g., p / n) opposite to the first device type. The nanostructure FETs 10U and 10L include semiconductor nanostructures 26' (comprising bottom semiconductor nanostructures 26'L and top semiconductor nanostructures 26'U), with the semiconductor nanostructures 26' acting as channel regions for the nanostructure FETs. The bottom semiconductor nanostructures 26'L are dedicated to the bottom nanostructure FET 10L, and the top semiconductor nanostructures 26'U are dedicated to the top nanostructure FET 10U.

[0011] Gate dielectrics 78 enclose the respective semiconductor nanostructures 26'. Gate electrodes 80 (comprising a lower gate electrode 80L and an upper gate electrode 80U) are disposed on the gate dielectrics 78. Source / drain regions 62 (comprising lower source / drain regions 62L and upper source / drain regions 62U) are disposed on opposite sides of the gate dielectrics 78 and the respective gate electrodes 80. The source / drain regions may refer to a source or a drain individually or collectively, depending on the context. Isolation elements (not shown) may be formed to separate desired ones of the source / drain regions 62 and / or desired ones of the gate electrodes 80.

[0012] Fig. 1 further shows reference cross-sections used in later figures. A cross-section A-A' is a vertical cross-section perpendicular to a cross-section B-B' and extending along a longitudinal axis of a gate electrode 80 of the CFET. The cross-section B-B' is a vertical cross-section parallel to a longitudinal axis of the semiconductor nanostructures 26' of a CFET and extending, for example, in a direction of current flow between the source / drain regions 62 of the CFET. Later figures may refer to these reference cross-sections for clarity.

[0013] The Fig. 2 to 14A, 14B, 14C show sectional views of intermediate stages in the fabrication of CFETs (shown schematically in Fig. 1) according to some embodiments. The corresponding processes are also schematically indicated in the process flow 200 shown in Fig. 24 is shown.

[0014] In Fig. 2, a wafer 2 is provided, which comprises a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. An SOI substrate may comprise a layer of a semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, such as a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, a III-V compound semiconductor, or the like, or a combination thereof.

[0015] A multilayer stack 22 is fabricated over the substrate 20. The multilayer stack 22 includes alternating dummy semiconductor layers 24 (including dummy semiconductor layers 24A and a dummy semiconductor layer 24B) and semiconductor layers 26 (including lower semiconductor layers 26L and upper semiconductor layers 26U). The lower semiconductor layers 26L and the upper semiconductor layers 26U are used to fabricate a lower FET and an upper FET, respectively.

[0016] Corresponding wells (not shown individually) can be created in the lower semiconductor layers 26L and the upper semiconductor layers 26U. For example, the semiconductor layers 26L and 26U can be doped in situ (when grown epitaxially) and / or they can be doped to desired conductivity types.

[0017] In the illustrated example, the multilayer stack 22 includes six of the dummy semiconductor layers 24 and six of the semiconductor layers 26. It should be understood that the multilayer stack 22 may include any number of dummy semiconductor layers 24 and semiconductor layers 26. Each layer of the multilayer stack 22 may be grown using a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or may be deposited using a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like.

[0018] The dummy semiconductor layers 24A are formed from a first semiconductor material, and the dummy semiconductor layer 24B is formed from a second semiconductor material that is different from the first semiconductor material. The first and second semiconductor materials can be selected from the semiconductor materials considered for the substrate 20. The first and second semiconductor materials have a high etch selectivity with respect to each other. This allows the dummy semiconductor layer 24B to be removed at a higher speed than the dummy semiconductor layers 24A in later processes.

[0019] The semiconductor layers 26 (which include the lower semiconductor layers 26L and the upper semiconductor layers 26U) are made of one or more semiconductor materials. The semiconductor materials can be selected from the semiconductor materials considered for the substrate 20. The lower semiconductor layers 26L and the upper semiconductor layers 26U can be made of the same semiconductor material or of different semiconductor materials.

[0020] In some embodiments, the dummy semiconductor layers 24A are made of (or include) silicon germanium, the semiconductor layers 26 are made of silicon, and the dummy semiconductor layer 24B may be made of germanium or silicon germanium having a higher percentage of germanium atoms than in the semiconductor layer 24A.

[0021] In Fig. 3, the multilayer stack 22 and the substrate 20 are patterned to produce semiconductor stripes 28. The corresponding process is indicated as a process 202 in the process flow 200, which is shown in Fig. 24. Each of the semiconductor stripes 28 comprises a semiconductor stripe 20' (the portions of the original substrate 20) and a multilayer stack 22', which is the remaining portion of the multilayer stack 22. The remaining portions 22' of the multilayer stack 22 are hereinafter referred to as nanostructures, which are designated using the corresponding reference numeral appended with the symbol. Accordingly, the multilayer stack 22' includes dummy nanostructures 24'A, dummy nanostructures 24'B, bottom semiconductor nanostructures 26'L, middle semiconductor nanostructures 26'M, and top semiconductor nanostructures 26'U. The etching may be performed using a suitable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. The dummy nanostructures 24'A and the dummy nanostructures 24'B may also be collectively referred to as dummy nanostructures 24'.The lower semiconductor nanostructures 26'L and the upper semiconductor nanostructures 26'U may also be collectively referred to as semiconductor nanostructures 26'.

[0022] The lower semiconductor nanostructures 26'L act as channel regions for lower nanostructure FETs of the CFETs. The upper semiconductor nanostructures 26'U act as channel regions for upper nanostructure FETs of the CFETs. The middle semiconductor nanostructures 26'M are the semiconductor nanostructures 26' that are located directly above / below (e.g., in contact with) the dummy nanostructures 24'B. The middle semiconductor nanostructures 26'M can be used for isolation and may or may not act as channel regions for the CFETs. The dummy nanostructures 24'B will later be replaced with isolation structures. The isolation structures and the middle semiconductor nanostructures 26'M can define boundaries of the lower and upper nanostructure FETs.

[0023] In Fig. 4, isolation regions 32 are created over the substrate 20 and between adjacent semiconductor strips 28. The isolation regions 32 may include a dielectric coating and a dielectric material over the dielectric coating.

[0024] Subsequently, the insulation regions 32 are recessed. Some upper portions of the semiconductor strips 28 (containing the multilayer stacks 22') protrude beyond the remaining insulation regions 32 and form projecting fins 34.

[0025] A dummy dielectric layer 36 is then formed on the protruding fins 34. The dummy dielectric layer 36 may be formed of or comprise, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited using suitable methods or thermally grown. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, using physical vapor deposition (PVD), CVD, or other methods and subsequently planarized, for example, using a CMP (chemical mechanical polishing) process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from a group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), or the like.A mask layer 40 is formed over the planarized dummy gate layer 38, which may contain, for example, silicon nitride, silicon oxynitride, or the like.

[0026] Subsequently, the mask layer 40 can be patterned using photolithography and etching processes to produce a mask, which is then used to etch and pattern the dummy gate layer 38 and, if applicable, the dummy dielectric layer 36. A resulting structure is shown in Fig. 5. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form dummy gate stack 42.

[0027] In Fig. 5, gate spacers 44 are formed over the multilayer stacks 22' and on exposed sidewalls of the dummy gate stacks 42. The gate spacers 44 may be formed by conformally depositing one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Suitable dielectric materials may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be deposited using a deposition process such as CVD, ALD, or the like. Fin spacers 45 are also formed.

[0028] Subsequently, source / drain recesses 46 are created in the semiconductor stripes 28. The source / drain recesses 46 are created by etching and may extend through the multilayer stacks 22' and into the semiconductor stripes 20'. Bottom surfaces of the source / drain recesses 46 may be located above, below, or flush with the top surfaces of the isolation regions 32. During the etching processes, the gate spacers 44 and the dummy gate stacks 42 mask some portions of the semiconductor stripes 28. The etching may comprise a single etching process or multiple etching processes. Timed etching processes may be used to stop the etching of the source / drain recesses 46 after reaching a desired depth.

[0029] In a subsequent process, the dummy nanostructures 24'A are laterally recessed, and a dielectric material is filled into the respective recesses to produce internal spacers 54. The resulting structure is shown in Fig. 6. In addition, the dummy nanostructures 24'B are also recessed and filled with a dielectric material to produce dielectric insulation layers 56.

[0030] Then, lower source / drain epitaxial regions 62L are formed in the lower parts of the source / drain recesses 46 ( Fig. 5). The lower source / drain regions 62L are in contact with the lower semiconductor nanostructures 26'L, but they are not in contact with the upper semiconductor nanostructures 26'U. The inner spacers 54 electrically isolate the lower source / drain epitaxial regions 62L from the dummy nanostructures 24'A, which will be replaced by replacement gates in later processes.

[0031] The lower source / drain epitaxial regions 62L are grown epitaxially and have a conductivity type appropriate for the device type (p or n) of the lower nanostructure FETs. When the lower source / drain epitaxial regions 62L are n-type source / drain regions, the respective material may be silicon or carbon-doped silicon doped with an n-type dopant such as phosphorus, arsenic, or the like. When the lower source / drain epitaxial regions 62L are p-type source / drain regions, the respective material may be silicon or silicon germanium doped with a p-type dopant such as boron, indium, or the like. The lower source / drain epitaxial regions 62L may be doped in situ, and they may or may not be doped with the corresponding p-type or n-type dopants.

[0032] A first contact etch stop layer (CESL) 66 and a first interlayer dielectric (ILD) 68 are formed. The first CESL 66 may be formed from a dielectric material having a high etch selectivity to the etch of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, using a suitable deposition method such as CVD, ALD, or the like. The first ILD 68 may be formed from a dielectric material deposited using a suitable method such as CVD, plasma-enhanced CVD (PECVD), or flowable CVD (FCVD). A suitable dielectric material for the first ILD 68 may be phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like.

[0033] The manufacturing processes may include depositing a conformal CESL, depositing a material for the first ILD 68, followed by a planarization process, and a subsequent etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. Then, an anisotropic etch process is performed to remove the portions of the first CESL 66 that are higher than the recessed first ILD 68. After the recessing, the sidewalls of the upper semiconductor nanostructures 26'U are exposed.

[0034] Then, upper source / drain epitaxial regions 62U are formed in the upper parts of the source / drain recesses 46. The materials for the upper source / drain epitaxial regions 62U can be selected from the same group of materials that are suitable for forming the lower source / drain regions 62L, depending on the desired conductivity type of the upper source / drain epitaxial regions 62U.

[0035] The conductivity type of the upper source / drain epitaxial regions 62U may be opposite to the conductivity type of the lower source / drain epitaxial regions 62L. In other words, the upper source / drain epitaxial regions 62U may be doped opposite to the lower source / drain epitaxial regions 62L. The upper source / drain epitaxial regions 62U may be doped in situ, and / or they may be doped with an n-type or a p-type dopant.

[0036] A second CESL 70 and a second ILD 72 are then fabricated. The materials and fabrication methods may be similar to those for the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail here. The fabrication process may include depositing layers for the CESL 70 and the ILD 72 and performing a planarization process to remove the excess portions of the respective layers. After the planarization process, top surfaces of the second ILD 72, the gate spacer 44, and the dummy gate stack 42 are coplanar (within process variations). The planarization process may or may not remove the masks 40.

[0037] Subsequently, the dummy gate stacks 42 are removed in one or more etching processes, so that recesses 74 are created, as shown in the Fig. 7A and Fig. 7B. The corresponding process is indicated as a process 204 in the process flow 200 shown in Fig. 24. The recesses 74 each expose and / or overlie portions of the multilayer stacks 22'.

[0038] The Fig. 7B can be the cross-section shown in Fig. 1 shown cross section A - A'. In Fig. 7B, three device regions 400, 500, and 600 are shown. Each of the device regions 400, 500, and 600 is used to fabricate a CFET with an upper FET and a lower FET. Each of the device regions 400, 500, and 600 can also be obtained from a vertical cross-section 14A-14A shown in Fig. 23, wherein the cross section 14A - 14A passes through metal gates to be manufactured.

[0039] Then, the remaining parts of the dummy nanostructures 24'A ( Fig. 6) are removed by etching so that the recesses 74 extend between the semiconductor nanostructures 26'. In the etching process, the dummy nanostructures 24'A are etched at a higher speed than the semiconductor nanostructures 26', the dielectric insulation layers 56, and the internal spacers 54. The etching may be isotropic. For example, if the dummy nanostructures 24'A are made of silicon germanium and the semiconductor nanostructures 26' are made of silicon, the etching process may be a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydrate (NH4OH), or the like.

[0040] The Fig. 8A, 8B, 9 to 13, 14A, 14B, and 14C show details of the fabrication of gate dielectrics 78 and gate electrodes 80 (including 80U and 80L) according to some embodiments. Fig. 8A and Fig. 8B, gate dielectrics 78 are formed in the recesses 74 and on the exposed semiconductor nanostructures 26'. The corresponding process is indicated as a process 206 in the process flow 200 shown in Fig. 24. The gate dielectrics 78 are formed on the exposed surfaces of the exposed features comprising the semiconductor nanostructures 26' and the gate spacers 44. The gate dielectrics 78 enclose all (e.g., four) sides of the semiconductor nanostructures 26`.

[0041] The gate dielectrics 78 may each include an interface layer 78IL, which is not shown but is separately labeled. The interface layer 78IL may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, combinations thereof, multilayers thereof, or the like. The interface layer 78IL may be formed using a thermal oxidation process and / or a deposition process.

[0042] Each gate dielectric 78 may further include a high-k dielectric layer 78HK above the interface layer, which may have a high dielectric constant (high-k value) of, for example, about 7.0, about 21, or higher. The high-k dielectric layer 78HK may be formed from or include a metal oxide or silicate of a metal selected from the group consisting of hafnium, zirconium, barium, titanium, lead, and combinations thereof. Molecular beam deposition (MBD), ALD, PECVD, and the like may be selected as the fabrication method for the high-k dielectric layer 78HK. The high-k dielectric layer 78HK may have a thickness of about 1 nm to about 5 nm. The gate dielectrics 78 in the device regions 400, 500, and 600 may be fabricated in common processes.

[0043] In Fig. 9, a lower gate electrode 80L is fabricated. The corresponding process is indicated as a process 208 in the process flow 200 shown in Fig. 24. In some embodiments, the bottom gate electrode 80L includes a work function layer. It may also include other layers, such as a capping layer below the work function layer or a blocking layer above the work function layer, and may or may not include a metal fill layer above the blocking layer. The formation of the bottom gate electrode 80L may be performed using deposition processes such as ALD, metal organic vapor deposition (MOCVD), PECVD, or the like. After the layers for the bottom gate electrode 80L have been deposited, a planarization process is performed to level the top surface of the bottom gate electrode 80L.

[0044] In some embodiments, the capping layer and the blocking layer may include TiN or TiSiN, and the material for the work function layer depends on whether the bottom FETs are NFETs or PFETs. For example, if the bottom FETs are NFETs, the work function layer may include TiAlN, TiAl, TiN, tungsten, or the like. If the bottom FETs are PFETs, the work function layer may include TiN, TaN, tungsten, or the like.

[0045] In some embodiments, the lower gate electrode 80L may or may not include grooves 81. The bottom surfaces of the grooves 81 are located near the bottom surface of the lower gate electrode 80L. In some embodiments, a width W1 of the grooves 81 may be about 1 nm to about 5 nm.

[0046] In Fig. 10, an etch-back process is performed to recess the lower gate electrode 80L. The corresponding process is indicated as a process 210 in the process flow 200 shown in Fig. 24. A top surface of the remaining lower gate electrode 80L is lower than a top surface of an upper one of the middle semiconductor nanostructures 26'M and higher than a bottom surface of a lower one of the middle semiconductor nanostructures 26'M.

[0047] The etchback process can be performed using a dry etching process or a wet etching process. For example, if a dry etch is chosen, chlorine (Cl2) can be used as an etching gas, although a carrier gas such as Ar, N2, or the like can also be used. The etching process can expose the grooves 81. In some embodiments, the etchback process can be performed using by-product-forming gases such as SiCl4, O2, CH4, N2, BCl3, and / or the like. This creates a by-product 84 that fills the grooves 81 during the etchback process. Depending on the gases used, the by-product 84 can include an inorganic material such as SiCO, SiCN, BN, or the like, a polymer material such as a polymeric carbon nitride (CN), or combinations thereof. The by-product 84 can also be a dielectric material.The by-product produced that fills the gaps 81 is also referred to as by-product areas 84.

[0048] In some embodiments, the by-product regions 84 completely fill the gaps 81. In some embodiments, the by-product regions 84 only partially fill the gaps 81. For example, the by-product regions 84 may fill the lower portions of the gaps 81, while upper portions remain unfilled. The by-product regions 84 may also form a conformal coating on sidewalls of the gaps 81, while the middle portions of the gaps 81 are not occupied. Throughout the description, the gaps 81 and the by-product regions 84 are referred to as regions 81 / 84, which means that the corresponding regions are gaps 81 in the form of air gaps and / or the by-product regions 84.

[0049] Fig. 11 shows the fabrication of a gate insulation layer 86. The corresponding process is indicated as a process 212 in the process flow 200, which is shown in Fig. 24. In some embodiments, the gate insulation layer 86 includes a dielectric material such as SiO, SiN, SiCN, SiOC, SiOCN, SiON, or the like. The manufacturing process may include: depositing the gate insulation layer 86 using a deposition process such as an ALD process, a CVD process, a PVD process, or the like; planarizing the top surface of the gate insulation layer 86 (e.g., by CMP or machine grinding); and etching back the dielectric layer. The resulting gate insulation layer 86 has a top surface that is lower than the top surface of the top of the middle semiconductor nanostructures 26'M.

[0050] Fig. 12 shows an optional patterning of the gate insulation layer 86, which may be performed by forming an etch mask (such as a patterned photoresist; not shown) and etching the gate insulation layer 86. The corresponding process is indicated as a process 214 in the process flow 200, which is shown in Fig. 24. After patterning the gate insulation layer 86, the regions 81 / 84 may be exposed or covered by the gate insulation layer 86, or only some parts of the regions 81 / 84 may be exposed while other parts of the regions 81 / 84 are covered by the gate insulation layer 86.

[0051] Fig. 13 illustrates the fabrication of a top gate electrode 80U according to some embodiments. The corresponding process is indicated as a process 216 in the process flow 200 shown in Fig. 24. The formation of the upper gate electrode 80U may include depositing a plurality of conductive layers and performing a planarization process. The description of the structure and materials of the upper gate electrode 80U can be found in the discussion of the lower gate electrode 80L, except that the corresponding upper FETs may have a conductivity type opposite to that of the lower FETs, and the material for the work function layer in the upper gate electrode 80U is selected to match the conductivity type of the upper FETs.

[0052] In some embodiments, grooves 81' are formed in the upper gate electrode 80U. When the grooves 81' are formed, they may have a width W2 that is smaller than the width W1 ( Fig. 9). In alternative embodiments, the joints 81' are not created.

[0053] Fig. 14A shows the formation of isolation regions 88 that electrically and physically isolate the gate electrodes 80U and 80L in the device regions 400, 500, and 600. The corresponding process is indicated as a process 218 in the process flow 200 shown in Fig. 24. The manufacturing process may include etching the upper gate electrode 80U and the lower gate electrode 80L to create an opening until the underlying gate dielectric 78 is exposed. The gate dielectric 78 may be etched to expose a deeper STI region 32, or it may not be etched. In a subsequent process, dielectric materials are filled into the opening to create the gate isolation regions 88.

[0054] In some embodiments, after creating a gate insulation region 88, the respective region 81 / 84 is completely removed. In alternative embodiments, after creating the gate insulation region 88, the respective region 81 / 84 is partially removed and partially remains, as in Fig. 14A. In still further alternative embodiments, an entirety of the region 81 / 84 remains because the corresponding gate isolation region 88 is not formed (while other gate isolation regions 88 may still be formed).

[0055] In some embodiments, the isolation regions 88 may be formed simultaneously with a contact etch stop layer (CESL) 90 and an interlayer dielectric (ILD) 92, and materials of the CESL 90 and ILD 92 that fill the openings form the isolation regions. In other embodiments, the isolation regions 88 are created using processes separate from the formation of the CESL 90 and ILD 92. In some embodiments, the CESL 90 may be formed from a nitride, such as SiN, SiC, SiOCN, or the like, while the ILD 92 may be formed from an oxide, such as SiO, SiOC, SiOCN, or the like. Gate contact plugs 94 are formed to extend into the ILD 92 to electrically connect to the top gate electrode 80U. An electrical connection is also formed to the bottom gate electrode 80L (not shown).

[0056] Throughout this specification, the gate electrodes 80L and the underlying gate dielectrics 78 are collectively referred to as the gate stack 94L, and the gate electrodes 80U and the underlying gate dielectrics 78 are collectively referred to as the gate stack 94U. This creates a CFET 10 that includes a lower FET 10L that connects the gate stacks 94L and source / drain regions 62L ( Fig. 14B) and includes an upper FET 10U, which includes the gate stacks 94U and source / drain regions 62U ( Fig. 14B).

[0057] The gate insulation layer 86 may be at the same level as the dielectric insulation layers 56. In alternative embodiments described in Fig. 14A, the top surface of the gate insulation layer 86 may be at the same height as the top surface of the upper one of the middle semiconductor nanostructures 26'M, and the corresponding gate insulation layer 86 is indicated by dashed lines 86'. In alternative embodiments, the bottom surface of the gate insulation layer 86 may be at the same height as the bottom surface of the lower one of the middle semiconductor nanostructures 26'M, and the corresponding gate insulation layer 86 is indicated by dashed lines 86". The gate insulation layer 86 may also be located at a position between the positions indicated by the dashed lines 86' and the dashed lines 86".

[0058] Fig. Figure 23 shows a perspective view of CFET 10 according to some embodiments. Here, source / drain regions 62L and 62U, gate electrodes 80U and 80L, gate insulation layer 86, STI regions 32, etc. are labeled.

[0059] The Fig. 14A shown sectional view is taken from the Fig. 23 shown vertical cross section 14A - 14A (and the one in Fig. 1 shown vertical cross section A - A'), which cross section cuts through the metal gate electrodes. Fig. 14B shows a Fig. 23 shown vertical cross section 14B - 14B (and the in Fig. 1), which cross section cuts through the nanostructures 26U and 26L (channel regions) and the source / drain regions 62L and 62U. Fig. 14C shows a Fig. 23, which cuts through the STI region 32 and the gate isolation region 88 to separate adjacent gate electrodes 80U and 80L.

[0060] As in Fig. 14A, in some embodiments, the regions 81 / 84 may be completely removed during the formation of the gate insulation regions 88. Some or all of the regions 81 / 84 may have some portions remaining, depending on the widths of the regions 81 / 84 and the widths of the gate insulation regions 88, as also shown in Fig. 14A. In some embodiments, some of the gate isolation regions 88 are not formed, and therefore the Fig. 13 shown areas 81 / 84 exist in the final structure.

[0061] The Fig. 15 to 22 show structures fabricated according to alternative embodiments. It should be understood that the structures fabricated according to these embodiments and the structures shown in the Fig. 14A to 14C may be present simultaneously in the same device die and the same device wafer and may be manufactured using the same manufacturing processes.

[0062] The Fig. 15 and Fig. 16 illustrate the formation of the lower gate electrode 80L, the gate insulation layer 86, and the upper gate electrode 80U according to some embodiments. The by-product regions 84 are also illustrated. By creating the by-product regions 84, the gate insulation layer 86 may more easily seal the lower seams 81'.

[0063] The Fig. 17 and Fig. 18 show the formation of the lower gate electrode 80L, the gate insulation layer 86, and the upper gate electrode 80U according to alternative embodiments. The illustrated grooves 81' are not filled with the by-product regions 84, or they may be only partially filled with them, e.g., only their lower parts being filled. Alternatively, the by-product regions 84 may be formed as conformal deposits. This structure may result if no by-product-forming gas is used in the etch-back process for the lower gate electrode 80L. Alternatively, this structure may result if the by-products are generated but do not fill the illustrated grooves 81' at all or only insufficiently. The gate insulation layer 86 thus has some parts that extend into and fill the upper parts of the lower grooves 81'.

[0064] The Fig. 19 and Fig. 20 illustrate the formation of the lower gate electrode 80L, the gate insulation layer 86, and the upper gate electrode 80U according to further alternative embodiments. The illustrated grooves 81' are not filled with the by-product regions 84, or they may be only partially filled, e.g., only their lower portions being filled. In some embodiments, the gate insulation layer 86 is formed using a bottom-up deposition process. As a result, the gate insulation layer 86 fills the remaining lower grooves 81'. The grooves 81' may or may not contain the by-products, and when the by-products are generated, the remaining grooves 81' that have not been filled with the by-products are filled with the gate insulation layer 86.

[0065] Fig. 21 illustrates the fabrication of the lower gate electrode 80L, the gate insulation layer 86, and the upper gate electrode 80U according to some embodiments. The gate insulation layer 86 is patterned, and the recessed grooves 81' may be re-exposed. As a result, the upper gate electrode 80U seals the recessed grooves 81'. Furthermore, the upper gate electrode 80U may extend into the recessed grooves 81'.

[0066] In some embodiments, the Fig. 22 is also present in the final structure, which is shown in Fig. 23. According to alternative embodiments, after the manufacture of the Fig. 22 shown structure of the Fig. 14A is performed to create the gate isolation regions 88, which are represented by dashed lines.

[0067] The embodiments of the present disclosure have several advantages. By forming a horizontal gate insulation layer between the top gate electrode and the bottom gate electrode in a CFET structure, the two electrodes are electrically isolated from each other. The process can be adapted to fill the gaps that may arise in the bottom gate electrode.

[0068] According to some embodiments of the present disclosure, a method comprises: forming a lower semiconductor region; forming an upper semiconductor region overlapping the lower semiconductor region; forming lower and upper gate dielectrics on the lower and upper semiconductor regions, respectively; forming a lower gate electrode on the lower and upper gate dielectrics; etching back the lower gate electrode; forming a gate insulation layer on the lower gate electrode that has been etched back; and forming an upper gate electrode over the gate insulation layer, wherein the upper gate electrode is arranged on the upper gate dielectric.

[0069] In one embodiment, the method further comprises patterning the gate insulation layer. In one embodiment, forming the gate insulation layer comprises: depositing a dielectric layer; planarizing the dielectric layer; and etching back the dielectric layer, wherein a remaining portion of the dielectric layer forms the gate insulation layer. In one embodiment, a groove is created in the lower gate electrode, wherein the groove is exposed after the lower gate electrode has been etched back.

[0070] In one embodiment, a byproduct is generated during the etchback of the lower gate electrode to at least partially fill the gap. In one embodiment, a silicon-containing process gas is supplied during the etchback of the lower gate electrode, and the byproduct is a silicon-containing dielectric. In one embodiment, the byproduct completely fills the gap. In one embodiment, the method further comprises: etching the lower and upper gate electrodes; and filling a dielectric region into gaps left by the etched lower gate electrode and the etched upper gate electrode.

[0071] In one embodiment, a gap is created in the lower gate electrode, wherein the gate insulation layer at least partially fills the gap. In one embodiment, the gate insulation layer completely fills the gap. In one embodiment, the lower semiconductor region comprises a first semiconductor nanostructure, and the upper semiconductor region comprises a second semiconductor nanostructure. The method further comprises: creating a first source / drain region adjacent to the first semiconductor nanostructure; and creating a second source / drain region adjacent to the second semiconductor nanostructure.

[0072] According to some embodiments of the present disclosure, a structure comprises: a lower transistor having a first semiconductor region, a first gate dielectric on the first semiconductor region, and a lower gate electrode on the first gate dielectric; an upper transistor having a second semiconductor region overlapping the first semiconductor region, a second gate dielectric on the second semiconductor region, and an upper gate electrode on the second gate dielectric; and a gate insulation layer above and in contact with the lower gate electrode, wherein the gate insulation layer is further disposed below and in contact with the upper gate electrode. In one embodiment, the lower and upper transistors have opposite conductivity types.

[0073] In one embodiment, the structure further comprises an isolation region having a sidewall contacting edges of the lower gate electrode, the gate insulation layer, and the upper gate electrode. In one embodiment, the lower gate electrode further comprises a silicon-containing dielectric region. In one embodiment, the lower gate electrode further comprises a gap filled with the same material as the gate insulation layer. In one embodiment, the lower gate electrode further comprises a gap as an air gap.

[0074] According to some embodiments of the present disclosure, a structure includes a first CFET (complementary field effect transistor) structure comprising: a first bottom field effect transistor (FET) having a first bottom gate electrode; a first top FET having a first top gate electrode overlapping the first bottom gate electrode; and a first gate insulation layer disposed between and adjacent to the first bottom gate electrode and the first top gate electrode. The structure further includes a second CFET structure comprising: a second bottom FET having a second bottom gate electrode, and a second top transistor having a second top gate electrode overlapping the second bottom gate electrode.The structure further includes an isolation region comprising: a first sidewall contacting first edges of the first lower gate electrode and the first upper gate electrode, and a second sidewall contacting second edges of the second lower gate electrode and the second upper gate electrode. In one embodiment, the structure further includes a second gate insulation layer disposed between and adjacent to the second lower gate electrode and the second upper gate electrode. In one embodiment, the second lower gate electrode physically contacts the second upper gate electrode.

[0075] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 620,304

[0001]

Claims

[1] Method comprising: Creating a lower semiconductor region; Creating an upper semiconductor region overlapping the lower semiconductor region; Forming a lower and an upper gate dielectric on the lower and upper semiconductor regions, respectively; Forming a lower gate electrode on the lower and upper gate dielectrics; Etching back the lower gate electrode; forming a gate insulation layer on the lower gate electrode which has been etched back; and Forming an upper gate electrode over the gate insulation layer, wherein the upper gate electrode is disposed on the upper gate dielectric. [2] The method of claim 1, further comprising patterning the gate insulation layer. [3] The method of claim 1 or 2, wherein forming the gate insulation layer comprises: Depositing a dielectric layer; Planarizing the dielectric layer; and Etching back the dielectric layer, with a remaining part of the dielectric layer forming the gate insulation layer. [4] Method according to one of the preceding claims, wherein: a gap is created in the lower gate electrode, and the gap is exposed after the lower gate electrode has been etched back. [5] Method according to one of the preceding claims, wherein: during the etching back of the lower gate electrode, a by-product is generated to at least partially fill the gap. [6] Method according to one of the preceding claims, wherein: during the etching back of the lower gate electrode, a silicon-containing process gas is supplied and the by-product is a silicon-containing dielectric. [7] A method according to claim 5 or 6, wherein the by-product completely fills the joint. [8] A method according to any one of the preceding claims, further comprising: Etching the lower and upper gate electrodes; and Filling a dielectric region in gaps left by the etched lower gate electrode and the etched upper gate electrode. [9] Method according to one of the preceding claims, wherein: a gap is created in the lower gate electrode, and the gate insulation layer at least partially fills the gap. [10] A method according to any one of the preceding claims, wherein the gate insulation layer completely fills the gap. [11] Method according to one of the preceding claims, wherein: the lower semiconductor region has a first semiconductor nanostructure and the upper semiconductor region has a second semiconductor nanostructure, and the procedure further includes: Creating a first source / drain region adjacent to the first semiconductor nanostructure; and Creating a second source / drain region adjacent to the second semiconductor nanostructure. [12] Structure with: a lower transistor which has the following: a first semiconductor region, a first gate dielectric on the first semiconductor region, and a lower gate electrode on the first gate dielectric; an upper transistor which has the following: a second semiconductor region overlapping the first semiconductor region, a second gate dielectric on the second semiconductor region, and an upper gate electrode on the second gate dielectric; and a gate insulation layer above and in contact with the lower gate electrode, the gate insulation layer also being arranged below and contacting the upper gate electrode. [13] Structure according to claim 12, wherein: the lower and upper transistors have opposite conductivity types. [14] The structure of claim 12 or 13, further comprising an isolation region having a sidewall contacting edges of the lower gate electrode, the gate insulation layer, and the upper gate electrode. [15] The structure of any one of claims 12 to 14, wherein the lower gate electrode further comprises a silicon-containing dielectric region. [16] Structure according to any one of claims 12 to 15, wherein: the lower gate electrode further comprises a gap filled with the same material as that of the gate insulation layer. [17] The structure of any one of claims 12 to 16, wherein the lower gate electrode further comprises a seam as an air gap. [18] Structure with: a first CFET structure (CFET: complementary field effect transistor) comprising: a first lower field effect transistor (FET) having a first lower gate electrode, a first upper FET having a first upper gate electrode overlapping the first lower gate electrode, and a first gate insulation layer disposed between and adjacent to the first lower gate electrode and the first upper gate electrode; a second CFET structure comprising: a second lower FET having a second lower gate electrode, and a second upper transistor having a second upper gate electrode overlapping the second lower gate electrode; and an isolation area that has the following: a first sidewall contacting first edges of the first lower gate electrode and the first upper gate electrode, and a second sidewall contacting second edges of the second lower gate electrode and the second upper gate electrode. [19] The structure of claim 18, further comprising a second gate insulation layer disposed between and adjacent to the second lower gate electrode and the second upper gate electrode. [20] The structure of claim 18 or 19, wherein the second lower gate electrode physically contacts the second upper gate electrode.

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