DISPLAY DEVICE

Abstract

A display device is provided. The display device comprises a first substrate including a plurality of upper contact pads; a second substrate including a plurality of lower contact pads; and a plurality of side leads connecting the plurality of upper contact pads and the plurality of lower contact pads, wherein each of the plurality of lower contact pads includes a first lower contact electrode disposed under the second substrate; a first insulating layer disposed under the first lower contact electrode; a second lower contact electrode disposed under the first insulating layer; a third lower contact electrode disposed under the second lower contact electrode; and a second insulating layer disposed under the third lower contact electrode, wherein the third lower contact electrode is formed of a transparent conductor material.Therefore, the manufacturing process and manufacturing cost of the display device can be reduced.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0028219, filed on February 27, 2024, in the Korean Intellectual Property Office. Area

[0002] The present disclosure relates to a display device and, more particularly, to a display device using a light-emitting diode (LED). background

[0003] As display devices used for a computer monitor, a television, a mobile phone, or the like, there are an organic light-emitting display device (OLED device) which is a self-emitting device, a liquid crystal display device (LCD device) which requires a separate light source, and the like.

[0004] An applicable field of the display device is diversified to personal digital assistants as well as computer monitors and televisions, and a display device with a large display area and a reduced volume and weight is investigated.

[0005] Furthermore, a display device incorporating a light-emitting diode (LED) has recently attracted attention as a next-generation display device. Since the LED is made of an inorganic material rather than an organic material, its reliability is excellent, resulting in a longer service life than that of a liquid crystal display device or an organic light-emitting display device. Furthermore, the LED exhibits a fast illumination speed, excellent luminous efficiency, and strong impact resistance, resulting in excellent stability and the ability to display an image with high luminance. SUMMARY

[0006] An object of the disclosure is to provide a display device with a reduced manufacturing process and reduced manufacturing costs.

[0007] Another object is to provide a display device in which a short circuit path is reduced to reduce an error problem.

[0008] Yet another object is to provide a display device with a reduced parasitic capacitor.

[0009] The object is achieved by the features of the independent claims. Preferred embodiments are given in the dependent claims.

[0010] According to one aspect of the present disclosure, a display device is provided. The display device comprises a first substrate including a plurality of upper pads; a second substrate including a plurality of lower pads; and a plurality of side leads connecting the plurality of upper pads and the plurality of lower pads, wherein each of the plurality of lower pads includes a first lower contact electrode disposed under the second substrate; a first insulating layer disposed under the first lower contact electrode; a second lower contact electrode disposed under the first insulating layer; a third lower contact electrode disposed under the second lower contact electrode; and a second insulating layer disposed under the third lower contact electrode, wherein the third lower contact electrode is formed of a transparent conductor material.

[0011] In one or more embodiments, the third lower contact electrode and the second lower contact electrode may completely overlap.

[0012] In one or more embodiments, the first insulating layer and the second insulating layer may be inorganic insulating layers.

[0013] In one or more embodiments, the second insulation layer may open a portion of the third lower contact electrode.

[0014] In one or more embodiments, the third lower contact electrode may be in contact with the plurality of side leads.

[0015] In one or more embodiments, the plurality of lower pads may include a plurality of first lower pads disposed in a first edge of the second substrate and a plurality of second lower pads disposed in a second edge of the second substrate.

[0016] In one or more embodiments, a high potential power voltage may be applied to the plurality of first lower pads.

[0017] In one or more embodiments, a low potential power voltage may be applied to the plurality of second lower pads.

[0018] In one or more embodiments, the plurality of upper pads may include a plurality of first upper pads and a plurality of second upper pads.

[0019] In one or more embodiments, the plurality of side lines may include a plurality of first side lines connecting the plurality of first upper pads and the plurality of first lower pads, and a plurality of second side lines connecting the plurality of second upper pads and the plurality of second lower pads.

[0020] In one or more embodiments, the display device may include a low potential power supply line, a high potential power supply line, and a plurality of data lines arranged on the second substrate.

[0021] In one or more embodiments, the plurality of data lines may overlap with a portion of the high potential power supply line.

[0022] In one or more embodiments, the display device may include a plurality of flexible thin layers disposed between the high-potential power supply line and the low-potential power supply line; and a plurality of auxiliary high-potential power supply lines disposed above the high-potential power supply line such that they are in contact with the high-potential power supply line.

[0023] In one or more embodiments, each of the plurality of auxiliary high potential power supply lines may be alternately arranged with each of the plurality of flexible thin layers.

[0024] In one or more embodiments, the high-potential power supply line may be formed of the same material as the first lower contact electrode, and the plurality of auxiliary high-potential power supply lines may be formed of the same material as the second lower contact electrode and the third lower contact electrode.

[0025] In one or more embodiments, a width of each of the plurality of auxiliary high-potential power supply lines may increase as it is adjacent to the low-potential power supply lines.

[0026] In one or more embodiments, the display device may include a plurality of COF pads disposed on the second substrate and connected to the flexible thin film.

[0027] In one or more embodiments, each of the plurality of COF pads may include a first COF contact electrode, a second COF contact electrode, and a third COF contact electrode, which may be formed from the same material as the first lower contact electrode, the second lower contact electrode, and the third lower contact electrode, respectively.

[0028] In one or more embodiments, the second COF contact electrode and the third COF contact electrode may completely overlap.

[0029] In one or more embodiments, the plurality of lower pads may include a plurality of first lower pads disposed in a first edge of the second substrate and a plurality of second lower pads disposed in a second edge of the second substrate.

[0030] In one or more embodiments, the high potential power supply line may be disposed in the first edge of the second substrate to connect to the plurality of first lower pads.

[0031] In one or more embodiments, the low potential power supply line may be disposed in the second edge of the second substrate to connect to the plurality of second lower pads.

[0032] In one or more embodiments, a width of the high-potential power supply line may correspond to a distance between outermost first lower pads among the plurality of first lower pads.

[0033] In one or more embodiments, a width of the low-potential power supply line may correspond to a distance between outermost second lower pads among the plurality of second lower pads.

[0034] In one or more embodiments, the low-potential power supply line may be formed of the same material as the first lower contact electrode, the second lower contact electrode, and the third lower contact electrode.

[0035] In another aspect, a display device is provided, comprising: a first substrate including a plurality of upper pads; a second substrate including a plurality of lower pads; a plurality of side leads connecting the plurality of upper pads and the plurality of lower pads; a plurality of flexible thin films; and a plurality of COF pads disposed on the second substrate and connected to the flexible thin film.

[0036] In one or more embodiments, each of the plurality of COF pads may include: a first COF contact electrode, a second COF contact electrode, and a third COF contact electrode.

[0037] In one or more embodiments, the first COF contact electrode may be disposed under the second substrate, the second COF contact electrode may be disposed under the first COF contact electrode, and the third COF contact electrode may be disposed under the second COF contact electrode.

[0038] In one or more embodiments, the second COF contact electrode and the third COF contact electrode may completely overlap.

[0039] In one or more embodiments, the third COF contact electrode may be formed from a transparent conductor material.

[0040] Further precise contents of the embodiments are contained in the detailed description and the drawings.

[0041] According to the disclosure, a mask process is reduced to reduce manufacturing costs of the display device.

[0042] According to the disclosure, a structure of a contact unit is improved to prevent a failure problem.

[0043] According to the disclosure, corrosion of the contact unit is prevented to improve the reliability of the contact unit.

[0044] The effects according to the disclosure are not limited to the contents illustrated above, and several different effects are included in the present application text. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above-described and other aspects, features and further advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic diagram of a display device according to an embodiment of the disclosure; Fig. 2A is a partial cross-sectional view of a display device according to an embodiment of the disclosure; Fig. 2B is a perspective view of a tile display device according to an embodiment of the disclosure; Fig. 3 is an enlarged plan view of a first substrate of a display device of one embodiment of the disclosure; Fig. 4 is an enlarged plan view of a second substrate of a display device according to an embodiment of the disclosure; Fig. 5 is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the disclosure; Fig. 6 is a cross-sectional view of a contact surface of a display device according to an embodiment of the disclosure; Fig. 7A is a cross-sectional view of a top pad of a display device according to an embodiment of the disclosure; Fig. 7B is a cross-sectional view of a bottom pad of a display device according to an embodiment of the disclosure; Fig. 8 is a cross-sectional view of a second substrate taken along the line AA' of Fig. 4 was taken; and Fig. 9 is a cross-sectional view of a second substrate taken along line BB' of Fig. 4 was taken. DETAILED DESCRIPTION OF THE EMBODIMENT

[0046] Advantages and features of the disclosure, and a method for achieving the advantages and features, will become apparent by reference to the embodiments described in detail below, together with the accompanying drawings. However, the disclosure is not limited to the embodiments disclosed herein, but may be implemented in various forms. The embodiments are provided merely by way of example so that those skilled in the art can fully understand the disclosure and the scope of the disclosure.

[0047] The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing embodiments of the disclosure are merely examples, and the disclosure is not limited thereto. Similar reference numerals generally designate similar elements throughout the application text. Furthermore, in the following description of the present disclosure, detailed explanation of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. The terms such as "including," "comprise," and "consisting of" used herein are generally intended to allow for the addition of other components, unless the terms are used with the term "merely." Any reference to the singular may include the plural unless expressly stated otherwise.

[0048] Components are interpreted to include a common error range, even if it is not explicitly stated.

[0049] When the positional relationship between two parts is described using terms such as "on", "over", "under", and "next to", one or more parts may be positioned between the two parts, provided the terms are not used with the term "immediate" or "direct".

[0050] When an element or layer is arranged "on" another element or layer, another layer or element may be arranged directly on the other element or between them.

[0051] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from the other components. Therefore, a first component mentioned below may be a second component in a technical concept of the disclosure.

[0052] Similar reference signs generally designate similar elements throughout the application text.

[0053] A size and a thickness of each component illustrated in the drawing are illustrated for convenience of description, and the disclosure is not limited to the size and thickness of the component illustrated.

[0054] The features of various embodiments of the disclosure may be partially or completely concatenated or combined and may interlock and operate in technically different ways, and the embodiments may be practiced independently or in conjunction with one another.

[0055] Hereinafter, a display device according to embodiments of the disclosure will be described in detail with reference to accompanying drawings.

[0056] Fig. 1 is a schematic diagram of a display device according to an embodiment of the disclosure. In Fig. 1, for the sake of simplicity of description, among various components of the display device 100, only a display panel PN, a gate driver GD, a data driver DD, and a timing control unit TC are illustrated.

[0057] With reference to Fig. 1, the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing control unit TC that controls the gate driver GD and the data driver DD.

[0058] The gate driver GD supplies a plurality of scanning signals to a plurality of scanning lines SL according to a plurality of gate control signals supplied from the timing control unit TC. Although in Fig. 1 illustrates that a gate driver GD is arranged to be spaced from one side of the display panel PN, the number of the gate drivers GD and their arrangement are not limited thereto.

[0059] The data driver DD converts image data input from the timing control unit TC into a data voltage using a reference gamma voltage according to a plurality of data control signals supplied from the timing control unit TC. The data driver DD can supply the converted data voltage to the plurality of data lines DL.

[0060] The timing control unit TC aligns image data input from the outside to supply the image data to the data driver DD. The timing control unit TC can generate a gate control signal and a data control signal using synchronization signals input from the outside, such as a pixel clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing control unit TC supplies the generated gate control signal and the generated data control signal to the gate driver GD and the data driver DD to control the gate driver GD and the data driver DD, respectively.

[0061] The display panel PN is a configuration that displays images to the user and includes the plurality of sub-pixels SP. In the display panel PN, the plurality of scanning lines SL and the plurality of data lines DL intersect each other, and the plurality of sub-pixels SP are connected to the scanning lines SL and the data lines DL, respectively. In addition, although not illustrated in the drawing, each of the plurality of sub-pixels SP may be connected to a high-potential power supply line, a low-potential power supply line, a reference line, and the like.

[0062] In the display panel PN, an active area AA and a non-active area NA, which at least partially encloses the active area AA, can be defined.

[0063] The active area AA is an area in which images are displayed in the display device 100. In the active area AA, a plurality of sub-pixels SP configuring a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be arranged. The plurality of sub-pixels SP are a minimum unit configuring the active area AA, and n sub-pixels SP may constitute one pixel PX. In each of the plurality of sub-pixels SP, a light-emitting diode, a thin-film transistor, and the like may be arranged for driving the light-emitting diode. The plurality of light-emitting diodes may be defined in various ways depending on the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting diode may be a light-emitting diode (LED) or a micro-LED.

[0064] A plurality of signal lines are arranged in the active area AA, which transmit various signals to the plurality of sub-pixels SP. For example, the plurality of signal lines may include a plurality of data lines DL that supply a data voltage to each of the plurality of sub-pixels SP, and a plurality of scan lines SL that supply a gate voltage to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend to one direction in the active area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend to a direction different from the one direction in the active area AA to be connected to the plurality of sub-pixels SP. In addition, a low-potential power supply line, a high-potential power supply line, and the like may be further arranged in the active area AA, but are not limited thereto.

[0065] The non-active area NA is an area where no images are displayed, so the non-active area NA can be defined as an area extending from the active area AA. In the non-active area NA, a connection line that transmits a signal to the sub-pixel SP of the active area AA, a terminal electrode, or a drive IC such as a gate driver IC or a data driver IC can be arranged. The non-active area NA can be arranged on a back surface of the display panel PN, that is, a surface where the sub-pixels SP are not arranged, or can be omitted, and is not limited to, as illustrated in the drawing.

[0066] Meanwhile, a driving device such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be mounted in the non-active area NA in a gate-in-panel (GIP) manner, or mounted between the multiple sub-pixels SP in the active area AA in a gate-in-active-area (GIA) manner. For example, the data driver DD and the timing controller TC are separately formed in a flexible thin film and a printed circuit board, and may be electrically connected to the display panel PN by contacting the flexible thin film and the printed circuit board with a terminal electrode formed in the non-active area NA of the display panel PN.When the gate driver GD is mounted in the GIP manner, and the data driver DD and the timing control unit TC transmit a signal to the display panel PN via a terminal electrode of the non-active area NA, an area of ​​the non-active area NA must be secured for arranging the gate driver GD and the contact electrode. This can increase the enclosure size.

[0067] On the other hand, when the gate driver GD is mounted in the active area AA in the GIA manner, and side lines SRL connecting the signal lines on the front surface of the display panel PN to the terminal electrodes on a rear surface of the display panel PN are formed to contact the flexible thin film and the printed circuit board on a rear surface of the display panel PN, the non-active area NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, the data driver DD, and the timing control unit TC are connected to the display panel PN as described above, a zero bezel in which there is substantially no bezel can be implemented, which will be explained with reference to Fig. 2A and Fig. 2B is described in more detail.

[0068] Fig. 2A is a partial cross-sectional view of a display device according to an embodiment of the disclosure. Fig. 2B is a perspective view of a tile display device according to an embodiment of the disclosure.

[0069] In the non-active area NA of the display panel PN, a plurality of terminal electrodes are arranged for transmitting various signals to the plurality of sub-pixels SP. For example, in a non-active area NA on the front surface of the display panel PN, an upper terminal pad TPAD is arranged, which transmits a signal to the plurality of sub-pixels SP. In a non-active area NA on the rear surface of the display panel PN, a lower terminal pad BPAD is arranged, which is electrically connected to a drive component such as a flexible thin film and the printed circuit board.

[0070] In this case, although not illustrated in the drawing, various signal lines connected to the plurality of sub-pixels SP, such as a scanning line SL or a data line DL, extend from the active area AA to the non-active area NA to be electrically connected to the upper pad TPAD.

[0071] The side lines SRL are arranged along a side surface of the display panel PN. The side lines SRL can electrically connect the upper pad TPAD of the front surface of the display panel PN and the lower pad BPAD on the back surface of the display panel PN. Therefore, a signal can be transmitted from a driving component on the back surface of the display panel PN to the plurality of sub-pixels SP via the lower pad BPAD, the side lines SRL, and the upper pad TPAD. Accordingly, a signal transmission path is formed from the front surface of the display panel PN to the side surface and the back surface to minimize an area of ​​the non-active area NA of the display panel PN.

[0072] With reference to Fig. 2B, a tile display device TD having a large screen size can be implemented by connecting multiple display devices 100. At this time, as shown in Fig. 2A, when the tile display device TD is implemented using a display device 100 with a minimized bezel, a seam area in which no image is displayed between the display devices 100 is minimized, so that a display device quality can be improved.

[0073] For example, the plurality of subpixels SP may form one pixel PX, and a distance D1 between an outer pixel PX of one display device 100 and an outer pixel PX of another display device 100 adjacent to the one display device may be implemented equal to a distance D1 between pixels PX in the one display device 100. Accordingly, the distance between pixels PX between the display devices 100 is configured to be constant to minimize the seam area.

[0074] However, Fig. 2A and Fig. 2B, such that the display device 100 according to the embodiment of the disclosure may be, but is not limited to, a general display device with a bezel.

[0075] Meanwhile, the display panel PN may include a first substrate and a second substrate.

[0076] In the following, the first substrate and the second substrate are described with reference to Fig. 3 and Fig. 4 described in detail.

[0077] Fig. 3 is an enlarged plan view of a first substrate of a display device according to an embodiment of the disclosure.

[0078] First, the display panel PN includes a first substrate 110. The first substrate 110 is a substrate that supports components arranged above the display device 100 and may be an insulating substrate. A plurality of pixels PX are formed on the first substrate 110 to display images. For example, the first substrate 110 may be formed of glass, resin, or the like. Further, the first substrate 110 may include polymer or plastic. In certain embodiments, the first substrate 110 may be formed of a plastic material having flexibility.

[0079] With reference to Fig. 3, a plurality of pixel areas UPA, a plurality of gate drive areas GA, and a plurality of upper contact areas are arranged in the first substrate 110. Among these, the plurality of pixel areas UPA and the plurality of gate drive areas GA may be included in the active area AA of the display panel PN.

[0080] First, the multiple pixel areas UPA are areas in which the multiple pixels PX are arranged. The multiple pixel areas UPA can be arranged to form multiple rows and multiple columns. Each of the multiple pixels PX arranged in the multiple pixel areas UPA contains multiple sub-pixels SP. Each of the multiple sub-pixels SP contains a light-emitting diode LED and a pixel circuit for independently radiating light.

[0081] The display panel PN includes each of a plurality of pixels PX, which are formed by a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light-emitting diode LED and a pixel circuit for independently radiating light. A pixel may include one or more first sub-pixels, one or more second sub-pixels, and one or more third sub-pixels. For example, a pixel may include two first sub-pixels, two second sub-pixels, and two third sub-pixels. Currently, the first sub-pixel may be a red sub-pixel, the second sub-pixel may be a green sub-pixel, and the third sub-pixel may be a blue sub-pixel, but is not limited to these.

[0082] The plurality of gate drive areas GA are areas in which gate drivers GD or parts thereof are arranged. The gate driver GD can be mounted in the active area AA in a gate-in-active-area (GIA) manner. For example, the gate drive area GA can be formed in a row direction and / or a column direction between the plurality of pixel areas UPA. The gate driver GD formed in the gate drive area GA can supply the scanning signal to the plurality of scanning lines SL.

[0083] The gate driver GD, arranged in the gate drive area GA, may include a circuit for outputting a scanning signal. For example, the gate driver GD may include a plurality of transistors and / or capacitors. Here, the active layers of the plurality of transistors may be formed of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. For example, the active layers of the plurality of transistors may be formed of the same material or different materials. Furthermore, the active layers of the transistors of the gate driver may be formed of the same material as the active layers of different transistors of the pixel circuit, or may be formed of different materials.

[0084] The plurality of upper contact surfaces includes a first upper contact surface TPA1 located at a first edge EG1 of the display panel PN, and a second upper contact surface TPA2 of the display panel PN located at a second edge EG2 of the display panel PN. Therefore, the first upper contact surface TPA1 is located at an upper edge EG1 of the panel, whereas the second upper contact surface TPA2 is located at the lower edge EG2.

[0085] The first upper contact area TPA1 and the second upper contact area TPA2 are areas in which a plurality of upper connection areas TPAD arranged on the first substrate 110 are arranged. The plurality of upper connection areas TPAD can transmit various signals to various wiring lines extending in a column direction in the active area AA.

[0086] A plurality of first upper pads TPAD1 may be arranged in the first upper contact pad TPA1. The plurality of first upper pads TPAD1 may include upper pads TPAD to which various signals are applied. For example, the first upper pad TPAD1 may include an upper data pad TDP that transmits a data voltage to an upper data line TDL, an upper gate contact TGP that transmits a clock signal, a start signal, a low gate voltage, a high gate voltage, and the like for driving the gate driver GD to the gate driver GD, and an upper high-potential power pad TVP1 that transmits a high-potential supply voltage to the upper high-potential power supply line TVL1.

[0087] A plurality of second upper pads TPAD2 may be arranged in the second upper contact pad TPA2. At this time, the plurality of second upper pads TPAD2 may be different from the plurality of first upper pads TPAD1. For example, the plurality of second upper pads TPAD2 may include an upper low-potential power pad TVP2 that transmits a low-potential supply voltage to the plurality of upper low-potential power supply lines TVL2.

[0088] At this time, the plurality of upper pads TPAD may be formed to have different sizes, respectively. For example, the plurality of upper data pads TDP, which are one-to-one connected to the plurality of upper data lines TDL of the plurality of first upper pads TPAD1, may have a smaller width, and the upper high-potential power pad TVP1 and the upper gate contact TGP may have larger widths. Furthermore, the upper low-potential power pad TVP2, which is the plurality of second upper pads TPAD2, may also have a larger width than the plurality of upper data pads TDP, and the upper low-potential power pads TVP2 may each have different widths.However, the widths of the upper data pad TDP, the upper gate contact TGP, the upper high-potential power pad TVP1 and the upper low-potential power pad TVP2 shown in . Fig. 3, illustratively, such that the upper pad TPAD can be configured in various sizes, but is not limited thereto.

[0089] Meanwhile, in order to reduce the bezel area of ​​the display panel PN, an edge of the display panel PN may be cut to be removed. The plurality of pixels PX, the plurality of wiring lines, and the plurality of upper pads TPAD are formed on an initial first substrate 110i, and an edge portion of the initial first substrate 110i is grounded to reduce the bezel area. During the grinding process, a portion of the initial first substrate 110i is removed to form a first substrate 110 with a smaller size. At this time, parts of the plurality of upper pads TPAD and wiring lines located at the edge of the first substrate 110 may be removed. Accordingly, only a part of the plurality of upper pads TPAD may remain on the first substrate 110.

[0090] A plurality of upper data lines TDL extending from the plurality of upper pads TPAD in the column direction are arranged in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. The plurality of upper data lines TDL may extend from the plurality of upper data pads TDP of the first upper pad TPA1 to the plurality of pixel areas UPA. The plurality of upper data lines TDL extend in a column direction and may be arranged to overlap with the plurality of pixel areas UPA. Therefore, the plurality of upper data lines TDL may transmit the data voltage to the pixel circuit of each of the plurality of sub-pixels SP.

[0091] The plurality of upper high-potential power supply lines TVL1, which extend in the column direction, are arranged in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. Some of the plurality of upper high-potential power supply lines TVL1 extend from the upper high-potential power connection pad TVP1 of the first upper contact pad TPA1 to the plurality of pixel areas UPA to transmit the high-potential power supply voltage to the light-emitting diode LED of each of the plurality of sub-pixels SP. The other of the plurality of upper high-potential power supply lines TVL1 may be electrically connected to the other upper high-potential power supply line TVL1 by means of an upper auxiliary high-potential power supply line TAVL1, which will be described below. Fig. 3, for the convenience of description, although it is illustrated that one upper high-potential power supply line TVL1 and one upper high-potential power pad TVP1 are arranged, a plurality of upper high-potential power supply lines TVL1 and upper high-potential power pad TVP1 may be arranged.

[0092] The plurality of upper low-potential power supply lines TVL2 extending in the column direction are arranged in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. At least a portion of the plurality of upper low-potential power supply lines TVL2 extends from the upper low-potential power pad TVP2 of the second upper contact pad TPA2 to the plurality of pixel areas UPA to transmit the low-potential power supply voltage to the pixel circuit of each of the plurality of sub-pixels SP. The other of the plurality of upper low-potential power supply lines TVL2 may be electrically connected to the other upper low-potential power supply line TVL2 via an auxiliary upper low-potential power supply line TAVL2, which will be described below.

[0093] The plurality of upper scan lines TSL extending in the row direction are arranged in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. The plurality of upper scan lines TSL extend in the row direction and may be arranged across the plurality of pixel areas UPA and the plurality of gate drive areas GA. The plurality of upper scan lines TSL may transmit the scan signal from the gate driver GD to the pixel circuits of the plurality of sub-pixels SP.

[0094] The plurality of upper auxiliary high-potential power supply lines TAVL1 extending in the row direction are arranged in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. The plurality of upper auxiliary high-potential power supply lines TAVL1 may be arranged in an area between the plurality of pixel areas UPA. The plurality of upper auxiliary high-potential power supply lines TAVL1 extending in the row direction are electrically connected to the plurality of upper high-potential power supply lines TVL1 extending in the column direction through a contact hole to form a mesh structure. Therefore, the plurality of upper auxiliary high-potential power supply lines TAVL1 and the plurality of upper high-potential power supply lines TVL1 are configured to form a mesh structure to minimize voltage drop and voltage deviation.

[0095] The plurality of upper auxiliary low-potential power supply lines TAVL2 extending in the row direction are arranged in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. The plurality of upper auxiliary low-potential power supply lines TAVL2 may be arranged in an area between the plurality of pixel areas UPA. The plurality of upper auxiliary low-potential power supply lines TAVL2 extending in the row direction are electrically connected to the plurality of upper low-potential power supply lines TVL2 extending in the column direction through a contact hole to form a mesh structure. Therefore, the plurality of upper auxiliary low-potential power supply lines TAVL2 and the plurality of upper low-potential power supply lines TVL2 are configured to form a mesh structure to reduce wiring resistance and minimize voltage deviation.

[0096] With reference to Fig. 3, the plurality of upper gate drive lines TGVL extending in the row direction and the column direction are arranged in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. Some of the plurality of upper gate drive lines TGVL extend from the upper gate contact TGP of the first upper contact pad TPA1 to the gate drive pad GA to transmit a signal to the gate driver GD. The other of the plurality of upper gate drive lines TGVL extend in the row direction and can transmit the signal to the gate drivers GD of the plurality of gate drive pads GA. Therefore, various signals are transmitted from the upper gate drive line TGVL to the gate driver GD to drive the gate driver GD.

[0097] The plurality of upper gate drive lines TGVL may include wiring lines that transmit a clock signal, a start signal, a high gate voltage, and a low gate voltage to the gate driver GD. Therefore, various signals are transmitted from the upper gate drive line TGVL to the gate driver GD to drive the gate driver GD.

[0098] For example, the plurality of upper gate drive lines TGVL may include a gate power supply line that transmits a supply voltage to the gate driver GD of the gate drive area GA. The plurality of gate power supply lines may include a first gate power supply line that transmits a high gate voltage to the gate driver GD and a second gate power supply line that transmits a low gate voltage to the gate driver GD.

[0099] A plurality of alignment keys AK1 and AK2 are arranged in an area between the plurality of pixel areas UPA in the display panel PN. The plurality of alignment keys AK1 and AK2 are used for alignment during the manufacturing process of the display panel PN. The plurality of alignment keys AK1 and AK2 include a first alignment key AK1 and a second alignment key AK2.

[0100] The first alignment key AK1 can be arranged in the gate drive area GA of the areas between the plurality of pixel areas UPA. The first alignment key AK1 can be used to examine an alignment position of the plurality of light-emitting diodes (LEDs). For example, the first alignment key AK1 can have a cross shape, but is not limited thereto.

[0101] The second alignment key AK2 may be arranged to overlap with the upper high-potential power supply line TVL1 of the areas between the plurality of pixel areas UPA. A hole overlapping the second alignment key AK2 is formed in the upper high-potential power supply line TVL1 to divide the second alignment key AK2 and the upper high-potential power supply line TVL1. The second alignment key AK2 may be used to align the display panel PN and a donor. The display panel PN and the donor are aligned using the second alignment key AK2, and the plurality of light-emitting diodes (LEDs) of the donor may be transferred to the display panel PN. For example, the second alignment key AK2 may have a circular ring shape, but is not limited thereto.

[0102] Fig. 4 is an enlarged plan view of a second substrate of a display device according to an embodiment of the disclosure.

[0103] First, the display panel PN includes a second substrate 130. The second substrate 130 is a substrate that supports components arranged beneath the display device 100 and may be an insulating substrate. For example, a plurality of flexible thin layers of COF and printed circuit boards (PCBs) that transmit signals to the plurality of sub-pixels SP may be arranged beneath the second substrate 130.

[0104] The second substrate 130 may be formed from glass, resin, or the like. Furthermore, the second substrate 130 may contain polymer or plastic. The second substrate 130 may be formed from the same material as the first substrate 110. In certain embodiments, the second substrate 130 may be formed from a plastic material that exhibits flexibility.

[0105] With reference to Fig. 4, the second substrate 130 may include a plurality of bottom contact pads, a COF contact pad BPA3, and a plurality of conductive pads.

[0106] The plurality of lower contact pads are areas in which a plurality of lower connection pads BPAD are arranged, which are arranged below the second substrate 130. For example, the plurality of lower contact pads may include a first lower contact pad BPA1 arranged in a first edge EG1 of the display panel PN, and a second lower contact pad BPA2 arranged in a second edge EG2. The plurality of lower connection pads BPAD may transmit different signals to different wiring lines arranged in the plurality of lower wiring pads.

[0107] With reference to Fig. 4, the plurality of first lower pads BPAD1 may be arranged in the first lower contact pad BPA1. The plurality of first lower pads BPAD1 may include a plurality of lower pads BPAD to which various signals are applied. For example, the plurality of first lower pads BPAD1 may include a lower data pad BDP, a lower gate contact BGP, and a lower high-potential power pad BVP1.

[0108] Meanwhile, each of the plurality of lower pads BPAD may be formed to have different sizes. For example, the plurality of first lower pads BPAD1 may each have different sizes. Specifically, the plurality of lower data pads BDP uniquely connected to the plurality of lower data lines BDL may have a narrower width, and the lower high-potential power pad BVP1 and the lower gate contact BGP may have a larger width. However, the widths of the lower data pad BDP, the lower gate contact BGP, and the lower high-potential power pad BVP1 formed in Fig. 4 are illustrative and the sizes of the lower pads BPAD may vary, but are not limited thereto.

[0109] A plurality of second lower pads BPAD2 may be arranged in the second lower contact pad BPA2. At this time, the plurality of second lower pads BPAD2 may be lower pads BPAD that are different from the plurality of first lower pads BPAD1. For example, the plurality of second lower pads BPAD2 may include a lower low-potential power pad BVP2 that transmits a low-potential supply voltage to the lower low-potential power supply line BVL2.

[0110] Meanwhile, the plurality of second lower pads BPAD2 may each have different sizes. For example, each of the plurality of second lower pads BPAD2 may have a smaller width than the plurality of lower data pads BDP of the plurality of first lower pads BPAD1, but is not limited thereto. Furthermore, the width of the lower low-potential power pad BVP2 shown in Fig. 4 is illustrative and the sizes of the lower pads BPAD may vary, but are not limited thereto.

[0111] Meanwhile, in order to reduce the bezel area of ​​the display panel PN, an edge of the display panel PN may be cut to be removed. The plurality of pixels PX, the plurality of wiring lines, and the plurality of lower pads BPAD are formed on an initial second substrate 130i, and an edge portion of the initial second substrate 130i is grounded together with the initial first substrate 110i to reduce the bezel area. During the grinding process, a portion of the initial second substrate 130i is removed to form a second substrate 130 with a smaller size. At this time, parts of the plurality of lower pads BPAD and wiring lines arranged in the edge of the second substrate 130 may be removed. Accordingly, only a portion of the plurality of lower pads BPAD may remain on a second substrate 130.

[0112] A COF contact surface BPA3 is arranged between the first lower contact surface BPA1 and the second lower contact surface BPA2. For example, the COF contact surface BPA3 may be arranged between the first lower contact surface BPA1 and the second lower contact surface BPA2, such that it is adjacent to the first lower contact surface BPA1, but is not limited thereto.

[0113] Several COF connection areas BPAD3 are arranged in the COF contact area BPA3.

[0114] The multiple COF pads BPAD3 are connected to multiple lower leads arranged in multiple lower lead pads, and can electrically connect the multiple lower leads and the multiple flexible thin layers COF and printed circuit boards PCB.

[0115] For example, the plurality of lower data interconnect lines BDL are connected to the plurality of COF pads BPAD3, and the plurality of COF pads BPAD3 may be electrically connected to the plurality of flexible COF thin layers. Accordingly, the plurality of COF pads BPAD3 may electrically connect the plurality of flexible COF thin layers and the plurality of lower data interconnect lines BDL.

[0116] The multiple COF pads BPAD3 are described with reference to Fig. 8 described in detail.

[0117] Meanwhile, the multiple flexible thin layers COF and printed circuit boards PCB can be arranged in the COF contact area BPA3.

[0118] The plurality of flexible COF thin films may be electrically connected to the plurality of COF pads BPAD3. The flexible COF thin film is a thin film in which various components are arranged on a thin base layer having deformability to deliver a signal to the sub-pixel SP and a drive component, and may be electrically connected to the display panel PN.

[0119] A drive IC such as a gate driver IC or a data driver IC may be arranged on the multiple flexible COF thin films. The drive IC is a component that processes data for displaying images and a drive signal for processing the data. The drive IC may be arranged in a chip-on-glass (COG) manner, a chip-on-thin-film (COF) manner, or a tape carrier assembly (TCP) manner depending on a mounting method. However, for the sake of simplicity, the drive IC is described as being mounted on the multiple flexible COF thin films by a chip-on-thin-film technique, but it is not limited thereto.

[0120] The printed circuit board (PCB) is electrically connected to several flexible thin layers of COF. The printed circuit board (PCB) is a component that delivers signals to the control IC. Various components can be arranged on the printed circuit board (PCB) to deliver various signals to the control IC.

[0121] Meanwhile, although in Fig. 4 illustrates that three flexible thin layers COF and one printed circuit board PCB are provided, the number of the plurality of flexible thin layers COF and printed circuit board PCB varies depending on a design, but is not limited thereto.

[0122] The plurality of lower conductive areas are areas in which a plurality of wiring lines connected to the plurality of lower terminal pads BPAD are arranged. The plurality of lower conductive areas may include a first lower conductive area BLA1 and a second lower conductive area BLA2.

[0123] With reference to Fig. 4, the first lower conduction surface BLA1 and the second lower conduction surface BLA2 are arranged between the first lower contact surface BPA1 and the second lower contact surface BPA2. The first lower conduction surface BLA1 and the second lower conduction surface BLA2 may be arranged such that they are spaced apart from each other with the COF contact surface BPA3 therebetween. For example, the first lower conduction surface BLA1 may be arranged between the first lower contact surface BPA1 and the COF contact surface BPA3, and the second lower conduction surface BLA2 may be arranged between the second lower contact surface BPA2 and the COF contact surface BPA3. Therefore, the first lower contact surface BPA1, the first lower conduction surface BLA1, the COF contact surface BPA3, the second lower conduction surface BLA2, and the second lower contact surface BPA2 may be arranged sequentially from the first edge EG1 to the second edge EG2 of the display panel PN.

[0124] In the first lower wiring area BLA1, the lower data connection line BDL, the lower gate connection line, the lower high-potential power supply line BVL1 and the plurality of lower auxiliary high-potential power supply lines BAVL1 may be arranged.

[0125] For example, a plurality of lower data connection lines BDL extending from the lower data pad BDP in the column direction are arranged in the first lower connection area BLA1 of the back surface of the second substrate 130. The plurality of lower data connection lines BDL extend to the COF pad BPA3 to connect to the plurality of flexible thin layers COF and the printed circuit board PCB. Furthermore, the plurality of lower data connection lines BDL may be arranged to overlap with the lower high-potential power supply line BVL1.

[0126] A plurality of lower gate interconnect lines extending from the lower gate contact BGP in the column direction are arranged in the first lower interconnect area BLA1 of the back surface of the second substrate 130. The plurality of lower gate interconnect lines extend to the COF contact area BPA3 to be connected to the plurality of COF pads BPAD3.

[0127] A plurality of lower high-potential power interconnection lines extending from the plurality of lower high-potential power pads BVP1 in the column direction are arranged in the first lower wiring area BLA1 of the back surface of the second substrate 130.

[0128] Each of the plurality of lower high-potential power connection lines extends in the column direction to be connected to the lower high-potential power supply line BVL1.

[0129] The lower high-potential power supply line BVL1 may have a longitudinal axis in the row direction. For example, a width of the lower high-potential power supply line BVL1 may correspond to a width of the first lower contact pad BPA1. For example, a width of the lower high-potential power supply line BVL1 may correspond to a distance between outermost first lower pads BPAD1 among the plurality of first lower pads BPAD1. Therefore, the lower high-potential power supply line BVL1 may be in contact with each of the plurality of lower high-potential power connection lines extending in the column direction.

[0130] A plurality of lower auxiliary high-potential power supply lines BAVL1 may be arranged in the first lower line area BLA1. The plurality of lower auxiliary high-potential power supply lines BAVL1 are arranged to overlap with the lower high-potential power supply line BVL1.

[0131] Meanwhile, the closer the lower low-potential power supply line BVL2 is to the lower low-potential power supply line, the wider the width of each of the plurality of lower auxiliary high-potential power supply lines BAVL1 becomes. For example, a planar shape of the plurality of lower auxiliary high-potential power supply lines BAVL1 may be triangular.

[0132] The plurality of lower auxiliary high-potential power supply lines BAVL1 are arranged such that they are spaced apart from each other, between the flexible thin layers COF, and may be arranged alternately with the flexible thin layer COF in the row direction.

[0133] The plurality of lower auxiliary high-potential power supply lines BAVL1 and the plurality of lower data connection lines BDL are described below with reference to Fig. 9 described in detail.

[0134] A plurality of lower low-potential power interconnection lines extending from the plurality of second lower pads BPAD2 in the column direction are arranged in the second lower interconnection area BLA2 of the back surface of the second substrate 130.

[0135] Each of the plurality of lower low-potential power connection lines runs in the column direction to be connected to the lower low-potential power supply line BVL2.

[0136] The lower low-potential power supply line BVL2 may have a longitudinal axis in the row direction. For example, a width of the lower low-potential power supply line BVL2 may correspond to a width of the second lower contact pad BPA2. For example, a width of the lower low-potential power supply line BVL2 may correspond to a distance between outermost second lower pads BPAD2 among the plurality of second lower pads BPAD2. Therefore, the lower low-potential power supply line BVL2 may be in contact with each of the plurality of lower low-potential power connection lines extending in the column direction.

[0137] Meanwhile, each of the lower data connection line BDL, the lower gate connection line, and the lower high-potential power connection line arranged in the first lower connection area BLA1 of the second substrate 130 extends to the plurality of first lower connection areas BPAD1 and may be connected to the plurality of first upper connection areas TPAD1 arranged on the first substrate 110 via first side lines to be described below.

[0138] The lower low-potential power connection lines arranged in the second lower conductive area BLA2 of the second substrate 130 extend to the plurality of second lower pads BPAD2 and may be connected to the plurality of second upper pads TPAD2 arranged on the first substrate 110 via second side lines to be described below.

[0139] The side lines SRL are described below with reference to Fig. 6 described in detail.

[0140] In the following, the plurality of sub-pixels SP of the pixel area UPA are described with reference to Fig. 5 described in more detail.

[0141] Fig. 5 is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the disclosure. In each of the plurality of sub-pixels SP of the display panel PN of the display device 100 according to the embodiment of the disclosure, a first substrate 110, a second substrate 130, a bonding layer BL, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarization layer 115, an adhesive layer 116, a second planarization layer 117, a third planarization layer 118, a passivation layer 119, a driving transistor DT, a light-emitting diode LED, a plurality of reflective electrodes RE1 and RE2, a plurality of connecting electrodes CE1 and CE2, a light-shielding layer LS, and an auxiliary electrode LE are arranged.

[0142] First, the first substrate 110 is a component for supporting various components included in the display device 100 and may be formed from an insulating material. For example, the first substrate 110 may be formed from glass or resin. Further, the first substrate 110 may be configured to contain polymers or plastics, or may be formed from a material that has flexibility.

[0143] The light-shielding layer LS is disposed in each of the plurality of sub-pixels SP on the first substrate 110. The light-shielding layer LS blocks light incident on an active layer ACT of the drive transistor DT, which will be described below, under the first substrate 110. Light incident on the active layer ACT of the drive transistor DT is blocked by the light-shielding layer LS to minimize leakage current. For example, the light-shielding layer LS may be formed of molybdenum (Mo), but is not limited thereto.

[0144] The buffer layer 111 is disposed on the first substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or contaminants through the first substrate 110. For example, the buffer layer 111 can be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 can be omitted depending on a type of the first substrate 110 or a type of transistor, but is not limited thereto.

[0145] The drive transistor DT is arranged on the buffer layer 111. The drive transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0146] The active layer ACT is arranged on the buffer layer 111. The active layer ACT may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0147] The gate insulation layer 112 is disposed on the active layer ACT. The gate insulation layer 112 is an insulation layer that insulates the active layer ACT from the gate electrode GE and may be configured by, but is not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0148] The gate electrode GE is arranged on the gate insulation layer 112. The gate electrode GE may be configured by a conductor material such as, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0149] The first insulating interlayer 113 is arranged at the gate electrode GE. A contact hole is formed in the first insulating interlayer 113, through which the source electrode SE and the drain electrode DE are each connected to the active layer ACT. The first insulating interlayer 113 is an insulating layer that protects components beneath the first insulating interlayer 113 and may be configured by, but is not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0150] The capacitor electrode C2 is arranged on the first insulating interlayer 113. The capacitor electrode C2 may be arranged such that it overlaps the gate electrode GE with the first insulating interlayer 113 therebetween.

[0151] The second insulating interlayer 114 is arranged on the capacitor electrode C2. A contact hole is formed in the second insulating interlayer 114, through which the source electrode SE and the drain electrode DE are each connected to the active layer ACT. The second insulating interlayer 114 is an insulating layer that protects components beneath the second insulating interlayer 114 and may be configured by, but is not limited to, a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx.

[0152] The source electrode SE and the drain electrode DE, which are electrically connected to the active layer ACT, are arranged on the second insulating interlayer 114. The source electrode SE and the drain electrode DE may be configured by a conductor material such as, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0153] Meanwhile, in the present disclosure, it is described that the first interlayer insulating layer 113 and the second interlayer insulating layer 114, that is, multiple insulating layers, are disposed between the gate electrode GE and the source electrode SE and the drain electrode DE. However, only one insulating layer may be disposed between the gate electrode GE and the source electrode SE and the drain electrode DE.

[0154] As illustrated in the drawings, when multiple insulating layers such as the first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed between the gate electrode GE and the source electrode SE and the drain electrode DE, an electrode may further be formed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The additionally formed electrode may form a capacitor with the further configuration disposed below the first interlayer insulating layer 113 or above the second interlayer insulating layer 114.

[0155] The auxiliary electrode LE is arranged on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS under the buffer layer 111 to one of the source electrode SE and the drain electrode DE on the second interlayer insulating layer 114. For example, the light-shielding layer LS is electrically connected to one of the source electrode SE and the drain electrode DE via the auxiliary electrode LE so as not to operate as a floating gate. Therefore, the fluctuation of a threshold voltage of the driving transistor DT caused by the light-shielding layer LS being set to a floating potential can be minimized. Although the light-shielding layer LS is connected to the source electrode SE in the drawing, the light-shielding layer LS may also be connected to the drain electrode DE, but is not limited thereto.

[0156] The first planarization layer 115 is disposed on the drive transistor DT. The first planarization layer 115 may planarize an upper portion of the first substrate 110 on which the drive transistor DT is disposed. The first planarization layer 115 may be configured as a single layer or a double layer and may be formed, for example, from photoresist or an organic acrylic material, but is not limited thereto.

[0157] A plurality of reflective electrodes RE1 and RE2, spaced apart from each other, are arranged on the first planarization layer 115. The plurality of reflective electrodes RE1 and RE2 electrically connect the LED to the power supply line and the drive transistor DT and can serve as a reflector that reflects light emitted from the LED to the upper portion of the LED. The plurality of reflective electrodes RE1 and RE2 are formed of a conductor material that has excellent reflective properties to reflect light emitted from the LED to the upper portion of the LED.

[0158] For example, the plurality of reflective electrodes RE1 and RE2 may be configured by a conductor material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0159] The plurality of reflective electrodes RE1 and RE2 include a first reflective electrode RE1 and a second reflective electrode RE2. The second reflective electrode RE2 can electrically connect the drive transistor DT and the light-emitting diode LED. The second reflective electrode RE2 can be connected to the source electrode SE or the drain electrode DE of the drive transistor DT through a contact hole formed in the first planarization layer 115. The second reflective electrode RE2 can be electrically connected to the first electrode 124 of the light-emitting diode LED through a second connection electrode CE2, which will be described below.

[0160] The first reflective electrode RE1 can electrically connect the power supply line and the light-emitting diode (LED). The first reflective electrode RE1 can be connected to the power supply line and can be electrically connected to the second electrode 125 of the light-emitting electrode (LED) through a first connection electrode CE1, which will be described below.

[0161] The passivation layer 119 is disposed on the plurality of reflective electrodes RE1 and RE2. A contact hole is disposed in the passivation layer 119, through which the plurality of reflective electrodes RE1 and RE2 are coupled to the first connection electrode CE1 and the second connection electrode CE2, respectively. The passivation layer 119 is an insulating layer that protects components beneath the passivation layer 119 and may be configured by, but is not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0162] The adhesive layer 116 is disposed on the plurality of reflective electrodes RE. The adhesive layer 116 is coated on the front surface of the first substrate 110 to fix the light-emitting diode (LED) disposed on the adhesive layer 116. For example, the adhesive layer 116 can be selected from, but is not limited to, an adhesive polymer, epoxy resin, UV resin, polyimide, acrylate, urethane, and polydimethylsiloxane (PDMS).

[0163] The plurality of light-emitting diodes (LEDs) are arranged in each of the plurality of sub-pixels SP on the adhesive layer 116. The plurality of light-emitting diodes (LEDs) are elements that emit light through a current and may include a light-emitting diode (LED) that emits red light, green light, and blue light, and may implement various colored light including white through a combination thereof. For example, the plurality of light-emitting diodes (LEDs) may be, but are not limited to, a light-emitting diode (LED) or a micro-LED.

[0164] The plurality of light-emitting diodes (LEDs) may include a first light-emitting diode, a second light-emitting diode, and a third light-emitting diode. The first light-emitting diode may be arranged in the first sub-pixel, the second light-emitting diode may be arranged in the second sub-pixel, and the third light-emitting diode may be arranged in the third sub-pixel. For example, the first light-emitting diode may be a red light-emitting diode, the second light-emitting diode may be a green light-emitting diode, and the third light-emitting diode may be a blue light-emitting diode.

[0165] Each of the plurality of light-emitting diodes (LEDs) includes a first semiconductor layer 121, an emission layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation layer 126.

[0166] The first semiconductor layer 121 is disposed on the adhesive layer 116, and the second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping n-type and p-type impurities into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers doped with n-type and p-type impurities into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (magnesium), zinc (Zn), beryllium (Be), and the like, and the n-type impurity may be silicon (Si), germanium, tin (Sn), and the like, but are not limited thereto.

[0167] The emission layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. Holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 are supplied to the emission layer 122 to emit light. The emission layer 122 may be formed by a single layer or a multiple quantum well (MQW) structure and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0168] The first electrode 124 is arranged on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the drive transistor DT and the first semiconductor layer 121. The first electrode 124 may be arranged on a top surface of the first semiconductor layer 121 exposed from the emission layer 122 and the second semiconductor layer 123. The first electrode 124 may be configured by a conductor material, for example, a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductor material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0169] The second electrode 125 is arranged on the second semiconductor layer 123. The second electrode 125 may be arranged on the top surface of the second semiconductor layer 123. The second electrode 125 is an electrode that electrically connects the power supply line and the second semiconductor layer 123. The second electrode 125 may be configured by a conductor material, for example, a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductor material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0170] Next, the encapsulation layer 126 is disposed, which encloses the first semiconductor layer 121, the emission layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation layer 126 is formed from an insulating material to protect the first semiconductor layer 121, the emission layer 122, and the second semiconductor layer 123. A contact hole is formed in the encapsulation layer 126, exposing the first electrode 124 and the second electrode 125, for electrically connecting a first connection electrode CE1 and a second connection electrode CE2 to the first electrode 124 and the second electrode 125.

[0171] The second planarization layer 117 and the third planarization layer 118 are arranged on the adhesive layer 116. The second planarization layer 117 overlaps with a portion of side surfaces of the plurality of light-emitting diodes (LEDs) to fix and protect the plurality of light-emitting diodes (LEDs). Specifically, although Fig. 5 illustrates that the encapsulation layer 126 encloses all side surfaces of the first semiconductor layer 121, a portion of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation layer 126. The light-emitting diode LED fabricated on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the process of separating the light-emitting diode LED from the wafer, a portion of the encapsulation layer 126 may crack. For example, a portion of the encapsulation layer 126 adjacent to a bottom edge of the first semiconductor layer 121 of the light-emitting diode LED cracks during the process of separating the light-emitting diode LED from the wafer. Accordingly, a portion of a bottom surface of the first semiconductor layer 121 may be exposed to the outside.However, although the lower portion of the light-emitting diode (LED) is exposed from the encapsulation layer 126, the first connection electrode CE1 and the second connection electrode CE2 are formed after the second planarization layer 117 covering the side surface of the first semiconductor layer 121 is formed. Accordingly, a short-circuit defect can be minimized.

[0172] Furthermore, the third planarization layer 118 is formed to cover upper portions of the second planarization layer 117 and the LED, and a contact hole exposing the first electrode 124 and the second electrode 125 of the LED may be formed. The first electrode 124 and the second electrode 125 of the LED are exposed from the third planarization layer 118, and the third planarization layer 118 is partially disposed in an area between the first electrode 124 and the second electrode 125 to minimize a short-circuit defect.

[0173] The second planarization layer 117 and the third planarization layer 118 may be configured as a single layer or a double layer, and may be formed from, for example, photoresist or an organic acrylic material, but are not limited thereto. Although the present disclosure describes the second planarization layer 117 and the third planarization layer 118 being arranged, the planarization layer may be formed as a single layer, but is not limited thereto.

[0174] A plurality of connection electrodes CE1 and CE2 are arranged on the third planarization layer 118. The plurality of connection electrodes CE1 and CE2 include a plurality of first connection electrodes CE1 and a second connection electrode CE2.

[0175] The second connection electrode CE2 is an electrode arranged in each of the plurality of sub-pixels SP to electrically connect the light-emitting diode LED and the driving transistor DT. The second connection electrode CE2 may be connected to the second reflective electrode RE2 through the contact hole formed in the third planarization layer 118, the second planarization layer 117, and the adhesive layer 116. Similarly, the second connection electrode CE2 may be electrically connected to one of the source electrode SE and the drain electrode DE of the driving transistor DT through the second reflective electrode RE2. The second connection electrode CE2 may be connected to the first electrode 124 of each of the plurality of light-emitting diodes LED through a contact hole formed in the third planarization layer 118.Accordingly, the second connection electrode CE2 can electrically connect the drive transistor DT to the first electrode 124 of the plurality of light-emitting diodes LED.

[0176] The first connection electrode CE1 is an electrode for electrically connecting the light-emitting diode (LED) and the power supply line. The first connection electrode CE1 can be connected to the first reflective electrode RE1 through the contact hole formed in the third planarization layer 118, the second planarization layer 117, and the adhesive layer 116. Furthermore, the first connection electrode CE1 can be electrically connected to the power supply line through the first reflective electrode RE1. The first connection electrode CE1 can be connected to the second electrode 125 of each of the plurality of light-emitting diodes (LED) through a contact hole formed in the third planarization layer 118. Accordingly, the first connection electrode CE1 can electrically connect the power supply line to the second electrode 125 of the plurality of light-emitting diodes (LED).

[0177] Bank BB is arranged at the first connection electrode CE1 and the second connection electrode CE2. Bank BB can be arranged such that it is spaced from the light-emitting diode LED at a predetermined interval.

[0178] The bank BB may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP and may be formed of, for example, but is not limited to, black resin.

[0179] The protective layer 190 is disposed on the first connection electrode CE1, the second connection electrode CE2, and the bank BB. The protective layer 190 is a layer for protecting a configuration below the protective layer 190 and may, for example, cover at least a portion of the light-emitting diode (LED). The protective layer 190 may be configured by, but is not limited to, a single layer or a double layer of a light-transmitting epoxy, silicon oxide (SiOx), or silicon nitride (SiNx).

[0180] Meanwhile, the second connection electrode CE2 connecting the drive transistor DT and the light-emitting diode LED arranged in each of the plurality of sub-pixels SP may be arranged individually in each of the plurality of sub-pixels SP.

[0181] In the following, several upper connection areas TPAD and several lower connection areas BPAD are described with reference to Fig. 6 to Fig. 7B together described in detail.

[0182] Fig. 6 is a cross-sectional view of a contact surface of a display device according to an embodiment of the present disclosure. Fig. 7A is a cross-sectional view of a top pad of a display device according to an embodiment of the present disclosure. Fig. 7B is a cross-sectional view of a bottom pad of a display device according to an embodiment of the present disclosure. In Fig. 7B, for convenience of illustration, it is illustrated that positions of the second substrate 130 and components under the second substrate 130 are reversed to place the second substrate 130 on the bottom side.

[0183] With reference to Fig. 6 and Fig. 7A, each of a plurality of upper pads TPAD may be formed by a plurality of conductive layers. For example, each of the plurality of upper pads TPAD may include a first upper contact electrode TPEa, a second upper contact electrode TPEb, and a third upper contact electrode TPEc. That is, each of the plurality of first upper pads TPAD1 and the plurality of second upper pads TPAD2 may include a first upper contact electrode TPEa, a second upper contact electrode TPEb, and a third upper contact electrode TPEc.

[0184] First, the first upper contact electrode TPEa is disposed on the second interlayer insulation layer 114. The first upper contact electrode TPEa may be formed of the same conductor material as the source electrode SE and the drain electrode DE, and may be configured, for example, by, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0185] The second upper contact electrode TPEb is arranged on the first upper contact electrode TPEa. The second upper contact electrode TPEb may be formed of the same conductor material as the plurality of reflective electrodes RE1 and RE2. The second upper contact electrode TPEb may be configured by a conductor material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0186] The third upper contact electrode TPEc is arranged on the second upper contact electrode TPEb. The third upper contact electrode TPEc may be formed of the same conductor material as the first connection electrode CE1 and the second connection electrode CE2, and may be, for example, a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0187] At this time, although not illustrated in the drawings, a portion of the plurality of upper contact electrodes of the upper pad TPAD is electrically connected to a plurality of wiring lines on the first substrate 110 to supply various signals to a plurality of wiring lines and a plurality of sub-pixels SP. For example, the first upper contact electrodes TPEa and / or the second upper contact electrodes TPEb of the upper pad TPAD are connected to the upper data line TDL, the upper high-potential power supply line TVL1, the upper low-potential power supply line TVL2, and the like arranged in the active area AA, respectively, to transmit signals thereto.

[0188] A first metal layer ML1, a second metal layer ML2, and a plurality of insulation layers may be disposed under the upper pad TPAD. The first metal layer ML1, the second metal layer ML2, and the plurality of insulation layers are disposed under the upper pad TPAD to adjust a step of the upper pad TPAD. For example, the buffer layer 111, the gate insulation layer 112, the first metal layer ML1, the first interlayer insulation layer 113, and the second metal layer ML2 may be sequentially disposed between the upper pad TPAD and the first substrate 110. The first metal layer ML1 may be formed of the same conductor material as the gate electrode GE, and the second metal layer ML2 may be formed of the same conductor material as a capacitor electrode C2.However, the plurality of insulation layers, the first metal layer ML1 and the second metal layer ML2 under the upper pad TPAD may be omitted depending on a design and are not limited thereto.

[0189] With reference to Fig. 5, a second substrate 130 is disposed beneath the first substrate 110. The second substrate 130 is a substrate that supports components disposed beneath the display device 100 and may be an insulating substrate. For example, the second substrate 130 may be formed from glass or resin. Further, the second substrate 130 may contain polymer or plastic. The second substrate 130 may be formed from the same material as the first substrate 110. In certain embodiments, the second substrate 130 may be formed from a plastic material that has flexibility.

[0190] With reference to Fig. 5, a contacting layer BL is arranged between the first substrate 110 and the second substrate 130. The contacting layer BL can be formed from a material hardened by various hardening methods to contact the first substrate 110 and the second substrate 130. The contacting layer BL can be arranged only in a partial area between the first substrate 110 and the second substrate 130 or can be arranged in the entire area therebetween.

[0191] A plurality of lower pads BPAD are arranged on the back surface of the second substrate 130. The plurality of lower pads BPAD are electrodes that transmit a signal from a drive component arranged on the back surface of the second substrate 130 to a plurality of side lines SRL, a plurality of upper pads TPAD, and a plurality of wiring lines on the first substrate 110. The plurality of lower pads BPAD are arranged in an end portion of the second substrate 130 in the non-active area NA to be electrically connected to the side lines SRL covering the end portion of the second substrate 130.

[0192] At this time, the plurality of lower pads BPAD may also be arranged to correspond to the plurality of lower pads. Each of the plurality of upper pads TPAD may be arranged to correspond to each of the plurality of lower pads BPAD, and then the upper pads TPAD and the lower pads BPAD, which overlap with each other through the side lines SRL, may be electrically connected.

[0193] Each of the plurality of lower pads BPAD includes a plurality of terminal electrodes. For example, each of the plurality of lower pads BPAD includes a first lower contact electrode BPEa, a second lower contact electrode BPEb, and a third lower contact electrode BPEc. That is, each of the plurality of first lower pads BPAD1 and the plurality of second lower pads BPAD2 includes a first lower contact electrode BPEa, a second lower contact electrode BPEb, and a third lower contact electrode BPEc.

[0194] In Fig. 7B, for convenience of illustration, it is illustrated that the lower pad BPAD is disposed on the second substrate 130, and the first lower contact electrode BPEa, the second lower contact electrode BPEb, and the third lower contact electrode BPEc are sequentially disposed above the second substrate 130.

[0195] However, the second substrate 130, which is in Fig. 7B, arranged upside down to be contacted with the first substrate 110. Therefore, in the contacted state of the second substrate 130 and the first substrate 110, as shown in Fig. 6, the plurality of lower pads BPAD may be arranged under the second substrate 130. Furthermore, the first lower contact electrode BPEa, the second lower contact electrode BPEb, and the third lower contact electrode BPEc may be arranged sequentially under the second substrate 130.

[0196] The following will be described based on a state in which the second substrate 130 is contacted with the first substrate 110, and it will be described that the first lower contact electrode BPEa, the second lower contact electrode BPEb, and the third lower contact electrode BPEc are sequentially arranged under the second substrate 130.

[0197] First, the first lower contact electrode BPEa is disposed under the second substrate 130. The first lower contact electrode BPEa may be configured by a conductor material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0198] The first insulation layer 131 is arranged under the first lower contact electrode BPEa. Referring to Fig. 7B, the first insulation layer 131 may cover a side surface of the first lower contact electrode BPEa. Meanwhile, the first insulation layer 131 may include an opening exposing a portion of a surface of the first lower contact electrode BPEa.

[0199] The first insulating layer 131 may be an inorganic insulating layer. For example, the first insulating layer 131 may be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0200] The second lower contact electrode BPEb is arranged under the first insulation layer 131. Referring to Fig. 7B, the second lower contact electrode BPEb may be in contact with a surface of the first lower contact electrode BPEa exposed through the opening of the first insulation layer 131.

[0201] The second lower contact electrode BPEb may be configured by a conductor material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0202] The third lower contact electrode BPEc is arranged below the second lower contact electrode BPEb. With reference to Fig. 7B, the third lower contact electrode BPEc may be in contact with a surface of the second lower contact electrode BPEb.

[0203] Meanwhile, with reference to Fig. 7B, the third lower contact electrode BPEc and the second lower contact electrode BPEb completely overlap. For example, an area in which the third lower contact electrode BPEc and the second substrate 130 overlap may be equal to an area in which the second lower contact electrode BPEb and the second substrate 130 overlap.

[0204] The third lower contact electrode BPEc may be formed of a material that hardly corrodes even when in contact with air or moisture to prevent corrosion of the second lower contact electrode BPEb. For example, the third lower contact electrode BPEc may be formed of a conductor material, such as, but not limited to, a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0205] The second insulating layer 132 is disposed beneath the third lower contact electrode BPEc. The second insulating layer 132 may be an inorganic insulating layer. For example, the second insulating layer 132 may be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0206] Meanwhile, the second insulation layer 132 may open a portion of the third lower contact electrode BPEc and may also cover a portion of an edge of the third lower contact electrode BPEc.

[0207] The third lower contact electrode BPEc exposed through the second insulation layer 132 may be in contact with side lines SRL to be described below.

[0208] Meanwhile, the first lower contact electrode BPEa, the second lower contact electrode BPEb, and the third lower contact electrode BPEc of the plurality of lower pads BPAD extend to the plurality of flexible COF thin films arranged on the back surface of the second substrate 130, which is electrically connected to the plurality of flexible COF thin films. The plurality of flexible COF thin films can supply various signals to the plurality of side lines SRL, the plurality of upper pads TPAD, the plurality of wiring lines, and the plurality of sub-pixels SP through the plurality of lower pads BPAD.Therefore, the signal from the driving component can be transmitted through the plurality of lower pads BPAD of the second substrate 130, the side lines SRL and the plurality of upper pads TPAD of the first substrate 110 to the signal line and the plurality of sub-pixels SP on the front surface of the first substrate 110.

[0209] With further reference to Fig. 6, the plurality of side lines SRL are arranged on the side surfaces of the first substrate 110 and the second substrate 130. The plurality of side lines SRL can electrically connect the plurality of upper pads TPAD formed on the top surface of the first substrate 110 and the plurality of lower pads BPAD formed on the back surface of the second substrate 130. For example, the plurality of side lines SRL can be arranged to enclose the side surface of the display device 100 while being in contact with the third upper contact electrode TPEc and the third lower contact electrode BPEc.Each of the plurality of side lines SRL may cover the plurality of upper pads TPAD in an end portion of the first substrate 110, a side surface of the first substrate 110, a side surface of the second substrate 130, and the plurality of lower pads BPAD in an end portion of the second substrate 130. For example, the plurality of side lines SRL may be formed by a contact printing method using a conductive ink containing silver (Ag), copper (Cu), molybdenum (Mo), and chromium (Cr).

[0210] The plurality of side lines SRL may include a plurality of first side lines and a plurality of second side lines. The plurality of first side lines are arranged to correspond to a first edge EG1 of the first substrate 110 and a first edge EG1 of the second substrate 130, and the plurality of second side lines are arranged to correspond to a second edge EG2 of the first substrate 110 and a second edge EG2 of the second substrate 130.

[0211] Therefore, among the plurality of side lines SRL, the plurality of first side lines may connect the plurality of first upper pads TPAD1 and the plurality of first lower pads BPAD1, and the plurality of second side lines may connect the plurality of second upper pads TPAD2 and the plurality of second lower pads BPAD2.

[0212] With reference to Fig. 6, a side insulation layer 150 is arranged to cover the plurality of side lines SRL. The side insulation layer 150 can be formed on the top surface of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 130, and the back surface of the second substrate 130 to cover the side lines SRL. The side insulation layer 150 can protect the plurality of side lines SRL.

[0213] Meanwhile, if the plurality of side lines SRL are formed of a metal material, there may be a problem that external light is reflected by the plurality of side lines SRL, or light emitted from the light-emitting diode LED is reflected by the plurality of side lines SRL in a way that is visible to the user. Therefore, the side insulation layer 150 is configured to include a black material to prevent reflection of the external light. For example, the side insulation layer 150 may be formed by a contact printing method using an insulation material containing a black material, such as a black ink.

[0214] A sealing member 160 is arranged covering the side insulation layer 150. The sealing member 160 is arranged to enclose the side surface of the display device 100 to protect the display device 100 from external influences, moisture, and oxygen. For example, the sealing member 160 can be formed from, but is not limited to, polyimide (PI), polyurethane, epoxy, or an acrylic-based insulation material.

[0215] A thin optical layer MF is disposed on the sealing member 160, the side insulation layer 150, and the protective layer 190. The thin optical layer MF may be a functional thin layer that implements higher image quality while protecting the display device 100. For example, the thin optical layer MF may include, but is not limited to, a scattering reduction thin layer, an anti-glare thin layer, a reflection reduction thin layer, a low-reflection thin layer, a controllable transmittance OLED thin layer, or a polarizer.

[0216] Meanwhile, although an adhesive layer may be further disposed between the thin optical layer MF and the sealing member 160 and the side insulation layer 150 and the protective layer 190, in Fig. 5 and Fig. 6, the adhesive layer is not illustrated for reasons of convenience. Alternatively, the thin optical layer MF may also be defined to include an adhesive layer disposed thereunder.

[0217] An edge of the sealing member 160 and an edge of the optical thin film MF may be arranged on the same line. The optical thin film MF, which has a larger size, is mounted over the first substrate 110 during the manufacturing process of the display device 100, and the sealing member 160 covering the side insulation layer 150 may be formed. After that, the laser is irradiated onto the sealing member 160 and the optical thin film MF so that it corresponds to an edge of the display device 100 to cut parts of the sealing member 160 and the optical thin film MF. Accordingly, the size of the display device 100 is adjusted by an outer peripheral cutting process of the sealing member 160 and the optical thin film MF, and the edge of the display device 100 may be formed to be flat.

[0218] Hereinafter, a COF contact surface BPA3 of the display device according to the embodiment of the disclosure will be described with reference to Fig. 8 described in more detail.

[0219] Fig. Figure 8 is a cross-sectional view of a second substrate taken along line AA' of Fig. 4 was taken. Fig. Figure 8 is a cross-sectional view of a COF contact surface BPA3. In Fig. In Figure 8, the flexible thin layer COF is not shown for simplicity, but the COF pad BPAD3 is shown. Fig. 8, for convenience of illustration, it is illustrated that the positions of the second substrate 130 and the COF pad BPAD3 are reversed, and the second substrate 130 is arranged on the bottom side in the drawing.

[0220] With reference to Fig. 8, several COF connection areas BPAD3 are arranged in the COF contact area BPA3.

[0221] Each of the plurality of COF pads BPAD3 may be formed by multiple conductive layers. For example, each of the plurality of COF pads BPAD3 may include a first COF contact electrode BPE3a, a second COF contact electrode BPE3b, and a third COF contact electrode BPE3c.

[0222] In Fig. 8, for convenience of illustration, it is illustrated that the COF pad BPAD3 is disposed on the second substrate 130, and the first COF contact electrode BPE3a, the second COF contact electrode BPE3b, and the third COF contact electrode BPE3c are sequentially disposed above the second substrate 130.

[0223] However, the second substrate 130, which is in Fig. 8, arranged upside down to be contacted with the first substrate 110. Therefore, in the contacted state of the second substrate 130 and the first substrate 110, the plurality of COF pads BPAD3 may be arranged under the second substrate 130. Further, the first COF contact electrode BPE3a, the second COF contact electrode BPE3b, and the third COF contact electrode BPE3c may be arranged sequentially under the second substrate 130.

[0224] The following will be described based on a state in which the second substrate 130 is contacted with the first substrate 110, and it will be described that the first COF contact electrode BPE3a, the second COF contact electrode BPE3b, and the third COF contact electrode BPE3c are sequentially arranged under the second substrate 130.

[0225] The first COF contact electrode BPE3a is arranged under the second substrate 130.

[0226] The first COF contact electrode BPE3a may be formed of the same material as the first lower contact electrode BPEa. For example, the first COF contact electrode BPE3a may be configured with, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0227] The second COF contact electrode BPE3b is arranged below the first COF contact electrode BPE3a. The second COF contact electrode BPE3b may be in contact with a surface of the first COF contact electrode BPE3a exposed through the first insulation layer 131.

[0228] The second COF contact electrode BPE3b may be formed of the same material as the second lower contact electrode BPEb. For example, the second COF contact electrode BPE3b may be configured with, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0229] The third COF contact electrode BPE3c is arranged below the second COF contact electrode BPE3b. The third COF contact electrode BPE3c can be in contact with a surface of the second COF contact electrode BPE3b.

[0230] The third COF contact electrode BPE3c and the second COF contact electrode BPE3b may completely overlap. For example, an area where the third COF contact electrode BPE3c and the second substrate 130 overlap is equal to an area where the second COF contact electrode BPE3b and the second substrate 130 overlap.

[0231] The third COF contact electrode BPE3c may be formed from the same material as the third lower contact electrode BPEc. For example, the third COF contact electrode BPE3c may be formed from a material that hardly corrodes even when in contact with air or moisture to prevent corrosion of the second COF contact electrode BPE3b. For example, the third COF contact electrode BPE3c may be formed from a conductor material, such as, but not limited to, a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0232] The plurality of COF pads BPAD3 may be electrically connected to the plurality of flexible COF thin layers through the third COF contact electrode BPE3c among the plurality of conductive layers that respectively configure the plurality of COF pads BPAD3. That is, the plurality of COF pads BPAD3 may be electrically connected to an external module through the third COF contact electrode BPE3c.

[0233] For example, the plurality of COF pads BPAD3 may be electrically connected to the plurality of flexible COF thin layers through the third COF contact electrode BPE3c exposed through the second insulation layer 132.

[0234] Although it is in Fig. 8, the plurality of COF pads BPAD3 may be electrically connected to the plurality of flexible COF thin layers through the third COF contact electrode BPE3c, among the plurality of conductive layers configuring the plurality of COF pads BPAD3, respectively.

[0235] The plurality of COF pads BPAD3 may be connected to the plurality of flexible COF thin layers via the adhesive layer. For example, the adhesive layer may be an anisotropic conductive thin layer (ACF) or a conductive paste. Furthermore, the plurality of flexible COF thin layers may be electrically connected to the plurality of COF pads BPAD3 of the second substrate 130 using heat and pressure, for example.

[0236] In the following, a lower power supply line is described with reference to Fig. 9 described in detail.

[0237] Fig. Fig. 9 is a cross-sectional view of a second substrate taken along line BB' of Fig. 4 was taken. Fig. 9 is a cross-sectional view of a first lower conduction surface BLA1 and a second lower conduction surface BLA2. In Fig. 9, for convenience of description, it is illustrated that positions of the second substrate 130 and components under the second substrate 130 are reversed to arrange the second substrate 130 on the bottom side.

[0238] With reference to Fig. 9, a lower high-potential power supply line BVL1, a lower auxiliary high-potential power supply line BAVL1 and a plurality of lower data connection lines BDL are arranged in the first lower line surface BLA1.

[0239] In Fig. 9, to simplify the illustration, a lower high-potential power supply line BVL1, a lower auxiliary high-potential power supply line BAVL1 and a plurality of lower data connection lines BDL are arranged on the second substrate 130.

[0240] However, the second substrate 130, which is in Fig. 9, arranged upside down to be contacted with the first substrate 110. Therefore, in the contacted state of the second substrate 130 and the first substrate 110, the lower high-potential power supply line BVL1, the lower auxiliary high-potential power supply line BAVL1, and the plurality of lower data connection lines BDL can be arranged under the second substrate 130.

[0241] Therefore, it will be described based on a state in which the second substrate 130 is contacted with the first substrate 110, and it will be described that the lower high-potential power supply line BVL1, the lower auxiliary high-potential power supply line BAVL1, and the plurality of lower data connection lines BDL are arranged under the second substrate 130.

[0242] The lower high-potential power supply line BVL1 is arranged under the second substrate 130.

[0243] The lower high-potential power supply line BVL1 may be formed of the same material as the first lower contact electrode BPEa and the first COF contact electrode BPE3a. For example, the lower high-potential power supply line BVL1 may be configured with, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0244] The first insulation layer 131 is disposed under the lower high-potential power supply line BVL1. The first insulation layer 131 may include a plurality of openings arranged in a position that overlaps the plurality of lower auxiliary high-potential power supply lines BAVL1. Meanwhile, the first insulation layer 131 is arranged to overlap the plurality of lower data connection lines BDL to isolate the lower high-potential power supply line BVL1 from the plurality of lower data connection lines BDL.

[0245] The plurality of lower auxiliary high-potential power supply lines BAVL1 and the plurality of lower data connection lines BDL are arranged under the first insulation layer 131.

[0246] First, the plurality of lower auxiliary high-potential power supply lines BAVL1 are arranged under the first insulation layer 131.

[0247] The plurality of lower auxiliary high-potential power supply lines BAVL1 may be in contact with the front surface of the lower high-potential power supply line BVL1 exposed through the first insulation layer 131. For example, the first insulation layer 131 and the plurality of lower auxiliary high-potential power supply lines BAVL1 are disposed below the lower high-potential power supply line BVL1, and the first insulation layer 131 may be disposed in an area other than between the flexible thin layers COF. Therefore, the plurality of lower auxiliary high-potential power supply lines BAVL1 may be in contact with the lower high-potential power supply line BVL1 in an area between the flexible thin layers COF where the first insulation layer 131 is exposed.

[0248] Therefore, the plurality of lower auxiliary high-potential power supply lines BAVL1 are in contact with the lower high-potential power supply line BVL1 to minimize voltage drop and voltage deviation.

[0249] Each of the plurality of lower auxiliary high-potential power supply lines BAVL1 includes a first lower auxiliary high-potential power supply line BAVL1a and a second lower auxiliary high-potential power supply line BAVL1b.

[0250] The first insulation layer 131 is arranged under the second substrate 130, and a part of the first lower auxiliary high-potential power supply line BAVL1a is arranged under the first insulation layer 131, and the other part is arranged at the same layer as the first insulation layer 131.

[0251] The first lower auxiliary high-potential power supply line BAVL1a may be formed of the same material as the second lower contact electrode BPEb and the second COF contact electrode BPE3b. For example, the first lower auxiliary high-potential power supply line BAVL1a may be configured with, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0252] The second lower auxiliary high-potential power supply line BAVL1b is arranged below the first lower auxiliary high-potential power supply line BAVL1a.

[0253] The second lower auxiliary high-potential power supply line BAVL1b may be formed of the same material as the third lower contact electrode BPEc and the third COF contact electrode BPE3c. For example, the second lower auxiliary high-potential power supply line BAVL1b may be formed of a material that hardly corrodes even when in contact with air or moisture to prevent corrosion of the first lower auxiliary high-potential power supply line BAVL1a. For example, the second lower auxiliary high-potential power supply line BAVL1b may be formed of a conductor material, such as, but not limited to, a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0254] The second lower auxiliary high-potential power supply line BAVL1b may be in contact with the front surface of the first lower auxiliary high-potential power supply line BAVL1a. Meanwhile, the second lower auxiliary high-potential power supply line BAVL1b may completely overlap with the first lower auxiliary high-potential power supply line BAVL1a. For example, an area where the second lower auxiliary high-potential power supply line BAVL1b and the second substrate 130 overlap may be equal to an area where the first lower auxiliary high-potential power supply line BAVL1a and the second substrate 130 overlap.

[0255] The plurality of lower auxiliary high-potential power supply lines BAVL1 may be formed of the same material as the second lower contact electrode BPEb and the second COF contact electrode BPE3b.

[0256] For example, the plurality of lower auxiliary high-potential power supply lines BAVL1 may be configured by, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0257] Several lower data connection lines BDL are arranged under the first insulation layer 131.

[0258] The plurality of lower data connection lines BDL may be arranged at the same layer as the plurality of lower auxiliary high-potential power supply lines BAVL1.

[0259] Furthermore, the plurality of lower data connection lines BDL may be arranged to overlap with the lower high-potential power supply line BVL1. For example, the plurality of lower data connection lines BDL may be arranged to overlap with the lower high-potential power supply line BVL1 with the first insulation layer 131 therebetween.

[0260] Each of the plurality of lower data connection lines BDL includes a first lower data connection line BDLa and a second lower data connection line BDLb.

[0261] The first insulation layer 131 is arranged under the second substrate 130 and the first lower data connection line BDLa is arranged under the first insulation layer 131.

[0262] The first lower data connection line BDLa may be formed of the same material as the second lower contact electrode BPEb and the second COF contact electrode BPE3b. For example, the first lower data connection line BDLa may be configured by a conductor material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0263] The second lower data connection line BDLb is arranged below the first lower data connection line BDLa.

[0264] The second lower data connection line BDLb may be formed of the same material as the third lower contact electrode BPEc and the third COF contact electrode BPE3c. For example, the second lower data connection line BDLb may be formed of a material that hardly corrodes even when in contact with air or moisture to prevent corrosion of the first lower data connection line BDLa. For example, the second lower data connection line BDLb may be formed of a conductor material, such as, but not limited to, a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0265] The second lower data connection line BDLb may be in contact with the front surface of the first lower data connection line BDLa. Meanwhile, the second lower data connection line BDLb may completely overlap with the first lower data connection line BDLa. For example, an area where the second lower data connection line BDLb and the second substrate 130 overlap may be equal to an area where the first lower data connection line BDLa and the second substrate 130 overlap.

[0266] The lower low-potential power supply line BVL2 is arranged in the second lower line area BLA2.

[0267] To simplify the presentation, Fig. 9 illustrates that the lower low-potential power supply line BVL2 is arranged on the second substrate 130, and the second substrate 130 shown in Fig.9 is arranged upside down to be contacted with the first substrate 110. Therefore, in a state where the second substrate 130 and the first substrate 110 are contacted, the lower low-potential power supply line BVL2 can be arranged under the second substrate 130.

[0268] The following will be described based on a state in which the second substrate 130 is contacted with the first substrate 110, and it will be described that the lower low-potential power supply line BVL2 is arranged under the second substrate 130.

[0269] The lower low-potential power supply line BVL2 includes a first lower low-potential power supply line BVL2a, a second lower low-potential power supply line BVL2b, and a third lower low-potential power supply line BVL2c.

[0270] The first lower low-potential power supply line BVL2a is arranged under the second substrate 130.

[0271] The first lower low-potential power supply line BVL2a may be formed of the same material as the first lower contact electrode BPEa and the first COF contact electrode BPE3a. For example, the first lower low-potential power supply line BVL2a may be configured by, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0272] The first insulation layer 131 is arranged under the first lower low-potential power supply line BVL2a and a part of the second lower low-potential power supply line BVL2b is arranged under the first insulation layer 131 and the other part is arranged at the same layer as the first insulation layer 131.

[0273] The second lower low-potential power supply line BVL2b may be in contact with the front surface of the first lower low-potential power supply line BVL2a exposed through the first insulation layer 131. For example, the first insulation layer 131 and the second lower low-potential power supply line BVL2b are disposed below the first lower low-potential power supply line BVL2a, and the first insulation layer 131 may be disposed in an area excluding the second lower line area BLA2. Therefore, the second lower low-potential power supply line BVL2b may be in contact with the first lower low-potential power supply line BVL2a in the second lower line area BLA2.

[0274] The second lower low-potential power supply line BVL2b may be formed of the same material as the second lower contact electrode BPEb and the second COF contact electrode BPE3b. For example, the second lower low-potential power supply line BVL2b may be configured with, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0275] The third lower low-potential power supply line BVL2c may be arranged below the second lower low-potential power supply line BVL2b.

[0276] The third lower low-potential power supply line BVL2c may be in contact with the front surface of the second lower low-potential power supply line BVL2b.

[0277] The third lower low-potential power supply line BVL2c may be formed of the same material as the third lower contact electrode BPEc and the third COF contact electrode BPE3c. For example, the third lower low-potential power supply line BVL2c may be formed of a conductor material, such as, but not limited to, a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0278] Meanwhile, the third lower low-potential power supply line BVL2c may completely overlap with the second lower low-potential power supply line BVL2b. For example, an area where the third lower low-potential power supply line BVL2c and the second substrate 130 overlap may be equal to an area where the second lower low-potential power supply line BVL2b and the second substrate 130 overlap.

[0279] When a plurality of metal layers arranged on the display panel are exposed to the outside, the plurality of metal layers react with air or moisture to corrode. For example, the plurality of upper pads arranged on the first substrate and the plurality of lower pads arranged under the second substrate react with the air or moisture to corrode. Therefore, to prevent corrosion of the plurality of upper pads and the plurality of lower pads, a transparent conductive layer may be used as the plurality of terminal electrodes configuring the plurality of upper pads and the plurality of lower pads.Currently, a plurality of power supply lines or a plurality of data lines can be arranged on the same layer as the transparent conductive layers of the plurality of upper pads and the plurality of lower pads. However, when forming the plurality of power supply lines or the plurality of data lines with the transparent conductive layer, a separate mask process is performed for patterning the transparent conductive layer. For example, a process of forming an insulating layer such as an organic insulating layer may be added above or below the transparent conductive layer. Accordingly, there are no problems of increasing the number of masks and increasing manufacturing costs and time.

[0280] Meanwhile, a wiring line formed from the transparent conductive layer may be arranged to overlap with the metal layer line having a different load. For example, the low-potential power supply line formed from the transparent conductive layer may be arranged on the back surface of the second substrate to overlap with the data line and the high-potential power supply line. At this time, a potential difference may occur between the low-potential power supply line and the data line, between the low-potential power supply line and the high-potential power supply line, and between the data line and the high-potential power supply line.Therefore, there may be a problem that a parasitic capacitance is generated between the low-potential power supply line, the data line, and the high-potential power supply line, and a short-circuit fault may occur due to the external environment between the high-potential power supply line, the low-potential power supply line, and the data line. Specifically, during the manufacturing process of a display device, a back surface of the second substrate is in contact with a support unit that supports the second substrate. At this time, a dent may be generated in the back surface of the second substrate due to the contact with the support unit. Specifically, when a thin optical layer is bonded to the first substrate, pressure is exerted from an upper portion of the first substrate to a lower portion of the second substrate, causing damage such as chipping due to the pressure.may cause a dent or scratch on the back surface of the second substrate. Therefore, due to external impact, a short-circuit path may be formed between the low-potential power supply line and the data line, and between the low-potential power supply lines.

[0281] Accordingly, in the display device 100 according to the embodiment of the disclosure, a transparent conductive layer disposed on the back surface of the second substrate 130 can be formed using the same mask as the metal layer. For example, the third lower contact electrode BPEc, which is disposed at the lowermost portion of the plurality of terminal electrodes configuring the plurality of lower pads BPAD and is formed of the transparent conductive layer, can be formed by the same process as the second lower contact electrode BPEb, which is formed of a metal layer. Therefore, mask processes can be reduced. Furthermore, the plurality of wiring lines disposed at the same layer as the third lower contact electrodes BPEc can be formed using the same mask as the plurality of wiring lines disposed at the same layer as the second lower contact electrode BPEb.For example, the second lower data connection line BDLb, which is arranged at the same layer as the third lower contact electrode BPEc, can be formed by the same process as the first lower data connection line BDLa, which is arranged at the same layer as the second lower contact electrode BPEb. Furthermore, the second lower auxiliary high-potential power supply line BAVL1b, which is arranged at the same layer as the third lower contact electrode BPEc, can be formed by the same process as the first lower auxiliary high-potential power supply line BAVL1a, which is arranged at the same layer as the second lower contact electrode BPEb. Therefore, the number of masks can be reduced, and the manufacturing cost and manufacturing time can be reduced.

[0282] Furthermore, in the display device 100 according to the embodiment of the disclosure, the transparent conductive layer disposed on the back surface of the second substrate 130 is formed by the same mask as the metal layer, so that only the second insulating layer 132 may be disposed under the lower data link BDL. For example, the lower data link BDL may include a first lower data link BDLa formed of a metal layer and a second lower data link BDLb formed of a transparent conductive layer. Therefore, the second lower data link BDLb, which has the same potential as the first lower data link BDLa, is disposed under the first lower data link BDLa. Therefore, when damage such as a chip occurs, the second insulating layer 132 may be disposed under the first lower data link BDLa.A dent or scratch on the back surface of the second substrate 130 prevents short-circuit faults from occurring between wiring lines carrying different loads. Therefore, the short-circuit path that may be generated on the back surface of the second substrate 130 is reduced, improving the reliability of the display device 100.

[0283] Although the embodiments of the disclosure have been described in detail with reference to the accompanying drawings, the disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the disclosure. Therefore, the embodiments of the disclosure are provided for illustrative purposes only, but are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the disclosure is not limited thereto. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and do not limit the disclosure. The scope of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the corresponding scope should be construed as falling within the scope of the disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2024-0028219

[0001]

Claims

[1] Display device comprising: a first substrate (110) containing a plurality of top pads (TPAD); a second substrate (130) containing a plurality of bottom pads (BPAD); and a plurality of side leads (SRL) for connecting the plurality of upper pads (TPAD) and the plurality of lower pads (BPAD), each of the plurality of lower pads (BPAD) including: a first lower contact electrode (BPEa) arranged under the second substrate (130); a first insulation layer (131) disposed under the first lower contact electrode (BPEa); a second lower contact electrode (BPEb) arranged under the first insulation layer (131); a third lower contact electrode (BPEc) arranged below the second lower contact electrode (BPEb); and a second insulation layer (132) disposed under the third lower contact electrode (BPEc), wherein the third lower contact electrode (BPEc) is formed of a transparent conductor material. [2] The display device according to claim 1, wherein the third lower contact electrode (BPEc) and the second lower contact electrode (BPEb) completely overlap. [3] The display device according to claim 1 or claim 2, wherein the first insulating layer (131) and the second insulating layer (132) are inorganic insulating layers, and the second insulating layer (132) opens a portion of the third lower contact electrode (BPEc). [4] A display device according to any preceding claim, wherein the third lower contact electrode (BPEc) is in contact with the plurality of side lines (SRL). [5] A display device according to any preceding claim, wherein the plurality of lower pads (BPAD) include: a plurality of first lower pads (BPAD1) arranged in a first edge (EG1) of the second substrate (130); and a plurality of second lower pads (BPAD2) arranged in a second edge (EG2) of the second substrate (130), wherein a high potential power voltage is applied to the plurality of first lower pads (BPAD1) and a low potential power voltage is applied to the plurality of second lower pads (BPAD2). [6] The display device according to claim 5, wherein the plurality of upper pads (TPAD) includes a plurality of first upper pads (TPAD1) and a plurality of second upper pads (TPAD2), and the plurality of side lines (SRL) includes: a plurality of first side lines (SRL) connecting the plurality of first upper pads (TPAD1) and the plurality of first lower pads (BPAD1); and a plurality of second side lines (SRL) connecting the plurality of second upper pads (TPAD2) and the plurality of second lower pads (BPAD2). [7] A display device according to any preceding claim, further comprising: a low-potential power supply line (BVL2), a high-potential power supply line (BVL1) and a plurality of data lines (DL) arranged on the second substrate (130), wherein the plurality of data lines (BDL) overlap with a portion of the high-potential power supply line (BVL1). [8] A display device according to claim 7, further comprising: a plurality of flexible thin films (COF) arranged between the high-potential power supply line (BVL1) and the low-potential power supply line (BVL2); and a plurality of auxiliary high-potential power supply lines (BAVL1) arranged above the high-potential power supply line (BVL1) in such a way that they are in contact with the high-potential power supply line (BVL1), wherein each of the plurality of auxiliary high-potential power supply lines (BAVL1) is arranged alternately with each of the plurality of flexible thin films (COF), preferably the high-potential power supply line (BVL1) is formed of the same material as the first lower contact electrode (BPEa), and the plurality of auxiliary high-potential power supply lines (BAVL1) are formed of the same material as the second lower contact electrode (BPEb) and the third lower contact electrode (BPEc). [9] A display device according to claim 8, wherein a width of each of the plurality of auxiliary high-potential power supply lines (BAVL1) increases as it is adjacent to the low-potential power supply lines (BVL2). [10] A display device according to any one of claims 8 or 9, further comprising: a plurality of COF pads (BPAD3) disposed on the second substrate (130) and connected to the flexible thin layer (COF), each of the plurality of COF pads (BPAD3) including: a first COF contact electrode (BPE3a), a second COF contact electrode (BPE3b) and a third COF contact electrode (BPE3c) formed of the same material as the first lower contact electrode (BPEa), the second lower contact electrode (BPEb) and the third lower contact electrode (BPEc), respectively, wherein preferably the second COF contact electrode (BPE3b) and the third COF contact electrode (BPE3c) completely overlap. [11] A display device according to any one of claims 7-10, wherein the plurality of lower pads (BPAD) include: a plurality of first lower pads (BPAD1) arranged in a first edge (EG1) of the second substrate (130); and a plurality of second lower pads (BPAD2) arranged in a second edge (EG2) of the second substrate (130), wherein the high-potential power supply line (BVL1) is arranged in the first edge (EG1) of the second substrate (130) to be connected to the plurality of first lower pads (BPAD1), and the low-potential power supply line (BVL2) is arranged in the second edge (EG2) of the second substrate (130) to be connected to the plurality of second lower pads (BPAD2), preferably a width of the high-potential power supply line (BVL1) corresponds to a distance between outermost first lower terminal surfaces (BPAD1) among the plurality of first lower terminal surfaces (BPAD1) and a width of the low-potential power supply line (BVL2) corresponds to a distance between outermost second lower pads (BPAD2) among the plurality of second lower pads (BPAD2). [12] The display device according to any one of claims 7-11, wherein the low-potential power supply line (BVL2) is formed of the same material as the first lower contact electrode (BPAD1), the second lower contact electrode (BPAD2) and the third lower contact electrode (BPAD3). [13] Display device comprising: a first substrate (110) containing a plurality of top pads (TPAD); a second substrate (130) containing a plurality of bottom pads (BPAD); a plurality of side leads (SRL) connecting the plurality of upper pads (TPAD) and the plurality of lower pads (BPAD); several flexible thin layers (COF) and a plurality of COF pads (BPAD3) arranged on the second substrate (130) and connected to the flexible thin layer (COF), wherein each of the plurality of COF pads (BPAD3) includes: a first COF contact electrode (BPE3a), a second COF contact electrode (BPE3b) and a third COF contact electrode (BPE3c), wherein the first COF contact electrode (BPE3a) is arranged under the second substrate (130), the second COF contact electrode (BPE3b) is arranged under the first COF contact electrode (BPE3a), and the third COF contact electrode (BPE3c) is arranged under the second COF contact electrode (BPE3b). [14] The display device according to claim 13, wherein the second COF contact electrode (BPE3b) and the third COF contact electrode (BPE3c) completely overlap and / or the third COF contact electrode (BPE3c) is formed of a transparent conductor material.

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