Method and device for an integrated circuit

Abstract

Method for a first integrated circuit arranged together with at least one further, for example second, integrated circuit on a substrate, comprising: sending a test signal to the at least one further integrated circuit, receiving a feedback signal associated with the test signal from the at least one further integrated circuit.

Description

State of the art

[0001] The disclosure relates to at least one method for an integrated circuit.

[0002] The disclosure further relates to at least one device for an integrated circuit. Disclosure of the invention

[0003] Some examples relate to a method, for example, a computer-implemented method, for a first integrated circuit arranged together with at least one further, for example, second, integrated circuit on a substrate, comprising: sending a test signal to the at least one further integrated circuit; receiving feedback associated with the test signal from the at least one further integrated circuit. In some examples, this enables monitoring of a transmission quality with respect to the test signal.

[0004] In some examples, the method comprises influencing an operation of at least one component of the first integrated circuit based on the feedback.

[0005] In some examples, it is provided that the first integrated circuit and the at least one further integrated circuit are each designed as a chip, for example a chiplet, wherein, for example, the first integrated circuit and the at least one further integrated circuit form a multi-chiplet system.

[0006] In some examples, it is provided that a first communication channel is used for sending the test signal, wherein, for example, the first communication channel is a main band of a communication interface which connects at least the first integrated circuit and the second integrated circuit to one another, wherein, for example, the communication interface is a, for example, unified, chiplet interface, for example of the type Universal Chiplet Interconnect Express, UCle, for example UCle 1.0.

[0007] In some examples, it is provided that a second communication channel is used to receive the feedback, wherein, for example, the second communication channel is a sideband of a communication interface that connects at least the first integrated circuit and the second integrated circuit to each other, wherein, for example, the communication interface is a, e.g., unified, chiplet interface, e.g., of the UCle type, for example UCle 1.0

[0008] In some examples, it is provided that influencing the operation comprises: controlling, for example influencing, a signal level with which the first integrated circuit sends information, for example data, for example via a or the first communication channel, to the at least one further integrated circuit.

[0009] In some examples, it is provided that the method comprises: providing the test signal, wherein, for example, the test signal has at least one, for example predefinable, signal pattern, for example test pattern, and, optionally, using the test signal.

[0010] In some examples, the provision includes providing an encrypted test signal or test pattern. For example, a standardized encryption method can be used.

[0011] In some examples, it is provided that the method comprises: controlling, for example influencing, a or the signal level with which the first integrated circuit sends information, for example data, for example via a or the first communication channel, to the at least one further integrated circuit, for example based on the feedback, wherein, for example, the controlling, for example influencing, is carried out dynamically, for example during operation of at least the first integrated circuit, for example repeatedly, for example periodically, for example several times within a fault tolerance time.

[0012] Some examples relate to a method, for example a computer-implemented method, for a or the second integrated circuit arranged together with at least one or the first integrated circuit on a or the substrate, comprising: receiving a or the test signal from the first integrated circuit, evaluating the received test signal, creating, based on the evaluation, a or the feedback associated with the test signal, sending the feedback to the first integrated circuit.

[0013] In some examples, as already described above, it is provided that the first integrated circuit and the second integrated circuit are each designed as a chip, for example a chiplet, wherein, for example, the first integrated circuit and the at least one further integrated circuit form a multi-chiplet system.

[0014] In some examples, it is provided that a first communication channel is used to receive the test signal, wherein, for example, the first communication channel is a main band of a communication interface that connects at least the first integrated circuit and the second integrated circuit to one another, wherein, for example, the communication interface is a, for example, unified, chiplet interface, for example of the type Universal Chiplet Interconnect Express, UCle, for example UCle 1.0.

[0015] In some examples, it is provided that a second communication channel is used for sending the feedback, wherein, for example, the second communication channel is a sideband of a or the communication interface that connects at least the first integrated circuit and the second integrated circuit to one another, wherein, for example, the communication interface is a, for example, unified, chiplet interface, for example of the UCle type, for example UCle 1.0.

[0016] In some examples, it is provided that the evaluation comprises at least one of the following elements: a) checking the received test signal, e.g. for correctness or agreement, e.g. with a, for example predefinable, signal pattern, e.g. test pattern, or b) analyzing a signal level of the received test signal, or c) analyzing a signal quality of the received test signal, or d) using at least one method based on artificial intelligence, e.g. machine learning, or e) using a multi-stage evaluation system.

[0017] Some examples relate to an apparatus for carrying out the method according to the disclosure.

[0018] Some examples relate to an integrated circuit, for example for a multi-chiplet system comprising a plurality of chiplets, comprising at least one device according to the disclosure, wherein, for example, the device or a functionality of the device is integrated into the integrated circuit.

[0019] Some examples relate to a system, for example a multi-chiplet system, comprising at least one device according to the disclosure or at least one integrated circuit according to the disclosure.

[0020] Some examples relate to a product, for example a control unit, for example for a motor vehicle, comprising at least one device according to the disclosure.

[0021] Some examples relate to a vehicle, for example a motor vehicle, comprising at least one device according to the disclosure and / or at least one product, for example a control unit, according to the disclosure.

[0022] Some examples relate to a computer-readable storage medium comprising instructions that, when executed by a computer, cause the computer to perform the method according to the disclosure.

[0023] Some examples relate to a computer program comprising instructions that, when executed by a computer, cause the computer to carry out the method according to the disclosure.

[0024] Some examples relate to a data carrier signal that characterizes and / or transmits the computer program according to the disclosure.

[0025] Some examples relate to a use of the method according to the disclosure and / or the device according to the disclosure and / or the integrated circuit according to the disclosure and / or the system according to the disclosure and / or the product according to the disclosure and / or the vehicle according to the disclosure and / or the computer-readable storage medium according to the disclosure and / or the computer program according to the disclosure and / or the data carrier signal according to the disclosure for at least one of the following elements: a) ensuring data communication between the first integrated circuit and the at least one further, for example second, integrated circuit, or b) increasing the robustness of data communication with respect to the first integrated circuit, for example between the first integrated circuit and the at least one further, for example second, integrated circuit,or c) increasing the reliability of data communication with respect to the first integrated circuit, or d) increasing the availability of the first integrated circuit and / or a system comprising the first integrated circuit, or e) increasing the design quality and / or manufacturing quality, for example based on feedback from operation of the first integrated circuit.

[0026] Further features, possible applications, and advantages of the invention will become apparent from the following description of examples of the invention, which are illustrated in the figures of the drawing. All described or illustrated features, individually or in any combination, constitute the subject matter of the invention, regardless of their summary in the claims or their references, as well as regardless of their wording or representation in the description or drawing.

[0027] The drawing shows: Fig. 1 schematically shows a simplified flow diagram, Fig. 2 schematically shows a simplified block diagram, Fig. 3 schematically shows a simplified flow diagram, Fig. 4 schematically shows a simplified flow diagram, Fig. 5 schematically shows a simplified flow diagram, Fig. 6 schematically shows a simplified block diagram, Fig. 7 schematically shows a simplified diagram, Fig. 8 schematically shows a simplified block diagram, Fig. 9 schematic examples of uses.

[0028] Some examples, Fig. 1, Fig. 2, relate to a method, for example a computer-implemented method, for a first integrated circuit 101, which is arranged together with at least one further, for example second, integrated circuit 102 on a substrate 104, comprising: sending 200 a test signal TS to the at least one further integrated circuit 102, receiving 202 a feedback signal RM associated with the test signal TS (for example dependent on the test signal TS or formed based on the test signal TS) from the at least one further integrated circuit 102. In some examples, this enables monitoring of a transmission quality with regard to the test signal TS.

[0029] In some examples, Fig. 1, it is provided that the method comprises: influencing 204 an operation BETR-101 of at least one component of the first integrated circuit 101 based on the feedback RM.

[0030] In some examples, Fig. 2, it is provided that the first integrated circuit 101 and the at least one further integrated circuit 102 are each designed as a chip, for example a chiplet, wherein, for example, the first integrated circuit 101 and the at least one further integrated circuit 102 form a multi-chiplet system 1000.

[0031] In some examples, Fig. 1, it is provided that a first communication channel K-1 is used for the transmission 200 of the test signal TS, see block 200a, wherein, for example, the first communication channel K-1 is a main band of a communication interface 110 ( Fig. 2) which connects at least the first integrated circuit 101 and the second integrated circuit 102 to one another, wherein, for example, the communication interface 110 is a, e.g. unified, chiplet interface, e.g. of the type Universal Chiplet Interconnect Express, UCle, for example UCle 1.0.

[0032] In some examples, Fig. 1, it is provided that a second communication channel K-2 is used for receiving 202 the feedback RM, see block 202a, wherein, for example, the second communication channel K-2 is a sideband of a communication interface 110 which connects at least the first integrated circuit 101 and the second integrated circuit 102 to one another.

[0033] In some examples, Fig. 1, it is provided that influencing 204 of the operation BETR-101 comprises: controlling, for example influencing, 204a a signal level TX-PEG, with which the first integrated circuit 101 sends information, for example data, for example via a or the first communication channel K-1, to the at least one further integrated circuit 102. In some examples, a closed-loop control of the signal level TX-PEG is thus possible, for example in the sense of a closed-loop control, based on the feedback RM.

[0034] In some examples, Fig. 3, it is provided that the method comprises: providing 210 the test signal TS, wherein, for example, the test signal TS has at least one, for example predefinable, signal pattern, for example test pattern, TP, and, optionally, using 212 the test signal TS, for example for sending 200 ( Fig. 1).

[0035] In some examples, Fig. 3, it is provided that the provision 210 comprises a provision 210a of an encrypted test signal TS' or test pattern TP'.

[0036] In some examples, Fig. 4, it is provided that the method comprises: controlling 220, for example influencing 220a, a or the signal level TX-PEG, with which the first integrated circuit 101 transmits information, for example data, for example via a or the first communication channel K-1 ( Fig. 2) to which at least one further integrated circuit 102 is sent, for example based on the feedback RM, wherein, for example, the controlling 220, for example influencing 220a, is carried out dynamically, for example during operation of at least the first integrated circuit 101, see block 220b, for example repeatedly, for example periodically, for example several times within a fault tolerance time. The optional block 222 symbolizes an optional communication COMM between the components 101, 102, for example using the signal level TX-PEG influenced according to block 220.

[0037] Some examples, Fig. 5, relate to a method, for example a computer-implemented method, for one or the second integrated circuit 102 ( Fig. 2), which is arranged together with at least one or the first integrated circuit 101 on one or the substrate 104, comprising: receiving 250 a or the test signal TS from the first integrated circuit 101, evaluating 252 the received test signal TS, creating 254, based on the evaluation 252, a or the feedback RM associated with the test signal TS, sending 256 the feedback RM to the first integrated circuit 101.

[0038] In some examples, as already described above, it is provided that the first integrated circuit 101 and the second integrated circuit 102 are each designed as a chip, for example a chiplet, wherein, for example, the first integrated circuit 101 and the at least one further integrated circuit 102 form a multi-chiplet system 1000.

[0039] In some examples, Fig. 5, it is provided that a first communication channel K-1 is used for receiving 250 the test signal TS, see block 250a, wherein, for example, the first communication channel is a main band of a communication interface 110 which connects at least the first integrated circuit 101 and the second integrated circuit 102 to one another, wherein, for example, the communication interface 110 is a, for example, unified, chiplet interface, for example of the UCle type, for example UCle 1.0.

[0040] In some examples, Fig. 5, it is provided that a second communication channel K-2 is used for sending 256 the feedback RM, see block 256a, wherein, for example, the second communication channel K-2 is a sideband of a or the communication interface 110 which connects at least the first integrated circuit and the second integrated circuit to one another, wherein, for example, the communication interface is a, for example, unified, chiplet interface, for example of the UCle type, for example UCle 1.0.

[0041] In some examples, Fig. 5, it is provided that the evaluation 252 comprises at least one of the following elements: a) checking 252a the received test signal TS, e.g. for correctness or agreement, e.g. with a, for example predefinable, signal pattern, e.g. test pattern, TP, or b) analyzing 252b a signal level of the received test signal TS, or c) analyzing 252c a signal quality of the received test signal TS, or d) using 252d at least one method based on artificial intelligence (AI), e.g. machine learning (ML), e.g. for the testing 252a and / or for the analysis 252b and / or 252c, or e) using 252e a multi-stage evaluation system, e.g. for an evaluation of results of the evaluation 252, e.g. instead of a binary evaluation (e.g. pass / fail).

[0042] Some examples, Fig. 6, refer to an apparatus 300 for carrying out the method according to the disclosure.

[0043] In some examples, Fig. 6, it is provided that the device 300 comprises: a computing device (“computer”) 302 having at least one computing core 302a, a memory device 304 assigned to the computing device 302 for at least temporarily storing at least one of the following elements: a) data DAT (e.g. data associated with the test signal TS and / or data associated with the feedback RM and / or data associated with the evaluation 252), b) computer program PRG, for example for carrying out the method according to the disclosure.

[0044] In further examples, the storage device 304 comprises a volatile memory (e.g., random access memory (RAM)) 304a, and / or a non-volatile (NVM) memory (e.g., flash EEPROM) 304b, or a combination thereof or with other memory types not explicitly mentioned.

[0045] In further examples, the device 300 is implemented as a hardware circuit, for example a pure hardware circuit (not shown).

[0046] Further examples, Fig. 6, refer to a computer-readable storage medium SM comprising instructions PRG which, when executed by a computer 302, cause the computer 302 to carry out the method according to the disclosure.

[0047] Further examples relate to a computer program PRG comprising instructions which, when the program PRG is executed by a computer 302, cause the computer 302 to carry out the method according to the disclosure.

[0048] Further examples relate to a data carrier signal DCS that characterizes and / or transmits the computer program PRG according to the disclosure. The data carrier signal DCS can be received, for example, via an optional data interface 306 of the device 300.

[0049] Some examples, Fig. 2, relate to an integrated circuit, e.g. a chiplet, 101, 102, for example for a multi-chiplet system 1000 comprising a plurality of chiplets, comprising at least one device 300 according to the disclosure, wherein, for example, the device 300 or a functionality of the device 300 is integrated into the integrated circuit 101, 102 (or, in some examples, e.g. arranged on the common substrate 104).

[0050] Some examples, Fig. 2, relate to a system, for example multi-chiplet system, 1000, comprising at least one device 300 according to the disclosure or at least one integrated circuit 101, 102 according to the disclosure.

[0051] Fig. 7 schematically shows a simplified diagram according to some examples. Element E1 symbolizes a first transmitting device of a first chiplet 101', for example, configured to transmit data via a UCle main band channel K-1' to a first receiving device E2 of a second chiplet 102'. Element E3 symbolizes the provision of a test signal, for example, an encrypted test signal TS', which in some examples can be transmitted by the first transmitting device E1 via the UCle main band channel K-1 to the first receiving device E2, and element TS" symbolizes the test signal received by the second chiplet 102'.

[0052] In some examples, the second chiplet 102' forms a feedback RM' based on the received encrypted test signal TS'', which can be sent by a transmitting device E4 of the second chiplet 102 via a UCle sideband channel K-2' to a corresponding receiving device E5 of the first chiplet 101'.

[0053] In some examples, the first chiplet 101' performs a level adjustment E6 of a level for information to be transmitted to the second chiplet 102' via the UCle Main Band channel K-1', for example, based on the feedback RM' received from the second chiplet 102'.

[0054] Element E7 symbolizes an analog / digital conversion according to some examples, for example of at least a part of the received test signal TS'', for example by means of an analog / digital converter based on the delta-sigma principle.

[0055] Element E8 symbolizes an evaluation of the test signal TS''' digitized by means of element E7 according to some examples, for example using methods based on AI, for example ML.

[0056] Element E9 symbolizes an evaluation of the results of the evaluation E8 according to some examples, for example, using a multi-level evaluation system, which leads, for example, to the feedback RM'. For example, the feedback RM' can indicate whether, in what manner, or to what extent the first chiplet 101' should adjust its transmission level, see block E6.

[0057] In further examples, findings obtained by means of element E8 can be used, for example, for the production of further chiplets or systems containing chiplets and / or for their testing, for example in the context of production.

[0058] Element E10 symbolizes an error detection according to some examples, for example for the detection of at least one of the following elements: a) electrical, e.g. DC, errors (e.g. open, short plus / GND, crosstalk), or b) timing errors (e.g. concerning edge steepness, latency times, ..), or c) plausibility errors (e.g. freeze data, value range, ...).

[0059] Further aspects and examples are described below, which - in the case of further examples - can each be combined individually or in any combination with at least one of the aspects and / or examples described above.

[0060] In some examples, Fig. 7, communication, e.g. of user data between the chiplets 101', 102', takes place unidirectionally, e.g. via a respective main-band channel, from which in Fig. 7 shows, by way of example, the channel K-1' from the chiplet 101' to the chiplet 102' (but not a possibly existing further main-band channel from the chiplet 102' to the chiplet 101'.

[0061] In some examples, Fig. 7, statuses and / or other operationally relevant information can be transmitted via the side-band channel K-2' via the elements E4, E5, e.g. in addition to the feedback RM'.

[0062] In some examples, the principle according to the disclosure enables the provision of multi-chiplet systems 1000, in which, for example, different chiplets 101, 102, ... can each be assigned to different, for example, application-specific, domains such as, for example, in the automotive sector, body, chassis, ADAS, IVI. In further examples, different types of chiplets and / or chiplets with different architectures (e.g., GPU, CPU, HWA, ...) can be combined into a multi-chiplet system, wherein communication between the chiplets can be ensured according to the principle according to the disclosure.

[0063] Some examples, Fig. 8, relate to a product, for example control unit, 12, for example for a motor vehicle 10, comprising at least one device 300 according to the disclosure.

[0064] Some examples, Fig. 8, relate to a vehicle, for example motor vehicle, 10, comprising at least one device 300 according to the disclosure and / or at least one product, for example control unit, 12 according to the disclosure.

[0065] Some examples, Fig.9, relate to a use 400 of the method according to the disclosure and / or the device 300 according to the disclosure and / or the integrated circuit 101, 102 according to the disclosure and / or the system 1000 according to the disclosure and / or the product 12 according to the disclosure and / or the vehicle 10 according to the disclosure and / or the computer-readable storage medium SM according to the disclosure and / or the computer program PRG according to the disclosure and / or the data carrier signal DCS according to the disclosure for at least one of the following elements: a) ensuring 401 data communication between the first integrated circuit 101 and the at least one further, for example second, integrated circuit 102, or b) increasing 402 a robustness of data communication with respect to the first integrated circuit, for example between the first integrated circuit and the at least one further, for example second,integrated circuit, or c) increasing 403 a reliability of data communication with respect to the first integrated circuit, or d) increasing 404 an availability of the first integrated circuit and / or a system 1000 comprising the first integrated circuit, or e) increasing 405 a design quality and / or manufacturing quality, for example based on feedback of findings from operation of the first integrated circuit.

Claims

[1] Method for a first integrated circuit (101) which is arranged together with at least one further, for example second, integrated circuit (102) on a substrate (104), comprising: sending (200) a test signal (TS) to the at least one further integrated circuit (102), receiving (202) a feedback signal (RM) associated with the test signal (TS) from the at least one further integrated circuit (102). [2] The method of claim 1, comprising: influencing (204) an operation (BETR-101) of at least one component of the first integrated circuit (101) based on the feedback (RM). [3] Method according to at least one of the preceding claims, wherein the first integrated circuit (101) and the at least one further integrated circuit (102) are each designed as a chip, for example a chiplet, wherein, for example, the first integrated circuit (101) and the at least one further integrated circuit (102) form a multi-chiplet system (1000). [4] Method according to at least one of the preceding claims, wherein a first communication channel (K-1) is used (200a) for sending (200) the test signal (TS), wherein, for example, the first communication channel (K-1) is a main band of a communication interface (110) which connects at least the first integrated circuit (101) and the second integrated circuit (102) to one another, wherein, for example, the communication interface (110) is a, for example, unified, chiplet interface, for example of the Universal Chiplet Interconnect Express, UCle, type. [5] Method according to at least one of the preceding claims, wherein a second communication channel (K-2) is used (202a) for receiving (202) the feedback (RM), wherein, for example, the second communication channel (K-2) is a sideband of a communication interface (110) which connects at least the first integrated circuit (101) and the second integrated circuit (102) to one another, wherein, for example, the communication interface (110) is a, for example, unified, chiplet interface, for example of the UCle type [6] Method according to at least one of the preceding claims, wherein influencing (204) the operation (BETR-101) comprises: controlling, for example influencing, (204a) a signal level (TX-PEG) with which the first integrated circuit (101) sends information, for example data, for example via a or the first communication channel (K-1), to the at least one further integrated circuit (102). [7] Method according to at least one of the preceding claims, comprising: providing (210) the test signal (TS), wherein, for example, the test signal (TS) has at least one, for example predefinable, signal pattern, for example test pattern, (TP), and, optionally, using (212) the test signal (TS; TS'). [8] The method according to claim 7, wherein the providing (210) comprises providing (210a) an encrypted test signal (TS') or test pattern (TP'). [9] Method according to at least one of the preceding claims, comprising: controlling (220), for example influencing (220a), a or the signal level (TX-PEG) with which the first integrated circuit (101) sends information, for example data, for example via a or the first communication channel (K-1), to the at least one further integrated circuit (102), for example based on the feedback (RM), wherein, for example, the controlling (220), for example influencing (220a), is carried out (220b) dynamically, for example during operation of at least the first integrated circuit (101), for example repeatedly, for example periodically, for example several times within a fault tolerance time. [10] Method for a second integrated circuit (102) arranged together with at least a first integrated circuit (101) on a substrate (104), comprising: receiving (250) a test signal (TS) from the first integrated circuit (101), evaluating (252) the received test signal (TS), creating (254), based on the evaluation (252), a feedback signal (RM) associated with the test signal (TS), sending (256) the feedback signal (RM) to the first integrated circuit (101). [11] Method according to claim 10, wherein the first integrated circuit (101) and the second integrated circuit (102) are each designed as a chip, for example a chiplet, wherein for example the first integrated circuit (101) and the at least one further integrated circuit (102) form a multi-chiplet system (1000). [12] Method according to at least one of claims 10 to 11, wherein a first communication channel (K-1) is used (250a) for receiving (250) the test signal (TS), wherein, for example, the first communication channel (K-1) is a main band of a communication interface (110) which connects at least the first integrated circuit (101) and the second integrated circuit (102) to one another, wherein, for example, the communication interface (110) is a, for example, unified, chiplet interface, for example of the Universal Chiplet Interconnect Express, UCle, type. [13] Method according to at least one of claims 10 to 12, wherein a second communication channel (K-2) is used (256a) for sending (256) the feedback (RM), wherein, for example, the second communication channel (K-2) is a sideband of a communication interface (110) which connects at least the first integrated circuit (101) and the second integrated circuit (102) to one another, wherein, for example, the communication interface (110) is a, for example, unified, chiplet interface, for example of the UCle type [14] Method according to at least one of claims 10 to 13, wherein the evaluation (252) comprises at least one of the following elements: a) checking (252a) the received test signal (TS), e.g. for correctness or agreement, e.g. with a, for example predeterminable, signal pattern, for example test pattern (TP), or b) analyzing (252b) a signal level of the received test signal (TS), or c) analyzing (252c) a signal quality of the received test signal (TS), or d) using (252d) at least one method based on artificial intelligence, for example machine learning, or e) using (252e) a multi-stage evaluation system. [15] Device (300) for carrying out the method according to at least one of the preceding claims. [16] Integrated circuit (101; 102), for example for a multi-chiplet system (1000) comprising a plurality of chiplets, comprising at least one device (300) according to claim 15, wherein, for example, the device (300) or a functionality of the device (300) is integrated into the integrated circuit (101; 102). [17] System, for example multi-chiplet system, (1000), comprising at least one device (300) according to claim 15 or at least one integrated circuit (101; 102) according to claim 16. [18] Product, for example control device (12), for example for a motor vehicle (10), comprising at least one device (300) according to claim 15. [19] Vehicle, for example a motor vehicle, (10), comprising at least one device (300) according to claim 15 and / or at least one product, for example a control device, (12) according to claim 18. [20] Computer-readable storage medium (SM) comprising instructions (PRG) which, when executed by a computer (302), cause the computer to carry out the method according to at least one of claims 1 to 14. [21] Computer program (PRG) comprising instructions which, when the computer program (PRG) is executed by a computer (302), cause the computer to carry out the method according to at least one of claims 1 to 14. [22] Data carrier signal (DCS) characterising and / or transmitting the computer program (PRG) according to claim 21. [23] Use (400) of the method according to at least one of claims 1 to 14 and / or the device (300) according to claim 15 and / or the integrated circuit (101; 102) according to claim 16 and / or the system (1000) according to claim 17 and / or the product (12) according to claim 18 and / or the vehicle (10) according to claim 19 and / or the computer-readable storage medium (SM) according to claim 20 and / or the computer program (PRG) according to claim 21 and / or the data carrier signal (DCS) according to claim 22 for at least one of the following elements: a) ensuring (401) data communication between the first integrated circuit (101) and the at least one further, for example second, integrated circuit (102), or b) increasing (402) a robustness of data communication with respect to the first integrated circuit (101), for example between the first integrated circuit (101) and the at least one further, for example second,integrated circuit (102), or c) increasing (403) a reliability of data communication with respect to the first integrated circuit (101), or d) increasing (404) an availability of the first integrated circuit (101) and / or a system (1000) comprising the first integrated circuit (101), or e) increasing (405) a design quality and / or manufacturing quality, for example based on feedback of findings from operation of the first integrated circuit (101).

Images