A buck power converter with pre-dropout control

Abstract

A buck converter is presented. The buck converter comprises a power stage with at least one phase, each phase comprising an inductor, a driver, and a clock source. The driver drives the power stage in a synchronous mode or in an asynchronous mode of operation with a minimum off-time. As the output voltage approaches the converter's input voltage, the converter's duty cycle increases to a value limited by the minimum off-time. The clock source generates a first clock signal with a predefined pulse width. The driver generates a first stretchable clock signal with an adjustable pulse width and an adjustable period. Upon transition from the synchronous mode to the asynchronous mode, the driver is configured to increase the adjustable pulse width and period of the first stretchable clock signal.

Description

Related ApplicationThis application relates to U.S. Patent Application Serial No. 16 / 533,691 filed August 6, 2019, which is hereby incorporated by reference in its entirety.Technical FieldThe present disclosure relates to a step-down converter; and more particularly, to a down converter operable in a synchronous mode and an asynchronous mode. The asynchronous mode may be referred to as pre-dropout (PDO) mode.BackgroundBuck converters typically used in chargers are often faced with the situation where the required output voltage is very close to the input voltage. This requires a duty cycle that exceeds the duty cycle that could be easily achieved based on a fixed period along with a fixed defined minimum off time.The duty cycle of buck converters is defined by the ratio of the output voltage to the input voltage. As the duty cycle approaches one, it is common for a buck converter (whether multi-stage or single-stage) to transition from a synchronous mode of operation to an asynchronous mode of operation. In a synchronous mode of operation, the turn-on of the power switch(s) is synchronous with a system clock signal. However, the on-time for a switching state is followed by a minimum off-time for that switching state. During low dropout operation, in which the input voltage is only slightly higher than the output voltage, synchronous operation is restricted by the minimum off time to shift the duty cycle in the direction of 100%. The maximum switching state on time set by the system clock signal minus the minimum off time limits the achievable duty cycle during synchronous operation.To increase the duty cycle for low dropout operation, it is common for the down converter to transition to an asynchronous operating mode in which the switching states are not turned on synchronously with the system clock signal. The on-time for a switching state may thus increase because it is no longer tied to the system clock signal period. The achievable duty cycle can thus be increased by an asynchronous operation.Thus, although asynchronous operation is advantageous, the buck converter must again transition back to synchronous operation as the duty cycle decreases.A fixed frequency may be chosen to optimize efficiency over the range of expected operating conditions including input and output voltage requirements as well as expected dynamic load range. This applies to both the simple buck converter and the hybrid converter. The multi-stage converters are a subset of the hybrid converters. Early methods to achieve this include stepwise lowering of the switching frequency as needed. With a longer period, a higher duty cycle is possible even with a minimum off-time constraint. In US 10998818B2 a method is presented which allows a smooth transition to and from the asynchronous mode, so that the period is naturally extended to maintain the required duty cycle, which allows an arbitrarily long period allowing a duty cycle close to one.However, in order to maintain regulation of the output voltage during the transition, the circuit proposed in US 10998818B2 uses a cycle timer. This increases the complexity and space requirement of the system. It is an object of the disclosure to solve one or more of the above-mentioned limitations.SummaryAccording to a first aspect of the disclosure, there is provided a step-down converter configured to receive an input voltage and provide an output voltage, the step-down converter comprising a power stage having at least one phase, each phase comprising an inductor; a driver configured to drive the power stage in a synchronous mode or in an asynchronous operating mode with a minimum off time; wherein as the output voltage approaches the input voltage, a duty cycle of the converter increases to a value limited by the minimum off time; a clock source configured to generate a first clock signal with a predefined pulse width; wherein the driver is configured to generate a first stretchable clock signal with an adjustable pulse width and an adjustable period; wherein the driver is configured to increase the adjustable pulse width and the period of the first stretchable clock signal at a transition from the synchronous mode to the asynchronous mode.Optionally, the driver comprises a first state machine configured to generate the first stretchable clock signal and adjust the pulse width and period of the first stretchable clock signal.Optionally, the first clock signal and the first stretchable clock signal are in phase.Optionally, the down converter comprises a first ramp generator configured to generate a first ramp signal in response to the first clock signal; and an error comparator configured to generate an error signal by comparing the output voltage to a reference voltage; wherein the pulse width of the stretchable clock signal increases as the error signal increases to a threshold.For example, the threshold may be set by a threshold of the first ramp signal. The threshold of the first ramp signal is an upper value that indicates how far the ramp signal is allowed to rise.Optionally, the down converter comprises a first comparator configured to compare the first ramp signal with the error signal, and wherein when the first ramp signal rises and becomes equal to the error signal, the comparator triggers and its output goes high.Optionally, if the first clock signal occurs before the comparator trigger event, the converter switches to asynchronous mode, otherwise the converter remains in synchronous mode.Optionally, the first state machine is configured to generate a first ramp reset signal to reset a first ramp signal; a first asynchronous mode signal indicating that the converter has entered the asynchronous mode; a first minimum off time trigger signal configured to trigger a start of a timer; and a first magnetization request signal configured to start inductor magnetization after expiration of the timer.Optionally, the down converter includes a first logic circuit coupled to the first state machine.Optionally, the first logic circuit comprises a plurality of persistence latches.For example, the persistence latches may include one or more wait cells and / or one or more arbiters.Optionally, the down converter comprises a second state machine coupled to a second logic circuit; wherein the second state machine is configured to generate a second extensible clock signal having an adjustable pulse width and an adjustable period.Optionally, the first logic circuit and the second logic circuit are configured to receive a logic signal for setting the state machine as master or slave such that when the first state machine is a master, the second state machine is a slave, and vice versa, when the first state machine is a slave, the second state machine is a master.Optionally, the down converter comprises a second ramp generator; wherein the second state machine is configured to generate a second ramp reset signal to reset the second ramp signal.Optionally, the second state machine is configured to generate a second asynchronous mode signal indicating that the converter has entered the asynchronous mode; a second minimum off time trigger signal configured to trigger a start of a timer; and a second magnetization request signal configured to start inductor magnetization after the timer expires.Optionally, the down converter comprises a minimum off time timer configured to start upon receipt of a trigger signal.For example, the minimum off time timer may comprise a constant current timer across the capacitor.According to a second aspect of the disclosure, there is provided a method of controlling a buck converter configured to receive an input voltage and provide an output voltage, the method comprisingproviding a driver configured to drive a power stage of the converter in a synchronous mode or in an asynchronous operating mode with a minimum off time; wherein as the output voltage approaches the input voltage, a duty cycle of the converter increases to a value limited by the minimum off time;generating a first clock signal having a predefined pulse width;generating a first expandable clock signal having an adjustable pulse width and an adjustable period; andin a transition from the synchronous mode to the asynchronous mode, increasing the adjustable pulse width and the adjustable period of the extensible clock signal.Optionally, the method comprises generating a first ramp signal in response to the first clock signal; generating an error signal by comparing the output voltage to a reference voltage; wherein the pulse width of the expandable clock signal increases as the error signal increases to a threshold.Optionally, the method comprises generating an enable signal to enable a transition between the synchronous mode of operation and the asynchronous mode of operation.Optionally, the method comprises generating a magnetization request signal for magnetizing the inductor.Optionally, magnetization of the inductor is initiated by expiration of a minimum off-time timer.According to a third aspect of the disclosure, there is provided a control device for use with a buck converter, the control device comprising a driver configured to drive a power stage of the converter in a synchronous mode or in an asynchronous mode of operation with a minimum off time; wherein as the output voltage approaches the input voltage, a duty cycle of the converter increases to a value limited by the minimum off time; a clock source configured to generate a first clock signal with a predefined pulse width; wherein the driver is configured to generate a first stretchable clock signal with an adjustable pulse width and an adjustable period; wherein upon a transition from the synchronous mode to the asynchronous mode, the driver is configured to increase the adjustable pulse width and the period of the first stretchable clock signal.DESCRIPTION OF THE DRAWINGSThe disclosure will be described in more detail below by way of example and with reference to the accompanying drawings, in which: FIG. 1 is a diagram of a power converter as described in US10998818B2; FIG. 2 is a flow diagram of a method for controlling a buck converter in accordance with the disclosure; FIG. 3A is a diagram of a power converter for implementing the method of FIG. 2 ; FIG. 3B is a diagram of the driver circuit used in the power converter of FIG. 3A ; FIG. 3C is a diagram of the PDO controller shown in FIG. 3B ; FIG. 4 is a diagram illustrating operation of the power conversion system of FIG. 3A ; FIG. 5 is a waveform diagram illustrating the interaction of two ramp signals with the magnetization request signals, the PWM peak detection signals, and the down clock; FIG. 6 is a timing diagram showing steady-state operation of the PDO controller in a normal (non-PDO) mode; FIG. 7A is a schematic diagram of a wait cell; FIG. 7B is a timing diagram illustrating the operation of the wait cell of FIG. 7A ; FIG. 8 is an example implementation of a MUTEX element or cell; FIGS. 9A, 9B, and 9C show a signal transition graph defining the order of causality of signals in the asynchronous finite state machine; FIG. 10 is an example implementation of a two-way arbiter; FIG. 11 is a waveform diagram illustrating the operation of a PDO controller as shown in FIG. 3C; FIGS. 12A and 12B show a more detailed transition from PWM to PDO operation; FIGS. 13A and 13B show a more detailed transition from PDO to PWM operation; FIGS. 14A and 14B show an example implementation of a sub-PDO controller as used in the PDO controller of FIG. 3C ; FIG. 15 is an example implementation of a minimum off time timer; FIGS. 16A and 16B illustrate the operation of a PDO controller with two synchronized ramps; and FIG. 17 is a diagram of a PDO controller implemented as a master controller.DESCRIPTION OF THE INVENTIONA power converter may operate in various modes, including a pulse width modulation (PWM) mode and an asynchronous pre-dropout mode or simply pre-dropout (PDO) mode. In the PWM mode, the switching activity of the power switches is controlled by a synchronous clock. In the PDO mode, the on-time of the power switches is controlled by a loop and the off-time is a fixed value that allows for any length of time that allows for a duty cycle close to one. Therefore, the switching activity is no longer controlled by a synchronous clock.FIG. 1 is a diagram of a multi-stage buck converter configured to transition between synchronous and asynchronous modes during low dropout operation as described in US 10998818B2.The multi-stage down converter 100 regulates output power at transitions between synchronous and asynchronous modes of operation.The multi-stage buck converter 100 includes switching transistors A, B, C, and D arranged in a conventional manner. In particular, switching transistor A has a first terminal connected to a node for an input voltage V_IN and a second terminal connected to a first terminal for a flying capacitor CF. Moreover, the second terminal for switching transistor A is connected to a first terminal for switching transistor B. As used herein, a transistor "terminal" refers to, for example, a drain or source terminal for a MOS field effect transistor. A second terminal for switching transistor B is connected to a switch (SW) terminal for an inductor L 1 connected to an output capacitor C 1 to smooth an output voltage V_OUT. The first terminal of the switching transistor C is connected to the SW node (the input node for the inductor L 1), and the second terminal is connected to a remaining terminal for the flying capacitor CF. In addition, the second terminal of the switching transistor C is connected to a first terminal of the switching transistor D, whose second terminal is in turn connected to ground.An error amplifier 130 generates an error signal voltage (ERV_OUT) in response to a difference between the output voltage and a reference voltage (REFV_OUT). The error signal is compared to two ramp signals that are 180° out of phase with each other (note that other phase relationships may be used in alternative embodiments). A first ramp generator 105 generates a first ramp signal in response to a clock signal (CLK) from a clock source 110. A second ramp generator 115 generates a second ramp signal in response to an inverted clock signal (CKL_B) from the clock source 110. The second ramp signal is thus 180° out of phase with the first ramp signal. A first comparator 120 compares the first ramp signal with the error signal to generate a first control signal 121. Similarly, a second comparator 125 compares the second ramp signal with the error signal to generate a second control signal 126.During synchronous operation, where the error signal is not too great, a rising edge of the clock signal CLK sets a reset set (RS) latch 135 to enable a first magnetizing signal (MAG 1). The rising edge of the clock signal CLK also triggers a first ramp generator 105 to begin ramping the first ramp signal. Once the first ramp signal rises to equal the error voltage, the first control signal 121 resets the RS latch 135 to reset (discharge) the first magnetizing signal. In synchronous operation, a rising edge of the complement clock signal CLK_B sets an RS latch 140 to enable a second magnetizing signal (MAG 2). The rising edge of the complement clock signal also triggers a second ramp generator 115 to begin ramping the second ramp signal. Once the second ramp signal rises to equal the error voltage, the second control signal 126 resets the RS latch 140 to reset (discharge) the second magnetizing signal.A switching controller and driver circuit 150 processes the first and second magnetization signals to determine the switching states during synchronous operation. For brevity, the switching controller and driver circuit 150 will be referred to simply as switching controller 150 in the following discussion. Switching transistors A, B, C, and D may be configured into one of four switching states, referred to herein as a D 1 switching state, a D 2 switching state, a DV switching state, and a DP switching state (see FIG. 1 insert). In the switching state D 1, the switching transistors A and C are turned on and the switching transistors B and D are turned off. In the switching state DV, only the switching transistors C and D are turned on. In the switching state D 2, only the switching transistors B and D are turned on. Finally, in the switching state DP, only the switching transistors A and B are switched on.The switching controller and driver circuit 150 interprets the Mag1 and Mag2 signals and creates the sequence. The high conversion rate (HCR) sequence is DP / D1 / DP / D2, where DP is magnetizing and D1 and D2 are two different paths used for demagnetization. The low conversion rate (LCR) sequence is D 1 / DV / D 2 / DV, where D 1 and D 2 are two different paths of magnetization, while DV is demagnetization. Thus, D1 and D2 may be either magnetizing (when in LCR) or demagnetizing (when in HCR). The decision as to whether to make a magnetizing signal D1, D2 or a DP is made within the block 150 based on the overlapping conditions of the two mag signals. When they overlap, they create a DP. If it underlaps (neither of them applies), a DV is created. If one is present and the other is not, then D1 is for Mag1 and D2 is for Mag2.Synchronous operation depends on the duty cycle, which in turn determines whether the error signal is less than 50% or greater than 50% of a center of the peak voltage for the two ramp signals (half the peak voltage). As the error signal rises, the on-time for the switching state D1 approaches the period for the clock signal. However, there is a minimum off time that prevents the first magnetization signal from having an on time corresponding to the clock period. Should the on-time for the first control signal 121 from the comparator 120 exceed the clock signal period minus the minimum off-time, the first control signal 121 is reset even if the first ramp signal has not yet increased to equal the error signal. A minimum off-time timer 122 timates the minimum off-time period. For example, the minimum off-time timer 122 may be formed by shifting the clock signal by the minimum off-time period. In such an embodiment, the minimum off-time timer 122 would activate the shifted clock signal at the beginning of the minimum off-time period prior to activation of the clock signal.The switching controller 150 monitors whether the first magnetization signal had to be reset due to the minimum off-time request to determine whether to transition from synchronous operation to asynchronous operation mode in which there is a relatively small dropout between the input voltage and the output voltage. In one embodiment, the switching controller 150 counts the number of successive cycles for the clock signal in which the first magnetizing signal was reset due to the minimum off-time request. For example, the shift control device 150 may transition to an asynchronous operation mode when the number is four.Regardless of how the transition to the asynchronous mode is triggered, the beginning of the on-time for the magnetizing signals is no longer synchronous with the clock signals. During asynchronous operation, the switching controller 150 activates an asynchronous trigger signal to trigger the first ramp generator to begin ramping the first ramp signal and to set the RS latch 135 to set the first magnetizing signal. The first magnetizing signal is reset in asynchronous mode only when the first ramp signal has increased equal to the error signal, even if the resulting on-time for the first magnetizing signal may exceed the clock signal period. Once the first magnetizing signal is reset, it is kept off for the minimum off time, and then the first ramp signal is triggered by the asynchronous trigger signal to restart ramping while the first magnetizing signal is set. Both the first ramp signal and the first magnetization signal are thus separated from the clock signal during asynchronous operation. Activation and deactivation of the second magnetization signal is analog during the asynchronous mode, as further explained herein.The asynchronous operation thus allows a sufficiently long on-time of the first magnetizing signal so that the output voltage can be maintained at a desired level despite a relatively small drop between the output voltage and the input voltage. However, once the duty cycle begins to drop, the shift controller 150 must again transition back to synchronous operation. A conventional transition from asynchronous to synchronous operation typically leads to a considerable disturbance of the output voltage. To prevent this disturbance and maintain regulation of the output voltage during the transition, the switching controller 150 uses a cycle timer 165 that timates a cycle timer period that is shorter than the clock signal period.FIG. 2 is a flow diagram of a method for controlling a buck converter in accordance with the disclosure. The buck converter may comprise one or more phases, each phase comprising an inductor. Each phase may include a high side power switch coupled at a switching node to a low side power switch. It is obvious that there may be more than two switches per phase. For example, each inductor phase may have four switches (see FIGS. 1 and 3A ).In step 210, a driver is provided. The driver is configured to drive a power stage of the converter in a synchronous mode or in an asynchronous mode of operation with a minimum off time. As the output voltage of the converter approaches the input voltage received by the converter, the duty cycle of the converter increases to a value limited by the minimum off time.In step 220, a first clock signal having a predefined pulse width is generated. The first clock may be referred to as a first buck clock. In step 230, a first stretchable clock signal having an adjustable pulse width and an adjustable period is generated.In step 240, the adjustable pulse width and adjustable period of the expandable clock signal are increased upon transition from the synchronous mode to the asynchronous mode. The cycle period may be stretched as needed when the on-time is stretched beyond the normal period limit as defined by the down clock.An error signal may be generated by comparing the output voltage to a reference voltage. The pulse width of the expandable clock signal increases as the error signal increases to a threshold. For example, the threshold may be set by a threshold value of a ramp signal. The threshold value of the ramp signal is an upper value that indicates how high the ramp signal is allowed to rise. This also sets a minimum frequency (longest period) which is allowed to achieve the desired duty cycle. When this limit is reached, the converter changes from PDO to DO; that is, the signal starts to decay, i.e., falls under the regulation.FIG. 3A is a diagram of a power converter for implementing the method of FIG. 2, and power converter 300 is similar to power converter 100 of FIG. 1, and the same reference numerals are used to represent corresponding components as described in FIG. 1. Compared to the converter of Figure 1, cycle timer 165 has been removed and block 150 is replaced by a driver 350 which includes a PDO controller 360. Consequently, the power converter can be implemented on a smaller chip area.The circuit 300 may be referred to as a hybrid multi-stage converter (3th in this case). The Mag1 signal represents the master signal, while the Mag2 signal represents the slave signal. Mag2 maintains a phase relationship to the Mag1 signal of 180 degrees. It will be appreciated that additional phases may be added at different phase angles.The input S of the (RS) latch 135 may be driven by the clock source 110 (buck_clk1 signal) or by the driver 350 (ramp_reset_1_ph1 signal). In non-PDO operation, latch 135 is driven by the clock source and in PDO mode, it is driven by PDO controller 360 within driver 350. The RS latch 135 will be referred to as a D1 PWM latch later in FIG. 4.FIG. 3B is a diagram of the driver circuit 350 used in the power converter of FIG. 3A. The driver circuit 350 includes a high-side driver 351 for driving the high-side power switches A and B; and a low-side driver 352 for driving the low-side power switches C and D. The driver is further provided with a PDO controller 360 and a driver finite state machine 353. The driver state machine controls the high-side and low-side drivers based on the magnetization signals "mag_req 1" and "mag_req 2" provided from the PDO controller 360.FIG. 3C is a diagram of the PDO controller 360. The PDO controller 360 includes a first PDO controller 361 (also referred to as a first sub-PDO controller) for controlling the operation of the first ramp generator 105, and a second PDO controller 362 (second sub-PDO controller) for controlling the operation of the second ramp generator 115. The first sub-PDO controller includes logic circuitry 361 acoupled to a finite state machine (FSM) 361 b. Similarly, the second sub-PDO controller includes logic circuitry 362 acoupled to a finite state machine (FSM) 362 b. The first and second control devices 361 and 362 are arranged in the same manner.The logic circuit receives multiple signals including the master clock "buck_clk", a master / slave signal "m_sb", an enable signal "pdo_en", a pdo input signal "pdo_in", and a comparator signal "pwm_n", an inverted comparator output from the PWM comparator (120 / 125).If m_sb is true, the controller is a master, otherwise it is a slave. If pdo_en is true, the system is allowed to enter pre-dropout mode to achieve the required duty cycle. If false, the system does not enter the pre-dropout mode even if the error amplifier requests a duty cycle that exceeds what would be possible given the fixed cycle time and the minimum off time. The pdo_in signal comes from the master pdo output to notify the slave pdo that the master is in the pdo mode.The FSM is configured to generate multiple signals including the stretched clock signal "clk1s", the ramp reset signal "ramp_reset" used to reset the ramp, the trigger signal "min_toff_trig"the asynchronous mode signal "pdo" indicating that the converter has transitioned to the asynchronous mode, and the magnetization request signal "mag_req" configured to start the inductor magnetization.FIG. 4 is a diagram illustrating operation of the power converter of FIG. 3A. Two regions are shown representing operation in synchronous mode and asynchronous mode. In this example, the synchronous mode is referred to as a normal PWM sequence and the asynchronous mode is referred to as a pre-dropout sequence. For convenience of description, the various states are numbered from state 1 to state 15.The synchronous mode (normal PWM sequence) comprises the states 1, 2, 3, 4, 5, 6 and 7. the asynchronous mode (pre-dropout sequence) comprises the states 10, 12, 13, 14, 15, 1, 2 and 3. the states 1, 2 and 3 are thus overlapping states used in both modes. State 11 is the transition state from synchronous mode to asynchronous mode.The process begins with state 1. In state 1, the system (in this case the state machine) waits for the rising edge of the buck clock. When the rising edge of the clock is detected, a stretched clock "clk1s" is asserted true in state 2. Next, in state 3, the system evaluates whether or not the PWM comparator (120 / 125) has triggered. A voltage ramp (of 105 / 115) begins to rise at the point at which the magnetizing signal (Mag 1 / Mag 2) is initiated. This is because the Mag1 signal initiates the ramp_reset signal. This has not yet taken place. The Mag1 signal corresponds to an on-time for the down converter. After the magnetization signal is initiated, the ramp begins to rise. When the ramp exceeds the output (ERV_OUT) of the error amplifier (130), the PWM comparator (120 / 125) triggers (goes high) causing the PWM on time to end, resetting the D1 PWM latch (135 / 140) in the diagram.If the D1 PWM latch (135 / 140) is not set, the system goes to state 4, otherwise it goes to state 10. in state 4 a min_off timer (122) is triggered (by the min_off_trig1 signal) and after its expiration the system goes to state 5 in which the PWM latch (135 / 140) is set and the inductor magnetization is started. This also results in a reset of the stretched clocks clk1s as the system proceeds through state 6.Once the inductor magnetization has begun, the system waits in state 7 to determine with an asynchronous arbiter whether the clock occurs first or the PWM comparator triggers first. When the PWM comparator triggers first, the inductor magnetization is terminated and the system returns to state 1 and waits for the next rising edge of the buck clock. Then, another cycle of the normal operation is performed.However, if the system is in state 7 in which we have just completed the stretched clock CLK1S and started the inductor magnetization, and if the buck clock edge occurs before the PWM comparator trigger event, then the system proceeds from state 7 to 11 rather than to state 1. This is because the duty cycle is large enough that the system requires a longer buck clock cycle period to achieve the required duty cycle while meeting the minimum off-time requirement.State 11 sets the stretched clock CLK1s and then proceeds to state 10. State 11 also sets a pre-dropout (PDO) signal, which notifies the system that it has entered the pre-dropout mode.In state 10, the system waits for the completion of the triggering of the PWM comparator. This is because the clock edge occurred before the triggering event of the PWM comparator. Once the PWM comparator has triggered, the minimum toff timer is triggered again in state 12 and the stretched clock is deactivated in state 13. Once the minimum toff time has elapsed, the PWM signal is set and a new inductor magnetization begins immediately at state 14.The system then proceeds to state 15. In this state, either a buck clock or a PWM comparator trigger may occur and the occurrence of one or the other event indicates whether the system should proceed to the pre-dropout (PDO sequence) or return to the normal PWM sequence.When the clock edge occurs first, the system goes to state 2 where it sets the stretched clk1s pulse. This is likely the direction to exit state 15 if the system continues to require continued pre-dropout operation. However, if the PWM comparator triggers first, the state machine goes to state 1 where it waits for another buck clock before proceeding. In this case, the PDO signal is reset and the system continues in the normal PWM mode.If the system has exited state 15 by the clock edge, then state 2 sets the stretched clock signal CLK1s and state 3 is entered. In this case, it is detected in state 3 that the PWM comparator has not been triggered and the method is continued again in state 10 in order to repeat the pre-dropout cycle.In summary, the state order for the PWM sequence is 1, 2, 3, 4, 5, 6, 7, 1,..., etc.When entering the pre-dropout, the state order goes from 7 to the following: states 11, 10, 12, 13, 14, 15, 2, 3 and back to 10.The proposed down converter provides a smooth transition to and from the "asynchronous dropout mode" while maintaining a relatively simple design. In particular, no cycle timer is required.FIG. 5 is a waveform diagram showing the following signals:The buck clock signals "buck_clk 1" and "buck_clk 2" generated by the clock 110 for the high side and low side, respectively.The magnetization request signals "mag_req_1_ph1" and "mag_req_2_ph1"generated by the high side and low side latches 135 and 140, respectively.The peak PWM detection signals "pwm_n_1_ph1" and "pwm_n_2_ph1"generated via the PWM comparators 120 and 125 for the high side and low side, respectively.The ramp reset signals "ramp_reset_1_ph1" and "ramp_reset_2_ph1"generated by the FSMs 361 band 362 band received by the ramp generators 105 and 115, respectively.The minimum toff restart signals "min_toff_trig1_ph1" and "min_toff_trig2_ph1"generated by the state machines 361 band 362 b; and the minimum toff return signals "min toff_rtnl_ph1" and "min_toff_rtn2_ph1".Also shown is signal "m_hpwm_n" - this is a similar signal to pwm_n above, but indicates that an alternative ramp has exceeded the error amplifier input.Also shown are the ramp signals ramp_ 1 510 and ramp_ 2 520 generated by the ramp generators 105 and 115, respectively, and the error amplifier voltage ERV_OUT 530 from the error amplifier 130.FIG. 5 shows the interaction of ramp signals 510 and 520 with magnetization request signals "mag_req_1_ph1" and "mag_req_2_ph1"PWM peak detections (pwm_n_1_ph1 and pwm_n_2_ph1), and the buck clock. In the normal synchronous mode shown, the buck clock starts a "min_off_trig" signal. After the minimum off time has elapsed, "min_toff_rtn" is activated. This causes a "mag_req" and a "mag_ack" which is not shown. This starts the ramp. When the ramp exceeds the error amplifier voltage 530, the signal "pwm_n" goes low, ending the magnetization and resetting the ramp. In the figure, two channels with 180 degrees of interleaved phase are shown. The inverse of the ramp_reset signals is effectively the magnetizing output.FIG. 6 is a timing chart showing the steady-state operation of the PDO control in the normal (NOT-PDO) mode. The arrows represent causality triggered by a rising or falling edge. The timing diagram shows the buck clock labeled "vco_clk" and a persistent version of the buck clock signal "vco_clk_pers". The persistent signal "vco_clk_pers" is the clock signal "vco_clk" as seen by an asynchronous wait cell controlled by the signal clk_1_go.Also shown is the stretched clock "clk1s". Its rising edge starts with the buck clock and its falling edge is based on the termination of the minimum off time timer "min_off_rtn" (see state 4 in FIG. 4 ). At the rising edge of the stretched clock clk1, the signal min_off_trig, which is the start of the minimum off-time timer, is activated. When this minimum off time is reached, the min_off_rtn signal is returned by the timer and must also be causally asserted by the state machine before it is deasserted. This works in a similar manner to the signal vco_clk_pers with the wait cell.The expiration of the timer then also leads to the beginning of the inductor magnetization, which is referred to as a signal with the designation PWM 1. Once this signal becomes true, the ramp begins to rise in voltage and when it exceeds the error amplification threshold, the PWM comparator signal is seen (see FIG. 5 ) and a persistent version thereof, labeled pwm_comp_pers, is seen by the asynchronous state machine. This results in termination of the inductor magnetization and we return to state 1 where we again wait for the next buck clock.FIG. 7A is a schematic diagram of a wait cell. A wait cell is also referred to as a persistence latch and is used in asynchronous circuits to detect a signal and present it to another asynchronous circuit as a persistent signal that remains there until its existence is causally confirmed.The wait cell comprises a MUTEX (Mutual Exclusion) cell with two inputs R1, R2 and two outputs G1, G2. The input R1 receives an input signal "in" via an inverter. The second input R2 is coupled to an AND gate receiving a reset signal rst_n and a go signal from an asynchronous circuit, for example an asynchronous state machine. The output G2 supplies the persistent signal "in-pers" to the asynchronous circuit.FIG. 7B is a timing diagram illustrating the operation of the wait cell of FIG. 7A. The asynchronous state machine awaits causal acknowledgement of all incoming signals. It effectively opens a time window when it searches for the presence of a signal (in this case referred to as "in"). This is done by activating the go signal. The MUTEX permits only grant 1 (G1) or grant 2 (G2). If both requests R1 and R2 are high, the corresponding grant R1->G1 or R2->G2 is issued only for the first-arrived request. After the grant is initiated, it remains true until its request is disabled. If the "in" signal prior to the go signal is low, the R1 input of the mutex is true while R2 is low and therefore G1 is output and remains true until R1 disappears. Then, the asynchronous circuit activates the go signal. Although R2 is output, G2 is not output until R1 is deactivated. When "in" becomes true, R1 is disabled causing G1 to turn off and since R2 is now still high, G2 eventually goes high. Once this occurs, it is never turned off until the go signal is disabled. This forces the persistent version of the signal to remain present as long as the asynchronous state machine needs to confirm its existence.FIG. 8 is an example implementation of a MUTEX element or cell.The MUTEX cell consists of an SR latch circuit receiving R1 and R2 coupled to a filter circuit providing G1 and G2. The MUTEX cell is configured to determine the order in which two input signals change with certainty. The main purpose of the MUTEX element is to capture each metastable event in itself and not allow that event to propagate to its output pins. Thus, if the SR latch becomes metastable because both R1 and R2 are activated within a metastable window time of each other because the outputs SR1 and SR2 are at VDD / 2, the N-channel FETs in the filter will both be on and the outputs G1 and G2 will both remain low until the metastability is resolved into itself. Only after this time is the winner allowed the inputs as output.FIGS. 9A, 9B, and 9C show a signal transition graph (STG) defining the sequence of causality of signals in the asynchronous finite state machine (AFM). The signals shown in parentheses are inputs to the state machine. The other signals are outputs of the state machine. The circled numbers correspond to the state numbers in Figure 4.The signals shown in brackets are internal signals that are present within the STG and are not brought out. They serve no purpose other than making the circuit synthesizable because they are used to resolve coding state conflicts. The state variable is the concatenation of the input, output and internal signals, and without the internal there are multiple locations in the state machine where the state of all signals is the same. This is solved by adding state bits, referred to as internal signals, so that each token location represents a unique, different state coding.The inputs were processed by a type of persistent latch similar to the wait cell in FIG. 7A and by arbiters including two-way arbiters. These devices are a special form of persistence latch that monitors two input signals "sig1" and "sig2" rather than one; and waits for the first to appear and its corresponding grant is set until it is asserted.Using a tool called Workcraft, this STG is compiled to logic gate circuitry that forces the causality of the output signals as long as the input signals (in brackets) belong to the causality also described in this diagram. The input signals are forced to pass causality relationships through the use of persistence latches and arbiters.FIG. 10 is an example implementation of a two-way arbiter. Arbiter 1000 comprises three MUTEX cells labeled g4, g4a, and g5. The first MUTEX cell g4 receives a signal sig1 via the inverter g1. The second MUTEX cell g3 receives a signal sig2 via the inverter g3. The third MUTEX cell g5 receives G2 outputs from g4 and g4a, respectively. Also provided are three AND gates designated g0, g8 and g7. The end gate g0 receives a control signal "ctrl" and a reset signal "rst_n". The end gate g8 receives the output G1 of g5 and the output of g0, and provides the signal me1. Similarly, the end gate g7 receives the output G2 of g5 and the output of g0, and provides the output me2.The function of the above 2-way arbiter is that when the ctrl input goes high, both mutex elements g4 and g4a have set R2. When sig1or sig2takes place, the respective mutex will activate its G2, which goes to the inputs R1or R2of g5, respectively. Element g5 determines the winning machine (which has occurred first). It will activate G1 or G2, which activates the mutually exclusive outputs me1 or me2 via g7 and g8. Which is set, it remains guaranteed to be set up to the ctrl signal (similar to the go signal in a simple persistence latch). This ensures that the signal seen by the circuit synthesized from STG of Figure 9 only sees persistent inputs.FIG. 11 is a waveform diagram illustrating the operation of a PDO controller, also referred to as a PDO module, as shown in FIG. 3C. Operation is for one inductor phase but two (180 degrees) ramp phases as shown in FIG. 3A. FIG. 11 shows the following signals:The buck clock signals "VCO_clk1" and "VCO_clk2" generated by the clock 110 for the high side and low side, respectively.The stretched clock signals "clk1s" and "clk2s".The PWM peak detection signals "D1_pwm" and "D2_pwm"generated by the PWM comparators 120 and 125 for the high side and low side, respectively. These signals correspond to "pwm_n_1_ph1" and "pwm_n_2_ph1" in FIG. 5.The minimum toff signals "Min_toff_D 1" and "Min_toff_D2".The signals "PWM Comp 1" and "PWM Comp 2". PWM_Comp1 is the raw comparator output that is inverted to generate D1_pwm(pwn_n_1_ph1).Also shown are the ramp signals ramp_ 1 1110 and ramp_ 2 1120 generated by the ramp generators 105 and 115, respectively, and the error amplifier voltage ERV_OUT 1130 from the error amplifier 130.Also shown are the output or load current 1140 and the inductor current 1150.As the error amplifier voltage ERV_OUT 1130 rises, the ramps 1110 and 1120 become higher and higher, resulting in broader cycles of the stretched clocks CLK1S and CLK2S whose falling edges define the new buck cycles.FIGS. 12A and 12B show a more detailed transition from PWM to PDO operation.FIGS. 13A and 13B show a more detailed transition from PDO to PWM operation.FIGS. 14A and 14B show an example implementation of a sub-PDO controller as used in the PDO controller of FIG. 3C. For the sake of clarity, the diagram is divided into two figures. The designations A, B... H indicates the connections between the elements of Figures 14A and 14B.The main block labeled g0of the PDO controller 1400 represents the finite state machine FSM (e.g., 361 bin FIG. 3C ), while the other elements for the logic circuit (e.g., logic circuit 361 ain FIG. 3C ). Block g0 is the FSM implementing the STG of Fig. 9. The remainder of the logic is used to connect and surround block g0 with persistent signals. The logic circuitry of the PDO controller or module 1400 includes 3 signal multiplexers (g9, g13, g7) and 8 persistence latches comprising 5 wait cells (g5, g6, g17, g18, g21) and 3 two-way arbiters (g1, g2, g8).The multiplexers are used to allow the PDO module to be a "master" or "slave.". For example, in a two-ramp system, the first ramp may be the master and the second may function as a slave. This is forced to ensure that the channels remain synchronized with each other and that both operate in PDO or PWM without one of them being in one mode and the other in the opposite mode.To explain the operation of the PDO control block, the outputs and inputs are first defined.The AFM (block g0) provides five output signals comprising:i) clk1s - this is the "stretched clock". In design, this is mainly a debugging signal that is output but is not used by any of the surrounding circuits. This signal can be observed and how the clock is modified can be seen very well.ii) ramp_reset - this signal is used to reset the ramp. It is generated by the pwm output of the STG circuit. When ramp_reset is low, the ramp increases when PWM is true. The ramp is reset to 0 when PWM is not true. For example, referring to FIG. 5, ramp 520 begins to rise as ramp_reset_1_ph1 goes low. When it again becomes true, the ramp falls back to the socket value.iii) min_off_trig - this is the trigger for a timer based on a constant current capacitor timer (Ion C) combined with a mutex element which indicates by the min_off_rtn signal (bottom in the inputs) that the minimum off time has expired. The I-on-C timer is shown in Fig. 15.IV) PDO - a signal indicating that STG has entered the pre-dropout mode; that is, the duty cycle has risen beyond the point at which it can be picked up without lengthening the cycle to maintain the required minimum off time.v) mag_req signal to the driver state machine 353 that the inductor magnetization is to begin.In addition, inverter g12 provides another output signal labeled "one_shot_trig" to the logic circuit - a signal driving a one shot that produces a short pulse at the leading edge of the m_hpwm_n signal (input of g12). This is provided to let the comparator output appear rather like the pwm_n signal, which is present only briefly. Its width determines how far the two ramps may deviate from each other without causing problems.The input signals include:i) buck_clk - this is the master clock in the system and defines the cycle boundaries if not in the pre-dropout mode. The buck_clk is received from g9.ii) m_sb - master / slave bar signal. If true, the module is a master channel and can control the other channels. If false, the module is a slave and then receives input on the pdo_in signal (described below). This feature is used to ensure that all ramp phases are in the same mode at all times. The signal m_sb is received by g19 and g7.iii) pdo_en - enable signal. If true, the system is allowed to go to the pre-dropout mode to achieve the required duty cycle. If false, the system does not enter the pre-dropout mode even if the error amplifier requests a duty cycle that exceeds what would be possible given the fixed cycle time and the minimum off time. The signal pdo_en is received by g3, g15 and g7.iv) pwm_n - this is the inverted comparator output, which notifies the system that the ramp has exceeded the error amplifier input. The signal pwm_n is received from g11.v) m_hpwm_n - this is a similar signal to pwm_n above, but it indicates that an alternative ramp has exceeded the error amplifier input. It may be used instead of pwm_n when the channel is a slave and when in pre-dropout mode. The signal m_hpwm_n is received from g12, g18, and g21.vi) pdo_in signal coming from the master pdo output to inform the slave pdo that the master is in pdo mode. For simplicity, this input should also be controlled at the master from the pdo output of the same master. The signal pdo_in is received by g22.vii) min_off_rtn - works together with the output "min_off_trig" as an indicator for the block that the time has elapsed since the occurrence of the trigger, i.e. the minimum off time. The min_off_rtn signal is received from g17.viii) ss_done - soft start done. This signal is used to ensure that the slave channel stops magnetizing when its own ramp crosses the error amplifier input in pre-dropout mode; otherwise it would use the m_hwpm_n signal. At system power-up, the error amplifiers for some phases may not be well matched, since the load distribution is not yet balanced. This signal is provided to the block so that it notifies the block when load balancing has occurred for multiple inductor phases, meaning that the error amplifiers are likely balanced and the slave can safely use the alternate ramp input. The signal ss_done is received by g21.ix) mag_ack - an input for confirming that the system has output the inductor magnetization requested by the output signal "ma&-req". The mag_ack signal is received from g0.x) one_shot_rtn - the return of the one-shot trigger triggered by the signal "pdo_in".The PDO controller or module contains 3 signal multiplexers (g9, g13, g7) and 8 persistence latches comprising 5 wait cells (g5, g6, g17, g18, g21) and 3 two-way arbiters (g1, g2, g8).The g9 multiplexer is used to select the source of the buck clock. If the module is a master, then this is always the buck clock input. But if it is a slave AND if pdo_en is true AND if the pdo_in signal from the master is true, then in this case the m_hpwm_n signal serves as a buck clock so that the slave remains synchronized with the master during pre-dropout operation.The g13 multiplexer is used to select the source of the peak detection signal used to end magnetization. If the PDO module is a master, then the source of this signal is always pwm_n. If it is a slave AND pdo_in is true, indicating that the master is in PDO mode AND pdo_en is true AND ss_done was seen, then the source of this signal is m_hpwm_n. Note that if m_hpwm_n is the clock and the peak comparison, it defines the pre-dropout magnetization itself that keeps the slave aligned with the master in a prescribed phase.The third multiplexer is g7 and is used to construct the pdo_en_y and pdo_en_n signals for the g2 arbiter, which is used by the FMS g0 as a sampler to determine whether it can go into the pdo portion of the FSM.The persistence latches (or sanitization registers, as sometimes referred to) are as follows:The wait cell g18 is used as a latch that samples pdo_in. It uses the m_hpwm_n signal as a clock. The wait cell g21 makes the same for the ss_done input. The two above-mentioned wait cells do not clean signals for the FSM g0, but are used as latches in the external logic. The wait cell g17 is used together with an I-on-C timer to clear the min_toff_rtn signal.The STG of Fig. 9 and the circuit of Fig. 14 represent one possible embodiment of a PDO controller. It is obvious that other designs are also conceivable.For a simple buck, a single sub-PCO controller would be used. For a converter circuit as shown in FIG. 3A, two PDO sub-controllers are used as shown in FIG. 3C. Other converters with more inductor phases are conceivable. For example, a converter with two inductor phases, both multi-stage (MLC), would require 4 sub-PDO converters, i.e., 1 master and 3 slaves.FIG. 15 shows an example implementation of the minimum off time timer 122 of FIG. 3A. In this example, the timer 122 is provided by an I-on-C timer constructed using the wait cell.The FSM outputs the signal min_off_trig, which is received by the AND gate in FIG. 15 and is shown as "go signal". This activates the "trig" signal provided to the I-on-C timer 1510. This in turn allows current to flow into the capacitor C 1, thereby increasing the voltage across the capacitor. If it exceeds the gate threshold (a comparator may be used for accuracy), the "rtn" signal will go to the mutex cell 1520 via the inverter and cause the "done" signal to be set high. As a result, the charging of the capacitor C 1 is turned off and discharged. The switching constant current source I1 is used to generate a linear ramp across the capacitor C1. The rtn output may be disturbed, but Mutex 1520 causes the done signal to have no disturbance and remain true until the go signal disappears. The go signal is not disabled until the done signal associated with the FSM min_off_rtn signal is seen; thereby providing the required causal confirmation.The two-way arbiter g2 is provided as a sampler by applying the true and complement values of the same signal to its two Sig inputs. Thus, when ctrl is asserted, either me1 or me2 is asserted and these outputs are connected to inputs pdo_en_y_pers (persistent yes) and pdo_en_n_pers (persistent no) of FSM g0. Each time the FSM loops through it, when it wants to go to the pre-dropout mode, it will scan this arbiter to determine whether or not it can go to it.The two-way arbiter g8 determines whether the buck clock or the PWM comparator trigger occurs first. This corresponds to state 7 in the STG of FIG. 9B (as well as the flowchart of FIG. 4 ). The FSM uses this to determine whether or not it wants to attempt to go to the pre-dropout mode. When the clock comes first, this indicates that a higher duty cycle is required than can be provided in the fixed cycle time with the fixed min_off request.The two-way arbiter g1 again determines whether the buck clock or the pwm comparator trigger occurs first. This corresponds to state 15 of the STG in FIG. 9B. In this state we determine whether we remain in the pre-dropout mode or return to the PWM mode. If the comparator triggers first, we leave the pre-dropout mode, but if the clock takes place first we remain in the pre-dropout mode.The wait cell g5 monitors the pwm_n signal (or its replacement in slave mode). This corresponds to state 10 of the STG in FIG. 9C (as well as the flow chart in FIG. 4 ).The wait cell g6 monitors the buck clock (or its replacement in slave mode). This corresponds to state 1 of the STG in FIG. 9A (as well as the flowchart in FIG. 4 ).Figures 16A and 16B show the operation of a PDO controller with two synchronized ramps.FIG. 16A shows the logic signal "m_hwpm_n" as one of the input signals received from the logic circuit of FIG. 14A (see g12, g18, and g21). The falling edge of the m_hwpm_n signal causes the signal "one_shot_trig" (output of g12). In PDO mode, this acts as a buck clock for the slave, so that the slave remains synchronized 180 degrees out of phase. The signal "m_hpwm_n" is a comparator output whose threshold is at 1⁄2 of the value of the error amplifier output, so that this is the beginning of the second channel ramp in the middle of the duty cycle. This should naturally coincide with the time at which the second ramp reaches its peak. However, there may be a finite difference in ramp rates.The one shot is generated to be wide enough that these two events overlap. This same capability can be used for additional channels. For example, at 4 ramps there could be a 1⁄2, 1⁄4 and 3⁄4 error amplifier signal based on the channel 1 ramp for channels 2, 3 and 4.FIG. 17 is a diagram of a PDO controller 1700 implemented as a master controller. The PDO controller 1700 includes an FSM and logic 1705, an I-on-C timer 1710, two delay modules 1730 and 1740, and a one-shot trigger 1750. The FSM and logic 1705 may be implemented as described in FIGS. 14A and 14B. The signal labeled pdo1_ph1 on the right side of 1705 is also fed back to the pdo_in signal on the left side of 1705. The I-on-C analog timer 1710 receives the ramp_reset signal from the FSM and logic 1705 which acts as the master. The main ramp generator comprises current source I1, capacitor C1 and comparator U4. Comparator U4 has an inverting input receiving the error amplifier output labeled IEA and a noninverting input receiving vramp1_ph1 (output of the I-on-C timer). Comparator U4 compares signal vramp1_ph1 with signal IEA to provide raw trigger output pwm_r1_ph1 which goes to the pwm_n input of FSM 1705.The min_off timer 1730 is modeled with the delay U30 and the AND gate U5. The AND gate U5 receives the "min_off_trig" signal from the FSM at one input and a delayed version of the "min_off_trig" signal at the other input. The output of the AND gate U5 is the "min_toff_rtn" received from the FSM.Another delay module 1740 is provided by the delay U 12 and the AND gate U 13. The delay module 1740 is used to model the response time of "mag_req.".The AND gate U13 receives the "mag_req" signal from the FSM at one input and a delayed version of the "mag_req" signal at the other input. The output of the AND gate U13 is the "mag_ack" received from the FSM.There is also a one-shot trigger U8 1750 used by the PDO module to ensure that the m_hpwm_n signal is seen as long as the ramps are equalized to each other within limits. The m_hpwm_n signal is tied low in FIG. 17 because it is a master channel that it does not use. The one shot is used to ensure that the system responds to the leading edge of the phase shifted comparator in the pre-dropout mode. It should be wide enough to compensate for the mismatch between the ramps. It should also be wide enough that it is still detected when one channel is within the limits but slower or faster than the other.The main difference between a master PDO controller as shown in FIG. 17 and a slave PDO controller would be that the signal "m_sb" would be set low and the "m_hpwm_n" would be connected to a comparator whose threshold is set to 1⁄2 of the error amplifier voltage, for example, so that it triggers at 180 degrees phase shift in the pre_dropout mode. The slave operation defined herein is also seen in Figure 17 where the operation of the additional ramp comparator threshold "m_hpwm_n" signal is used to keep the ramps synchronized with the proper phase with respect to the defined master.It will be apparent to those skilled in the art that variations of the disclosed arrangements are possible without departing from the disclosure. Accordingly, the above description of specific embodiments is provided by way of example only and not for purposes of limitation. It will be apparent to those skilled in the art that minor modifications may be made without substantial changes to the described operation.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedUS 16 / 533,691

[0001] US 10998818B2 [0007,0008,0036,0038]

Claims

A buck converter configured to receive an input voltage and provide an output voltage, the buck converter comprising: a power stage having at least one phase, each phase comprising an inductor; a driver (350) configured to drive the power stage in a synchronous mode or in an asynchronous mode of operation with a minimum off time; wherein as the output voltage approaches the input voltage, a duty cycle of the converter increases to a value limited by the minimum off time; and a clock source (110) configured to generate a first clock signal having a predefined pulse width; wherein the driver (350) is configured to generate a first stretchable clock signal having an adjustable pulse width and an adjustable period; and wherein, upon a transition from the synchronous mode to the asynchronous mode, the driver is configured to increase the adjustable pulse width and the period of the first stretchable clock signal.The down converter of claim 1, wherein the driver (350) comprises a first state machine (361b) configured to generate the first stretchable clock signal and adjust the pulse width and period of the first stretchable clock signal.The down converter of claim 1 or 2, wherein the first clock signal and the first stretchable clock signal are in phase.The buck converter of claim 2 or 3, comprising: a first ramp generator (105) configured to generate a first ramp signal in response to the first clock signal; and an error comparator (130) configured to generate an error signal by comparing the output voltage with a reference voltage, wherein the pulse width of the stretchable clock signal increases as the error signal increases to a threshold.The down converter of claim 4, comprising a first comparator (120) configured to compare the first ramp signal with the error signal, and wherein when the first ramp signal rises and becomes equal to the error signal, the comparator triggers and its output becomes high.The buck converter of claim 5, wherein if the first clock signal occurs prior to the comparator trigger event, the converter transitions to the asynchronous mode, otherwise the converter remains in the synchronous mode.The buck converter of any of claims 2 to 6, wherein the first state machine (361b) is configured to generate a first ramp reset signal to reset a first ramp signal; a first asynchronous mode signal indicating that the converter has entered the asynchronous mode; a first minimum off-time trigger signal configured to trigger a start of a timer; and a first magnetization request signal configured to start inductor magnetization after the timer expires.The down converter of any of claims 2 to 7, comprising a first logic circuit (361a) coupled to the first state machine (361b).The buck converter of claim 8, wherein the first logic circuit (361a) comprises a plurality of persistence latches.The down converter of claim 8 or 9, comprising a second state machine (362b) coupled to a second logic circuit (362a); wherein the second state machine is configured to generate a second extensible clock signal having an adjustable pulse width and an adjustable period.The down converter of claim 10, wherein the first logic circuit (361a) and the second logic circuit (362a) are configured to receive a logic signal for setting the state machine as master or slave such that when the first state machine is a master, the second state machine is a slave, and vice versa, when the first state machine is a slave, the second state machine is a master.The down converter of claim 10 or 11, comprising a second ramp generator (115); wherein the second state machine (362b) is configured to generate a second ramp reset signal to reset the second ramp signal.The buck converter of any of claims 10 to 12, wherein the second state machine (362b) is configured to generate a second asynchronous mode signal indicating that the converter has entered the asynchronous mode; a second minimum off-time trigger signal configured to trigger a start of a timer; and a second magnetization request signal configured to start inductor magnetization after the timer expires.The down converter of any preceding claim, comprising a minimum off-time timer (122) configured to start upon receipt of a trigger signal.A method of controlling a buck converter configured to receive an input voltage and provide an output voltage, the method comprising providing a driver configured to drive a power stage of the converter in a synchronous mode or in an asynchronous mode of operation with a minimum off time; wherein as the output voltage approaches the input voltage, a duty cycle of the converter increases to a value limited by the minimum off time; generating a first clock signal with a predefined pulse width; generating a first stretchable clock signal with an adjustable pulse width and an adjustable period; and upon a transition from the synchronous mode to the asynchronous mode, increasing the adjustable pulse width and the adjustable period of the stretchable clock signal.The method of claim 15, comprising: generating a first ramp signal in response to the first clock signal; and generating an error signal by comparing the output voltage to a reference voltage; wherein the pulse width of the expandable clock signal increases as the error signal increases to a threshold.The method of claim 15 or 16, comprising generating an enable signal to enable a transition between the synchronous mode of operation and the asynchronous mode of operation.The method of any of claims 15 to 17, comprising generating a magnetization request signal for magnetizing the inductor.The method of any of claims 15 to 18, wherein magnetization of the inductor is caused by expiration of a minimum off time timer.A controller for use with a buck converter, the controller comprising: a driver configured to drive a power stage of the converter in a synchronous mode or in an asynchronous mode of operation with a minimum off time; wherein as the output voltage approaches the input voltage, a duty cycle of the converter increases to a value limited by the minimum off time; and a clock source configured to generate a first clock signal with a predefined pulse width; wherein the driver is configured to generate a first stretchable clock signal with an adjustable pulse width and an adjustable period; and wherein upon a transition from the synchronous mode to the asynchronous mode, the driver is configured to increase the adjustable pulse width and the period of the first stretchable clock signal.

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