Electronic component separated from wafer by back side groove and groove extension

Abstract

A method for separating electronic components (100) from a wafer (102), the method comprising: providing the wafer (102) with a semiconductor substrate (104) having a front side (106) with an active region (108) and a back side (110) covered by a functional layer (112), the wafer (102) having several integrally connected electronic components (100) arranged side by side, forming a back side groove (114) extending through the functional layer (112) into the semiconductor substrate (104) between adjacent electronic components (100), and forming a groove extension (116) connected to the back side groove (114) to form a through hole (118) extending through the front side (106) to separate adjacent electronic components (100), the back side groove (114) having a maximum horizontal width (w1) is formedwhich is greater than a maximum horizontal width (w2) of the groove extension (116).

Description

Background Technical field

[0001] Various embodiments relate to a method for separating electronic components from a wafer and an electronic component. Description of the state of the art

[0002] Packages can be described, for example, as encapsulated electronic chips that have electrical connections and are mounted on an electronic peripheral, such as a printed circuit board. Before packaging, a semiconductor wafer is separated into a multitude of electronic chips. After the wafer has been separated into the individual electronic chips, the electronic chips from the wafer can then be used for further processing.

[0003] Separation can be achieved by mechanical or laser cutting of the wafer. However, a separation process can be slow and may result in the loss of a significant portion of the wafer that could be used to manufacture electronic components, especially smaller electronic devices. Summary of the invention

[0004] There may be a need to separate electronic components from a wafer with highly efficient use of wafer area and in a fast manner.

[0005] According to an exemplary embodiment, a method for separating electronic components from a wafer is provided, wherein the method comprises: providing the wafer with a semiconductor substrate having a front side with an active region and a back side covered by a functional layer, wherein the wafer has several integrally connected electronic components arranged side by side, forming a back side groove extending through the functional layer into the semiconductor substrate between adjacent electronic components, and forming a groove extension connected to the back side groove to form a through-hole extending through the front side to separate adjacent electronic components from each other, wherein the back side groove is formed with a maximum horizontal width greater than a maximum horizontal width of the groove extension.

[0006] According to another exemplary embodiment, an electronic component is provided which has a semiconductor substrate, an active region on a front side of the semiconductor substrate and a functional layer on a back side of the semiconductor substrate, wherein a side wall of the electronic component has a notch that extends laterally into the functional layer and into a connected section of the semiconductor substrate.

[0007] According to an exemplary embodiment, an efficient and rapid method for separating a wafer with an active region on the front and a functional layer on the back into individual electronic devices is provided. A corresponding separation method can form a backside groove through the functional layer and into a portion of the semiconductor substrate. Subsequently, the separation method can form a groove extension such that the backside groove and the groove extension are connected to form a through-hole, which contributes to separating the wafer into individual electronic devices. Advantageously, the groove extension has a smaller maximum horizontal width than the backside groove.Advantageously, the separation process only needs to remove a small width of material from the front side adjacent to the active area, making it possible to obtain a large number of electronic devices per wafer area with minimal losses in a single slicing line, for example, by plasma slicing. Simultaneously, the described manufacturing process enables the rapid formation of the wider backside groove, for example, by mechanical slicing, which already separates the functional layer and extends into a portion of the semiconductor substrate thickness. The absence of an active area on the backside makes the removal of a larger amount of material, locally confined to the backside region, less critical with regard to the efficient use of the wafer volume.A correspondingly obtained electronic component may, for example, exhibit a sidewall with a notch in the functional layer and in a connected section of the semiconductor substrate, serving as a fingerprint of the described manufacturing process. This notch may be located where the backside groove was formed during the manufacturing process. Description of further examples of implementation

[0008] Further examples of the method and the electronic component are explained below.

[0009] In the context of the present application, the term "wafer" can, in particular, refer to a semiconductor-based plate or disk that has been processed to form a plurality of integrated circuit elements in an active region of the wafer and that can be isolated into a plurality of separate electronic devices or chips. For example, a wafer may have a matrix-like arrangement of electronic devices in rows and columns. It is possible for a wafer to have a circular geometry or a polygonal geometry (such as a rectangular or triangular geometry).

[0010] In the context of the present application, the term "electronic component" may include, in particular, a semiconductor chip (especially a power semiconductor chip), an active electronic device (such as a transistor), a passive electronic device (such as a capacitor, an inductor, or a resistor), a sensor (such as a pressure sensor, a light sensor, or a gas sensor), an actuator (for example, a loudspeaker), and a microelectromechanical system (MEMS, for example, a loudspeaker, an element comprising a mechanical spring, etc.). However, in other embodiments, the electronic component may also be of a different type, such as a mechatronic element, in particular a mechanical switch, etc.

[0011] In the context of the present application, the term "semiconductor substrate" can, in particular, refer to a body comprising a semiconductor material. The semiconductor body may initially be part of a semiconductor wafer and may be separated from the wafer composite during a manufacturing process. For example, the semiconductor body may comprise silicon or silicon carbide. The semiconductor body may be predominantly made of a semiconductor material. For example, the semiconductor body may be a plate-shaped, cuboid-shaped, or disk-shaped structure.

[0012] In the context of the present application, the term "active region" may, in particular, refer to a surface region of a semiconductor substrate of a wafer or of an electronic component in and / or on which at least one monolithically integrated circuit element (such as a transistor, a diode, a capacitor, a resistor, etc.) is formed. In particular, such an active region may form a surface region of a wafer or of an electronic component on its front face.

[0013] In the context of the present application, the term "functional layer" can, in particular, refer to a layer that may be arranged (for example, attached) to the back side of a wafer or electronic device to provide an assigned function during the use of the easily manufactured electronic device and / or during the manufacture of the electronic device. For example, the functional layer may be a dark band. However, many different functions can be fulfilled by a functional layer, such as an electrical and / or thermal insulation function, an electrical and / or thermal conductivity function, a mechanical function, a protective function against chemical and / or physical influences, and / or an optical function, such as shielding or absorbing light or improving contrast.

[0014] In the context of this application, the term "backside groove" can, in particular, refer to a long, narrow channel or recess extending into the back side of the semiconductor substrate. A backside groove can extend along a plurality of adjacent electronic devices on a wafer. Thus, a backside groove can be an elongated blind hole extending through the functional layer and a portion of the semiconductor substrate. The backside groove can be straight and / or curved. A plurality of backside grooves can be formed along rows and columns to assist in separating a two-dimensional wafer into individual electronic devices. Each separate electronic device can be surrounded by four backside grooves along four side walls of the electronic device.

[0015] In the context of the present application, the term "slot extension" can, in particular, refer to a cavity region extending from the front face of the semiconductor substrate to the back face slot. Consequently, the slot extension and the back face slot together can form a through-hole extending across the entire wafer. In particular, the slot extension—without the associated back face slot—can be a front face slot, i.e., a long, narrow channel or depression extending into the front face of the semiconductor substrate. The slot extension can have a single continuous width along its entire vertical extent or can have two or more vertical sections of different widths. The slot extension can be straight and / or curved.A multitude of slot extensions can be formed along rows and columns to contribute to the separation of a two-dimensional wafer into individual electronic devices. Each separate electronic device can be surrounded by four slot extensions along four side walls of the electronic device.

[0016] In the context of the present application, the term "through hole" can, in particular, refer to a cavity region extending along the entire path between the front and back sides of the semiconductor substrate, including the functional layer thereon. The through hole can be elongated. The through holes can have a straight and / or curved shape. A plurality of through holes can be formed along rows and columns to separate a two-dimensional wafer into individual electronic devices.

[0017] In the context of the present application, the term “maximum horizontal width” may in particular refer to the greatest horizontal width along an entire vertical extent of a groove, recess, hole or cavity structure, such as a backside groove or a groove extension or part thereof, which extends through at least a part of the semiconductor substrate and / or functional layer.

[0018] In the context of this application, the term "notch" can, in particular, refer to a sidewall recess. The notch can be defined in a section of the semiconductor substrate and in the functional layer thereon. Optionally, a further notch can be defined in another section of the semiconductor substrate and in a back-end-of-the-line structure thereon. For example, such a notch can be a blind hole in a sidewall. Such a notch can be bounded exclusively by material of the semiconductor substrate and the functional layer or by material of the semiconductor substrate and the back-end-of-line structure. Such a notch can be closed circumferentially around an electronic device, for example, in an annular manner.

[0019] In one embodiment, the method involves forming the backside groove by mechanical cutting or laser cutting. In particular, mechanical cutting can lead to a rapid singulation process, while a resulting relatively wide scribing line on the backside does not negatively affect the number of electronic components available per wafer.

[0020] In one embodiment, the method involves forming the groove extension by machining from the front side until the groove extension is joined to the back side groove. Machining the back side groove from the back and the groove extension from the front side can result in a simple separation process.

[0021] In another embodiment, however, the groove extension can also be formed by machining from the back.

[0022] In one embodiment, the method involves forming at least part of the groove extension by plasma cutting. Advantageously, plasma cutting can result in a very narrow scoring line, which can positively affect the number of electronic components available per wafer.

[0023] In one embodiment, the method involves forming the groove extension through two processing stages, in particular through two scribing stages. For example, the first can be specifically configured to open a back-end-of-the-line structure, whereas the second can be specifically configured to obtain a narrow scribing line for obtaining a large number of electronic components per wafer.

[0024] In one embodiment, the method involves forming an outer section of the groove extension, which extends to the front face, by laser ablation. Advantageously, the laser ablation can be capable of cutting through a back-end-of-the-line structure.

[0025] In one embodiment, the method involves forming an inner section of the groove extension vertically between the backside groove and the outer section by plasma cutting. Plasma cutting is an excellent choice for obtaining a narrow scribe line in the interior of the semiconductor body, thus enabling the production of a large number of electronic devices per wafer.

[0026] In one embodiment, the method involves preparing the semiconductor substrate with a back-end-of-the-line (BEOL) structure on the active area and forming the groove extension through the back-end-of-the-line structure. Such a back-end-of-the-line structure can have a metallization pattern that can be sectioned, for example, by laser ablation.

[0027] In one embodiment, the method involves forming the backside groove with a maximum horizontal width in the range of 20 µm to 50 µm, particularly in the range of 25 µm to 35 µm. Although relatively large, such a backside scoring line does not negatively affect the number of electronic components per wafer due to the absence of an active area on the backside. However, it can advantageously lead to a fast initial part of the singulation process.

[0028] In one embodiment, the method involves forming an outer section of the groove extension with a maximum horizontal width in the range of 10 µm to 35 µm, particularly in the range of 15 µm to 25 µm. A corresponding scribing line can be formed by laser ablation. The moderate width of the scribing line in such a process can be compatible with efficient use of wafer area while enabling the opening of a BEOL structure.

[0029] In one embodiment, the method involves forming an inner section of the groove extension with a maximum horizontal width in the range of 5 µm to 30 µm, particularly in the range of 10 µm to 20 µm. Such an extremely small scribing line, obtainable by plasma cutting, can advantageously lead to a very high number of electronic components per wafer.

[0030] In one embodiment, the method involves forming the backside groove wider (particularly with a greater maximum horizontal width) than an outer section of the groove extension, while in particular forming an inner section of the groove extension narrower (particularly with a smaller maximum horizontal width) than the outer section of the groove extension. This configuration can be obtained by forming the backside groove by mechanical cutting, the outer section of the groove extension by laser ablation, and the inner section of the groove extension by plasma cutting.

[0031] In one embodiment, the method involves forming the inner section of the groove extension with substantially vertical sidewalls. Such a geometry can be obtained by plasma cutting.

[0032] In one embodiment, the method involves forming a concave tapered section at an interface between the outer and inner sections of the groove extension. Such a concave tapered section can be a fingerprint of a laser ablation process used to form the outer section.

[0033] In one embodiment, the method involves forming a concave tapered section at an interface between the backside groove and the inner section of the groove extension. Such a concave tapered section can be a fingerprint of a mechanical parting process used to form the backside groove.

[0034] In one embodiment, the method comprises forming electrically conductive interconnect structures on the front side and embedding these structures in a temporary protective substrate, followed by thinning the semiconductor substrate on the back side, forming the functional layer on the back side of the thinned semiconductor substrate before forming the backside groove, and removing the temporary protective substrate that forms the backside groove. For example, the electrically conductive interconnect structures can be solder structures, particularly solder bumps or solder balls. Other electrically conductive interconnect structures are possible, such as sintered structures or electrically conductive adhesives.An electrically conductive interconnect structure can be protected against influences during the thinning of the semiconductor substrate by looping by temporarily covering the electrically conductive interconnect structure with a protective substrate (especially against slurry or dirt). The latter can be removed after the semiconductor substrate has been thinned and after the formation and severing of the functional layer.

[0035] In one embodiment, the method comprises forming electrically conductive interconnect structures on the front face and coating these structures with a plasma-resistant coating, followed by forming a groove extension in the semiconductor substrate that extends through the plasma-resistant coating, and then removing the plasma-resistant coating. Advantageously, the electrically conductive interconnect structures (such as solder bumps) can be temporarily protected against the effects of plasma cutting. Furthermore, a corresponding temporary plasma-resistant coating can also be compatible with a laser process that can be used when forming the groove extension.

[0036] In one embodiment, the transition between the functional layer and the connected section of the semiconductor substrate at the notch is continuous and seamless. In particular, the functional layer and the semiconductor substrate can define a vertical, inclined, and / or curved notch surface without any discontinuity between them. This can result from the formation of the notch by mechanical cutting.

[0037] In one embodiment, the side wall has a step between the notch and another connected section of the semiconductor substrate. Such a geometric feature on the side wall of the electronic device can be obtained if the notch is formed by mechanical cutting.

[0038] In one embodiment, the further connected section has a vertical section adjacent to the step, wherein, in particular, the further connected section has a further notch adjacent to the vertical section, the notch extending laterally deeper into the semiconductor substrate than the further notch. The vertical section can be obtained by forming a corresponding sidewall section by plasma cutting. The further notch can be the result of forming a corresponding sidewall section by laser ablation. A notch formed by laser ablation can be less pronounced than a notch formed by mechanical cutting.

[0039] In an alternative embodiment, the vertical portion of the further connected section extends straight from the step to the front face. Thus, it is possible that a further step is omitted (for example, if the material does not contain low dielectrics in the back-end-of-line stack). In this case, the material removal forming the further notch can be replaced by plasma etching, so that the further step can then be omitted and the groove already has the width of the vertical section.

[0040] In one embodiment, the functional layer comprises at least one protective layer, an insulating layer, a metallization layer, a plastic layer, a chip mounting layer, an opaque layer, and an optical contrast-enhancing layer. The functional layer can be a permanent layer that forms part of the finished electronic component. For example, the functional layer may provide protection, insulation, contribute to chip mounting, provide a dark color so that optical inspection of the electronic components is not disrupted by light refraction, serve as a marking function, or provide a metal reservoir for improved mounting or shielding. The functional layer may be electrically insulating, electrically conductive, light-absorbing, contrast-enhancing, and / or protective against mechanical and / or chemical influences.

[0041] In one embodiment, the electronic component is a power semiconductor chip. Such a power semiconductor chip can integrate one or more integrated circuit elements, such as transistors (for example, field-effect transistors like metal-oxide-semiconductor field-effect transistors and / or bipolar transistors like insulated-gate bipolar transistors) and / or diodes. Examples of applications that can be provided by such integrated circuit elements include switching. For example, such an integrated circuit element of a power semiconductor device can be integrated into a half-bridge or a full-bridge. Examples of such applications include automotive applications.

[0042] The electronic component (in particular the semiconductor chip) can comprise at least one component from the group consisting of a diode and a transistor, in particular a bipolar transistor with an insulated gate. For example, the electronic chip can be used as a semiconductor chip for power applications, for example in the automotive sector. In one embodiment, at least one semiconductor chip can comprise a logic IC or a semiconductor chip for RF power applications. In another embodiment, the semiconductor component can be used as one or more sensors or actuators in microelectromechanical systems (MEMS), for example as pressure sensors or accelerometers, as a microphone, as a loudspeaker, etc.

[0043] A semiconductor substrate, i.e., a silicon substrate, can be used as the substrate or wafer for the semiconductor devices. Alternatively, a silicon oxide or another insulator substrate can be provided. It is also possible to implement a germanium substrate or a III-V semiconductor material. For example, embodiments can be implemented using GaN or SiC technology.

[0044] Furthermore, embodiments can utilize standard semiconductor processing technologies, such as suitable etching technologies (including isotropic and anisotropic etching technologies, in particular plasma etching, dry etching, wet etching), structuring technologies (which may include lithographic masks), deposition technologies (such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.). Brief description of the drawings

[0045] The accompanying drawings, which are included to provide a further understanding of exemplary embodiments and form part of the description, illustrate exemplary embodiments.

[0046] The drawings show: Fig. 1 A cross-sectional view of an electronic component according to an exemplary embodiment. Fig. 2 A cross-sectional view of a wafer that has already been separated into a multitude of electronic components, according to an exemplary embodiment. Fig. 3 to Fig. 9 Cross-sectional views of structures obtained during the execution of a method for separating electronic components from a wafer, according to an exemplary embodiment. Fig. 10 a flowchart of a method for separating electronic components from a wafer according to an embodiment. Fig. 11 to Fig. 17 Cross-sectional views of structures obtained during the execution of a method for separating electronic components from a wafer, according to a further embodiment. Detailed description of exemplary embodiments

[0047] The representation in the drawing is schematic and not to scale.

[0048] Before exemplary embodiments are described in more detail with reference to the figures, some general considerations are summarized on the basis of which exemplary embodiments were developed.

[0049] Plasma cutting can be a preferred separation method for very small chips due to the smaller required scribe line width (e.g., around 30 µm) compared to other methods. Thus, separating electronic components from a wafer by plasma cutting can lead to a significant increase in the number of available semiconductor chips per wafer.

[0050] For example, a typical chip size for certain applications might be 600 × 600 µm² or 600 × 1200 µm². Considering a typical scribing line width of, say, 60 µm, it becomes clear that a significant amount of wafer area is lost through singulation. In particular, plasma slicing can reduce a scribing line width from 60 µm to 24 µm, potentially leading to a significant increase in the number of chips per wafer. A loss of wafer area due to slicing can be especially problematic when processing expensive wafers, particularly those with complex wafer-to-wafer bonding processes. Given the above, increasing the number of semiconductor chips per wafer is highly desirable. Enabling plasma slicing could save a significant amount of scribing line width, for example, 30 µm, compared to a mechanical slicing process.

[0051] However, there may be applications and scenarios where plasma cutting is undesirable or deemed impossible. For example, some applications may require a backside protection strip that cannot be cut by plasma. Similarly, applications using chip thicknesses of 200 µm to 250 µm may be too thick for efficient plasma cutting. Furthermore, applying a solder ball, for instance, with a diameter of 170 µm, to an electronic component requires a thick coating during the plasma process, which can complicate the manufacturing process.

[0052] According to one embodiment, a semiconductor wafer can be separated into individual electronic components with high efficiency. The wafer and each of the electronic components, which are initially integrally connected within the wafer matrix, can have an active area with an integrated circuit on the front side and an attached functional layer on the back side. A separation process can first involve forming a backside groove that extends through the functional layer and an attached portion of the wafer's semiconductor substrate. In one or more additional processing steps, a groove extension can be formed on the front side with its active area and aligned with the backside groove, so that the frontside groove and the groove extension together separate the wafer into individual electronic components.Advantageously, the groove extension can be narrower laterally than the backside groove, so that only a small amount of material is removed from the frontside with its active area during separation. Consequently, the number of electronic components achievable from a wafer can be very high thanks to the minimal losses due to frontside cutting. A larger material loss on the backside may be acceptable because the backside is spatially separated from the active area, allowing the use of a cutting technology that ensures rapid backside groove formation to accelerate the singulation process. An electronic component obtained from such a manufacturing process, for example, may have a notched sidewall section on the backside covered by the functional layer.The notch may be the fingerprint of the formation of the backside groove during singulation.

[0053] In particular, exemplary embodiments can enable plasma cutting for the singulation of electronic components with a permanent backside adhesive tape as an example of a functional layer. The functional layer, together with an associated semiconductor section, can be subjected to mechanical cutting to rapidly form a backside groove. Subsequently, a groove extension on the frontside can be formed, at least partially, by plasma cutting, optionally and preferably supported by laser ablation. Thanks to the plasma cutting, a very small scribe line can be achieved on the frontside, resulting in a large number of electronic components per wafer. Therefore, the semiconductor thickness can be locally reduced by a rapid mechanical cutting process, such as mechanical cutting, to open the backside functional layer into the semiconductor substrate.Afterwards, an optional laser slicing process (which may have a narrower scribe line than the mechanical slicing process mentioned above) can be performed from the front side, which can slice through a back-end-of-the-line structure and a further part of the semiconductor substrate, and the remainder of the wafer thickness can then be cut by plasma etching with a very narrow scribe line.

[0054] In one embodiment, a method for plasma cutting a chip with a back-side adhesive tape is provided. In particular, a wafer plasma cutting method can be provided, wherein the wafer has an adhesive tape on its back side. The method can include grinding the wafer and laminating its back side with a tape, mechanical cutting and creating half-cuts in the back side, applying a plurality of spheres to the front side and embedding them in a tape, applying cutting tape to the back side, coating the spheres and front side with a high-viscosity coating material (such as a laser- and plasma-compatible coating), laser ablation of the front side, plasma cutting of the chip, and rinsing (for example, with water).

[0055] Integrating front-side plasma cutting into the singulation process allows for the creation of a small scribing line (e.g., in the range of 10 µm to 20 µm), which can be significantly smaller than a scribing line width obtained through mechanical cutting. This can increase the number of chips per wafer. Advantageously, back-side mechanical cutting can enable cutting through the ribbon or other type of functional layer (e.g., with a scribing line width in the range of 25 µm to 40 µm). Thus, such a process can facilitate simple structuring of the backside ribbon. Furthermore, an efficient mechanical cutting process can be achieved with a single cut and a high feed rate. Additionally, a mechanical cutting process can operate on an undivided wafer.Since a chip-to-chip distance on the front side can be smaller than a separation channel, the separation disk width does not limit the number of chips per wafer. Furthermore, advantageously, implementing a mechanical sectioning process for groove formation can extend the chip thickness range to thicknesses that are not efficient for plasma sectioning alone. Additionally, chip collisions during uptake may be less likely due to a larger chip-to-chip distance on the back side.

[0056] In another embodiment, it may be possible to reduce the plasma etching width to 3 µm to 10 µm and to use tape stretching to achieve a final chip-to-chip distance.

[0057] In yet another embodiment, it may be possible to change the order of processing, i.e., to perform front-side processing before back-side processing.

[0058] Furthermore, a process flow can be with or without balls or columns, which are therefore optional.

[0059] Fig. Figure 1 shows a cross-sectional view of an electronic component 100 according to an exemplary embodiment. The illustrated electronic component 100 can be a semiconductor chip, for example a power semiconductor chip.

[0060] In its vertical middle section, the electronic component 100 has a semiconductor substrate 104, for example, a silicon body. The thickness of the semiconductor substrate 104 can be in the range of 100 µm to 500 µm, for example, 250 µm. An active region 108 can be formed in a front-side section on a front face 106 of the semiconductor substrate 104. For example, the active region 108 can extend to a depth of 10 µm to 40 µm, in particular 20 µm to 30 µm, into the semiconductor substrate 104. For example, the active region 108 can include one or more monolithically integrated circuit elements such as a field-effect transistor and / or a diode. The active region 108 can be formed by semiconductor processing techniques.

[0061] A back-end-of-the-line (BEOL) structure 124 can be formed on the active region 108. The back-end-of-the-line structure 124 can, for example, have metal compound layers on the semiconductor substrate 104 that are already structured and connected to integrated device(s) in the active region 108. The back-end-of-the-line structure 124 can also connect one or more integrated circuit elements (such as transistors, capacitors, resistors, etc.) with metal wiring. For example, the back-end-of-the-line structure 124 can have a front-side metallization with a structured stack of metallic layers.

[0062] As also shown, the electronic component 100 can have one or more electrically conductive interconnect structures 130 on the back-end-of-the-line structure 124 above the active area 108. For example, such an electrically conductive interconnect structure 130 can be a solder bump. In the embodiment shown, a plurality of solder bumps, designed as solder balls, for example with a diameter of 170 µm, are provided. Alternatively, other electrically conductive interconnect structures 130 can be provided, for example a sintered paste, an electrically conductive adhesive, etc.

[0063] Opposite the front side 106 of the semiconductor substrate 104 is a back side 110. A functional layer 112 can be attached to the back side 110 of the semiconductor substrate 104. For example, the vertical thickness of the functional layer 112 can be in the range of 10 µm to 50 µm. In the embodiment shown, the functional layer 112 can be a black band, for example, made of a plastic material, which is attached to the back side 110. The functional layer 112 remains permanently attached to the semiconductor substrate 104 and can therefore be referred to as a permanent functional layer 112. However, in other embodiments, the functional layer 112 can have various functions.For example, the functional layer 112 can be a protective layer (for example, to protect the interior of the electronic component 100 against chemical or mechanical influences), an insulating layer (for example, to protect the electronic component 100 against electrical leakage current), a metallization layer (for example, to shield the electronic component 100 against electromagnetic radiation), a chip mounting layer (for example, having an adhesive for attaching the electronic component 100 to a substrate), an opaque layer (to protect the electronic component 100 against light) and / or an optical contrast-enhancing layer (for example, to improve optical contrast or to engrave alphanumeric information).

[0064] The sidewalls 136 of the electronic component 100 form a circumferential and lateral boundary surface of the electronic component 100 between the horizontal front 106 and the horizontal back 110. For example, the electronic component 100 can have a substantially rectangular or cuboid shape. For example, each of the four circumferential sidewall sections can have a shape corresponding to the opposite sidewalls 136, which are in Fig. Figure 1 shows that each of the two opposing side walls 136 has a notch 138 extending laterally into the functional layer 112 and into a connected section 142 of the semiconductor substrate 104. Specifically, the notch 138 extends laterally into the entire functional layer 112 and into a connected section of the semiconductor substrate 104, starting from the rear side 110 and extending to a central section of the semiconductor substrate 104. As shown, the transition between the functional layer 112 and the connected section 142 of the semiconductor substrate 104 at the notch 138 is continuous and seamless. Thus, there is no structural discontinuity in the notch 138 at the rear side 110 forming an interface between the functional layer 112 and the semiconductor substrate 104.Although not shown, the side wall 136 can have the notch 138 extending along the entire circumference of the electronic component 100. Thus, the notch 138 can be a closed loop notch extending along the lateral circumference of the electronic component 100.

[0065] With reference to Fig. Each of the sidewalls 136 can have a step 146 between the notch 138 and another connected section 144 of the semiconductor substrate 104. The further connected section 144 can extend from the step 146 at the upper end of the notch 138 to the front end 106 of the semiconductor substrate 104. As shown, the further connected section 144 has a straight vertical section 148 adjacent to the step 146 and extends upward from the step 146 to another step 152. For example, the vertical thickness of the sidewall section between the step 146 and the further step 152 can be in a range of 20 µm to 150 µm. Furthermore, the further connected section 144 has a further notch 140 adjacent to the vertical section 148 and extends from the further step 152 upwards to the front 106 and beyond through the entire rear end of the conductor structure 124.For example, the vertical extent of the further notch 140 can lie in a range of 5 µm to 20 µm. As also shown from . Fig. 1 can be removed, the deeper notch 138 extends laterally deeper into the semiconductor substrate 104 than the shallower further notch 140.

[0066] In an alternative embodiment (not shown), the vertical section 148 of the further connected section 144 can extend straight from the step 146 to the front face 106 and optionally also through the rear end of the conductor structure 140. Thus, it may be possible to omit a further notch 140 and a further step 152 (for example, if the material does not contain low dielectrics in the rear end of the conductor stack 124). In that case, the ablation or the further notch 140 formed by laser processing (as described below) can be omitted, for example, if the laser processing is replaced by plasma etching. The further step 152 can then be omitted, and the entire section of the side wall 136 above the step 146 already has the width of the vertical section 148 up to the upper main surface of the electronic device 100.

[0067] For example, the electronic component can be 100 of Fig. 1. are formed by the manufacturing process, which is described below with reference to Fig. 3 to Fig. 9 is described. The alternative described above, without the additional notch 140, can be obtained through the manufacturing process by taking the precaution that the two-stage laser processing and plasma splitting into the front face 106 can be replaced by a single plasma splitting process without laser processing. The plasma splitting process may be slower than a mechanical splitting process used to form the notch 138, but it can result in a narrow bottleneck in the interior of the wafer 102 between two adjacent electronic devices 100. Advantageously, the use of plasma splitting can save wafer area and can increase the yield of the electronic devices 100 due to a narrow plasma splitting scribe line.

[0068] Fig. Figure 2 shows a cross-sectional view of a wafer 102, which has already been separated into a plurality of electronic components 100, according to an exemplary embodiment. The following description of Fig. 3 to Fig. 9 will show how the structure of Fig. 2 can be obtained. With reference to Fig. 2. Some geometric attributes of the structure are described. Fig. Figure 2 shows two electronic components 102 arranged side by side and separated by a common wafer 102. The separated electronic components 100 of Fig. The two components are still mounted on a common dividing strip 154. A through-hole-like separation channel or trench 156 is formed between the adjacent electronic components 100, extending through the functional layer 112, the entire semiconductor substrate 104 from the front 106 to the back 110 and the back end of the line structure 124.

[0069] As in Fig. As shown in Figure 2, a backside groove 114 – forming a notch 138 of the electronic components 100 – is formed in the wafer 102 with a maximum horizontal width w1, preferably in a range of 25 µm to 35 µm. For example, a vertical extension of the backside groove 114 can be at least 50%, and in particular at least 60%, of the thickness of the electronic component 100. The backside groove 114 can preferably be formed by mechanical cutting using a cutting disc or by laser ablation. Furthermore, an outer section 120 of a groove extension 116 – forming another notch 140 of the electronic components 100 – is formed in the wafer 102 with a maximum horizontal width w2, preferably in a range of 15 µm to 25 µm.Furthermore, an inner section 122 of the groove extension 116—which forms a straight vertical section 148 of the electronic components 100—is formed in the wafer 102 with a maximum horizontal width w3, preferably in a range of 10 µm to 20 µm. The maximum horizontal width w3 can also be referred to as the plasma etching width, since it can be defined by a plasma etching process. As shown, the aforementioned maximum horizontal widths w1, w2, and w3 are formed to satisfy the condition w1 > w2 > w3. Advantageously, w2 and w3 are smaller than w1, which allows for efficient use of the area of ​​the wafer 102 to form a large number of electronic components 100 without excessive losses due to etching lines. The section according to w1 can, however, be formed by a rapid mechanical slicing process without affecting the active area 108 of the respective electronic component 100.Therefore, efficient use of a wafer area can be synergistically combined with a fast division process.

[0070] A minimum opening required for plasma etching (e.g., 10 µm to 20 µm) can correspond to a lower laser ablation width. An upper laser ablation width (corresponding to the maximum horizontal width w2) can, for example, be in the range of 15 µm to 25 µm. Furthermore, a taper between the upper and lower ablation widths (due to a laser profile) can be formed, for example, with a dimension of approximately 5 µm.

[0071] Fig. 3 to Fig. Figure 9 shows cross-sectional views of structures obtained during the execution of a method for separating electronic components 100 from a wafer 102, according to an exemplary embodiment.

[0072] With reference to Fig. 3. The wafer 102 is provided in a state where the formation of integrated circuit elements within the wafer 102 is complete. The wafer 102 is provided with a semiconductor substrate 104, such as a silicon body, which has a front face 106 with an active area 108 and integrated circuit elements, and a back face 110. The wafer 102 has several integrally connected electronic components 100, such as semiconductor chips, arranged side by side. For example, the integrally connected electronic components 100 can be arranged in rows and columns within the wafer interconnect. As shown, the semiconductor substrate 104 is provided with a back-end-of-the-line structure 124, i.e., a BEOL stack such as a structured metallization, on the active area 108. Furthermore, electrically conductive interconnect structures 130, such as solder bumps, can be formed on the front face 106.For example, the electrically conductive connection structures 130 can have a diameter in the range of 100 µm to 250 µm; for example, they can be solder balls with a diameter of 170 µm. After singulating individual electronic components 100, an electronic component 100 can be connected to an electronic peripheral, for example, a mounting base such as a printed circuit board or a carrier such as a conductor frame structure, by creating a solder joint using the electrically conductive connection structures 130 of the solder type.

[0073] The in Fig. Wafer 102, shown in section 3, is ready for separation into 100 individual electronic components. Thus, it shows Fig. 3 the incoming wafer 102 after ball application and wafer testing.

[0074] With reference to Fig. 4. The electrically conductive interconnect structures 130 can be embedded in a temporary protective substrate 132. For example, the temporary protective substrate 132 can be an abrasive belt or a glass substrate. The temporary protective substrate 132 can be used to embed the spherical electrically conductive interconnect structures 130 in order to protect them during a subsequent thinning process, particularly with regard to slurry or grinding debris generated during such a thinning process.

[0075] The resulting structure can then be thinned on the back side 110 by removing material from the semiconductor substrate 104 until a target thickness of the semiconductor substrate 104 is achieved. For example, this can be done by mechanical grinding.

[0076] With reference to Fig. 5. A functional layer 112, such as a backside protection strip, is attached to the backside 110 after the thinning process. This can be done, for example, by adhesive or lamination. Thus, the functional layer 112 can be formed on the backside 110 of the thinned semiconductor substrate 104 before a backside groove 114 is formed. The process then continues with the formation of the backside groove 114, which extends through the functional layer 112 into the semiconductor substrate 104 between adjacent electronic components 100. Advantageously, the backside groove 114 is formed by a rapid splitting process, such as mechanical splitting. Alternatively, laser splitting can be performed to form the backside groove 114, which extends through the entire functional layer 112 and a backside section of the semiconductor substrate 104.The process of forming the backside groove 114 ends in the interior of the semiconductor substrate 104. Backside alignment can be advantageous during the described mechanical parting of the backside 110 of the semiconductor substrate 104. For example, such backside alignment can be achieved by taking a camera image from the underside.

[0077] With reference to Fig. Figure 6 shows a cross-sectional view of the entire wafer 102 after a plurality of parallel backside grooves 114 have been formed between each pair of adjacent electronic components 100. Additional backside grooves 114 can also be formed in a direction perpendicular to the backside grooves 114 in the surface plane of the wafer 102 to separate all four sides of each electronic component 100. Optionally, no cutting across a wafer edge (such as dipping) is performed for stabilization.

[0078] With reference to Fig. In step 7, the functional layer 112, which had meanwhile been structured by the backside groove 114, was mounted on a sectioning type 154. Furthermore, the temporary protective carrier 132 can be removed after thinning and after forming the backside groove 114. Subsequently, the exposed electrically conductive connection structures 130 can be coated with a plasma-resistant coating 134. This plasma-resistant coating 134 protects the electrically conductive connection structures 130 during a subsequent plasma sectioning process. Furthermore, this plasma-resistant coating 134 can also provide some protection for the electrically conductive connection structures 130 during a subsequent laser process. Thus, the material of the plasma-resistant coating 134 can be a laser- and plasma-compatible coating material, preferably exhibiting high viscosity.

[0079] Then, the first of two processes for forming a groove extension 116 is performed. This first process forms an outer section 120 of the groove extension 116, which extends into the front face 106 by laser ablation. As in Fig. As shown in Figure 7, the outer section 120 of the groove extension 116 extends through the entire thickness of the plasma-resistant coating 134, through the rear end of the conductor structure 124, and into a front-side section of the semiconductor substrate 104. As shown, the laser ablation process is performed from the front side 106. As also shown in Figure 7, the outer section 120 of the groove extension 116 extends through the entire thickness of the plasma-resistant coating 134, through the rear end of the conductor structure 124, and into a front-side section of the semiconductor substrate 104. Fig. As can be seen from Figure 7, the horizontal width of the outer section 120 of the groove extension 116, which is currently being formed, is smaller than the horizontal width of the backside groove 114. This is due to the fact that the outer section 120 is formed by laser ablation, whereas the backside groove 114 is formed by mechanical cutting.

[0080] In summary, the wafer 102 with its functional layer 112 can be mounted on the slicing belt 154, the plasma-resistant coating 134 is provided with a laser- and plasma-compatible coating material with high viscosity on the electrically conductive interconnect structures 130, and then the laser ablation is carried out from the front 106.

[0081] With reference to Fig. In step 8, the second process of the two-stage process for forming the slot extension 116 is carried out to complete the separation of the individual electronic components 100. During the second process, the remaining thickness of the semiconductor substrate 104 between the outer section 120 of the slot extension 116 and the backside slot 114 is bridged by removing further material of the semiconductor substrate 104 between them from the front side 106 via plasma fracturing, thereby forming a narrow inner section 122 of the slot extension 116. Thus, the formation of the slot extension 116 can be completed, with the slot extension 116 joining with the backside slot 114 to form a through-hole 118 that extends vertically through the entire wafer 102 to separate adjacent electronic components 100 from one another.Advantageously, the groove extension 116 can be formed with its outer section 120 by laser ablation and with its inner section 122 by plasma cutting. Thus, the formation of the inner section 122 of the groove extension 116 can be carried out vertically between the backside groove 114 and the outer section 120 by plasma cutting. Plasma cutting can be performed until the opposite backside groove 114 or the saw hole is reached. Therefore, the groove extension 116 can be formed by machining from the front side 106 until the groove extension 116 is connected to the backside groove 114. In particular, plasma cutting can be carried out using reactive ion etching (RIE).Advantageously, plasma cutting can form very narrow scribe lines, so that only a minimal amount of wafer volume is lost during the singulation process and a high number of electronic components 100 per area of ​​the wafer 102 can be obtained. After the groove extension 116 has been formed, the individual electronic components 100 are separated from the wafer interconnect. As shown, a large number of electronic components 100 can be produced according to [reference missing]. Fig. 1 will be received.

[0082] It is possible that the inner section 122 of the groove extension 116, with substantially vertical side walls 150, is formed within the straight vertical section 148. Furthermore, a concave tapered section 126 can be formed at an interface between the outer section 120 of the groove extension 116 and the inner section 122 of the groove extension 116. In addition, another concave tapered section 128 can be formed at an interface between the rear groove 114 and the inner section 122 of the groove extension 116.

[0083] With reference also to Fig. 2. The backside groove 114 is formed with a maximum horizontal width w1, which is greater than the maximum horizontal width w2 of the groove extension 116. The smallest width at a constriction of the through-hole 118 between two separate electronic components 100 can be the maximum horizontal width w3 in the inner section 122 formed by plasma segmentation. Accordingly, the backside groove 114 can be wider than the outer section 120 of the groove extension 116, with the inner section 122 of the groove extension 116 even being narrower than the outer section 120 of the groove extension 116.

[0084] In another embodiment (not shown) it may also be possible to form the entire groove extension 116 by a single further division process, preferably only by plasma division.

[0085] With reference to Fig. 9. The plasma-resistant coating 134 can be removed to expose the electrically conductive connection structures 130. This removal process can, for example, be a water rinsing process. Afterwards, the electronic components 100 can be removed from the slicing belt 154. The finished electronic components 100 can, for example, be used for packaging. This can involve creating a solder joint between the exposed electrically conductive connection structures 130 and another electronic component.

[0086] Fig. Figure 10 shows a flowchart 200 of a method for separating electronic components 100 from a wafer 102 according to an embodiment.

[0087] Referring to Block 202 (compare Fig. 3) Electrically conductive connection structures 130 are formed on a front side 106 of the wafer 102.

[0088] Referring to Block 204 (compare Fig. 4) The resulting structure is subjected to a thinning process on the back side 110.

[0089] Referring to Block 206 (compare Fig. 5) A functional layer 112 is attached to the back side 110 and a back side groove 114 is formed.

[0090] Referring to Block 208 (compare Fig. 7) A first of two processes for forming a groove extension 116 is carried out by forming an outer section 120 of the groove extension 116 which extends into the front face 106.

[0091] Referring to Block 210 (compare Fig. 8) A second process of the two-stage process for forming the slot extension 116 is carried out to complete the separation of the individual electronic components 100.

[0092] Fig. 11 to Fig. Figure 17 shows cross-sectional views of structures obtained during the execution of a method for separating electronic components 100 from a wafer 102, according to a further embodiment.

[0093] With reference to Fig. 11. A wafer 100 with a medium semiconductor substrate 104 can be provided, which has an active area 108 and a back-end-of-the-line structure 124 on a front side 106. A functional layer 112 can be attached to the back side 110 of the semiconductor substrate 104. Thus, Fig. 11 the wafer 102 after grinding and laminating the functional layer 112, which can be designed as a backside band.

[0094] With reference to Fig. 12 The backside groove 114 can be formed by mechanical cutting through the functional layer 112 and into the backside 110 of the semiconductor substrate 104. The mechanical cutting process can be carried out from the backside 110, and a backside alignment process may be advantageous.

[0095] With reference to Fig. Figure 13 provides an overview of the entire wafer 102. Optionally, no cutting across the wafer edge can be performed for stabilization purposes.

[0096] With reference to Fig. 14 Electrically conductive connection structures 130, such as solder balls, can be attached to the rear end of the conductor structure 124 for electrical connection purposes.

[0097] With reference to Fig. 15. A plasma-resistant coating 134 can be formed to cover the electrically conductive interconnect structures 130. The wafer 102 can be mounted on its functional layer 112 on a slicing belt 154. Subsequently, a laser ablation process is used to form an outer section 120 of a groove extension 116 (completely in Fig. 16 shown).

[0098] With reference to Fig. 16 An inner section 122 of the groove extension 116 is formed by plasma cutting. A through-hole 118 is formed, extending through the wafer 102 to separate individual electronic components 100 by combining the rear groove 114 and the groove extension 116 (which consists of its inner section 122 and its outer section 120).

[0099] With reference to Fig.17. The plasma-resistant coating 134 is removed by a water rinsing process. The individual electronic components 100 can be removed from the cutting belt 154 and can be further processed.

[0100] It should be noted that the term "having" does not exclude other elements or features, and "a" or "a" does not exclude a plurality. Elements described in connection with different embodiments may also be combined. It should also be noted that reference numerals should not be interpreted as limiting the scope of protection of the claims. Furthermore, the scope of protection of the present application is not intended to be limited to the specific embodiments of the process, machine, manufacture, composition, means, methods, and steps described in the description. Accordingly, the appended claims are intended to include such processes, machines, manufacture, compositions, means, methods, or steps within their scope of protection.

Claims

[1] Method for separating electronic components (100) from a wafer (102), wherein the method comprises: • Providing the wafer (102) with a semiconductor substrate (104) having a front side (106) with an active area (108) and a back side (110) covered by a functional layer (112), wherein the wafer (102) has several integrally connected electronic components (100) arranged side by side; • Forming a backside groove (114) extending through the functional layer (112) into the semiconductor substrate (104) between adjacent electronic components (100); and • Forming a groove extension (116) connected to the rear groove (114) to form a through hole (118) extending through the front (106) to separate adjacent electronic components (100) from each other, wherein the rear groove (114) is formed with a maximum horizontal width (w1) greater than a maximum horizontal width (w2) of the groove extension (116). [2] Method according to claim 1, wherein the method comprises forming the backside groove (114) by mechanical cutting or by laser cutting. [3] Method according to claim 1 or 2, wherein the method comprises forming the groove extension (116) by machining from the front (106) until the groove extension (116) is connected to the back groove (114). [4] Method according to any one of claims 1 to 3, wherein the method comprises forming at least part of the groove extension (116) by plasma cutting. [5] Method according to any one of claims 1 to 4, wherein the method comprises forming the groove extension (116) by two processing stages. [6] Method according to any one of claims 1 to 5, wherein the method comprises forming an outer section (120) of the groove extension (116) extending to the front (106) by laser ablation. [7] Method according to claim 6, wherein the method comprises forming an inner section (122) of the groove extension (116) vertically between the rear groove (114) and the outer section (120) by plasma cutting. [8] Method according to any one of claims 1 to 7, wherein the method comprises preparing the semiconductor substrate (104) with a back-end-of-the-line structure (124) on the active area (108) and forming the slot extension (116) through the back-end-of-the-line structure (124). [9] Method according to any one of claims 1 to 8, comprising at least one of the following features: wherein the method comprises forming the backside groove (114) with a maximum horizontal width (w1) in a range of 20 µm to 50 µm, in particular in a range of 25 µm to 35 µm; wherein the method comprises forming an outer section (120) of the groove extension (116) with a maximum horizontal width (w2) in a range of 10 µm to 35 µm, in particular in a range of 15 µm to 25 µm; wherein the method comprises forming an inner section (122) of the groove extension (116) with a maximum horizontal width (w3) in a range of 5 µm to 30 µm, in particular in a range of 10 µm to 20 µm. [10] Method according to any one of claims 1 to 9, wherein the method comprises forming the backside groove (114) wider than an outer section (120) of the groove extension (116), wherein in particular an inner section (122) of the groove extension (116) is formed narrower than the outer section (120) of the groove extension (116). [11] Method according to claim 10, wherein the method comprises forming the inner section (122) of the groove extension (116) with substantially vertical side walls (150). [12] Method according to claim 10 or 11, wherein the method comprises forming a concave tapered section (126) at an interface between the outer section (120) of the groove extension (116) and the inner section (122) of the groove extension (116). [13] Method according to any one of claims 10 to 12, wherein the method comprises forming a concave tapered section (128) at an interface between the rear groove (114) and the inner section (122) of the groove extension (116). [14] Method according to any one of claims 1 to 13, wherein the method comprises: Forming electrically conductive connection structures (130) on the front side (106) and embedding the electrically conductive connection structures (130) in a temporary protective carrier (132); then thinning of the semiconductor substrate (104) on the back side (110); then forming the functional layer (112) on the back side (110) of the thinned semiconductor substrate (104) before forming the back side groove (114); and Removing the temporary protective carrier (132) after forming the backside groove (114). [15] Method according to any one of claims 1 to 14, wherein the method comprises: Forming electrically conductive connection structures (130) on the front side (106) and coating the electrically conductive connection structures (130) with a plasma-resistant coating (134); then forming the groove extension (116) in the semiconductor substrate (104) which extends through the plasma-resistant coating (134); and then removing the plasma-resistant coating (134). [16] Electronic component (100) comprising: • a semiconductor substrate (104); • an active region (108) on a front side (106) of the semiconductor substrate (104); and • a functional layer (112) on a back side (110) of the semiconductor substrate (104); • wherein a side wall (136) of the electronic component (100) has a notch (138) which extends laterally into the functional layer (112) and into a connected section (142) of the semiconductor substrate (104). [17] Electronic component (100) according to claim 16, wherein the side wall (136) has a step (146) between the notch (138) and a further connected section (144) of the semiconductor substrate (104). [18] Electronic component (100) according to claim 17, wherein the further connected section (144) has a vertical section (148) adjacent to the step (146). [19] Electronic component (100) according to claim 18, comprising one of the following features: wherein the further connected section (144) has a further notch (140) adjacent to the vertical section (148), wherein in particular the notch (138) extends laterally deeper into the semiconductor substrate (104) than the further notch (140); wherein the vertical section (148) of the further connected section (144) extends straight from the step (146) to the front (106). [20] Electronic component (100) according to one of claims 16 to 19, comprising at least one of the following features: wherein a transition between the functional layer (112) and the connected section (142) of the semiconductor substrate (104) at the notch (138) is continuous and stepless; wherein the functional layer (112) comprises at least one of a protective layer, an insulating layer, a metallization layer, a plastic layer, a chip mounting layer, an opaque layer and an optical contrast-enhancing layer; exhibiting a back-end-of-the-line structure (124) on the active area (108); comprising at least one electrically conductive connection structure (130) on or above the active area (108), in particular on a back-end-of-the-line structure (124) on the active area (108); wherein the side wall (136) has the notch (138) which extends along the entire circumference of the electronic component (100).

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