Asymmetric data rates for high-speed interconnections

Abstract

Embodiments described herein may include devices, systems, techniques, or processes related to semiconductor interconnects, such as on-package die-to-die (D2D) interconnects. In particular, embodiments herein may relate to on-package D2D interconnects for memory using or related to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

Description

BACKGROUNDAdvances in semiconductor processing and logic design have enabled an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single integrated circuit or circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present on single integrated circuits as well as other interfaces integrated in such processors. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memories, controller hubs, etc.Due to the greater ability to accommodate more computing power in smaller packages, smaller computing devices have gained popularity. The spread of smart phones, tablets, ultra-flat notebooks, and other user devices has grown exponentially. However, these smaller devices rely on servers for both data storage and complex processing beyond the form factor. Consequently, demand in the field of the high performance computing market (e.g., server space) has also increased. For example, in modern servers, there is usually not only a single processor with multiple cores, but also multiple physical processors (also referred to as multiple sockets) to increase computing power. However, as processing power increases with the number of devices in a computing system, communication between sockets and other devices becomes more critical.Indeed, interconnects (interconnects) have grown to fully-designed interconnect architectures that enable fast communication from the more conventional multi-drop buses that primarily perform electrical communications. Unfortunately, since the demand for future processors at even higher rates requires a corresponding demand, the capabilities of existing interconnect architectures are unfortunately placed on.BRIEF DESCRIPTION OF THE VARIOUS VIEWS OF THE DRAWINGSTo facilitate the discussion of any particular element or action, the foremost digit or digits in a reference numeral refers / refer to the figure number in which that element is first introduced. FIG. 1 illustrates a first system according to an embodiment. FIG. 2 illustrates an interconnect stack according to an embodiment. FIG. 3 illustrates a link initialization logic flow, according to an embodiment. FIG. 4 illustrates an initialized logic flow, according to an embodiment. FIG. 5 illustrates a second system according to an embodiment. FIG. 6 illustrates a third system according to an embodiment. FIG. 7 illustrates a logic flow according to an embodiment. FIG. 8 illustrates a fourth system according to an embodiment. FIG. 9 illustrates a top view of a semiconductor package according to an embodiment. FIG. 10 illustrates a computer readable storage medium according to an embodiment.DETAILED DESCRIPTIONEmbodiments described herein may include devices, systems, techniques, or processes related to high-speed semiconductor interconnects. Some embodiments relate in particular to on-package die-to-die (D2D) interconnects. In particular, embodiments herein may relate to on-package D2D interconnects for memories that use or are associated with the universal chiplet interconnect express (UCIe) protocol layer, the D2D adapter, or the physical layer (PHY).Embodiments relate generally to improvements for interconnects capable of communicating information between semiconductor dies arranged in on-package memory architectures. Some embodiments particularly relate to implementing an interconnect, such as a universal chiplet interconnect express (UCIe™) interconnect as defined by a universal chiplet interconnect express (UCIe™) specification promulgated by the UCle consortium, such as the UCle specification version 1.1, August 8, 2023, along with any follow-up statements, revisions, and variants (collectively referred to as the "UCle specification"). Although some embodiments implement a UCIe interconnect, it should be appreciated that other semiconductor interconnects defined by other semiconductor specifications may be used. The embodiments are not limited in this context.Generally, UCIe is an open industry standard interconnect that provides high bandwidth, low latency, power efficient, and low cost on-package connectivity between chiplets, which are specialized integrated circuits (ICs). Although the UCIe interconnect is primarily configured to handle communications between chiplets, embodiments implement techniques for extending the UCIe interconnect to manage communications between any types of semiconductor dies, sometimes referred to as semiconductor devices or simply devices. Examples of devices include, but are not limited to, central processing unit (CPU) dies, memory dies such as dynamic random access memory (DRAM) and flash memory, graphics processing unit (GPU) dies, sensor dies, power management integrated circuit (PMIC) dies, system-on-a-chip (SoC) dies, and so forth. For example, a UCIe interconnect may transport information between a SoC and one or more memory ICs referred to as memory chips. The SoC and memory chips are implemented in different architectures as separate semiconductor dies in the same semiconductor package. The SoC and memory chips each implement UCIe interfaces and associated interface logic to enable the SoC and memory chips to communicate standard memory signals as UCIe signals carried over the UCIe interconnect. This allows a unified solution to scale on-package memory to support various applications ranging from handheld computer-suitable applications to high-performance computing (HPC) applications.When two or more peer devices communicate via a UCle interconnect, the peer devices are sometimes referred to as "modules", wherein a transmitting device is referred to as a "module" and a receiving device is referred to as a "module partner". In many cases, the module and the module partner are able to operate at different data rates. When this rate discrepancy occurs, the devices may negotiate a least common multiple (LCM) between the different data rates to achieve a negotiated data rate for the UCIe interconnect. A negotiated data rate is the result of a process in which two or more devices achieve mutual agreement over the maximum transmission speed at which they can reliably communicate with each other, sometimes also referred to as a symmetric data rate. A symmetric data rate refers to a data transmission rate and / or a data reception rate that are equal or almost equal. This negotiation normally occurs during the initialization phase of the communication session. During this process, the semiconductor dies exchange information about their capabilities and determine the highest data rate that both can support without compromising the quality and integrity of the data transmission. The negotiated data rate ensures efficient and effective data transfer between devices while accounting for their respective capabilities and constraints. For example, it is assumed that one of the devices could operate at a maximum data rate of 16 gigabits per second (Gbps), while the other semiconductor die could operate at a maximum data rate of only 12 Gbps, or vice versa. The devices could negotiate a 12 Gbps symmetric data rate for the entire communications over the UCle interconnect.However, in some cases, peer devices may want to communicate information over the UCIe interconnect using an asymmetric data rate. An asymmetric data rate refers to a data transmission rate and / or data reception rate that are different from each other. Referring again to the preceding example, it is assumed that one of the devices could operate at a maximum data rate of 16 Gbps while the other semiconductor die could operate at a maximum data rate of only 12 Gbps, or vice versa. The devices may negotiate an asymmetric data rate of 16 Gbps for a first device communicating over a first transmit channel of the UCIe interconnect and 12 Gbps for a second device communicating over a second transmit channel of the UCIe interconnect, or the opposite for the first and second receive channels.Modern on-chip or off-chip protocols, including the UCIe specification, do not currently support asymmetric data rates within a UCIe interconnect. For example, Peripheral Component Interconnect Express (PCIe) supports a width reduction option in which PCIe can transfer the data through a limited number of lanes rather than using all data lanes. This option effectively reduces the bandwidth of the UCIe interconnect, but does not allow asymmetric data rates. In another example, the unified parallel interface (UPI) protocol uses fixed speed and bandwidth to transport data between CPUs. Neither of these protocols has sideband support and therefore are unable to support an asymmetric data rate option.Embodiments generally relate to techniques configured to achieve asymmetric data rates within a UCIe interconnect on an on-package die-to-die (D2D) UCIe interface. The UCle protocol offers a unique opportunity to implement asymmetric data rates. This is because the UCIe protocol at least partially defines a separate sideband protocol that supports initialization of a main band for the UCIe interconnect. The main band consists of a physical link that carries the actual data traffic. One of the applications of the sideband protocol in the UCIe specification is to exchange link parameters from one remote die to another remote die to establish a symmetric data rate for the main band communication over the UCIe interconnect. Embodiments extend the use of the sideband protocol to establish an asymmetric data rate for the main band communications over the UCIe interconnect. Further, embodiments use a forwarded sideband protocol clock feature to support the asymmetric data rate.Implementation of an asymmetric data rate for high speed interconnects, such as a UCIe interconnect, provides some technical advantages. A technical advantage is that some applications running on-die or off-die have a specific need for asymmetric bandwidth. For example, assume the foregoing case where one semiconductor die is a system on a chip (SoC) and another semiconductor die is a memory chip in the same semiconductor package. The SoC may implement an application that performs memory reads at a higher rate than memory writes. In this case of core-to-memory interactions, more bandwidth may be required for reads than for writes. Another technical advantage is that although a link layer of a semiconductor die may operate at a higher data rate than another semiconductor die, the negotiated symmetric data rate determines the total data rate and the throughput of the D2D interactions. Therefore, using asymmetric data rates will improve overall performance of the semiconductor dies and the UCIe interconnect. Yet another technical advantage is that the current UCIe specification supports only a symmetric data rate during the main band initialization, which is typically the slowest speed of both dies. Rather than using the slowest speed, the use of asymmetric data rates allows peer dies to operate at the highest possible data rate. Embodiments therefore result in increased system performance, lower computational costs, higher interconnect throughput, more efficient memory usage, and improved resource allocation and usage by a device, system, or application.FIG. 1 illustrates an example of a system 100. The system 100 may be an electronic system, such as a computing system that implements one or more semiconductor devices on a semiconductor die in a system-on-a-chip (SoC) implementation. The semiconductor die may implement one or more interconnects and associated connection protocols defined by a semiconductor specification, such as the UCIe specification, for example. UCIe is an open industry standard interconnect that provides high bandwidth, low latency, power efficient, and low cost on-package connectivity between chiplets.The system 100 illustrates an example of multiple semiconductor devices in a SoC 118. The system 100 illustrates die-level integration to provide power efficient and cost effective performance. The SoC 118 may be integrated with other package-level semiconductor dies with hand-held to high-end server applicability with multiple source dies connected by different packaging options in the same package.As shown in FIG. 1, the SoC 118 includes one or more processors 102 and one or more memories 106 coupled to a SoC fabric 104. A processor 102 may include any processing element, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or other processor. Each processor 102 is coupled to the SoC fabric 104 via a link 120, such as, for example, a front side bus (FSB). In one embodiment, link 120 is a serial point-to-point interconnect, as described below. In another embodiment, link 120 includes a serial differential interconnect architecture that conforms to various interconnect standards. Interconnect protocols and features discussed below may be used to implement the links 120 that couple the set of components introduced herein in FIG. 1.The memory 106 includes any storage device, such as random access memory (RAM), non-volatile (NV) memory, or other memory that can be accessed by devices in the system 100. The memory 106 is coupled to the SoC fabric 104 by a link 120, such as a memory interface. Examples of a memory interface include a dual data rate (DDR) memory interface, a dual channel DDR memory interface, a low power DDR (LPDDR) memory interface, a dynamic RAM (DRAM) memory interface, or other types of memory interfaces.The SoC fabric 104 is an interconnect infrastructure within a SoC design. It includes a network of wires, buses, and interconnects that enable communication and data transfer between various components and subsystems integrated on a single chip. The SoC fabric 104 serves as the backbone for interconnecting various functional blocks, such as the central processing unit (CPU) cores, memory controllers, input / output interfaces, graphics processors, accelerators, and other Intellectual Property (IP) blocks. It allows these components to communicate, share and cooperate data to efficiently perform the desired tasks. The SoC fabric 104 is responsible for managing data flow, routing signals, and maintaining the necessary data paths between various components. It ensures that data is transmitted accurately and with low latency while optimizing power consumption and overall performance.Although not shown, the SoC fabric 104 may be coupled to die external devices. Input / output (I / O) modules, also referred to as interfaces or ports, may implement a layered protocol stack to provide communication between the SoC fabric 104 and one or more semiconductor devices implemented on other semiconductor dies in a semiconductor package.The SoC 118 may further include one or more accelerators 108. An accelerator is a separate sub-structure of the architecture designed using a different set of objectives than the base processor, these objectives being derived from the requirements of a particular class of applications. Examples of accelerators include a graphics accelerator to improve graphics speaking capability, a cryptographic accelerator to assist in encryption or decryption, a web accelerator to improve web applications, a hypertext preprocessor (PHP) accelerator to assist in web development, and so forth.The SoC 118 may include other semiconductor devices or components to implement various computing or communication functions, such as a radio frequency circuit 110, a modem 112, an optical device 114, an analog device 116, and so forth. Embodiments are not limited in the type or number of semiconductor devices implemented for the SoC 118.FIG. 2 illustrates a UCIe interconnect stack 200. In various embodiments, the SoC 118 may implement a UCIe interconnect 212 as defined by the UCIe specification. The SoC 118 may use the UCle interconnect 212 to communicate with other semiconductor dies within the same semiconductor package, as described with reference to FIG. 5.Generally, a UCIe is an open industry standard interconnect that provides high bandwidth, low latency, power efficient, and low cost on-package connectivity between chiplets. The UCle specification defines a ubiquitous package-level interconnect and covers the die-to-die (D2D) input / output (I / O) physical layer, D2D protocols, and software stacks that utilize the well-established industry standards peripheral component interconnect express (PCI express® or PCIe®) and compute express Link™ (CXL™).The UCIe specification details the full standardized D2D interconnect with physical layer, protocol stack, software model, and compliance tests that will allow end users to easily mix and balance chiplet components from a multi-provider environment for system-on-chip (SoC) design, including an adjusted SoC. The physical layer supports up to 32 gigatransfers per second (GT / s) with 16 to 64 lanes and uses a 256 byte flow control unit (FCU) for data similar to PCIe 6.0. The protocol layer is based on compute express link with the protocols CXL.io (PCIe), CXL.mem and CXL.cache. Various die-internal interconnect technologies are defined, such as organic substrate for a "standard" 2D package or embedded silicon bridge (EMIB), silicon interposer, and fanout embedded bridge for "advanced" 2.5D / 3D packages. Physical specifications based on the Advanced Interface Bus (AIB) as defined by Intel® Corporation, located in Santa Clara, California.UCIe supports different data rates, widths, bump spacings, and channel ranges to ensure maximum interoperability. It defines a sideband interface for ease of design and validation. The design unit of the interconnect is a cluster that includes N unbalanced, unidirectional, full-duplex data lanes (where N=16 applies to a standard package and 64 applies to an advanced package), an unbalanced lane for validation, a lane for tracking, a differential propagated clock per direction, and 2 lanes per direction for the sideband (e.g., unbalanced, a 1200 MHz clock, and a data lane). The advanced chassis supports spare lanes to handle faulty lanes (e.g., including clock, validation, sideband, etc.), while the standard chassis supports width reduction to handle failures. Multiple clusters may be aggregated to provide more performance per link.UCIe is a layered protocol as represented by a UCIe interconnect stack 200. The UCIe interconnect stack 200 may include a protocol layer 202, a die-to-die adapter 204, and a physical layer 206.The physical layer 206 may be coupled to a UCle interconnect 212. Physical layer 206 is responsible for electrical signaling, timing, link training, lane repair, lane reversal, scrambling / descrambling, sideband initialization and transfers, analog front end (AFE), clock forwarding, and other physical layer operations. The main data path of the UCIe on the physical bumps is organized as a group of lanes, referred to as a module. A module constitutes the atomic granularity for the structural design implementation of the UCIe analog front end (AFE). The number of lanes per module for standard and advanced enclosures is specified in Chapter 4.0 of the UCIe specification. A given instance of the protocol layer 202 or the de-to-die adapter 204 may send data over multiple modules where bandwidth scaling is required.The physical layer 206 of the UCIe includes two connections, referred to as a sideband sub-component 214 and a main band sub-component 216.Sideband subcomponent 214 forms a connection that is used for parameter swaps, debug / compliance register accesses, and coordination with a remote partner for link training and management. It comprises a Forward Clock pin and a Data pin in each direction. In one embodiment, the clock is fixed to 800 megahertz (MHz) regardless of the speed of the main data path. The sideband logic for the UCIe physical layer 206 should be auxiliary power and an "always on" domain. Each module has its own set of sideband pins. For the advanced package option, a redundant pair of clock and data pins is provided in each direction for repair.The main band sub-component 216 forms a link that represents the main data path of the UCIe. It consists of a forwarded clock, a valid data pin and N data lanes per module. For the advanced package option, N=64 (also referred to as x64) and a total of four additional pins are provided for lane repair in the bump card. For the standard package option, N=16 (also referred to as x16) and no additional pins are provided for repair.A logical physical layer (PHY) coordinates the various functions and their relative sequencing for proper link setup and management(s) (e.g., sideband transfers, master band training, and repair, etc.). The logical PHY includes the following functions: link initialization, training, and power management states; byte-to-lane allocation for data transmissions over lanes; interconnect redundancy reallocation (if necessary); transmission and reception of sideband messages; scrambling and training pattern generation; lane reversal; and width reduction (if appropriate). An example of link initialization operations are described with reference to FIG. 3.Information may be passed between the physical layer 206 and the die-to-die adapter 204 via a raw D2D interface (RDI) 210. The die-to-die adapter 204 provides link state management and parameter negotiation for chiplets and semiconductor dies, such as, for example, the SoC 118. Optionally, it guarantees reliable delivery of data through its cyclic redundancy check (CRC) and link level retry (link level retry) mechanism. When multiple protocols are supported, it defines the underlying arbitration mechanism. A 256 byte flow control unit (FCU) level interface transfer (FLIT) defines the underlying transfer mechanism when the adapter is responsible for reliable transfer. Information may be passed between the die-to-die adapter 204 and the protocol layer 202 via a FLITbewusst D2D interface (FDI) 208.UCle natively maps PCIe and CXL protocols since they are widely deployed at the board level across all computing segments. This is done to ensure seamless interoperability by exploiting the existing ecosystem. With PCIe and CXL, SoC setup, link management, and security solutions already deployed can be used for UCl. The addressed usage models are also comprised of: data transfer using direct memory access, software discovery, error handling, etc., are addressed with PCIe / CXL.io; the memory usage cases are handled by CXL.mem; and caching requests for applications such as accelerators are addressed with CXL.cache. UCIe also defines a "streaming protocol" that can be used to map to any other protocol. Further, in future, with future developing usage models, the UCle consortium may develop protocol re-establishments optimized for chiplets and semiconductor dies.Although the UCle interconnect 212 is configured to handle communications between chiplets that are specialized integrated circuits (ICs), it may be extended to manage communications between any semiconductor dies, such as the SoC 118 and one or more memory ICs referred to as memory chips. The SoC 118 and the memory chips are implemented as separate semiconductor dies in the same semiconductor package. The SoC 118 and memory chips each implement UCIe interfaces and associated interface logic to enable the SoC 118 and memory chips to communicate standard memory signals as UCIe signals carried over the UCIe interconnect 212. For example, the memory controller 122 of the SoC 118 may send read or write commands and data for an on-package memory unit using a standard memory interface and associated memory signals. Similarly, the on-package memory unit may receive the memory signals and send a response to the memory controller 122 using a standard memory interface and associated memory signals. Therebetween, the UCIe interfaces and associated interface logic map the memory signals to UCIe signals for transport over the UCIe interconnect 212 and the UCIe signals back to memory signals for communication to the memory controller 122 or the memory units. This allows a unified solution to scale on-package memory to support various applications ranging from handheld computer-suitable applications to HPC applications.FIG. 3 illustrates a link initialization logic flow 334 for the main band sub-component 216. The link initialization logic flow 334 includes four stages before protocol flit transfer can begin on a main band channel of the UCle interconnect 212. An example of link initialization logic flow 334 and corresponding operations are described in section 3.2 of the UCIe specification.Link initialization logic flow 334 shows the high-level steps involved in the link initialization flow for a D2D channel 314 of UCle interconnect 212 over time. Stage 0 is die specific and occurs independently for each die; the corresponding boxes in FIG. 3 have different sizes to indicate that different dies may require different amounts of time to end stage 0. Stage 1 includes sideband detection and training. Level 2 includes main band training and repair. Level 3 includes parameter exchanges, such as configuration parameters, between die-to-die adapters 204 to negotiate the protocol and flit formats.As shown in FIG. 3, a protocol layer die 0 302, a D2D adapter die 0 304, and a physical layer die 0 306 perform stage 0 318. Stage 0 318 performs a reset flow for Die 0 independent of Die 1. Meanwhile, a physical layer die 1 308, a D2D adapter die 1 310, and a protocol layer die 1 312 also execute stage 0 320. Stage 0 320 performs a reset flow for die 1 regardless of die 0. Once stage 0 318 and stage 0 320 are completed, physical layer die 0 306 and physical layer die 1 308 perform stage 1 322. Stage 1 322 performs sideband detection and training operations.Once stage 1 322 is completed, physical layer die 0 306 and physical layer die 1 308 execute stage 2 324. Stage 2 324 performs training parameter exchanges on a sideband channel and main band lane repair and training operations. During stage 2 324, the training parameter swap operations may include swapping parameters for main band initialization and training, including establishment and negotiation of data rates of die 0 and die 1. Phase 2 324 is complete when the state machine of the RDI 210 transitions to the active state. The initialization flow of the RDI 210 to transition the status from reset to active is described in section 8.1.6 of the UCIe specification.Once phase 2 324 is complete, the D2D adapters must follow a sequence of steps to determine local capabilities, complete parameter swaps, and set the FDI state machine to active. For example, the D2D adapter die 0 304 and the D2D adapter die 1 310 perform stage 3 326. Stage 3 326 performs protocol parameter exchanges on the sideband channel of the D2D channel 314.FIG. 4 illustrates an initialization logic flow 420 suitable for stage 2 324. UCIe has a hierarchical approach to link state management to have a well-defined function partitioning between the different layers and also to enable common state transitions or sequencing at FDI 208 and FDI 210.Initialization logic flow 420 shows a high level initialization flow with different states. A high level description of state definitions for initialization is presented in Table 1 as follows. TABLE 1 TABLE 1RESETThis is the state following a primary reset or exit from TRAINERRORSBINITSideband Initialization State in which the sideband is detected, repaired (if appropriate), and transmitted from the Reset MessageMBINITFollowing sideband initialization, the master band (MB) is initialized at the lowest speed. Both dies perform on-die calibration followed by interconnect repair (if appropriate)MBTRAINMaster band (data, clock and valid signals) operation speed is set to the highest negotiated data rate. The main band die training is performed to center the clock with respect to dataLINKINITThis state is used to exchange adapter and link management messagesACTIVEThis is the state in which transactions are sent and receivedL1 / L2Power Management StatePHYRETRAINThis state is used to begin the retraining flow for the link during runtimeTRAIN ERRORThis state is entered when a fatal or non-fatal event occurs at any point during link training or operationInitialization logic flow 420 represents flow between various states, referred to as RESET 402, SBINIT 404, MBINIT 406, MBTRAIN 408, LINKINIT 410, ACTIVE 412, L1 / L2 414, PHYRETRAIN 416, and TRAINERROR 418. Each of these states corresponds to descriptions as provided in the UCIe specification.In particular, the UCIe specification defines the MBINIT 406 state. In this state, the master tape interface is initialized and repaired or reduced (if appropriate). The data rate on the main band is set to the lowest supported data rate (4 GT / s). Repair may be required for an advanced package interface interconnect. The substate in MBINIT allows the detection and repair of data, clock, track and valid lanes. No lane repair is required for the standard package interface. Substates are used to test functionality at the lowest data rate and width reduction, if necessary.The UCle specification also defines the MBTRAIN 408 state. The state of MBTRAIN 408 is to establish the operation speed and perform a clock for data centering. At higher speeds, additional calibrations such as Rx clock correction, transmit (Tx), and receive (Rx) equalization may be required to ensure link performance. MBTRAIN 408 uses substates to perform all the required(s) calibrations and training. UCIe modules must enter each substate and the exit from each substate is coordinated between the UCIe module partners by sideband handshakes. If a particular action within a substate is not required, the UCle module may exit the substate through the relevant slave handshake without performing the described operations in that substate.In state MBINIT 406, MBINIT.PARAM is used to perform an exchange of parameters required to establish the maximum negotiated speed and other PHY settings. Main band transmitters remain with three states and main band receivers may be disabled. The following parameters are exchanged with a UCIe module (e.g., Die 0) and a UCIe module partner (e.g., Die 1).1. "Voltage swing": The five-bit value indicates the transmitter voltage swing to the UCIe module partner. The UCle module partner must use this value and its receiver termination information to set the reference voltage (Vref) for its receivers. The corresponding bits in {MBINIT.PARAM configuration resp} are reserved.2. "Maximum Data Rate": The four-bit value indicates the maximum supported data rate for the UCIe module partner. This value must take all the required features into account in the data rate (bit error rate (BER), cyclic redundancy check (CRC), retry, quadrature clock phase support, etc.). The UCIe module partner must compare this value with its supported maximum data rate and must respond with the maximum shared data rate coding in MBITI.PARAM configuration resp}. For example, a UCIe module is capable of 8 GT / s, while the UCIe module partner 16 indicates GT / s, and the UCIe module must select and return 8 GT / s in response.3. "Clock mode": The one bit value indicates the request of the UCIe module to the UCIe module partner for a strobe or continuous clock. The UCIe module partner must use this information to establish the clock mode on its clock transmitter. {MBITI.PARAM configuration resp} must reflect the same value.4. "Clock phase": The one-bit value indicates the request of the UCIe module to the UCIe module partner for clock phase support on a forwarded clock of the UCIe module. This value should be set to 1b only if the maximum data rate indicated allows it (see Table 35 of the UCle specification). The corresponding bit in {MBINIT.PARAM configuration resp} must be set to 1b if requested and the operating data rate allowed.5. "Module ID": The UCle module sends its "Module ID". This can be used by the UCIe module partner in a multi-module configuration for byte allocation, module activation / deactivation information, etc. The corresponding bits in {MBINIT.PARAM configuration resp} are reserved.6. "UCle-A x32": This bit is set to 1b if the APMW bit in DVSEC-UCle-Link Capability Register (see section 7.5.1.4) is set to 1b (OR) "Force x32 width Mode in x64 Modules" in the PHY Control Register (see section 7.5.3.23); otherwise, the bit is set to 0b. When an x64 Advanced Package Module supports width reduction to cooperate with an x32 Advanced Package Module, it uses this information from its link partner to condition the results during MBINIT.REVERSELMB. The corresponding bits in {MBINIT.PARAM configuration resp} are reserved.The following is an example sequence for parameter exchange: (1) the UCIe module sends the sideband message {MBINIT.PARAM configuration req} to exchange parameters with the UCIe module partner; and (2) once {MBINIT.PARAM configuration req} is received, the UCIe module partner releases this and responds with a {{MBINIT.PARAM configuration resp} sideband message.As previously stated, the UCIe module sends a maximum supported data rate parameter to the UCIe module partner. The UCIe module partner compares this value with its supported maximum data rate and must respond with the maximum shared data rate coding in MBITI.PARAM configuration resp}. For example, a UCIe module is capable of 8 GT / s, while the UCIe module partner 16 indicates GT / s, and the UCIe module must select and return 8 GT / s in response. The maximum common data rate is an example of a symmetric data rate between the UCIe module and the UCIe module partner.Embodiments implement techniques that enable the UCIe module and the UCIe module partner to each operate at an asymmetric data rate, wherein the asymmetric data rate comprises each of their own maximum possible data rates, rather than using a negotiated data rate. The UCle interconnect 212 may be trained to use the symmetric data rate or the asymmetric data rate in response to a signal that enables a given transport mode, where the transport mode uses the symmetric data rate or the asymmetric data rate. The transport mode may be set by an application residing on the die or off the die. For example, the application logic may generate an application signal to enable a given transport mode. The UCIe module supporting this feature will first negotiate the link speed, but when the traffic begins it has the flexibility to operate at a higher rate than the negotiated rate.To this end, embodiments add a novel exchange of parameters between the UCIe module and the UCIe module partner to negotiate and establish an asymmetric data rate. Embodiments may use an existing parameter such as MBINIT.PARAM configuration request and / or MBINIT.PARAM configuration response or a newly defined parameter, for example MBINIT.PARAM.AS. An example of a representative system 566 for implementing modified versions of MBITI 406 and / or MBTRAIN 408 for initializing, training, and utilizing asymmetric data rates for the main band of the UCIe interconnect 212 will be described with reference to FIG. 5.FIG. 5 illustrates a system 566 that provides an example for implementing the embodiments as described herein. Example 566 includes a semiconductor package 508. The semiconductor package 508 includes a semiconductor die 0 502 and a semiconductor die 1 504 that can communicate control and data signals via the UCle interconnect 212.As shown in FIG. 5, semiconductor die 0 502 includes interface logic 570, such as main band logic 510 and sideband logic 512, coupled to a PHY 514. The main band logic 510 and the sideband logic 512 may include examples of the logic for the die-to-die adapter 204 and the D2D adapter die 0 304 to perform link initialization and training, such as described at link initialization logic flow 334 and / or initialization logic flow 420. The PHY 514 includes one or more of a transmit FIFO 550 and a receive FIFO 552. A first-in-first-out (FIFO) is used to organize and manipulate data in a particular order using a data structure called a FIFO queue. In a FIFO queue, new elements are added to the queue at the end (also known as the tail) and removal of elements takes place at the beginning (also referred to as the head) of the queue. This ensures that the oldest element in the queue is always the first to be removed. For example, in one embodiment, each side of the UCIe interconnect 212 may instantiate the cross-clock FIFOs internally as needed, as long as it does not violate the requirements on the interface itself.The semiconductor die 1 504 implements similar structures to the semiconductor die 0 502. The semiconductor die 1 504 includes interface logic 572, such as main band logic 518 and sideband logic 520, coupled to a PHY 522. The PHY 522 includes at least one of a receive FIFO 554 and a transmit FIFO 556.The semiconductor die 0 502 and the semiconductor die 1 504 communicate UCle signals to carry information among each other over one or more main data paths, such as main data path 526 and main data path 528, for example. The main data path 526 and the main data path 528 use one or more lanes and modules as described above. The main data path 526 carries information from the transmit FIFO 550 of the semiconductor die 0 502 to the receive FIFO 554 of the semiconductor die 1 504. The main data path 528 carries information from the transmit FIFO 556 of the semiconductor die 1 504 to the receive FIFO 552 of the semiconductor die 0 502. Although a single main data path 526 and main data path 528 are illustrated in FIG. 5, it should be appreciated that multiple main data paths 526 and multiple main data paths 528 may be implemented using corresponding modules for bandwidth scaling. It is also noteworthy that from the perspective of the semiconductor die 0 502, the main data path 526 is used to transmit information to the semiconductor die 1 504, and is sometimes also referred to as a transmit channel for the semiconductor die 0 502. However, from the perspective of the semiconductor die 1 504, the main data path 526 is used to receive information from the semiconductor die 0 502, and is sometimes referred to as a receive channel for the semiconductor die 1 504. The same concept applies to the main data path 528. Thus, depending on whether the semiconductor die 0 502 and the semiconductor die 1 504 transmit information or receive information, the main data path 526 and the main data path 528 may be considered to be transmit channels or receive channels.The semiconductor die 0 502 and the semiconductor die 1 504 may also exchange sideband information transmitted as sideband signal 558 and / or sideband signal 560 over one or more transmit channels or receive channels of the UCIe interconnect 212. The sideband information may include configuration parameters for the semiconductor die 0 502 and the semiconductor die 1 504. The main band logic 510, main band logic 518, sideband logic 512, and / or sideband logic 520 may use the configuration parameters for link initialization, link training, link transport, and other operations as described above.In particular, the sideband information may be used to initialize, train, and negotiate a symmetric data rate and / or an asymmetric data rate for a main band of the UCIe interconnect 212, as represented by the main data path 526 and the main data path 528.As described above, sideband logic 512 of semiconductor die 0 502 may negotiate a symmetric data rate for main data path 526 and main data path 528. In an embodiment, the symmetric data rate may include a four-bit value indicating the maximum supported data rate X 546 from the semiconductor die 0 502 to the semiconductor die 1 504. This value takes into account all the required characteristics in data rate (bit error rate (BER), cyclic redundancy check (CRC), retry, quadrature clock phase support, etc.). The sideband logic 520 of the semiconductor die 1 504 compares this value to its supported maximum data rate Y 548 and responds at the maximum common data rate C 568 encoded in {MBITT.PARAM configuration resp}. For example, it is assumed that semiconductor die 0 502 is capable of 16 GT / s while semiconductor die 1 504 indicates 12 GT / s, and semiconductor die 1 504 selects 12 GT / s for both main data path 526 and main data path 528 and, in response, sends the symmetric data rate back to semiconductor die 0 502.Additionally or alternatively, sideband logic 512 of semiconductor die 0 502 may negotiate an asymmetric data rate for main data path 526 and main data path 528. In an embodiment, the symmetric data rate may comprise a four-bit value indicating the maximum supported data rate from the semiconductor die 0 502 to the semiconductor die 1 504. This value takes into account all the required characteristics in data rate (bit error rate (BER), cyclic redundancy check (CRC), retry, quadrature clock phase support, etc.). The sideband logic 520 of the semiconductor die 1 504 compares this value to its supported maximum data rate and responds to its maximum common data rate encoded in {MBINIT.PARAM configuration resp}. For example, it is assumed that semiconductor die 0 502 is capable of 16 GT / s while semiconductor die 1 504 indicates 12 GT / s, and semiconductor die 1 504 selects 16 GT / s for main data path 526 and 12 GT / s for main data path 528, and in response, sends the asymmetric data rate back to semiconductor die 0 502.FIG. 6 illustrates a system 626. The system 626 provides a more detailed view of the semiconductor die 0 502 and the semiconductor die 1 504 introduced into the system 566 of FIG. 5.In particular, the semiconductor die 0 502 includes a Main Band Initialization (MBINIT) Finite State Machine (FSM), referred to as MBINIT FSM 604, coupled to the sideband logic 512 and a link layer clock 606. MBINIT FSM 604 implements a state machine for main band logic 510 to perform main band initialization operations as described above. The link layer clock 606 is a clocking mechanism, such as a hardware or software clock, for link layer operations implemented by the semiconductor die 0 502. The UCIe interconnect 212 supports multiple protocols (e.g., PCIe, CXL, streaming, and a raw format that can be used to allocate any protocol as long as both ends support this) on a common physical and link layer. In one embodiment, the UCIe interconnect 212 allows a single UCIe link to be shared among multiple protocol stacks.Similarly, the semiconductor die 1 504 includes a Main Band Initialization (MBINIT) Finite State Machine (FSM), referred to as MBINIT FSM 608, coupled to the sideband logic 520 and a link layer clock 610. MBINIT FSM 604 implements a state machine for main band logic 518 to perform main band initialization operations as described above. The link layer clock 610 is a clocking mechanism, such as a hardware or software clock, for link layer operations implemented by the semiconductor die 0 502.As described above with reference to FIG. 5, the PHY 514 of the semiconductor die 0 502 and the PHY 522 of the semiconductor die 1 504 may exchange information via the main data path 526 and the main data path 528. In one embodiment, the PHY 514 of the semiconductor die 0 502 may transmit a main band signal 628 from the transmit FIFO 550 to the receive FIFO 554 via the main data path 526 via a transmit channel of the main data path 526. The PHY 522 of the semiconductor die 1 504 may receive the main band signal 628 from the transmit FIFO 550 over a receive channel of the main data path 526 through the receive FIFO 554 over the main data path 526. In one embodiment, the PHY 522 of the semiconductor die 1 504 may transmit a main band signal 630 from the transmit FIFO 556 to the receive FIFO 552 via a transmit channel of the main data path 528 via the main data path 528. The PHY 514 of the semiconductor die 0 502 may receive the main band signal 630 from the transmit FIFO 556 over a receive channel of the main data path 528 through the receive FIFO 552 over the main data path 528.As described above with reference to FIG. 5, the PHY 514 of the semiconductor die 0 502 and the PHY 522 of the semiconductor die 1 504 may also exchange the sideband signal 558 and the sideband signal 560 to carry sideband information such as configuration parameters, for example. In addition, PHY 514 and PHY 522 may exchange clock information via forwarded clock signals 618 and forwarded clock signals 622 and data via data signals 620 and data signals 624 as specified by the UCIe specification. In an embodiment, the forwarded clock signals 618 may include clock information from the link layer clock 606 of the semiconductor die 0 502. In an embodiment, the forwarded clock signals 622 may include clock information from the link layer clock 610 of the semiconductor die 1 504.The operations for the semiconductor die 0 502 and / or the semiconductor die 1 504 are further described with reference to FIG. 7.Operations for the disclosed embodiments may be further described with reference to the following figures. Some of the figures may include a logic flow. Although such figures presented herein may include a particular logic flow, it should be understood that the logic flow provides only one example of how the general functionality described herein may be implemented. Further, a given logic flow need not necessarily be performed in the presented order unless otherwise indicated. Additionally, in some embodiments, not all actions illustrated in a logic flow may be required. In addition, the given logic flow may be implemented by a hardware element, a software element executed by a processor, or any combination thereof. The embodiments are not limited in this context.FIG. 7 illustrates an embodiment of a logic flow 700. Logic flow 700 may be representative of some or all of the operations performed by one or more embodiments described herein. For example, logic flow 700 may include some or all of the operations performed by devices or entities described herein. In particular, logic flow 700 illustrates an example where semiconductor die 0 502 and semiconductor die 1 504 communicate UCIe signals over a sideband channel and / or a main band channel of UCIe interconnect 212.In block 702, the logic flow 700 encodes a first configuration parameter for a main band of a universal chiplet interconnect express (UCIe) interconnect for a first sideband signal, the first configuration parameter representing a first data rate for the main band of the UCIe interconnect. In block 704, logic flow 700 decodes a second configuration parameter for the main band of the UCIe interconnect from a second sideband signal, the second configuration parameter representing a second data rate for the main band of the UCIe interconnect. In block 706, the logic flow 700 decodes a third configuration parameter for the main band of the UCIe interconnect from an application signal, the third configuration parameter representing a transport mode for the UCIe interconnect. At block 708, the logic flow 700 encodes information for a first main band signal for transport over a transmission channel of the UCIe interconnect at the first data rate when the transport mode for the UCIe interconnect is set to an asymmetric mode. In block 710, the logic flow 700 encodes information into the first main band signal for transport over the transmission channel of the UCIe interconnect at a third data rate when the transport mode for the UCIe interconnect is set to a symmetric mode, the third data rate representing a smallest common multiple between the first data rate and the second data rate.For example, with reference to semiconductor die 0 502 and / or semiconductor die 1 504, sideband logic 512 of semiconductor die 0 502 encodes a first configuration parameter for a main data path 526 of UCIe interconnect 212 in a first sideband signal 558. The first configuration parameter represents a first data rate X 546 for the main band of the UCle interconnect 212, where X represents any positive integer. Sideband logic 512 also decodes a second configuration parameter for main data path 528 of UCIe interconnect 212 from a second sideband signal 558. The second configuration parameter represents a second data rate Y 548 for the main data path 528 of the UCIe interconnect 212, where Y represents any positive integer.In one embodiment, the first data rate X 546 may be equal or nearly equal to the second data rate Y 548 (e.g., X=Y). In one embodiment, the first data rate may deviate from the second data rate. For example, the first data rate X 546 may be higher than the second data rate Y 548 (e.g., X>Y), or the first data rate X 546 may be lower than the second data rate Y 548 (e.g., X<Y), and vice versa (e.g., Y>X or Y<X).In an embodiment, the first data rate X 546 for the main data path 526 of the UCle interconnect 212 represents a maximum transmit data rate and / or a maximum receive data rate of the semiconductor die 0 502. Similarly, the second data rate Y 548 for the main data path 528 of the UCle interconnect 212 represents a maximum transmit data rate and / or a maximum receive data rate of the semiconductor die 1 504.Sideband logic 512 decodes a third configuration parameter for main data path 526 and main data path 528 of UCIe interconnect 212 from an application signal 602. For example, application logic 544 may be implemented by an internal die or external die application that utilizes the transport services of UCIe interconnect 212. The application may require different data rates for transmitting and receiving data. For example, assume that the application uses a memory controller implemented by semiconductor die 0 502 to read and write data to a memory unit implemented by semiconductor die 1 504. The read operations may occur more frequently than the write operations, or vice versa. In such cases, the application may encode a transport mode 614 and a transport mode 616 in an application signal 602 and an application signal 612, respectively, to indicate that an asymmetric data rate is required.The main band logic 510 encodes information for a first main band signal 628 for transport over a transmit channel of the main data path 526 of the UCIe interconnect 212 at the first data rate X 546 when the transport mode 614 for the UCIe interconnect 212 is set to an asymmetric mode. The main band logic 510 may also decode information from a second main band signal 630 from a receive channel of the UCIe interconnect 212 at the second data rate Y 548 when the transport mode for the UCIe interconnect is set to the asymmetric mode. For example, in one embodiment, the main band logic 510 may decode information from the second main band signal 630 using a third side band signal 560, where the third side band signal 560 includes one or more forwarded clock signals 622 from the link layer clock 610.Additionally or alternatively, the main band logic 510 encodes information for the first main band signal 628 for transport over the main data path 526 of the UCIe interconnect 212 at a third data rate C 568 when the transport mode 614 for the UCIe interconnect 212 is set to a symmetric mode, where Z represents any positive integer. In one embodiment, the third data rate C 568 represents a smallest common multiple between the first data rate X 546 and the second data rate Y 548.The foregoing examples illustrate operations from the perspective of semiconductor die 0 502. The same examples may be reversed to illustrate the same operations from the perspective of the semiconductor die 1 504. In one embodiment, the UCle interconnect 212 transports signals between the semiconductor die 0 502 and the semiconductor die 1 504 when implemented in a single semiconductor package 508. In one embodiment, the UCle interconnect 212 transports signals between the semiconductor die 0 502 and the semiconductor die 1 504 when implemented in different semiconductor packages 508 or when mounted on a common substrate such as a printed circuit board (PCB), for example.In particular, during initialization of the UCIe interconnect 212, a speed is negotiated between the semiconductor die 0 502 and the semiconductor die 1 504, both dies exchanging the maximum data rate value at which each of them can operate. Based on these values, both dies are designed to operate at the lowest common multiple data rate value. The current UCIe specification mentions no asymmetric data rate option in which the semiconductor die 0 502 and the semiconductor die 1 504 may operate at a different data rate based on individual capabilities. However, an asymmetric data rate option is possible because the RX FIFO operates on the forwarded clock from the TX side.The various possible combinations are below based on a current version of the UCIe specification that defines symmetric data rates. If the semiconductor die 0 502 and the semiconductor die 1 504 have a common maximum frequency, both are all in charge of operating at this value. If the semiconductor die 0 502 supports X Gbps and the semiconductor die 1 504 supports Y Gbps, where X>Y, then the semiconductor die 0 502 will negotiate with X'=Y during negotiation. The semiconductor die 0 502 and the semiconductor die 1 504 then operate at a Y data rate. If the semiconductor die supports 0 502 X Gbps and the semiconductor die supports 1 504 Y Gbps, where X<Y, then the semiconductor die 1 504 will negotiate with Y'=X during negotiation. The semiconductor die 0 502 and the semiconductor die 1 504 then operate at an X data rate.The various possible combinations are based on a future version of the UCIe specification that uses asymmetric data rates. If the semiconductor die 0 502 and the semiconductor die 1 504 have a common maximum frequency, both are all in charge of operating at this value. If the semiconductor die 0 502 supports X Gbps and the semiconductor die 1 504 supports Y Gbps, where X>Y, then the semiconductor die 0 502 will negotiate with X'=Y during negotiation. The semiconductor die 0 502 operates at an X data rate and the semiconductor die 1 504 operates at a Y data rate. If the semiconductor die supports 0 502 X Gbps and the semiconductor die supports 1 504 Y Gbps, where X<Y, then the semiconductor die 1 504 will negotiate with Y'=X during negotiation. The semiconductor die 0 502 operates at an X data rate and the semiconductor die 1 504 operates at a Y data rate.In a first case, it is assumed that PHY 514 of semiconductor die 0 502 may operate at a maximum of an X data rate and PHY 522 of semiconductor die 1 504 may operate at a maximum of a Y data rate, where X>Y. The PHY 514 and PHY 522 may negotiate a symmetric data rate of Y and both dies then operate at the Y data rate. Alternatively, PHY 514 and PHY 522 may negotiate an asymmetric data rate, where the negotiated speed from PHY 522 will be Y and the negotiated speed from PHY 514 will be X. There is a data rate X' now known to PHY 514, where X' = negotiated speed is less than the actual speed of PHY 514. However, PHY 514 does not perform some part of its logic with X', but all of the logic in PHY 514 operates at an X data rate. The PHY 514 transmission will run on a phase locked loop (PLL) of the semiconductor die 0 502, and reception of the PHY 522 will operate on propagated clock signals 618 from the sideband logic 512. Even if this physical channel can operate at a Y data rate, it will continue to operate at an X data rate due to the clock signals 618 being passed.The PHY 522 transmission will run on a PLL of the semiconductor die 1 504, and reception of the PHY 514 will operate on forwarded clock signals 622 from the semiconductor die 1 504. Even if this physical channel can operate at an X data rate, it will continue to operate at a Y data rate due to clock signals 622 being passed.It is assumed that the link layer clock 606 operates at a Z data rate, where Z represents any positive integer. Further, the case where Z>X>Y is assumed. The bottleneck in each communication system is typically the PHY layer. Previously, the PHY layer was used to operate at a lower speed than the PHY layer of the 2 dies, i.e., at the symmetric data rate. However, by enabling an asymmetric data rate, the PHY layers of the 2 dies can operate at a highest possible data rate on their channel. The link may still operate at an even higher data rate, such as when Z>>X>Y applies. Table 2 provides some example values. TABLE 2 TABLE 244Agreed / Negotiated=12Agreed / negotiated = X' = 1288Module will work with 12Module will still operate at 161212(Y)Partner will work with 12Partner will still work with 1216(X)Z>X>YIn a second case, it is assumed that PHY 514 of semiconductor die 0 502 may operate at a maximum of an X data rate and PHY 522 of semiconductor die 1 504 may operate at a maximum of a Y data rate, where X<Y. The PHY 514 and PHY 522 can negotiate a symmetric data rate of X and both dies then operate at the Y data rate. Alternatively, PHY 514 and PHY 522 may negotiate an asymmetric data rate, where the negotiated speed from PHY 522 will be Y and the negotiated speed from PHY 514 will be X. There is a data rate Y' now known to PHY 522, where Y' = negotiated speed is less than the actual speed of PHY 514. However, PHY 522 does not perform some part of its logic with Y', but the entire logic in PHY 522 operates at a Y data rate. The PHY 514 transmission will run on a PLL of the semiconductor die 0 502, and the reception of the PHY 522 will operate on forwarded clock signals 618 from the sideband logic 512. Even if this physical channel can operate at a Y data rate, it will continue to operate at an X data rate due to the clock signals 618 being passed.The PHY 522 transmission will run on a PLL of the semiconductor die 1 504, and reception of the PHY 514 will operate on forwarded clock signals 622 from the semiconductor die 1 504. Even if this physical channel can operate at an X data rate, it will continue to operate at a Y data rate due to clock signals 622 being passed.It is assumed that the link layer clock 606 operates at a Z data rate. Further, the case where Z>Y>X is assumed. The bottleneck in each communication system is typically the PHY layer. Previously, the PHY layer was used to operate at a lower speed than the PHY layer of the 2 dies, i.e., at the symmetric data rate. However, by enabling an asymmetric data rate, the PHY layers of the 2 dies can operate at a highest possible data rate on their channel. The link may still operate at an even higher data rate, such as when Z>> Y>> X applies. Table 3 provides some example values. TABLE 3 TABLE 344Agreed / Negotiated=12Agreed / negotiated = Y' = 1288Module will work with 12Module will still operate at 1212(X)12Partner will work with 12Partner will still work with 1616(Y)Z>>Y>XEmbodiments are not limited to these examples.FIG. 8 illustrates a system 800. The system 800 illustrates a particular example of a pair of semiconductor dies similar to the semiconductor die 0 502 and the semiconductor die 1 504 implemented by the system 566 and / or the system 626. The example semiconductor dies may implement the symmetric data rate technique and the asymmetric data rate technique as described herein.The system 800 may include a SoC 118 and a memory chip 802 integrated into a single semiconductor package 806. The SoC 118 may exchange signals with the memory chip 802 via a UCle interconnect 804. The SoC 118 and the memory chip 802 may implement the UCIe interface 808 and the UCIe interface 810, respectively. The SoC 118 and the memory chip 802 may also implement interface logic 822 and interface logic 824, respectively. In one embodiment, the UCIe interface 808, the UCIe interface 810, the interface logic 822, the interface logic 824, and the UCIe interconnect 804 may conform to the UCIe specification.In various embodiments, operations for UCIe interface 808 and interface logic 822 mirror operations for UCIe interface 810 and interface logic 824, and vice versa. Thus, operations discussed with respect to the UCIe interface 808 and the interface logic 822 of the SoC 118 are the same or similar to those for the UCIe interface 810 and the interface logic 824 of the memory chip 802, and vice versa.In various embodiments, the memory controller 122 of the SoC 118 may communicate with a memory 812 of the memory chip 802 via the UCle interconnect 804. For example, in one embodiment, UCIe interface 808 and UCIe interface 810 may each implement interface logic 822 and interface logic 824, respectively, to manage communications over UCIe interconnect 804. Interface logic 822 and interface logic 824 each manage the transport of data via UCle interconnect 804 in a transmit and receive mode.From the perspective of the SoC 118, the UCle interface 808 receives memory signals from the memory controller 122 in the transmit mode. The memory signals may include, for example, write or read commands represented as dynamic random access memory family interface (DFI) signals. Interface logic 822 decodes the DFI signals and maps the memory signals to corresponding UCIe signals. Interface logic 822 encodes the UCIe signals for transmission over a transmission channel 818 of UCIe interconnect 804.From the perspective of the memory chip 802, in receive mode, the UCIe interface 810 receives the UCIe signals from the transmission channel 818. Interface logic 824 decodes the UCIe signals and maps the UCIe signals to corresponding memory signals, such as the DFI signals. The UCIe interface 810 sends the DFI signals to the memory 812. The memory 812 receives the DFI signals and generates a response. For example, if the DFI signals represent a read request, the memory 812 fetches the requested data and sends the data back to the UCIe interface 810 as DFI signals. In the transmit mode, the interface logic 824 decodes the DFI signals and maps the memory signals to corresponding UCIe signals. The UCIe interface 810 sends the UCIe signals to the SoC 118 over the receive channel 820 of the UCIe interconnect 804.Returning to the perspective of the SoC 118, in receive mode, the UCIe interface 808 receives the UCIe signals from the receive channel 820 of the UCIe interconnect 804. Interface logic 822 decodes the UCIe signals and maps the UCIe signals to memory signals and encodes the memory signals as DFI signals for transmission to memory controller 122.In various embodiments, the memory signals are DDR (Dual Data Rate) memory signals or HBM (High Bandwidth Memory) memory signals. For example, the memory signals may include signals associated with a DDR memory interface, a dual channel DDR memory interface, an LPDDR memory interface, a dynamic RAM (DRAM) memory interface, or other types of memory interfaces.FIG. 9 illustrates a semiconductor package 900. The semiconductor package 900 includes the SoC 118 and the memory chip 802 mounted on a substrate 902. The SoC 118 and the memory chip 802 may communicate over a set of reference channels 904. In an embodiment, the reference channels 904 are embedded in the substrate 902. The reference channels 904 may be implemented as wire bonds, conductive traces, a silicon bridge, an interposer, and other communication media.The semiconductor package 900 may have different physical configurations for semiconductor testing, wherein the different physical configurations are defined using different reference packages, such as a strict reference package and form factor, a flexible reference package and form factor, and a user-defined original equipment manufacturer (OEM) reference package.FIG. 10 illustrates a device 1000. The apparatus 1000 may include any non-transitory computer readable storage medium 1002 or machine readable storage medium, such as an optical, magnetic, or semiconductor storage medium. In various embodiments, the apparatus 1000 may comprise an article of manufacture or a product. In some embodiments, computer readable storage medium 1002 may store computer executable instructions that circuitry may execute. For example, computer-executable instructions 1004 may include instructions for implementing operations described with reference to any logic flows described herein. Examples of the computer readable storage medium 1002 or a machine readable storage medium may include any tangible media capable of storing electronic data including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so forth. Examples of the computer-executable instructions 1004 may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like.The components and features of the devices described above may be implemented using any combination of discrete circuitry, application specific integrated circuits (ASICs), logic gates, and / or single chip architectures. Further, the features of the devices may be implemented using microcontrollers, programmable logic arrays and / or microprocessors, or any combination of the foregoing, where appropriate. It should be noted that hardware, firmware, and / or software elements may be collectively or individually referred to herein as "logic" or "circuitry.".It should be appreciated that the example devices shown in the block diagrams described above may represent a functionally descriptive example of many possible implementations. Accordingly, division, omission, or inclusion of block functions illustrated in the accompanying figures does not mean that the hardware components, circuits, software, and / or elements for implementing these functions necessarily need to be divided, omitted, or included in embodiments.At least one computer readable storage medium may include instructions that, when executed, cause a system to perform any of the computer-implemented methods described above.Some embodiments may be described using the phrase "exactly one embodiment" or "an embodiment" along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Moreover, unless otherwise stated, the features described above are considered to be usable together in any combination. Thus, any separately described features may be employed in combination with each other, unless it is noted that the features are not compatible with each other.With general reference to previously used notations and nomenclature, the detailed descriptions herein may be provided with respect to program procedures executed on a computer or network of computers. These procedural descriptions and representations are used by one skilled in the art to most effectively convey the substance of their work to others skilled in the art.A procedure is considered herein and generally as a self-consistent sequence of acts that results in a desired result. These procedures are those requiring physical manipulations of physical quantities. These quantities are usually, but not necessarily, in the form of electrical, magnetic or optical signals which can be stored, transferred, combined, compared and otherwise manipulated. It is sometimes convenient, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be noted, however, that all of these and similar terms are intended to be associated with the appropriate physical quantities and are appropriate terms applied only to those quantities.Further, manipulations performed are often referred to as items such as adding or comparing that are commonly associated with mental operations performed by a human operator. Such a human operator's ability is in most cases not necessary or desirable in any of the processes described herein that are part of one or more embodiments. Rather, the operations are machine operations. Useful machines for performing operations of various embodiments include general purpose digital computers or similar devices.Some embodiments may be described using the term "coupled" and "connected" along with their derivatives. These terms are not necessarily intended to be synonymous with each other. For example, some embodiments may be described using the terms "connected" and / or "coupled" to indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.Various embodiments also relate to apparatus or systems for performing these operations. This device may be specially constructed for the required purposes or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. The procedures presented herein do not inherently relate to a particular computer or other device. Various general purpose machines may be used with programs written in accordance with the present teachings or it may prove convenient to construct more specialized apparatus to perform the required process steps. The required structure for a plurality of these machines will be apparent from the description given.What has been described above includes examples of the disclosed architecture. It is, of course, not possible to describe any conceivable combination of components and / or methodologies, but one of ordinary skill in the art will understand that many other combinations and permutations are possible. Accordingly, the novel architecture is intended to include all such changes, modifications and variations as fall within the spirit and scope of the appended claims.The various elements of the devices as described above with reference to FIGS. 1-18 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software elements may include software components, programs, applications, computer programs, application programs, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computational code, computer code, code segments, computer code segments, words, values, characters, or any combination thereof. However, determining whether an embodiment is implemented using hardware elements and / or software elements may vary according to any number of factors, such as desired computational rate, power levels, thermal tolerances, processing cycle budget, input data rates, output data, memory resources, data bus speeds, and other design or performance constraints, as desired for a given implementation.One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium representing various logic within the processor, which, when read by a machine, cause the machine to fabricate logic to perform the techniques described herein. Such representations, known as "IP cores", may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into the manufacturing machines that manufacture the logic or processor. Some embodiments may be implemented, for example, using a machine-readable medium or article that may store an instruction or set of instructions that, when executed by a machine, may cause the machine to perform a method and / or operations according to the embodiments. Such a machine may include, for example, one(s)(n) any suitable processing platform(s / n), computing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware and / or software. The machine-readable medium or article may include, for example, any suitable type of storage unit, storage device, storage article, storage medium, storage device, storage article, storage medium, and / or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writable or rewritable media, digital or analog media, hard drive, floppy disk, compact disk read only memory (CD-ROM), compact disk recordable (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of digital versatile disk (DVD), tape, a cartridge or the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, and the like, implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.It should be appreciated that the example devices shown in the block diagrams described above may represent a functionally descriptive example of many possible implementations. Accordingly, division, omission, or inclusion of block functions illustrated in the accompanying figures does not mean that the hardware components, circuits, software, and / or elements for implementing these functions necessarily need to be divided, omitted, or included in embodiments.At least one computer readable storage medium may include instructions that, when executed, cause a system to perform any of the computer-implemented methods described above.Some embodiments may be described using the phrase "exactly one embodiment" or "an embodiment" along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Moreover, unless otherwise stated, the features described above are considered to be usable together in any combination. Thus, any separately described features may be employed in combination with each other, unless it is noted that the features are not compatible with each other.The following examples are directed to other embodiments from which numerous permutations and configurations will be apparent.In one example, a method includes: encoding a first configuration parameter for a main band of a universal chiplet interconnect express (UCIe) interconnect into a first sideband signal, the first configuration parameter representing a first data rate for the main band of the UCIe interconnect; decoding a second configuration parameter for the main band of the UCIe interconnect from a second sideband signal, the second configuration parameter representing a second data rate for the main band of the UCIe interconnect; decoding a third configuration parameter for the main band of the UCIe interconnect from an application signal, the third configuration parameter representing a transport mode for the UCIe interconnect, and encoding information into a first main band signal for transport over a transmission channel of the UCIe interconnect at the first data rate when the transport mode for the UCIe interconnect is set to an asymmetric mode.The method of any preceding claim may also include decoding information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode.The method of any preceding claim may also include decoding information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode using a third sideband signal, wherein the third sideband signal includes a forwarded clock signal.The method of any preceding claim may also include encoding information into the first main band signal for transport over the transmission channel of the UCIe interconnect at a third data rate when the transport mode for the UCIe interconnect is set to a symmetric mode, wherein the third data rate represents a smallest common multiple between the first data rate and the second data rate.The method of any preceding claim may also include the first data rate being different than the second data rate.The method of any preceding claim may also include the first data rate for the main band of the UCIe interconnect representing a maximum transmit data rate and a maximum receive data rate of a first semiconductor die.The method of any preceding claim may also include the second data rate for the main band of the UCIe interconnect representing a maximum transmit data rate and a maximum receive data rate of a second semiconductor die.The method of any preceding claim may also include the UCle interconnect transporting signals between a plurality of semiconductor dies in a semiconductor package. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.In one example, an apparatus includes: a universal chiplet interconnect express (UCIe) die including a die-to-die (D2D) adapter coupled to a physical layer (PHY) for a UCIe interconnect, the UCIe interconnect including interface logic for managing transport of data over the UCIe interconnect, the interface logic configured to: encode a first configuration parameter for a main band of the UCIe interconnect into a first sideband signal, the first configuration parameter representing a first data rate for the main band of the UCIe interconnect, decoding a second configuration parameter for the main band of the UCIe interconnect from a second sideband signal, the second configuration parameter representing a second data rate for the main band of the UCIe interconnect, decoding a third configuration parameter for the main band of the UCIe interconnect from an application signal, the third configuration parameter representing a transport mode for the UCIe interconnect, and encoding information for a first main band signal for transport over a transmit channel of the UCIe interconnect at the first data rate when the transport mode for the UCIe interconnect is set to an asymmetric mode.The apparatus of the preceding claim may also include the interface logic to decode information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode.The apparatus of the preceding claim may also include the interface logic to decode information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode using a third sideband signal, wherein the third sideband signal includes a forwarded clock signal.The apparatus of the preceding claim may also include the interface logic to encode information into the first main band signal for transport over the transmission channel of the UCIe interconnect at a third data rate when the transport mode for the UCIe interconnect is set to a symmetric mode, wherein the third data rate represents a smallest common multiple between the first data rate and the second data rate.The apparatus of any preceding claim may also include the first data rate being different than the second data rate.The apparatus of any preceding claim may also include the first data rate for the main band of the UCle interconnect representing a maximum transmit data rate and a maximum receive data rate of a first semiconductor die.The apparatus of any preceding claim may also include the second data rate for the main band of the UCle interconnect representing a maximum transmit data rate and a maximum receive data rate of a second semiconductor die.The apparatus of any preceding claim may also include the UCle interconnect transporting signals between a plurality of semiconductor dies in a semiconductor package. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.In one example, a system includes: a semiconductor package including a first semiconductor die coupled by a universal chiplet interconnect express (UCIe) interconnect, the UCIe interconnect including interface logic to manage transport of data over the UCIe interconnect, the interface logic configured to: encode a first configuration parameter for a main band of the UCIe interconnect into a first sideband signal, the first configuration parameter representing a first data rate for the main band of the UCIe interconnect from the first semiconductor die, decode a second configuration parameter for the main band of the UCIe interconnect from a second sideband signal, wherein the second configuration parameter represents a second data rate for the main band of the UCIe interconnect, decoding a third configuration parameter for the main band of the UCIe interconnect from an application signal, wherein the third configuration parameter represents a transport mode for the UCIe interconnect, and encoding information for a first main band signal for transport over a transmit channel of the UCIe interconnect at the first data rate from the first semiconductor die when the transport mode for the UCIe interconnect is set to an asymmetric mode.The system of any preceding claim may also include the semiconductor package including a second semiconductor die coupled by the UCIe interconnect and the interface logic to decode information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate transmitted from the second semiconductor die to the first semiconductor die when the transport mode for the UCIe interconnect is set to the asymmetric mode using a third sideband signal, the third sideband signal including a forwarded clock signal.The system of any preceding claim may also include the first data rate for the main band of the UCle interconnect representing a maximum transmit data rate and a maximum receive data rate of the first semiconductor die.The system of any preceding claim may also include the second data rate for the main band of the UCle interconnect representing a maximum transmit data rate and a maximum receive data rate of a second semiconductor die. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.In one example, an apparatus includes: means for encoding a first configuration parameter for a main band of a universal chiplet interconnect express (UCIe) interconnect into a first sideband signal, the first configuration parameter representing a first data rate for the main band of the UCIe interconnect; means for decoding a second configuration parameter for the main band of the UCIe interconnect from a second sideband signal, the second configuration parameter representing a second data rate for the main band of the UCIe interconnect; means for decoding a third configuration parameter for the main band of the UCIe interconnect from an application signal, the third configuration parameter representing a transport mode for the UCIe interconnect, and means for encoding information into a first main band signal for transport over a transmit channel of the UCIe interconnect at the first data rate when the transport mode for the UCIe interconnect is set to an asymmetric mode.The apparatus of the preceding claim may also include means for decoding information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode.The apparatus of the preceding claim may also include means for decoding information from a second baseband signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode using a third sideband signal, wherein the third sideband signal includes a forwarded clock signal.The apparatus of the preceding claim may also include means for encoding information into the first main band signal for transport over the transmission channel of the UCIe interconnect at a third data rate when the transport mode for the UCIe interconnect is set to a symmetric mode, wherein the third data rate represents a smallest common multiple between the first data rate and the second data rate.The apparatus of any preceding claim may also include the first data rate being different than the second data rate.The apparatus of any preceding claim may also include the first data rate for the main band of the UCle interconnect representing a maximum transmit data rate and a maximum receive data rate of a first semiconductor die.The apparatus of any preceding claim may also include the second data rate for the main band of the UCle interconnect representing a maximum transmit data rate and a maximum receive data rate of a second semiconductor die.The apparatus of any preceding claim may also include the UCle interconnect transporting signals between a plurality of semiconductor dies in a semiconductor package. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.It is emphasized that the Abstract of the Disclosure is provided to enable a reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as set forth in the following claims, the inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. In the appended claims, the terms "including" and "in which" are used as the generally understood equivalents of the respective terms "comprising" and "wherein", respectively. In addition, the terms "first / r / s", "second / r / s", "third / r / s", and so forth are used merely as labels, and are not intended to impose numerical requirements on their objects.The foregoing description of embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in another manner and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

A method comprising: encoding a first configuration parameter for a main band of a universal chiplet interconnect express (UCIe) interconnect into a first sideband signal, wherein the first configuration parameter represents a first data rate for the main band of the UCIe interconnect; decoding a second configuration parameter for the main band of the UCIe interconnect from a second sideband signal, wherein the second configuration parameter represents a second data rate for the main band of the UCIe interconnect; decoding a third configuration parameter for the main band of the UCIe interconnect from an application signal, wherein the third configuration parameter represents a transport mode for the UCIe interconnect; and encoding information into a first main band signal for transport over a transmission channel of the UCIe interconnect at the first data rate when the transport mode for the UCIe interconnect is set to an asymmetric mode.The method of claim 1, comprising decoding information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode.The method of any of claims 1 to 2, comprising decoding information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode using a third sideband signal, wherein the third sideband signal comprises a forwarded clock signal.The method of any of claims 1 to 3, comprising encoding information into the first main band signal for transport over the transmission channel of the UCIe interconnect at a third data rate when the transport mode for the UCIe interconnect is set to a symmetric mode, wherein the third data rate represents a smallest common multiple between the first data rate and the second data rate.The method of any one of claims 1 to 4, wherein the first data rate is different than the second data rate.The method of any of claims 1 to 5, wherein the first data rate for the main band of the UCle interconnect represents a maximum transmit data rate and a maximum receive data rate of a first semiconductor die.The method of any of claims 1 to 6, wherein the second data rate for the main band of the UCle interconnect represents a maximum transmit data rate and a maximum receive data rate of a second semiconductor die.The method of any of claims 1 to 7, wherein the UCle interconnect carries signals between a plurality of semiconductor dies in a semiconductor package.An apparatus comprising: a universal chiplet interconnect express (UCIe) die comprising a die-to-die (D2D) adapter coupled to a physical layer (PHY) for a UCIe interconnect, the UCIe interconnect comprising interface logic for managing transport of data over the UCIe interconnect, the interface logic configured to: encode a first configuration parameter for a main band of the UCIe interconnect into a first sideband signal, the first configuration parameter representing a first data rate for the main band of the UCIe interconnect; decoding a second configuration parameter for the main band of the UCIe interconnect from a second sideband signal, the second configuration parameter representing a second data rate for the main band of the UCIe interconnect; decoding a third configuration parameter for the main band of the UCIe interconnect from an application signal, the third configuration parameter representing a transport mode for the UCIe interconnect; and encoding information for a first main band signal for transport over a transmit channel of the UCIe interconnect at the first data rate when the transport mode for the UCIe interconnect is set to an asymmetric mode.The apparatus of claim 9, wherein the interface logic is configured to decode information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode.The apparatus of any of claims 9 to 10, wherein the interface logic is configured to decode information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode using a third sideband signal, wherein the third sideband signal comprises a forwarded clock signal.The apparatus of any of claims 9 to 11, wherein the interface logic is configured to encode information into the first main band signal for transport over the transmission channel of the UCIe interconnect at a third data rate when the transport mode for the UCIe interconnect is set to a symmetric mode, wherein the third data rate represents a smallest common multiple between the first data rate and the second data rate.The apparatus of any of claims 9 to 12, wherein the first data rate is different than the second data rate.The apparatus of any of claims 9 to 13, wherein the first data rate for the main band of the UCle interconnect represents a maximum transmit data rate and a maximum receive data rate of a first semiconductor die.The apparatus of any of claims 9 to 14, wherein the second data rate for the main band of the UCle interconnect represents a maximum transmit data rate and a maximum receive data rate of a second semiconductor die.The apparatus of any of claims 9 to 15, wherein the UCle interconnect carries signals between a plurality of semiconductor dies in a semiconductor package.A system comprising: a semiconductor package comprising a first semiconductor die coupled by a universal chiplet interconnect express (UCIe) interconnect, the UCIe interconnect comprising interface logic for managing transport of data over the UCIe interconnect, the interface logic configured to: encode a first configuration parameter for a main band of the UCIe interconnect into a first sideband signal, the first configuration parameter representing a first data rate for the main band of the UCIe interconnect from the first semiconductor die; decoding a second configuration parameter for the main band of the UCIe interconnect from a second sideband signal, the second configuration parameter representing a second data rate for the main band of the UCIe interconnect; decoding a third configuration parameter for the main band of the UCIe interconnect from an application signal, the third configuration parameter representing a transport mode for the UCIe interconnect; and encoding information for a first main band signal for transport over a transmit channel of the UCIe interconnect at the first data rate from the first semiconductor die when the transport mode for the UCIe interconnect is set to an asymmetric mode.The system of claim 17, comprising: the semiconductor package comprising a second semiconductor die coupled by the UCIe interconnect; and wherein the interface logic is configured to decode information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate transmitted from the second semiconductor die to the first semiconductor die when the transport mode for the UCIe interconnect is set to the asymmetric mode using a third sideband signal, wherein the third sideband signal comprises a forwarded clock signal.The system of any of claims 17 to 18, wherein the first data rate for the main band of the UCle interconnect represents a maximum transmit data rate and a maximum receive data rate of the first semiconductor die.The system of any of claims 17 to 19, wherein the second data rate for the main band of the UCle interconnect represents a maximum transmit data rate and a maximum receive data rate of a second semiconductor die.An apparatus comprising: means for encoding a first configuration parameter for a main band of a universal chiplet interconnect express (UCIe) interconnect into a first sideband signal, the first configuration parameter representing a first data rate for the main band of the UCIe interconnect; means for decoding a second configuration parameter for the main band of the UCIe interconnect from a second sideband signal, the second configuration parameter representing a second data rate for the main band of the UCIe interconnect; means for decoding a third configuration parameter for the main band of the UCIe interconnect from an application signal, the third configuration parameter representing a transport mode for the UCIe interconnect; and means for encoding information into a first main band signal for transport over a transmit channel of the UCIe interconnect at the first data rate when the transport mode for the UCIe interconnect is set to an asymmetric mode.The apparatus of claim 21, comprising means for decoding information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode.The apparatus of any of claims 21 to 22, comprising means for decoding information from a second main band signal from a receive channel of the UCIe interconnect at the second data rate when the transport mode for the UCIe interconnect is set to the asymmetric mode using a third sideband signal, wherein the third sideband signal comprises a forwarded clock signal.The apparatus of any of claims 21 to 23, comprising means for encoding information into the first main band signal for transport over the transmission channel of the UCIe interconnect at a third data rate when the transport mode for the UCIe interconnect is set to a symmetric mode, wherein the third data rate represents a smallest common multiple between the first data rate and the second data rate.The apparatus of any of claims 21 to 24, wherein the first data rate is different than the second data rate.

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