Assembled storage chips for wafer-level testing

Abstract

A semiconductor wafer contains multiple memory chips arranged on it. The majority of memory chips are arranged as a plurality of superchips for testing, with each superchip containing two or more of the majority of memory chips. At least a subset of components from the two or more memory chips in each superchip are electrically short-circuited to receive shared test signals from test equipment during testing.

Description

TECHNICAL FIELD

[0001] Embodiments of the invention generally relate to storage devices, and in particular to interconnected memory chips for wafer-level testing. BACKGROUND

[0002] A storage subsystem can include one or more storage devices for storing data. These storage devices can be, for example, non-volatile or volatile. Generally, a host system can use a storage subsystem to store data in and read data from the storage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present invention is made more understandable by the detailed description below and by the accompanying drawings of various embodiments of the invention. Fig. Figure 1 is a block diagram illustrating a system for wafer-level testing of memory chips according to some embodiments of the present invention. Fig. Figure 2 is a block diagram illustrating interconnected memory chips for wafer-level testing according to some embodiments of the present invention. Fig. 3A and Fig. Figure 3B shows circuit diagrams illustrating a super-pad used with interconnected memory chips for wafer-level testing according to some embodiments of the present invention. Fig. Figure 4 is a block diagram illustrating analog power components in interconnected memory chips for wafer-level testing according to some embodiments of the present invention. Fig. Figure 5 is a block diagram illustrating the switching of control signals in interconnected memory chips for wafer-level testing according to some embodiments of the present invention. Fig. Figure 6A shows an example of a computer system comprising a memory subsystem according to some embodiments of the present invention. Fig. Figure 6B is a block diagram of a storage device that is connected to a storage subsystem controller of a storage subsystem, according to some embodiments of the present invention. Fig. 7 is a schematic representation of parts of an array of memory cells, as they are found in a memory of the with reference to Fig. 6B can be used according to some embodiments of the present invention. Fig. Figure 8 is a flowchart of an exemplary method for forming interconnected memory chips for wafer-level testing according to some embodiments of the present invention. Fig. Figure 9 is a block diagram of an exemplary computer system in which embodiments of the present invention can be operated. DETAILED DESCRIPTION

[0004] Aspects of the present invention relate to interconnected memory chips for wafer-level testing. A memory subsystem can be a memory device, a memory module, or a combination of a memory device and a memory module. Examples of memory devices and memory modules are given below with reference to Fig. 6A describes this. In general, a host system can use a storage subsystem, which includes one or more components, such as storage devices, to store data. The host system can provide data to be stored in the storage subsystem and request data to be read from the storage subsystem.

[0005] A storage subsystem may include high-density non-volatile storage devices where data retention is desired when the storage device is not powered. For example, NAND flash memory, such as 3D NAND flash memory, provides storage in compact, high-density configurations. A non-volatile storage device is a package of one or more chips, each comprising one or more layers. In some types of non-volatile storage devices (e.g., NAND flash memory), each layer contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and can have various logical states that correlate with the number of bits stored.Logical states can be represented by binary values, such as "0" and "1" or combinations of such values.

[0006] A storage device can be constructed using bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells of a storage device, which are used with one or more bit lines to generate the address of each of the memory cells. The intersection of a bit line and a word line forms the address of the memory cells. A block, hereinafter referred to as a unit of the storage device used to store data, can comprise a group of memory cells, a group of word lines, a single word line, or individual memory cells. One or more blocks can be grouped together to form separate partitions (e.g.,to form levels) of the storage device to allow concurrent operations to occur at each level. The storage device may include circuitry to perform concurrent memory page accesses across two or more memory levels. For example, the storage device may have multiple access line driver circuitry and power circuitry that can be shared by the levels of the storage device to facilitate concurrent access to pages from two or more memory levels, including different types of pages. For simplicity, these circuitry circuitry can be referred to as independent level driver circuitry. Depending on the memory architecture used, data may be stored across memory levels (i.e., in strips). Consequently, a request to read a segment of data (e.g.,corresponding to one or more data addresses) lead to read operations that are performed with respect to two or more of the storage levels of the storage device.

[0007] Each memory device can be designed as a single memory chip containing an array of memory cells and other associated circuitry, such as control logic, analog voltage generators, signal drivers, input / output circuitry (e.g., signal communication pads), etc. A number of individual memory chips can be fabricated together on a silicon wafer. A semiconductor fabrication process can be used to deposit and structure multiple layers of material onto the wafer to form the circuitry of the individual memory chips in parallel. After fabrication is complete, the individual memory chips can be tested and then separated for use in separate memory subsystems.

[0008] To reduce manufacturing time and costs, it is desirable to maximize the number of memory chips contained on each wafer (i.e., the number of chips per wafer (DPW)). Furthermore, as manufacturing processes improve, the size of individual chips decreases, allowing more chips to be produced on each wafer. However, the increasing number of chips per wafer introduces new challenges related to memory chip testing. In a conventional test setup, the test equipment (e.g., a probe card) includes a number of micro-probes (i.e., needles) that physically contact (i.e., touch) the metal signal communication pads on the memory chip to provide power, control, and data signals, and to acquire data and other measurements. The test equipment can analyze the acquired data to evaluate the functionality of the memory chip.Often, test equipment is designed to test all or at least some of the chips on the wafer in parallel. This is achieved by positioning one or more micro-probes to simultaneously contact the signal communication pads of multiple chips, capturing and delivering their respective test signals. With smaller memory chips and a greater number of chips per wafer, the spacing between the chips decreases, making it more difficult to align the micro-probes with their respective signal communication pads. For example, physical size limitations of the test board and the spacing between micro-probes can reduce the percentage of memory chips on the wafer that can be tested simultaneously. Consequently, multiple sequential test cycles may be required, with, for example, every second chip being tested in a first cycle and the remaining chips being tested in a second cycle.This increases the overall testing time, the complexity of the testing process, and the costs associated with the manufacture of memory chips.

[0009] Aspects of the present invention overcome the aforementioned and other disadvantages of interconnecting memory chips for wafer-level testing. In one embodiment, two or more memory chips (e.g., a pair of memory chips) are interconnected on the silicon wafer to form a "superchip," so that each of the memory chips in the superchip can be tested simultaneously with only one set of micro-probes. Although each individual memory chip has a separate set of signal communication pads, certain components of the individual memory chips can, for example, be physically short-circuited together, so that power signals, control signals, and data signals from the test equipment are supplied to the signal communication pads of only one of the individual memory chips (i.e., a primary chip) but can be shared with one or more other memory chips (i.e., a secondary chip).In one embodiment, certain portions of the power supply networks and signal buses used to deliver control signals from the respective control logic components to the respective memory arrays on each memory chip are short-circuited to share corresponding signals. This allows the control logic on the secondary chip to be disabled during testing, and the control logic on the primary chip to be used to control the test operations for the entire superchip. After testing is complete, the individual memory chips can optionally be separated, for example, by disconnecting the physical short circuits between them, so that the memory chips can be integrated into separate memory subsystems.

[0010] The advantages of this approach include, but are not limited to, improved performance in memory chip fabrication and wafer-level testing. This allows for a reduction in the size of individual chips and the spacing between them on the wafer, thereby increasing the overall yield, while simultaneously enabling wafer-level testing. This wafer-level testing can be performed more efficiently (i.e., with shorter test times and using fewer parts for the test equipment), thus reducing the overall cost of memory chip fabrication.

[0011] Fig. Figure 1 is a diagram illustrating a system for wafer-level testing of memory chips according to some embodiments of the present invention. In a semiconductor fabrication process carried out using the system, a number of identical integrated circuits, such as memory chips 130, are formed as individual semiconductor chips on a semiconductor wafer 190 or another bulk semiconductor substrate. The number of memory chips 130 on the wafer 190 can be hundreds or even thousands of individual semiconductor chips, generally repeated in a two-dimensional arrangement across the wafer 190. In some embodiments, two or more individual memory chips 130 can be combined, at least temporarily, to form a “super-chip,” such as the super-chip 194.

[0012] Once the memory chips 130 and / or super-chips 194 have been fabricated at the semiconductor chip positions on the semiconductor wafer 190, they can be tested to determine which chips are at least nominally functional. In some embodiments, the testing can be performed by test equipment, such as the test card 196, which can test each memory chip and / or super-chip 194 individually. Testing of individual semiconductor chips can be performed by the test card 196 while the chips are still mounted together on the wafer 190. For example, the test card 196 can contact the respective micro-probes 198 associated signal communication pads on the memory chips 130 and / or super-chips 194. Certain probe tests include testing each individual chip to determine the correct and acceptable functionality of the chip.As described in more detail below, the multiple memory chips that make up each Super-Chip 194 can be tested simultaneously with just a single set of Micro-Probes 198. In this way, performing wafer-level tests on the Super-Chips 194 significantly reduces the overall test time, costs, and resource utilization compared to testing each individual memory chip 130 separately.

[0013] Fig. Figure 2 is a block diagram illustrating interconnected memory chips for wafer-level testing according to some embodiments of the present invention. In one embodiment, a primary memory chip 130a and a secondary chip 130b are interconnected, at least temporarily, to form a super-chip 194. As described, the individual memory chips 130a and 130b that constitute the super-chip 194 can be tested simultaneously using only a single set of micro-probes 198. Although the super-chip 194 comprises only two individual memory chips, it should be understood that in other embodiments, a different number of individual memory chips can be interconnected to form a super-chip 194.

[0014] Each primary memory chip 130a and each secondary memory chip 130b comprises a control logic component 135a, 135b, a memory array 104a, 104b, and an analog power component 292a, 292b, which are interconnected within each memory chip via a communication bus 294a, 294b. Furthermore, each of the memory chips 130a and 130b can include a set of signal communication pads 296a, 296b, which provide an interface for transmitting signals between the components of each respective memory chip and any off-chip circuit, such as the test card 196. For example, the micro-probes 198 of the test card 196 can come into contact with any of the signal communication pads to supply current signals, control signals and data signals to the memory chips 130a and 130b and to acquire data and other measured values ​​from the memory chips 130a and 130b.It should be understood that the 130a and 130b memory chips may contain different and / or additional components not shown here. Generally, the 130a and 130b memory chips are identical, meaning they contain the same internal components. In some cases, the arrangement and orientation of these components may be identical; in other cases, the arrangement and orientation of these components may vary from chip to chip. For example, in... Fig. As shown in Figure 2, the set of communication pads 296a is aligned on the top side of the primary chip 130a, while the set of communication pads 296b is aligned on the bottom side of the secondary chip 130b. In other embodiments, the sets of communication pads may be located on the top side of each respective memory chip, on the bottom side of each respective memory chip, or on opposite sides of each respective memory chip.

[0015] In one embodiment, one or more communication pads in the respective sets of communication pads 296a, 296b can be electrically short-circuited 295 to each other, so that signals can be shared between the pads. For example, communication pads that are coupled to the respective power supply networks of the memory chips 130a and 130b and configured to receive external power supply signals (e.g., from the test card 196) can be electrically short-circuited 295, so that the power supply signals are shared between the respective power supply networks. Similarly, communication pads that are coupled to the respective communication buses 294a, 294b and configured to receive external data signals (e.g., from the test card 196) can be electrically short-circuited 295, so that the data signals are shared between the respective communication buses 294a, 294b.Other communication pads in the sets of communication pads 296a and 296b can be short-circuited in a similar manner. In this way, both memory chips 130a and 130b, which form the super-chip 194, can be tested simultaneously with only one set of micro-probes 198.

[0016] The designation of the primary memory chip 130a, as opposed to the secondary memory chip 130b, indicates which memory chip is physically contacted by the micro-probes 198. For example, to test the super-chip 194, the micro-probes 198 can contact the set of communication pads 296a of the primary memory chip 130a. All signals received by the primary memory chip 130a at the communication pads 296a can be transmitted via the electrical short circuits 295 to the communication pads 296b of the secondary memory chip 130b. Similarly, all data, measurements, or other test information generated by the secondary chip 130b can be transmitted via the electrical short circuits 295 to the communication pads 296a of the primary chip 130a and ultimately to the test card 196.In one embodiment, each set of communication pads 296a, 296b comprises a specific super-pad 298a, 298b which can be used to indicate which memory chip is the primary memory chip 130a and which is the secondary memory chip 130b, as described below with reference to . Fig. 3A and Fig. 3B is described in more detail. Certain components in both memory chips 130a and 130b can remain active during the test process (e.g., memory arrays 104a, 104b, analog power components 292a, 292b, and communication buses 294a, 294b), while certain components of the secondary memory chip 130b are deactivated during the test process (e.g., the control logic component 135b), while the testing is performed by the corresponding component in the primary memory chip 130a.

[0017] Fig. Figure 3A is a circuit diagram showing a super-pad used with interconnected memory chips for wafer-level testing according to some embodiments of the present invention. The circuit 300 comprises a super-pad 298, which is either the super-pad 298a or 298b. Fig. 2 can represent a pull-up resistor 302 and a slow input buffer 304. The pull-up resistor 302 is coupled between a power supply source (Vcc) and the super-pad 298, while the slow input buffer 304 is connected to a sampling node 306 between the pull-up resistor 302 and the super-pad 298.

[0018] As described above, each of the primary memory chips 130a and secondary memory chips 130b can include a respective Super-Pad 298 and associated circuits 300. During testing, the test card 196 can apply a ground voltage signal to the Super-Pad 298a on the primary memory chip 130a (e.g., via one of the Micro-Probes 198), while no signal is applied to the Super-Pad 298b on the secondary memory chip. The circuit 300 can be used by the respective control logic components 135a and 135b to determine whether a particular memory chip is the primary memory chip 130a, in which case the control logic component 135a should remain active during testing, or whether it is the secondary memory chip 130b, in which case the control logic component 135b should be deactivated during testing.

[0019] In one embodiment, when no signal is present at the super-pad 298, the pull-up resistor pulls the voltage at the sampling node 306 up to the Vcc level (e.g., 1.2 volts). The voltage at the sampling node 306 is detected at the input of the slow input buffer 304, which can transmit a corresponding logical value (e.g., a logical "1") to the respective control logic on the memory chip. The control logic can decode the logical value as an indication that the memory chip is the secondary memory chip 130b, and thus the control logic 135b can be deactivated for the remainder of the test process. Conversely, the voltage at the sampling node 306 is at or near ground level (e.g., 0 volts) when a ground signal is present at the super-pad 298. The voltage at the sampling node 306 is detected at the input of the slow input buffer 304, which can transmit a corresponding logical value (e.g.,a logical "0") can be transmitted to the respective control logic on the memory chip. The control logic can decode the logical value as an indication that the memory chip is the primary memory chip 130a, so that the control logic 135a can remain active for the remainder of the test process.

[0020] In another embodiment, as in Fig. As shown in Figure 3B, circuit 310 can contain a pull-down resistor 312 instead of the pull-up resistor 302. The pull-down resistor is coupled between the super-pad 298 and a ground supply (GND). In this implementation, when no signal is present at the super-pad 298, the pull-down resistor 312 pulls the voltage at the sampling node 306 down to ground (e.g., 0 volts). The voltage at the sampling node 306 is detected at the input of the slow input buffer 304, which can transmit a corresponding logical value (e.g., a logical "0") to the respective control logic on the memory chip. The control logic can interpret the logical value as an indication that the memory chip is the secondary memory chip 130b, and thus the control logic 135b can be deactivated for the remainder of the test process. Conversely, the voltage at sampling node 306 is at or near this voltage level (e.g.1.2 volts), if a higher voltage signal is applied to the super-pad 298. The voltage at the sampling node 306 is detected at the input of the slow input buffer 304, which can transmit a corresponding logical value (e.g., a logical "1") to the respective control logic on the memory chip. The control logic can decode the logical value as an indication that the memory chip is the primary memory chip 130a, so that the control logic 135a can remain active for the remainder of the test process.

[0021] Fig. Figure 4 is a block diagram illustrating analog power components in interconnected memory chips for wafer-level testing according to some embodiments of the present invention. In one embodiment, the primary memory chip 130a and the secondary memory chip 130b are interconnected, at least temporarily, to form a superchip 194. As described above, each primary memory chip 130a and each secondary memory chip 130b comprises a control logic component 135a, 135b, analog power components, and possible other components not shown. The analog power components are arranged in Fig. 4 is shown in more detail. For example, the analog power components in each memory chip can include a common voltage generator (COM) 402a, 402b, which generates a common supply voltage for all levels of the memory chip, and individual level-level circuits (PLNs) 404a, 404b, each corresponding to one level of the memory chip, with each PLN 404a, 404b connected to a respective set of data line drivers and a side buffer, together 406a, 406b, for that level. In addition, the analog power components in each memory chip can include a low-voltage and band-gap generator (BG) 408a, 408b and one or more low-dropout regulators (LDOs) 410a, 410b, which provide internally regulated voltage supplies for a number of circuits connected to the respective power grid 412a, 412b on each memory chip.In general, each primary memory chip 130a and each secondary chip 130b is configured with the same components, although the orientation and / or arrangement may differ. Additionally, each memory chip may contain a corresponding set of communication pads, which are not shown for simplicity. Various analog power components within each memory chip may be connected to corresponding communication pads.

[0022] In one embodiment, one or more components in each of the memory chips 130a and 130b can be electrically short-circuited 295. For example, the communication pads to which these components are connected can be electrically short-circuited 295. In one embodiment, the low-voltage and band-gap generator (BG) 408a, 408b in each memory chip are electrically short-circuited 295, and the low-voltage regulators (LDO) 410a, 410b are electrically short-circuited 295. In this way, external power supply signals, such as those received at the corresponding communication pad on the primary chip 130a from the test card 196, can be shared with the components on the secondary chip 130b. In one embodiment, the remaining parts of the respective power supply networks 412a, 412b on each memory chip remain isolated from one another.For example, each low-dropout regulator (LDO) 410a, 410b can receive the same external power supply signal, but each low-dropout regulator (LDO) 410a, 410b can generate its own internal power supply signal, which is fed to the corresponding power supply network 412a, 412b on the same memory chip. This arrangement prevents interference between the components of the power supply networks 412a, 412b on the memory chips 130a and 130b.

[0023] Fig. Figure 5 is a block diagram illustrating the switching of control signals in interconnected memory chips for wafer-level testing according to some embodiments of the present invention. In one embodiment, the primary memory chip 130a and the secondary memory chip 130b are interconnected, at least temporarily, to form a superchip 194. As described above, each of the primary memory chips 130a and secondary memory chips 130b comprises a control logic component 135a, 135b, a set of signal communication pads 296a, 296b, which provide an interface for transmitting signals between the components of each respective memory chip and any off-chip circuitry, such as a test card 196, and possibly other components not shown.The control logic components 135a, 135b are designed to send control signals via respective communication buses 294a, 294b to these other components within each memory chip.

[0024] In one embodiment, the communication buses 294a and 294b are electrically short-circuited. For example, the communication pads connecting the communication buses 294a and 294b can be electrically short-circuited. As mentioned above, the control logic component 135a remains active during testing, and the control logic component 135b is deactivated during testing, so that the control logic component 135a can send control signals to the components on both memory chips 130a and 130b during testing. In general, the components on both memory chips 130a and 130b can receive the same control signals from the control logic 135a during testing.The test results, such as the data read from the respective memory chips during testing, can be separated so that errors related to the primary memory chip 130a or the secondary memory chip 130b can be correctly assigned. Since only one control logic component 135a is used and the communication buses 294a and 294b are electrically short-circuited, the data read from each memory chip can be transmitted with a time delay.

[0025] In one embodiment, each memory chip comprises a switching circuit 590a, 590b (e.g., a multiplexer). Each switching circuit 590a, 590b can receive an input signal from each of the control logic components 135a, 135b and, based on a corresponding control signal, provide a corresponding output signal to the corresponding communication bus 294a, 294b. In one embodiment, each control signal is received by the control logic components 135a, 135b and can be based on the corresponding super-pad 298a, 298b. As described above, in one embodiment, the test card 196 can apply a ground voltage signal to the super-pad 298a on the primary memory chip 130a (e.g., via one of the micro-probes 198) during testing, while no signal is applied to the super-pad 298b on the secondary memory chip 130b. Consequently, the voltage at the Super-Pad 298b is high (i.e., a logical “1”), and the voltage at the Super-Pad 298a is low (i.e., a logical “0”).When the inputs of switching circuits 590a and 590b are connected as shown, the input signal from control logic 135a is supplied to the output of both switching circuits 590a and 590b. Since the signal from control logic 135a is connected to the "0" input of switching circuit 590a and to the "1" input of switching circuit 590b, the logic "0" of super-pad 298a and the logic "1" of super-pad 298b select the signal from control logic 135a, which is supplied to both communication buses 294a and 294b. Conversely, if the probe card 196 applies a ground voltage signal to the super-pad 298b on the secondary memory chip 130b (e.g. via one of the micro-probes 198), while no signal is applied to the super-pad 298a on the primary memory chip 130a, the voltage at the super-pad 298a is high (i.e. a logical "1") and the voltage at the super-pad 298b is low (i.e. a logical "0").When the inputs of switching circuits 590a and 590b are connected as shown, the input signal from control logic 135b is supplied to the output of both switching circuits 590a and 590b. Since the signal from control logic 135b is connected to the "0" input of switching circuit 590b and to the "1" input of switching circuit 590a, the logic "0" of super-pad 298b and the logic "1" of super-pad 298a select the signal from control logic 135b, which is supplied to both communication buses 294a and 294b. It should be noted that the polarity would be reversed if a pull-down resistor 312 were used with super-pads 298a and 298b instead of a pull-up resistor 302.

[0026] Fig. Figure 6A shows an example of a computer system 100 comprising a storage subsystem 110 according to some embodiments of the present invention. The storage subsystem 110 may comprise media such as one or more volatile storage devices (e.g., storage device 140), one or more non-volatile storage devices (e.g., storage device 130), or a combination thereof.

[0027] A Memory Subsystem 110 can be a memory device, a memory module, or a hybrid of both. Examples of a memory device include a solid-state drive (SSD), a flash drive, a USB (Universal Serial Bus) flash drive, an embedded multimedia card drive (eMMC drive), a universal flash storage drive (UFS drive), a secure digital card (SD card), and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small-outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The Computer System 100 can be a computer device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or another means of transport), a device suitable for the Internet of Things (IoT), an embedded computer (e.g., one contained in a vehicle, an industrial plant, or a networked commercial device), or a computer device that includes a storage and processing unit.

[0029] The computer system 100 can comprise a host system 120 coupled with one or more storage subsystems 110. In some embodiments, the host system 120 can be coupled with different types of storage subsystems 110. Fig. Figure 6A shows an example of a host system 120 coupled to a storage subsystem 110. As used here, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication link or a direct communication link (e.g., without intermediary components), either wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0030] The host system 120 can contain a processor chipset and a software stack that is executed by the processor chipset. The processor chipset can contain one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a memory protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses, for example, the memory subsystem 110 to write data to and read data from the memory subsystem 110.

[0031] The host system 120 can be coupled to the storage subsystem 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Compute Express Link (CXL) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS) interface, a Double Data Rate Memory Bus (DDR) interface, a Small Computer System Interface (SCSI), a Dual In-Line Memory Module (DIMM) interface (e.g., a DIMM socket interface that supports Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the storage subsystem 110.The host system 120 can also use an NVM Express interface (NVMe interface) to access the storage components (e.g., the storage devices 130) when the storage subsystem 110 is connected to the host system 120 via the PCIe interface. The physical host interface can provide an interface for transmitting control signals, address signals, data signals, and other signals between the storage subsystem 110 and the host system 120. Fig. Figure 6A shows a storage subsystem 110 as an example. In general, the host system 120 can access multiple storage subsystems via the same communication link, multiple separate communication links, and / or a combination of communication links.

[0032] The storage devices 130 and 140 can contain any combination of different types of non-volatile and / or volatile storage devices. The volatile storage devices (e.g., storage device 140) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile storage devices (e.g., the Storage Device 130) include negative-AND-type flash memory (NAND) and write-in-place memory, such as three-dimensional cross-point memory (3D cross-point memory). A cross-point array of non-volatile memory can store bits based on a change in bulk resistance in conjunction with a stackable cross-gridded data access array. Furthermore, unlike many flash-based memories, cross-volatile memory can perform a write-in-place operation, allowing a non-volatile memory cell to be programmed without first erasing it. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the storage devices 130 can contain one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the storage devices 130 can contain one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination thereof. In some embodiments, a particular storage device can contain an SLC area and an MLC area, a TLC area, or a QLC area of ​​memory cells. The memory cells of the storage devices 130 can be grouped as pages of the storage device, which are used to store data. With some types of memory (e.g., NAND), pages can be grouped into blocks.

[0035] Although non-volatile memory components, such as a 3D cross-point array of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND), are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor RAM (FeTRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), spin-transfer-torque MRAM (STT-MRAM), conductive-bridging RAM (CBRAM), resistive RAM (RRAM), oxide-based RRAM (OxRAM), negative-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0036] A memory subsystem controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading, writing, or erasing data from the memory devices 130, as well as other such operations. The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include a digital circuit with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 can be a microcontroller, a special logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0037] The memory subsystem controller 115 can contain a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 contains embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, the local memory 119 can contain memory registers to store memory pointers, retrieved data, etc. The local memory 119 can also include a read-only memory (ROM) for storing microcode. Although the exemplary memory subsystem 110 in Fig. 6A is shown to contain the memory subsystem controller 115, in another embodiment of the present invention a memory subsystem 110 does not contain a memory subsystem controller 115 and can instead rely on external control (which is provided, for example, by an external host or by a processor or controller separate from the memory subsystem).

[0039] In general, the storage subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the storage devices 130. The storage subsystem controller 115 can also be responsible for other operations, such as wear-balancing operations, garbage collection operations, error detection and correction (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) related to the storage devices 130.The storage subsystem controller 115 may also include a host interface circuit to communicate with the host system 120 via the physical host interface. The host interface circuit can translate commands received from the host system into command instructions to access the storage devices 130 and to translate responses related to the storage devices 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and addressing circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory subsystem controller 115 and decode the address to access the memory devices 130.

[0041] In some embodiments, the storage devices 130 include local media controllers 135 that work in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the storage devices 130. An external controller (e.g., the memory subsystem controller 115) can manage the storage device 130 externally (e.g., perform media management operations on the storage device 130). In some embodiments, a storage device 130 is a managed storage device, which is a raw storage device 130 with control logic (e.g., a local controller 135) on the chip and a controller (e.g., a memory subsystem controller 115) for media management within the same storage device package. An example of a managed storage device is a managed NAND device (MNAND).The storage device 130 can, for example, represent a single chip on which certain control logic (e.g., local media controller 135) is implemented. In some embodiments, one or more components of the storage subsystem 110 can be omitted.

[0042] Fig. Figure 6B is a simplified block diagram of a first device in the form of a storage device 130, which according to one embodiment is connected to a second device in the form of a storage subsystem controller 115 of a storage subsystem (e.g., storage subsystem 110). Fig. 6A). Some examples of electronic systems are personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, household appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller outside the memory device 130) can be a memory controller or another external host device.

[0043] The storage device 130 comprises an array of memory cells 104 arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a word line), while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line can be connected to more than one logical row of memory cells, and a single data line can be connected to more than one logical column. Memory cells (not in Fig. (shown in Figure 6B) of at least one area of ​​the array of memory cells 104 can be programmed to one of at least two target data states.

[0044] The row decoder circuit 108 and the column decoder circuit 109 are designed to decode address signals. Address signals are received and decoded to access the array of memory cells 104. The storage device 130 also includes an input / output control circuit (I / O controller) 160 to manage the input of instructions, addresses, and data to the storage device 130, as well as the output of data and status information from the storage device 130. An address register 114 is connected to the I / O control circuit 160 and the row decoder circuit 108 and the column decoder circuit 109 to lock the address signals before decoding. An instruction register 124 is connected to the I / O control circuit 160 and the local media controller 135 to lock incoming instructions.

[0045] A controller (e.g., the local media controller 135 within the storage device 130) controls access to the array of memory cells 104 in response to instructions and generates status information for the external memory subsystem controller 115. That is, the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the array of memory cells 104. The local media controller 135 is interconnected with the row decoder circuit 108 and the column decoder circuit 109 to control the row decoder circuit 108 and the column decoder circuit 109 in response to addresses. In one embodiment, the local media controller 135 includes a proofreading module 134 that can implement partial block offset proofreading of the storage device 130, as described herein.

[0046] The local media controller 135 is also connected to a cache register 172. The cache register 172 stores data, either incoming or outgoing, as instructed by the local media controller 135, to temporarily store data while the array of memory cells 104 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be passed from the cache register 172 to the data register 170 for transfer to the array of memory cells 104; subsequently, new data can be locked into the cache register 172 by the I / O control circuit 160. During a read operation, data can be passed from the cache register 172 to the I / O control circuit 160 for output to the memory subsystem controller 115; subsequently, new data can be passed from the data register 170 to the cache register 172.The cache register 172 and / or the data register 170 can (e.g., can form a portion thereof) constitute a side buffer of the storage device 130. A side buffer can also contain acquisition devices (in . Fig. (6B not shown) to capture a data state of a memory cell of the array of memory cells 104, e.g., by capturing a state of a data line connected to that memory cell. A status register 122 can be connected to the I / O control circuit 160 and the local media controller 135 to lock the status information for output to the memory subsystem controller 115.

[0047] The storage device 130 receives control signals from the local media controller 135 at the storage subsystem controller 115 via a control link 182. These control signals can include, for example, a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write-protect signal WP#. Depending on the type of storage device 130, additional or alternative control signals (not shown) can be received via the control link 132. In one embodiment, the storage device 130 receives command signals (representing commands), address signals (representing addresses) and data signals (representing data) from the storage subsystem controller 115 via a multiplex input / output bus (I / O bus) 184 and outputs data to the storage subsystem controller 115 via the I / O bus 184.

[0048] For example, commands can be received via the input / output pins (I / O pins) [7:0] of I / O bus 184 at I / O control circuit 160 and then written to instruction register 124. Addresses can be received via the input / output pins (I / O pins) [7:0] of I / O bus 184 at I / O control circuit 160 and then written to address register 114. Data can be received via the input / output pins (I / O pins) [7:0] for an 8-bit device or via the input / output pins (I / O pins) [15:0] for a 16-bit device at I / O control circuit 160 and then written to cache register 172. The data can then be written to data register 170 to program the array of memory cells 104.

[0049] In one embodiment, the cache register 172 can be omitted, and the data can be written directly to the data register 170. Data can also be output via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference can be made to I / O pins, these can include any conductive node that enables an electrical connection to the storage device 130 by an external device (e.g., the memory subsystem controller 115), such as conductive contacts or conductive bumps as are commonly used.

[0050] It is obvious to the person skilled in the art that further circuits and signals can be provided, and that the storage device 130 in Fig. 6B is a simplified representation. It should be noted that the functionality of the various block components, which are referenced in... Fig. The functionality described in section 6B does not necessarily have to be divided among different components or component areas of an integrated circuit device. For example, a single component or component area of ​​an integrated circuit device may be designed to provide the functionality of more than one block component. Fig. 6B to comply. Alternatively, one or more components or component areas of an integrated circuit device could be combined to provide the functionality of a single block component. Fig. 6B to comply. Furthermore, although specific I / O pins are described according to common conventions for receiving and outputting the various signals, it should be noted that different combinations or numbers of I / O pins (or other I / O node structures) may be used in the various embodiments.

[0051] Fig. Figure 7 is a schematic representation of areas of an array of memory cells 104, such as a NAND memory array, as used in a memory of the in Fig. The type described in Section 6B can be used according to one embodiment. The memory array 104 includes access lines, such as word lines 2020 to 202. N , and data lines, such as bit lines 2040 to 204 M The word lines 202 can be used with global access lines (e.g., global word lines) that are in Fig. 7, which are not shown, are connected in a many-to-one relationship. In some embodiments, the storage array 104 can be formed over a semiconductor, which may, for example, be conductively doped to obtain a type of conductivity, such as p-type conductivity, e.g. to form a p-well, or n-type conductivity, e.g. to form an n-well.

[0052] The memory array 104 can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of serially connected memory cells (e.g., non-volatile memory cells), such as one of the NAND strings 2060 to 206. M Each NAND string 206 can be connected (e.g. selectively connected) to a common source (SRC) 216 and can represent memory cells 2080 to 208. NThe memory cells 208 can represent non-volatile memory cells for storing data. The memory cells 208 of each NAND string 206 can be connected in series between a select gate 210 (e.g., a field-effect transistor), such as one of the select gates 2100 to 210. M (These could be, for example, source-select transistors, which are usually referred to as select-gate-source) and a select-gate 212 (e.g., a field-effect transistor), such as one of the select-gates 2120 to 212. M (These can be, for example, drain-select transistors, which are commonly referred to as select-gate-drain) connected. The select gates 2100 to 210 M can be connected together with a Select line 214, such as a Source Select line (SGS), and the Select gates 2120 to 212 MThey can be connected together with a select line 215, such as a drain select line (SGD). Although represented as conventional field-effect transistors, the select gates 210 and 212 can use a structure similar to (e.g., the same as) that of the memory cells 208. The select gates 210 and 212 can represent a number of select gates connected in series, with each select gate in series configured to receive an identical or an independent control signal.

[0053] Each select gate 210 can have a source connected to a common source 216. Each select gate 210 can have a drain connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 210 can be connected to memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect a corresponding NAND string 206 to the common source 216. Each select gate 210 can have a control gate connected to the select line 214.

[0054] The drain of each select gate 212 can be connected to bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to a memory cell 208. Nof the corresponding NAND string 206. For example, the source of the select gate 2120 can be connected to memory cell 208. N of the corresponding NAND string 2060. Therefore, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to the corresponding bit line 204. A control gate of each select gate 212 can be connected to the select line 215.

[0055] The memory array 104 from Fig. 7 can be a quasi-two-dimensional memory array and can have a generally planar structure, with, for example, the common source 216, the NAND strings 206, and the bit lines 204 extending in essentially parallel planes. Alternatively, the memory array 104 can consist of Fig. 2 a three-dimensional memory array wherein, for example, the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and to a plane containing the bit lines 204, which can run substantially parallel to the plane containing the common source 216.

[0056] A typical design of memory cells 208 comprises a data storage structure 234 (e.g., a floating gate, a charge trap, and the like) that can determine a data state of the memory cell (e.g., by changes in the threshold voltage), and a control gate 236, as shown in Fig. Figure 7 is shown. The data storage structure 234 can contain both conductive and dielectric structures, while the control gate 236 is generally formed from one or more conductive materials. In some cases, memory cells 208 can further have a defined source / drain (e.g., Source) 230 and a defined source / drain (e.g., Drain) 232. The control gates 236 of the memory cells 208 are connected to (and in some cases form) a word line 202.

[0057] A column of memory cells 208 can be a NAND string 206 or a number of NAND strings 206 selectively connected to a given bit line 204. A row of memory cells 208 can be memory cells 208 that are connected together to a given word line 202. A row of memory cells 208 may, but need not, contain all the memory cells 208 that are connected together to a given word line 202. Rows of memory cells 208 can often be subdivided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 often contain every other memory cell 208 that is connected together to a given word line 202. For example, the memory cells 208 that are connected together to word line 202 Nare connected and selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.), be a physical side of the memory cells 208 (e.g., even-numbered memory cells), while memory cells 208, which are connected to the word line 202 N are connected and are selectively connected to odd-numbered bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.), and can be another physical side of the memory cells 208 (e.g., odd-numbered memory cells).

[0058] Although the bit lines 2043-2045 in Fig. Although bit lines 7 are not explicitly shown, it is evident from the figure that the bit lines 204 of the array of memory cells 104 extend from bit line 2040 to bit line 204. Mcan be numbered consecutively. Other groupings of memory cells 208 that are connected together to a given word line 202 can also define a physical page of memory cells 208. For certain memory devices, all memory cells that are connected together to a given word line can be considered a physical page of memory cells. The portion of a physical page of memory cells (which in some embodiments may still be the entire row) that is read during a single read operation or programmed during a single program operation (e.g., an upper or lower page of memory cells) can be considered a logical page of memory cells. A block of memory cells can contain those memory cells that are configured to be erased together, such as all memory cells connected to word lines 2020-202. Nare connected (e.g., all NAND strings 206 that use the common word lines 202). Unless explicitly stated otherwise, a reference here to a side of memory cells refers to the memory cells of a logical side of memory cells. Although the example from Fig. 7 in connection with NAND flash, the embodiments and concepts described here are not limited to a specific array architecture or array structure and can include other structures (e.g. SONOS, phase shift, ferroelectric, etc.) and other architectures (e.g. AND arrays, NOR arrays, etc.).

[0059] Fig. Figure 8 is a flowchart of an exemplary method for forming interconnected memory chips for wafer-level testing according to some embodiments of the present invention. The method can be carried out by processing logic that may include hardware (e.g., a processing device, circuits, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions executed or running on a processing device), or a combination thereof. Although shown in a particular order or sequence, the order of the processes may be changed unless otherwise specified. Therefore, the embodiments shown are to be understood as examples only, and the processes shown may be carried out in a different order, and some processes may be carried out in parallel.Furthermore, one or more processes can be omitted in different embodiments. Therefore, not all processes are required in every embodiment. Other process sequences are possible.

[0060] In Operation 805, memory chips are formed. In one embodiment, the processing logic (e.g., a semiconductor fabrication tool) can form a plurality of memory chips, such as memory chips 130, on a semiconductor wafer, such as wafer 190. In one embodiment, the memory chips are formed in a two-dimensional array comprising rows and columns of memory chips 130 on wafer 190 with a certain spacing between them. In one embodiment, the spacing between the memory chips in each column is smaller than the spacing between the memory chips in each row. In another embodiment, the spacing between the memory chips in each row is smaller than the spacing between the memory chips in each column.

[0061] In Operation 810, superchips are formed. In one embodiment, the processing logic can arrange the plurality of memory chips 130 as a plurality of superchips, for example, superchips 194, for testing. In one embodiment, each of the plurality of superchips 194 comprises two or more of the plurality of memory chips 130, such as a primary memory chip 130a and a secondary memory chip 130b. At least a subset of components of the two or more of the plurality of memory chips 130 in each of the plurality of superchips 194 are electrically short-circuited 295 to receive common test signals from the test equipment during testing.

[0062] In Operation 815, the superchips are tested. In one embodiment, the processing logic (e.g., test equipment) can perform one or more test operations on the superchips 194. For example, the micro-probes 198 of a test card 196, used to perform the testing, can make contact with a set of communication pads 296a on the primary memory chip 130a to provide common test signals. A set of communication pads 296b on the secondary memory chip 130b is not contacted by the micro-probes 198, thus reducing the distance between adjacent memory chips that make up the superchip 194. Instead, the secondary memory chip 130b can receive the common test signals from the primary memory chip, for example, via the electrical short circuits 295.

[0063] In Operation 820, the superchips are separated. In one embodiment, the processing logic (e.g., the semiconductor fabrication tool) can physically separate the individual memory chips 130 from the wafer 190 (e.g., by cutting). In one embodiment, the superchips 194 are separated from each other while remaining intact. In another embodiment, the individual memory chips, such as the primary memory chip 130a and the secondary memory chip 130b, which form a superchip 194, are physically separated from each other, for example, by cutting the electrical short circuits 295 between the memory chips. In this way, the individual memory chips 130 can be used in different implementations, for example, in a memory subsystem 110.

[0064] Fig. Figure 9 shows an exemplary machine of a computer system 900 in which a set of instructions can be executed that cause the machine to perform one or more of the methods described herein. In some embodiments, the computer system 900 can be connected to a host system (e.g., the host system 120 from Fig. 6A) correspond to a memory subsystem (e.g., memory subsystem 110 from Fig. 6A) contains, is coupled to, or uses, or can be used to perform the operations of a controller (e.g., to run an operating system, to perform operations according to the local media controller 135 from Fig. 6A). In alternative embodiments, the machine can be connected (e.g., networked) with other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can function as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer network environment (or distributed network environment), or as a server or client machine in a cloud computing infrastructure or environment.

[0065] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web device, server, network router, switch or bridge, or any other machine capable of executing a set of instructions (sequentially or otherwise) specifying the actions to be performed by that machine. Although a single machine is depicted, the term "machine" also includes any collection of machines that, individually or collectively, execute a set (or sets) of instructions to perform one or more of the procedures described herein.

[0066] The exemplary computer system 900 comprises a processing device 902, a main memory 904 (e.g., a read-only memory (ROM), a flash memory, a dynamic random-access memory (DRAM), such as a synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 906 (e.g., flash memory, static random-access memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0067] The processing device 902 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. Specifically, the processing device may be a CISC (Complex Instruction Set Computing) microprocessor, a RISC (Reduced Instruction Set Computing) microprocessor, a VLIW (Very Long Instruction Word) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 902 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like.The processing device 902 is configured to execute instructions 926 for performing the operations and steps described herein. The computer system 900 may also include a network interface device 908 for communication over the network 920.

[0068] The data storage system 918 may include a machine-readable storage medium 924 (also known as a computer-readable medium) on which one or more sets of instructions 926 or software are stored, comprising one or more of the methods or functions described herein. The instructions 926 may also reside wholly or at least partially in the main memory 904 and / or the processing device 902 while being executed by the computer system 900, the main memory 904 and the processing device 902 also being machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or the main memory 904 may be connected to the storage subsystem 110. Fig. 6A corresponds.

[0069] In one embodiment, the instructions 926 contain instructions for implementing functionality that is provided to the memory subsystem controller 115 or the local media controller 135 from Fig.6A. Although the machine-readable storage medium 924 is shown in an exemplary embodiment as a single medium, the term “machine-readable storage medium” shall be understood to include a single medium or multiple media that store one or more sets of instructions. The term “machine-readable storage medium” shall also include any other medium capable of storing or encoding a set of instructions for execution by the machine and causing the machine to execute one or more of the methods described in the present disclosure. The term “machine-readable storage medium” shall therefore include, but not be limited to, solid-state storage media, optical media, and magnetic media.

[0070] Some parts of the preceding detailed descriptions have been presented in the form of algorithms and symbolic representations of operations concerning data bits in computer memory. These algorithmic descriptions and representations are those used by experts in the field of data processing to most effectively communicate the content of their work to other experts. An algorithm is understood here, and generally, as a consistent sequence of operations that leads to a desired result. The operations are those that require physical manipulations of physical quantities. Typically, though not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated.It has sometimes proven useful to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like, mainly for reasons of general usage.

[0071] It should be borne in mind, however, that all these and similar terms must be associated with the corresponding physical quantities and are merely simplified designations for these quantities. The present invention may relate to the action and processes of a computer system or similar electronic computer device for converting data represented as physical (electronic) quantities in the registers and memories of the computer system into other data represented in a similar manner as physical quantities in the memories or registers of the computer system or in other such information storage systems.

[0072] The present invention also relates to a device for performing the operations described herein. This device may be specifically designed for the intended purposes or may include a general-purpose computer that is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as any type of floppy disk, including floppy disks, optical disks, CD-ROMs and magnetic-optical disks, read-only memory (ROMs), random-access memory (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0073] The algorithms and displays presented here are not tied to a specific computer or other device. Various general-purpose systems can be used with programs according to the teachings contained herein, or it may prove advantageous to construct a more specialized device for carrying out the method. The structure for a multitude of such systems is presented in this description. Furthermore, the present invention is not described with reference to a specific programming language. It is understood that a multitude of programming languages ​​can be used to implement the teachings described herein.

[0074] The present invention can be provided as a computer program product or as software, which may include a machine-readable medium containing instructions stored thereon that can be used to program a computer system (or other electronic devices) to perform a process according to the present invention. A machine-readable medium comprises any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium comprises a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory (“ROM”), random-access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, flash memory components, etc.

[0075] In the foregoing description, embodiments of the disclosure have been described with reference to specific exemplary embodiments. It is obvious that various modifications can be made to these without deviating from the broader spirit and scope of the embodiments of the disclosure, as set forth in the following claims. Accordingly, the description and the drawings should be regarded as illustrative rather than limiting.

Claims

[1] Storage device comprising: a plurality of memory chips, each memory chip containing a plurality of memory chips: a communications bus; a memory array containing a plurality of memory cells coupled to the communication bus; a control logic component that is coupled to the communication bus; an analog power component coupled to the communication bus and the memory array; and a plurality of signal communication pads coupled to the communication bus, wherein one or more of the plurality of signal communication pads are electrically short-circuited with one or more signal communication pads on another memory chip of the plurality of memory chips in order to share signals between the plurality of memory chips during testing of the storage device. [2] Storage device according to claim 1, wherein one of the multiple memory chips is designated as a primary memory chip and the remaining of the multiple memory chips are designated as secondary memory chips. [3] Storage device according to claim 2, wherein the control logic components of the secondary memory chips are deactivated during testing of the storage device, wherein control signals sent by the control logic component of the primary memory chip control both the primary memory chip and the secondary memory chips during testing of the storage device, and wherein the control logic components of the secondary memory chips are tested separately in a subsequent test operation. [4] Storage device according to claim 2, wherein the plurality of signal communication pads comprise a super-pad configured to receive a signal from an external test equipment, the signal indicating whether a corresponding memory chip is the primary memory chip or a secondary memory chip. [5] Storage device according to claim 4, wherein each memory chip of the plurality of memory chips further comprises: a pull-up resistor coupled between a supply voltage at a supply level and a sampling node, wherein the super-pad is coupled to the sampling node, wherein, when a ground voltage is applied to the super-pad, the sampling node is at the ground voltage and an input buffer can decode the ground voltage at the sampling node as an indication that the memory chip is the primary memory chip, and wherein, when no voltage is applied to the super-pad, the sampling node is at the supply voltage level and the input buffer can decode the supply voltage level at the sampling node as an indication that the memory chip is the secondary memory chip. [6] Storage device according to claim 4, wherein each memory chip of the plurality of memory chips further comprises: a pull-down resistor coupled between a ground voltage and a sampling node, wherein the super-pad is coupled to the sampling node, wherein, when a voltage is applied to the super-pad, the sampling node is at the voltage and an input buffer can decode the voltage at the sampling node as an indication that the memory chip is the primary memory chip, and wherein, when no voltage is applied to the super-pad, the sampling node is at ground voltage and the input buffer can decode the ground voltage supply level at the sampling node as an indication that the memory chip is the secondary memory chip. [7] Storage device according to claim 4, wherein each memory chip of the plurality of memory chips has a switching circuit which is coupled to the control logic component of the primary memory chip and to the control logic component of the secondary memory chip, and wherein a control signal from the super-pad controls the switching circuit via the control logic component to cause a data signal to be transferred from the control logic component of the primary memory chip to the communication bus of the primary memory chip and to the communication bus of the secondary memory chip. [8] Device comprising: a semiconductor wafer; and a plurality of memory chips arranged on the semiconductor wafer, wherein the plurality of memory chips are arranged as a plurality of super-chips for testing, each of the plurality of super-chips comprising two or more of the plurality of memory chips, and wherein at least a subset of components of the two or more of the plurality of memory chips in each of the plurality of super-chips are electrically short-circuited to receive shared test signals from the test equipment during testing. [9] Device according to claim 8, wherein a first memory chip of the two or more of the plurality of memory chips in each of the plurality of super-chips is designated as a primary memory chip and a second memory chip of the two or more of the plurality of memory chips in each of the plurality of super-chips is designated as a secondary memory chip. [10] Device according to claim 9, wherein each of the plurality of memory chips has a control logic component, wherein the control logic component of the secondary memory chip is deactivated during testing, and wherein control signals sent by the control logic component of the primary memory chip control both the primary memory chip and the secondary memory chip during testing. [11] Device according to claim 9, wherein each of the plurality of memory chips has a plurality of signal communication pads, and wherein the plurality of signal communication pads on the primary memory chip are configured to be contacted by a set of micro-probes of the test equipment to receive the shared test signals. [12] Device according to claim 11, wherein the majority of signal communication pads on the secondary memory chip are not contacted by the set of micro-probes during testing, and wherein the secondary memory chip receives the shared test signals from the primary memory chip. [13] Device according to claim 11, wherein the plurality of signal communication pads comprise a super-pad configured to receive a signal from the test equipment, the signal indicating whether a corresponding memory chip is the primary memory chip or the secondary memory chip. [14] Device according to claim 8, wherein each has a plurality of memory chips: a communications bus; a memory array containing a plurality of memory cells coupled to the communication bus; a control logic component that is coupled to the communication bus; and an analog power component that is coupled to the communication bus. [15] Procedures, including: Forming a plurality of memory chips on a semiconductor wafer; and Arranging a plurality of memory chips as a plurality of super-chips for testing, wherein each of the plurality of super-chips comprises two or more of the plurality of memory chips, and wherein at least a subset of components of the two or more of the plurality of memory chips in each of the plurality of super-chips are electrically short-circuited to receive shared test signals from a test equipment during testing. [16] Method according to claim 15, wherein a first memory chip of the two or more of the plurality of memory chips in each of the plurality of super-chips is designated as a primary memory chip and a second memory chip of the two or more of the plurality of memory chips in each of the plurality of super-chips is designated as a secondary memory chip. [17] Method according to claim 16, wherein each of the plurality of memory chips has a control logic component, wherein the control logic component of the secondary memory chip is deactivated during testing, and wherein control signals sent by the control logic component of the primary memory chip control both the primary memory chip and the secondary memory chip during testing. [18] Method according to claim 16, wherein each of the plurality of memory chips has a plurality of signal communication pads, and wherein the plurality of signal communication pads on the primary memory chip are configured to be contacted by a set of micro-probes of the test equipment to receive the shared test signals. [19] Method according to claim 18, wherein the majority of signal communication pads on the secondary memory chip are not contacted by the set of micro-probes during testing, and wherein the secondary memory chip receives the shared test signals from the primary memory chip. [20] Method according to claim 18, wherein the plurality of signal communication pads comprise a super-pad configured to receive a signal from the test equipment, the signal indicating whether a corresponding memory chip is the primary memory chip or the secondary memory chip.

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