Semiconductor component with input buffer circuit

Abstract

An exemplary apparatus comprises: a first input circuit coupled between a common source line and a first circuit node, wherein the first input circuit is configured to be controlled by a first signal; a second input circuit coupled between the common source line and a second circuit node, wherein the second input circuit is configured to be controlled by a second signal; an amplifier circuit configured to amplify a potential difference between the first and second circuit nodes; and an auxiliary current path configured to allow current to flow from the common source line to the first and second circuit nodes independently of the first and second signals.

Description

BACKGROUND

[0001] There is a case where a differential input buffer, which compares the level of an input signal and the level of a reference potential, is used for a semiconductor device, such as a DRAM. With such a differential input buffer, the characteristics of one transistor forming a circuit on the input side and the characteristics of another transistor forming a circuit on the reference side must be matched. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram showing a configuration of a semiconductor storage device according to an embodiment of the present invention; Fig. 2 is a block diagram showing a configuration of the main components of a data control circuit; and Fig. Figures 3A-3C are circuit diagrams of a data latch circuit. DETAILED DESCRIPTION

[0002] Various embodiments of the present invention are explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate certain aspects and various embodiments of the present invention. The detailed description contains sufficient detail to enable those skilled in the art to implement these embodiments of the present invention. Other embodiments may also be used, and structural, logical, and electrical modifications may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, since some of the disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0003] Fig. Figure 1 is a block diagram showing a configuration of a semiconductor storage device 10 according to an embodiment of the present invention. The diagram shown in Figure 1 is a block diagram showing a configuration of a semiconductor storage device 10 according to an embodiment of the present invention. Fig. The semiconductor memory device 10 shown in Figure 1 is an LPDDR5 DRAM and comprises a memory cell array 11. When the memory cell array 11 is accessed, an instruction address signal CA is input from an external source into an instruction address port 12. The instruction address signal CA is fed to an access control circuit 13. The access control circuit 13 is synchronized with complementary clock signals CKT and CKC, respectively, which are input into clock ports 14 and 15, respectively. This circuit decodes the instruction address signal CA, counts latencies, and performs other functions.

[0004] When an instruction contained in the command address signal CA specifies a read operation, the access control circuit 13 performs a read access to a memory cell contained in the memory cell array 11 based on an address contained in the command address signal CA. The read data DQ from the accessed memory cell is output externally via a data I / O port 17 and a data control circuit 16. When the instruction contained in the command address signal CA specifies a write operation, the write data DQ input to the data I / O port 17 is transferred to the memory cell array 11 via an input buffer circuit 20 contained in the data control circuit 16. The write data DQ is input to the memory cell array 11 while being synchronized with complementary data strobe signals DQST and DQSC, which are supplied to the data strobe ports 18 and 19, respectively.The write data DQ transferred to memory cell array 11 is written to the memory cell contained in memory cell array 11, based on the address contained in the instruction address signal CA.

[0005] Fig. Figure 2 is a block diagram showing a configuration of the main components of the data control circuit 16. As shown in Fig. As shown in Figure 2, the data control circuit 16 comprises a gating circuit 22 that receives data strobe signals DQST and DQSC via an input buffer 21. The internal data strobe signals DS and DSF output by the gating circuit 22 correspond to the data strobe signals DQST and DQSC, respectively. The internal data strobe signals DS and DSF are fed into a divider circuit 23. By dividing the internal data strobe signals DS and DSF, the divider circuit 23 generates four-phase internal data strobe signals DQS0, DQS90, DQS180, and DQS270. If the phase of the internal data strobe signal DQS0 is 0°, then the phases of the internal data strobe signals DQS90, DQS180, and DQS270 are 90°, 180°, and 270°, respectively. The internal data strobe signals DQS0, DQS90, DQS180, and DQS270 are fed to input buffer 20.

[0006] The input buffer 20 includes a data latch circuit 200 synchronized with the internal data strobe signal DQS0 to hold the write data DQ, a data latch circuit 201 synchronized with the internal data strobe signal DQS90 to hold the write data DQ, a data latch circuit 202 synchronized with the internal data strobe signal DQS180 to hold the write data DQ, and a data latch circuit 203 synchronized with the internal data strobe signal DQS270 to hold the write data DQ. The write data IDQ0, the write data IDQ90, the write data IDQ180 and the write data IDQ270, which are each held or stored in the data latch circuits 200 to 203, are transferred to the memory cell array 11.

[0007] Data latch circuits 200, 201, 202, and 203 each comprise a DFE (Decision Feedback Equalizer) circuit 200A, a DFE circuit 201A, a DFE circuit 202A, and a DFE circuit 203A, respectively, each of which reduces ISI (Intersymbol Interference) noise. Data held in data latch circuit 200 is fed back to DFE circuit 201A, which is contained in data latch circuit 201. Data held in data latch circuit 201 is fed back to DFE circuit 202A, which is contained in data latch circuit 202. The data held in data latch circuit 202 is fed back to DFE circuit 203A contained in data latch circuit 203. The data held in data latch circuit 203 is fed back to DFE circuit 200A contained in data latch circuit 200.

[0008] In this way, four data latch circuits 200 to 203 are assigned to one data I / O port 17. Although in the Fig. 1 and Fig. Figure 2 shows only one data I / O port 17, but in practice a plurality (for example eight) of data I / O ports 17 are provided, and each of the data I / O ports 17 is assigned four data latch circuits 200 to 203.

[0009] Fig. 3A is a circuit diagram of the data latch circuit 200 according to the first example. As in Fig. As shown in Figure 3A, the data latch circuit comprises 200 P-channel MOS transistors 210 to 218, N-channel MOS transistors 220 to 227, and current control circuits 230 and 240. Transistor 210 is coupled between a supply line L1, supplied with a supply potential VDD, and a common source line L3. An inversion signal DQS0B of the internal data strobe signal DQS0 is applied to a gate electrode of transistor 210. Transistor 211 is coupled between the common source line L3 and a circuit node N5. The write data DQ is applied externally via data I / O pin 17 to a gate electrode of transistor 211. Transistor 212 is coupled between the common source line L3 and a circuit node N6. A reference potential VREF is applied to a gate electrode of transistor 212.Transistors 211 and 212 form a differential amplifier circuit A1, which controls the current flowing into circuit nodes N5 and N6 based on a potential difference between the reference potential VREF and the write data DQ. Differential amplifier circuit A1 is activated when the inversion signal DQS0B of the internal data strobe signal DQS0 reaches a low level. Transistor 220 is coupled between circuit node N5 and a supply line L2 connected to ground potential VSS. Transistor 221 is coupled between circuit node N6 and the supply line L2 connected to ground potential VSS. The inversion signal DQS0B of the internal data strobe signal DQS0 is applied to the gate electrodes of transistors 220 and 221.In this configuration, circuit nodes N5 and N6 are pre-charged to ground potential VSS, and an amplifier circuit A1 is deactivated when the inversion signal DQS0B of the internal data strobe signal DQS0 reaches a high level. Additionally, the DFE circuit 200A is coupled to each of circuit nodes N5 and N6. In some examples, transistors 211 and 212 can be referred to as input transistors 211 and 212.

[0010] Transistors 215, 216, 222, and 223 form a flip-flop circuit F. Specifically, transistors 215 and 222 are connected in series between the supply line L1 (which is supplied with the supply potential VDD) and a circuit node N1, and their gate electrodes are coupled to the drains of transistors 216 and 223. Circuit node N1 forms an input node of the flip-flop circuit F. Transistors 216 and 223 are connected in series between the supply line L1 (which is supplied with the supply potential VDD) and a circuit node N2, and their gate electrodes are coupled to the drains of transistors 215 and 222. Circuit node N2 forms the other input node of the flip-flop circuit F. Internal write data IDQ0T is output by the drains of transistors 215 and 222, which form an output node.Internal write data IDQ0B is output from the drains of transistors 216 and 223, which form the other output node. When the internal data strobe signal DQS0 reaches a low level, the internal write data IDQ0T / B is pre-charged to the supply potential VDD by transistors 213 and 214.

[0011] Transistor 224 is coupled between circuit node N1 and circuit node N3. A gate electrode of transistor 224 is coupled to circuit node N5. Circuit node N3 is coupled via current control circuit 230 and transistor 226 to supply line L2, which is supplied to ground potential VSS. Transistor 225 is coupled between circuit node N2 and circuit node N4. A gate electrode of transistor 225 is coupled to circuit node N6. Circuit node N4 is coupled via current control circuit 240 and transistor 227 to supply line L2, which is supplied to ground potential VSS. With this configuration, transistors 224 and 225 form an amplifier circuit A2, which supplies an operating current to the flip-flop circuit F based on the potentials of circuit nodes N5 and N6.

[0012] The current control circuit 230 comprises transistors 231, 232, and 234, which are coupled in parallel between circuit node N3 and the supply line L2, which is connected to ground potential VSS. Inversion signals from each of the bits DN0, DN1, and DN2, forming a down-code signal DN, are applied to the gate electrodes of transistors 231, 232, and 234, respectively. The down-code signal DN is a binary signal. Bit DN0 is the least significant bit of the down-code signal DN, and transistor 231, supplied with an inversion signal of bit DN0, forms a least significant transistor. Bit DN2 is the most significant bit of the down-code signal DN, and transistor 234, supplied with an inversion signal of bit DN2, forms a most significant transistor. If the transistor size of transistor 231 is set to "1", the transistor size of transistor 232 is "2", and the transistor size of transistor 234 is "4".Furthermore, transistor 226 is connected in parallel to the current control circuit 230. Since the supply potential VDD is permanently applied to a gate electrode of transistor 226, transistor 226 is switched on independently of the down-code signal DN.

[0013] The current control circuit 240 comprises transistors 241, 242, and 244, which are coupled in parallel between circuit node N4 and the supply line L2, which is connected to ground potential VSS. Inversion signals from each of the bits UP0, UP1, and UP2, forming an upcode signal UP, are applied to the gate electrodes of transistors 241, 242, and 244, respectively. The upcode signal UP is a binary signal. Bit UP0 is the least significant bit of the upcode signal UP, and transistor 241, supplied with an inversion signal of bit UP0, forms the least significant transistor. Bit UP2 is the most significant bit of the upcode signal UP, and transistor 244, supplied with an inversion signal of bit UP2, forms the most significant transistor. If the transistor size of transistor 241 is set to "1", the transistor size of transistor 242 is "2", and the transistor size of transistor 244 is "4".Furthermore, transistor 227 is connected in parallel to the current control circuit 240. Since the supply potential VDD is permanently applied to a gate electrode of transistor 227, transistor 227 is switched on independently of the up-code signal UP.

[0014] Here, the dimensions of transistor 231 and transistor 241 are identical. The dimensions of transistor 232 and transistor 242 are identical. The dimensions of transistor 234 and transistor 244 are identical. The dimensions of transistor 226 and transistor 227 are identical.

[0015] With such a circuit configuration, the amount of current flowing into current control circuit 230 according to the down-code signal DN can be adjusted. Likewise, the amount of current flowing into current control circuit 240 according to the up-code signal UP can be adjusted. Therefore, if there is an input offset in data latch circuit 200, the input offset can be corrected by adjusting the amount of current flowing into current control circuits 230 and 240 using the down-code signal DN and the up-code signal UP.

[0016] The in Fig. The data latch circuit 200 shown in Figure 3A further includes transistors 217 and 218. Transistor 217 is connected between the common source line L3 and circuit node N5. That is, transistor 217 is connected in parallel with transistor 211. Transistor 218 is connected between the common source line L3 and circuit node N6. That is, transistor 218 is connected in parallel with transistor 212. The gate electrode of each of transistors 217 and 218 is connected to the supply line L2. That is, the gate electrode of each of transistors 217 and 218 is fixed to ground potential VSS. Therefore, transistors 217 and 218 are always in the ON state. Here, the size of transistors 217 and 218 is sufficiently smaller than the size of transistors 211 and 212. A high-resistance resistor can be used instead of transistors 217 and 218.In some examples, transistors 217 and 218 can be referred to as auxiliary transistors 217 and 218.

[0017] As explained, the data latch circuit comprises 200 auxiliary transistors 217 and 218 connected in parallel to the input transistors 211 and 212, respectively. Therefore, when the inverted signal DQS0B of the internal data strobe signal DQS0 is activated to a low level to turn on transistor 210, a small current flows from the common source line L3 through transistors 217 and 218 to circuit nodes N5 and N6. Since the levels of circuit nodes N5 and N6 rise to a low level immediately after the activation of the inverted signal DQS0B of the internal data strobe signal DQS0, it is consequently possible for the amplifier circuit A2 and the flip-flop circuit F to respond quickly after the write data DQ appears, even if the level of the available supply potential VDD is set relatively low.

[0018] Fig. Figure 3B is a circuit diagram of a data latch circuit 200 according to the second example. The in Fig. The data latch circuit 200 shown in 3B differs from the one in Fig. The data latch circuit 200 shown in Figure 3A is achieved by applying a selection signal SEL to the gate electrodes of transistors 217 and 218. The level of the selection signal SEL is determined by a parameter set in the mode register 30, which is implemented in the access control circuit 13 according to Figure 3A. Fig. 1 is included. For example, if the parameter set in mode register 30 indicates that the level of the available supply potential VDD is below a predetermined value, the level of the selection signal SEL is set to ground potential VSS. If the parameter indicates that the level of the supply potential VDD is equal to or greater than the predetermined value, the level of the selection signal SEL is set to the supply potential VDD. Consequently, if the level of the supply potential VDD is below the predetermined value, transistors 217 and 218 are activated, so that the same operation as in Fig. The data latch circuit 200 shown in Figure 3A can be used. On the other hand, if the level of the supply potential VDD is equal to or greater than the predetermined value, transistors 217 and 218 are deactivated, thus preventing a reduction in the potential difference between circuit nodes N5 and N6 caused by the activation of transistors 217 and 218. Alternatively, the level of the selection signal SEL can be changed in several steps according to the parameters set in mode register 30. This makes it possible to fine-tune the amount of current flowing through transistors 217 and 218.

[0019] Fig. 3C is a circuit diagram of a data latch circuit 200 according to the third example. The in Fig. The data latch circuit 200 shown in 3C differs from the one in Fig. The data latch circuit 200 shown in Figure 3A is configured by connecting two transistors 217A and 217B in parallel with transistor 211 and by connecting two transistors 218A and 218B in parallel with transistor 212. The dimensions of transistors 217A, 217B, 218A, and 218B can be the same, or the dimensions of transistors 217A and 218A can be larger than the dimensions of transistors 217B and 218B. At a minimum, the dimensions of transistors 217A and 218A are the same, and the dimensions of transistors 217B and 218B are the same. A selection signal SELA is applied jointly to the gate electrodes of transistors 217A and 218A, and a selection signal SELB is applied jointly to the gate electrodes of transistors 217B and 218B. The levels of the selection signals SELA and SELB are determined by parameters set in the mode register 30, which is contained in the access control circuit 13, as shown in Fig. 1 shown. This makes it possible to adjust the amount of current flowing through transistors 217A, 217B, 218A and 218B in several stages according to the level of the supply potential VDD, which is specified by the parameters set in mode register 30.

[0020] Each of the other data latch circuits 201 to 203, which form the input buffer 20, has a circuit configuration that corresponds to that of the circuits described in the Fig. The data latch circuit 200 shown in 3A-3C is identical. Different down-code signals DN and up-code signals UP are used for each of the data latch circuits 200 to 203, thus canceling out any input offset in the data latch circuits 200 to 203 in each of these circuits.

[0021] Although this invention has been disclosed in connection with certain preferred embodiments and examples, it will be clear to the person skilled in the art that, beyond the specifically disclosed embodiments, the inventions also include other alternative embodiments and / or uses of the inventions, as well as obvious modifications and equivalents thereof. Furthermore, other modifications that fall within the scope of this invention will be readily apparent to the person skilled in the art based on this disclosure. It is also conceivable that various combinations or subcombinations of the specific features and aspects of the embodiments can be produced and still fall within the scope of the inventions. It is understood that various features and aspects of the disclosed embodiments can be combined with one another or interchanged to form different embodiments of the disclosed invention.Therefore, the scope of at least some of the inventions disclosed herein should not be limited by the special embodiments described above.

Claims

[1] Device comprising: a differential amplifier circuit with a pair of a first and a second input transistor; a first auxiliary transistor connected in parallel to the first input transistor; and a second auxiliary transistor connected in parallel to the second input transistor, where the first and second auxiliary transistors are configured to always be in an ON state. [2] Device according to claim 1, wherein the first and second auxiliary transistors each have a smaller size than the first and second input transistors. [3] Device according to claim 1, wherein a control electrode of the first auxiliary transistor is short-circuited with a control electrode of the second auxiliary transistor. [4] Device according to claim 1, where the first input transistor is configured to be controlled by externally supplied input data, and where the second input transistor is configured to be controlled by a reference potential with respect to the input data. [5] Device according to claim 4, further comprising a common-source transistor connected between a first supply line and a common source of the first and second input transistors, wherein the common-source transistor has a control electrode supplied with an internal data strobe signal. [6] Device according to claim 1, wherein each of the first and second auxiliary transistors has the same conductivity type as each of the first and second input transistors. [7] Device comprising: a first input circuit coupled between a common source line and a first circuit node, wherein the first input circuit is configured to be controlled by a first signal; a second input circuit coupled between the common source line and a second circuit node, wherein the second input circuit is configured to be controlled by a second signal; an amplifier circuit configured to amplify a potential difference between the first and second circuit nodes; and an auxiliary current path configured to allow current to flow functionally from the common source line to the first and second circuit nodes, independent of the first and second signals. [8] Device according to claim 7, wherein the auxiliary current path comprises a first transistor connected in parallel to the first input circuit and a second transistor connected in parallel to the second input circuit. [9] Device according to claim 8, wherein the first input circuit includes a third transistor connected between the common source line and the first circuit node, wherein the second input circuit includes a fourth transistor connected between the common source line and the second circuit node, and where each of the first and second transistors is smaller than each of the third and fourth transistors. [10] Device according to claim 8, wherein a control electrode of the first transistor is short-circuited with a control electrode of the second transistor. [11] Device according to claim 10, wherein the control electrode of the first and second transistors is set to an active level. [12] Device according to claim 10, further comprising a control circuit configured to control a level of the control electrodes of the first and second transistors. [13] Device according to claim 10, wherein the control electrode of each of the first and second transistors is supplied with an active level in a first operating mode, and wherein the control electrode of each of the first and second transistors is supplied with an inactive level in a second operating mode. [14] Device according to claim 10, wherein the auxiliary current path further comprises a fifth transistor connected in parallel to the first input circuit and a sixth transistor connected in parallel to the second input circuit. [15] Device according to claim 14, further comprising a control circuit configured to control a level of the control electrodes of the first and second transistors and to control a level of the control electrodes of the fifth and sixth transistors. [16] Device according to claim 7, wherein the amplifier circuit comprises: a first transistor with a control electrode coupled to the first circuit node; a second transistor with a control electrode coupled to the second circuit node; and a flip-flop circuit configured to operate based on the current flowing through the first and second transistors. [17] Device according to claim 16, further comprising a third transistor connected between a supply line and the common source line, wherein the third transistor has a control electrode supplied with an internal data strobe signal. [18] Device according to claim 17, wherein the first signal contains input data supplied from outside. [19] Device according to claim 18, wherein the second signal is a reference potential with respect to the input data. [20] Device comprising: a first and a second supply line, which are fed by a first and a second supply potential that are different from each other; a first transistor connected between the first supply line and a common source line; a second transistor connected between the common source line and a first circuit node; a third transistor connected between the common source line and a second circuit node; a fourth transistor, which is connected between the first circuit node and the second supply line; a fifth transistor, which is connected between the second circuit node and the second supply line; an amplifier circuit configured to amplify a potential difference between the first and second circuit nodes; a sixth transistor connected in parallel to the first transistor; and a seventh transistor connected in parallel to the second transistor, where each of the first, second, third, sixth and seventh transistors has a first conductivity type, where each of the fourth and fifth transistors has a second conductivity type that is different from the first conductivity type, wherein each of the first, second, third, fourth and fifth transistors has a control electrode which is supplied with an internal data strobe signal, and wherein each of the sixth and seventh transistors has a control electrode which is short-circuited to the second supply line.

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