STORAGE DEVICE AND METHOD FOR FORMING THE SAME

Abstract

A method for fabricating a semiconductor device comprises forming a stack having channel layers between which sacrificial layers are arranged, structuring the stack to form a fin-shaped structure, forming a dummy gate stack across the fin-shaped structure, selectively removing the sacrificial layers to expose the channel layers as channel elements, depositing a dummy layer in the space between the channel elements, removing the dummy gate stack, removing the dummy layer, forming a gate structure to enclose each of the channel elements, depositing a backside dielectric layer on a rear side of the semiconductor device, structuring the backside dielectric layer to form a backside gate via directly beneath the gate structure.the doping of a threshold voltage-optimizing dopant through the back-side gate via opening in the gate structure, and after doping the threshold voltage-optimizing dopant, the formation of a back-side gate via in the back-side gate via opening.

Description

PRIORITY DATA

[0001] This application claims priority over the preliminary US patent application No. 63 / 652,956, filed on May 29, 2024, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND

[0002] The integrated semiconductor (IC) industry has experienced exponential growth. Technological advances in IC materials and design have spawned entire generations of integrated circuits, each generation featuring smaller and more complex circuits than the previous one. As integrated circuits (ICs) evolve, functional density (the number of interconnected components per chip area) has generally increased, while geometric size (the smallest component (or trace) that can be created using a manufacturing process) has decreased. This scaling process typically offers advantages, increasing production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of machining and manufacturing ICs.

[0003] In conjunction with the technology of integrated submicron circuits, static random-access memory (SRAM) devices have become a popular memory unit for high-speed communication, image processing, and system-on-a-chip (SoC) products. The number of embedded SRAM devices in microprocessors and SoCs is increasing to meet the performance requirements of each new generation of technology. As the scope and importance of silicon technology grow with each generation, the manufacturing of SRAM devices faces certain limitations. For example, SRAM devices can encounter problems due to low cell ratios, such as a low beta ratio. The beta ratio is the ratio of the drive current of pull-down transistors to the drive current of the corresponding pass-through gate transistors. The beta ratio is important for the stability of SRAM cells.A beta ratio greater than 1 generally provides a larger operating window for read operations. However, when creating high-density SRAM arrays, a beta ratio greater than 1 presents challenges in the manufacturing process. For example, it is extremely difficult to meet these requirements while simultaneously keeping cell size small. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various elements are not shown to scale and are for illustrative purposes only. In fact, the dimensions of various features or elements may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1A and Fig. Figure 1B represents a perspective view or a top view of a section of a storage device in accordance with some embodiments of the present disclosure. Fig. Figure 2 shows a cross-sectional view of different layers of a storage device in accordance with some embodiments of the present disclosure. Fig. Figure 3 represents a circuit diagram of a static random access memory cell (SRAM cell) in accordance with some embodiments of the present disclosure. Fig. 4 represents a design of the SRAM cell according to Fig. 3 in accordance with some embodiments of the present disclosure. The Fig. 5 and Fig. Figure 6 represents designs of front-side features of a 2 x 2 SRAM arrangement in accordance with some embodiments of the present disclosure. The Fig. 7 and Fig. Figure 8 represents designs of rear-side features of a 2 × 2 SRAM arrangement in accordance with some embodiments of the present disclosure. Fig. Figure 9 shows a flowchart of a method for forming an integrated circuit comprising a plurality of SRAM cells, in accordance with some embodiments of the present disclosure. The Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31, Fig. 32, Fig. 33, Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42, Fig. 43 and Fig. Figure 44 shows cross-sectional views of an integrated circuit containing SRAM cells during the manufacturing process according to the method of Fig. 9 in accordance with some embodiments of the present disclosure. The Fig. 45, Fig. 46, Fig. 47 and Fig. Figure 48 shows graphical representations of a limit-optimizing dopant concentration in a gate structure of pass-through gate transistors in SRAM cells in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides numerous different embodiments, or examples, for implementing various features / elements of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and should not be considered as limitations. For example, the formation of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact with each other, but may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact with each other.

[0006] Furthermore, the present disclosure may repeat reference numerals and / or reference symbols in the various examples. This repetition serves the purpose of simplification and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed. Moreover, the formation of an element that is connected and / or coupled to another element in the present disclosure may have embodiments in which the elements are formed in direct contact with one another, and may also have embodiments in which additional elements are formed between the elements, such that the elements cannot be arranged in direct contact with one another. Furthermore, terms of spatial relationships, for example, "lower," "upper," "horizontal," "vertical," "above," "over," "below," "underneath," "upward," "downward," "above," "below," etc., are used.The terms spatial relationships, as well as their derivatives (for example, adverbial forms thereof and the like), are used to simplify the present disclosure of the relationship of one feature to another. The terms spatial relationships are intended to cover different orientations of the device incorporating the elements. Furthermore, if a number or range of numbers is described by "about," "approximately," and the like, the expression shall include numbers that lie within + / - 10% of the described number, unless otherwise specified. For example, the term "approximately 5 nm" may encompass the dimensional range from 4.5 nm to 5.5 nm.

[0007] The present disclosure provides various embodiments of a storage device. In particular, the present disclosure provides various embodiments of a static random-access memory device structure (SRAM device structure) with a beta ratio greater than 1. The term "beta ratio" is defined as the ratio of the drive current of pull-down transistors to the drive current of the corresponding pass-gate transistors in an SRAM cell. The beta ratio is an important parameter with regard to the stability of SRAM cells. The beta ratio influences the stability of an SRAM cell. If the beta ratio is greater than 1, this means that the pull-down transistors are more powerful than the pass-gate transistors, thus ensuring that the stored data is not accidentally inverted during a read operation.If the beta ratio is greater than 1, the static noise margin (SNM) is also improved during a read operation, as is the maximum voltage level (Vmax) to which the memory node of an SRAM cell can rise during a read operation.

[0008] In some implementations, an SRAM cell features pull-down and pass-through gate transistors of the same transistor type, with identical active area dimensions and the same work-effect metal layer (WFM) material composition in the gate structures. Thus, the pull-down and pull-up transistors in the same SRAM cell would have the same threshold voltage (Vt) and current-driving capability, resulting in a beta ratio of 1. However, the aggressive miniaturization of IC dimensions has led to closely spaced active areas and gate structures, making it challenging to vary the active area dimensions and WFM material composition in the gate structures for different transistors.

[0009] In the embodiments of the present disclosure, the threshold voltage of the forward-gate transistors is adjusted separately by doping the WFM layer in the gate structures of the forward-gate transistors with dopants that optimize the threshold voltage (Vt) during the formation of the gate vias. The dopants that optimize the threshold voltage Vt increase the threshold voltage of the forward-gate transistors and decrease their current-driving capability relative to the pull-down transistors, thereby increasing the beta ratio. The introduction of the dopants that optimize Vt is continued up to the gate via formation step to ensure that the front-end-of-line (FEOL) process, which includes the formation of the transistor structures, remains unchanged.

[0010] The gate vias on the pass-through transistors provide electrical connections between the gate structures and word lines in the multilayer interconnect structure. In SRAM devices, the multilayer interconnect structure is formed via source / drain contacts and gate vias of the memory cell transistors. The multilayer interconnect structure provides metal routings for connecting power lines and signal lines (such as bit lines and word lines) within and between the memory cells of SRAM devices. As SRAM devices have become increasingly miniaturized, the metal traces in the multilayer interconnect structure are also reduced in size. Because the available layout area is more limited, the metal traces are formed with reduced dimensions, resulting in larger voltage drops.One solution involves forming metal traces on the back of SRAM cells in addition to those on the front, which reduces the routing density. The multilayer interconnect structures formed on both the front and back of SRAM cells are referred to as double-sided multilayer interconnect structures. Accordingly, gate vias can be formed on the front, back, or both sides of the SRAM cells. These gate vias, formed on the gate structures of the forward-gate transistors, provide a way to further adjust the forward-gate transistor threshold voltages during the manufacturing process and increase the beta ratio of SRAM cells.

[0011] The details of the device structures disclosed herein are described with reference to the attached figures. Some embodiments relate to multi-gate transistors, but are not limited to them. Multi-gate transistors have been introduced to improve gate control by increasing gate-channel coupling, reducing turn-off current, and reducing short-channel effects (SCEs). One such multi-gate transistor that has been introduced is the fin-like field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure that extends from a substrate on which it is formed and is used to create the FET channel. Another multi-gate transistor, which has been introduced in part to address performance challenges associated with the FinFET, is the wrap-around gate transistor (GAA transistor).The GAA transistor gets its name from its gate structure, which can extend around the channel region (for example, a stack of channel elements), thus providing access to the channel on four sides. The GAA transistor is compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and its structure enables aggressive miniaturization while maintaining gate control and minimizing SCEs. The following disclosure continues with one or more GAA examples to illustrate different embodiments of the present disclosure. However, it is understood that the application is not limited to a particular device type unless expressly stated otherwise. For example, aspects of the present disclosure may also be applicable to an implementation based on FinFETs or planar FETs.

[0012] The Fig. 1A and Fig. Figure 1B represents a perspective view or a top view of a section of an integrated circuit component (IC component) 10, such as an SRAM component, implemented using multi-gate transistors, such as GAA transistors. Referring to Fig. In section 1A, the IC component 10 has a substrate 12. The substrate 12 can contain an elemental semiconductor (consisting of a single element), such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 12 can be a single-layer material with a uniform composition. Alternatively, the substrate 12 can have multiple layers of material with the same or different compositions suitable for the fabrication of IC components.In one example, the substrate 12 can be a silicon-on-insulator (SOI) substrate, which has a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 12 can have a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source / drain regions, can be formed in or on the substrate 12. Depending on the design requirements, the doped regions can be doped with n-type dopants, such as phosphorus or arsenic, and / or p-type dopants, such as boron. The doped regions can be formed directly on the substrate 12, in a p-well structure, an n-well structure, a double-well structure, or using a raised structure.Doped regions can be formed by implantation of dopant atoms, doped epitaxial growth in situ and / or other suitable techniques.

[0013] Three-dimensional active regions 14 are formed on the substrate 12. An active region for a transistor refers to an area in which a source region, a drain region, and a channel region are formed beneath a gate structure of the transistor. In this context, an active region can also be referred to as an “oxide definition region (OD region)”. Each of the active regions 14 exhibits longitudinally extended nanostructures 70 (as shown in Fig. (2 shown) are defined in channel regions within the active region and stacked vertically above a fin-shaped base. The fin-shaped base projects upwards from the substrate 12. Source / drain elements 16 are defined in source / drain regions within the active region and formed above the fin-shaped base. The source / drain elements 16 border two opposite sides of the nanostructures 70. The source / drain elements 16 can have epilayers that are epitaxially grown on the fin-shaped base.

[0014] The IC component 10 further comprises insulating structures (or insulating elements) 18 formed over the substrate 12. The insulating structures 18 electrically isolate different components of the IC component 10 from one another. The insulating structures 18 can contain silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a dielectric material with a low K-value, and / or other suitable materials. In some embodiments, the insulating structures 18 can comprise shallow trench insulating elements (STI elements). In one embodiment, the insulating structures 18 are formed by etching trenches in the substrate 12 during the formation of the active regions 14. The trenches can then be filled with an insulating material as described above, followed by a chemical-mechanical planarization (CMP) process.Other insulation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, can also be implemented as the insulation structures 18. Alternatively, the insulation structures 18 can have a multilayer structure, which, for example, includes one or more thermal oxide lining layers.

[0015] The IC component 10 also features gate structures (or gate stacks) 20 formed over channel regions and interpenetrating them in the active regions 14. The gate structures 20 can be dummy gate structures (which, for example, have an oxide gate dielectric and a polysilicon gate electrode) or can be high-kΩ metal gate structures (HCMF structures), which have a high-kΩ gate dielectric and a metal gate electrode, the HCMF structures being formed by replacing the dummy gate structures. Although not shown here, the gate structures 20 can have additional material layers, such as an interface layer, a cover layer, other suitable layers, or combinations thereof.

[0016] Referring to Fig. In 1B, several active regions 14 are aligned lengthwise along the X-direction, and several gate structures 20 are aligned lengthwise along the Y-direction, that is, generally perpendicular to the active regions 14. Transistors are formed at the intersections of the active regions 14 and the gate structures 20. In many embodiments, the IC component 10 has additional elements, such as gate spacers arranged along the side walls of the gate structures 20, and numerous other elements.

[0017] Fig. Figure 2 is a schematically represented partial cross-sectional view of various layers (planes) that can be formed above and below a semiconductor substrate (or a wafer) to form a section of a storage device, such as an IC chip. Fig. 1A and Fig. 1B, to form in accordance with various aspects of the present revelation. As in Fig. As shown in Figure 2, the different layers have a component layer DL, a front-side multilayer interconnect structure FMLI arranged above the component layer DL, and a rear-side multilayer interconnect structure BMLI arranged below the component layer DL.

[0018] The component layer DL comprises components (for example, transistors, resistors, capacitors and / or inductors) and / or component parts (for example, doped wells, gate structures and / or source / drain elements). In embodiments which Fig. As represented in Figure 2, the component layer DL comprises the substrate 12, doped regions 62 (for example, n-wells and / or p-wells) arranged in the substrate 12, an insulating element 18, and transistors T. In the illustrated embodiment, the transistors T have floating channel layers (also referred to as channel elements) 70 in the form of nanostructures (for example, nanowires or nanosheets) and gate structures 20 arranged between source / drain elements 16, wherein the gate structures 20 envelop and / or surround the floating channel layers 70. Each of the gate structures 20 has a metal gate stack formed from a gate electrode 74 arranged over a dielectric gate layer 76 together with spacer elements 78 arranged along the side walls of the metal gate stack.

[0019] The multilayer interconnect structures FMLI and BMLI electrically connect various components of the DL layer, enabling them to operate according to the design requirements of the storage device. Each FMLI and BMLI multilayer interconnect structure can have one or more interconnect layers.

[0020] In the illustrated embodiment, the front-side multilayer interconnect structure FMLI comprises a contact interconnect layer (CO layer), a through-hole interconnect layer (Vo layer), a metal zero interconnect layer (Mo layer), a through-hole interconnect layer (V1 layer), a metal one interconnect layer (M1 layer), a through-hole interconnect layer (V2 layer), a metal two interconnect layer (M2 layer), a through-hole interconnect layer (V3 layer), and a metal three interconnect layer (M3 layer). Each of the CO, Vo, Mo, V1, M1, V2, M2, V3, and M3 layers can be designated as a metal layer. Metal conductors formed on the Mo layer can be designated as Mo metal conductors.Similarly, vias or metal conductors formed on levels V1, M1, V2, M2, V3, and M3, respectively, can be designated as V1 vias, M1 metal conductors, V2 vias, M2 metal conductors, V3 vias, and M3 metal conductors, respectively. The present disclosure considers a multilayer interconnect structure FMLI, which has more or fewer interconnect layers and / or levels, for example, a total of N interconnect layers (levels) of the multilayer interconnect structure FMLI, where N is an integer between 1 and 10. Each level of the multilayer interconnect structure FMLI has conductive elements (for example, metal conductors, metal vias, and / or metal contacts) arranged in one or more dielectric layers (for example, an intermediate dielectric layer (ILD layer) and an etch stop layer (ESL)).The dielectric layers of the multilayer interconnect structure FMLI are collectively referred to as a dielectric structure 66. In some embodiments, conductive elements in the same plane of the multilayer interconnect structure FMLI, such as the Mo plane, are formed simultaneously. In some embodiments, conductive elements in the same plane of the multilayer interconnect structure FMLI have essentially coplanar upper surfaces and / or essentially coplanar lower surfaces.

[0021] In the illustrated embodiment, the CO layer has source / drain contacts MD arranged in the dielectric structure 66. The source / drain contacts MD can be formed on or in direct contact with silicide layers arranged directly on the source / drain elements 16. The Vo layer has gate vias VG arranged on the gate structures and source / drain contact vias VD arranged on the source / drain contacts MD, wherein the gate vias VG connect gate structures to Mo metal conductors, and source / drain vias Vo connect source / drain contacts MD to Mo metal conductors. In some embodiments, the Vo layer can also have butt contacts arranged in the dielectric structure 66.The V1 layer features V1 vias arranged in the dielectric structure 66, the V1 vias connecting M0 metal conductors to M1 metal conductors. The M1 layer features M1 metal conductors in the dielectric structure 66. The V2 layer features V2 vias arranged in the dielectric structure 66, the V2 vias connecting M1 metal conductors to M2 metal conductors. The M2 layer features M2 metal conductors arranged in the dielectric structure 66. The V3 layer features V3 vias arranged in the dielectric structure 66, the V3 vias connecting M2 metal conductors to M3 metal conductors.

[0022] In the illustrated embodiment, the backside multilayer interconnect structure BMLI comprises a backside via zero interconnect layer (BVo layer), a backside metal zero layer (BMo layer), a backside via one interconnect layer (BV1 layer), and a backside metal one interconnect layer (BM1 layer). Each of the BVo, BMo, BV1, and BM1 layers can be referred to as a metal layer. Metal conductors formed at the BM0 layer can be referred to as BMo metal conductors. Likewise, vias or metal conductors formed at the BV0, BV1, or BM1 layers can be referred to as BV0 vias, BV1 vias, or BM1 metal conductors, respectively.The present disclosure relates to a multilayer interconnect structure BMLI, which has more or fewer interconnect layers and / or levels, for example, a total of M interconnect layers (levels) of the multilayer interconnect structure BMLI, where M is an integer between 1 and 10. Each level of the multilayer interconnect structure BMLI has conductive elements (for example, metal conductors, metal vias, and / or metal contacts) arranged in one or more dielectric layers (for example, an intermediate dielectric layer (ILD layer) and an etch stop layer (ESL)). The dielectric layers of the multilayer interconnect structure BMLI are collectively referred to as a backside dielectric structure 66'. In some embodiments, conductive elements in the same level of the backside multilayer interconnect structure BMLI, such as the BMo level, are formed simultaneously.In some embodiments, conductive elements in the same plane of the multilayer interconnect structure BMLI have upper surfaces which are essentially coplanar and / or lower surfaces which are essentially coplanar.

[0023] In the illustrated embodiment, the BVo layer features vias BV0 formed beneath the DL layer. For example, the BV0 vias can include one or more back-side gate vias formed directly beneath and in direct contact with the gate structure(s) of the DL layer. The BV0 vias can also include one or more back-side source / drain vias formed directly beneath the source / drain elements of the DL layer and connected to these source / drain elements by means of a silicide layer. The BM0 layer features BM0 metal conductors formed beneath the BV0 layer. The back-side gate vias connect gate structures to BM0 metal conductors, and the back-side source / drain vias connect source / drain elements to BM0 metal conductors.The BV1 layer features BV1 vias arranged in the backside dielectric structure 66', with the BV1 vias connecting BM0 metal conductors to BM1 metal conductors. The BM1 layer includes BM1 metal conductors formed beneath the BV1 layer.

[0024] Fig. Section 2 has been simplified for the sake of clarity and a better understanding of the inventive concepts of the present disclosure. Additional features / elements can be added in the various layers of the memory, and some of the described elements can be replaced, modified, or omitted in other embodiments of the memory. Fig. Figure 2 is only an example and may not represent an actual cross-sectional view of the IC chip 10 and / or the SRAM cells 100, which are described in more detail below.

[0025] Now referring to Fig. Figure 3 shows an exemplary circuit diagram for an SRAM cell 100. The SRAM cell 100 has two cross-coupled inverters to store a data bit and also has a pass-through gate which is electrically connected to the two inverters for reading from and writing to the SRAM cell. Fig. Paragraph 3 has been simplified for the sake of clarity and a better understanding of the inventive concepts of the present disclosure. Additional features may be added to the SRAM cell 104, and some of the elements or features described below may be replaced, modified, or omitted in other embodiments of the SRAM cell 100.

[0026] The exemplary SRAM cell 100 comprises six transistors: a pass-through gate transistor PG-1, a pass-through gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-1. Thus, the exemplary SRAM cell 100 is referred to as a 6-transistor SRAM cell (6-T SRAM cell). The 6-T SRAM cell is used to illustrate and explain the features and elements, but does not in any way limit the embodiments or the appended claims. This non-restrictive embodiment can further be extended to SRAM cells comprising more than six transistors, such as an 8-T SRAM cell, a 10-T SRAM cell, and content-addressable memory cells (CAM cells).

[0027] Furthermore, the exemplary SRAM cell 100 is a single-port SRAM cell which has a write port, which is used to illustrate and explain the features / elements, but this does not in any way restrict the embodiments or the appended claims. This non-restrictive embodiment can further be extended to a multi-port SRAM cell, such as a two-port SRAM cell which has a write port and a read port.

[0028] During operation, the pass-through gate transistors PG-1 and PG-2 provide access to a memory section of SRAM cell 100, which contains a cross-coupled pair of inverters: a first inverter INV1 and a second inverter INV2. The first inverter INV1 has the pull-up transistor PU-1 and the pull-down transistor PD-1, and the second inverter INV2 has the pull-up transistor PU-2 and the pull-down transistor PD-2.

[0029] A gate of pull-up transistor PU-1 is located between a source (electrically connected to a voltage line, also known as the VDD line) and a first common drain (CD1), and a gate of pull-down transistor PD-1 is located between a source (electrically connected to an electrical ground line, also known as the VSS line) and the first common drain (CD1). A gate of pull-up transistor PU-2 is located between a source (electrically connected to the VDD line) and a second common drain (CD2), and a gate of pull-down transistor PD-2 is located between a source (electrically connected to the VSS line) and the second common drain (CD2).In some embodiments, the first common drain (CD1) is a memory node (SN) that stores data in true form, and the second common drain (CD2) is a memory node (SNB) that stores data in complementary form. The gate of pull-up transistor PU-1 and the gate of pull-down transistor PD-1 are connected to the second common drain (CD2), and the gate of pull-up transistor PU-2 and the gate of pull-down transistor PD-2 are connected to the first common drain (CD1). A gate of pass-through transistor PG-1 is located between a source (electrically connected to a bit line BL) and a drain that is electrically connected to the first common drain (CD1). A gate of pass-through transistor PG-2 is located between a source (electrically connected to a complementary bit line BLB) and a drain that is electrically connected to the second common drain (CD2).The gates of the pass-through gate transistors PG-1 and PG-2 are electrically connected to a word line WL. In some configurations, the pass-through gate transistors PG-1 and PG-2 provide access to the memory nodes SN and SNB during read and / or write operations. For example, the pass-through gate transistors PG-1 and PG-2 connect the memory nodes SN and SNB to the bit lines BL and BLB, respectively, in response to a voltage applied to the gates of the pass-through gate transistors PG-1 and PG-2 via the word lines WL.

[0030] When SRAM cell 100 is read, a positive voltage is applied to the word line WL, and the pass-through gate transistors PG-1 and PG-2 enable the connection of the bit lines BL and BLB to the memory nodes SN and SNB, and the reception of data from them. Unlike a dynamic memory cell or DRAM cell, an SRAM cell does not lose its stored state during a read operation, so no data "write-back" operation is required after a read. The bit lines BL and BLB form a complementary pair of data lines. As is known to trained professionals, these paired data lines can be connected to a differential read amplifier (not shown); and the differential voltage read from SRAM cells can be detected and amplified. The amplified detected signal, which has a logic-level voltage, can then be output as read data to other control circuits in the device.

[0031] In some embodiments, the pull-up transistors PU-1 and PU-2 are configured as p-type field-effect transistors (PFETs), and the pull-down transistors PD-1 and PD-2 are configured as n-type field-effect transistors (NFETs). In some implementations, the pass-gate transistors PG-1 and PG-2 are also configured as NFETs. Various NFETs and PFETs, such as fin-type FETs (FinFETs) or all-around gate FETs (GAA-FETs), can be implemented using appropriate technology.

[0032] Fig. Figure 4 shows a layout of 200 of the SRAM cell 100 (represented by a dashed box), whose circuit diagram is shown in Fig. 3 is shown, in accordance with various aspects of the present revelation. Fig. Section 4 has been simplified for the sake of clarity and a better understanding of the inventive concepts of the present disclosure. For better understanding of the presentation, the simplified layout 200, which is shown in Fig. Figure 4 shows, among other elements and features, a layout of basins, active areas, gate structures, source / drain contacts formed on source / drain areas, gate contacts formed on gate structures, and gate insulating elements in gate trenches (CMG trenches) cut into the metal, which "cut" an otherwise continuous gate structure into multiple segments. Depending on the context, the source / drain area(s) may refer individually or collectively to a source or a drain. Trained professionals should also recognize that Fig. Figure 4 shows only an exemplary layout of a 6-T SRAM bit cell for illustrative purposes. Additional elements may be added to the layout 200, and some of the elements or features described below may be substituted, modified, or omitted in other embodiments of the SRAM cell 100.

[0033] Further referring to Fig. The SRAM cell 100 has six transistors: a forward-gate transistor PG-1, a forward-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-1. Layout 200 thus represents a layout of a 6-T SRAM cell. The SRAM cell 100 has a region 314, which provides an n-well between region 316A and region 316B, each of which has a p-well (and together are referred to as region 316). The pull-up transistors PU-1 and PU-2 are arranged across region 314; the pull-down transistor PD-1 and the forward-gate transistor PG-1 are arranged across region 316A. and the pull-down transistor PD-2 and the pass-through gate transistor PG-2 are located above area 316B.In some implementations, the pull-up transistors PU-1, PU-2 are designed as PFETs, and the pull-down transistors PD-1, PD-2 as well as the pass-through gate transistors PG-1, PG-2 are designed as NFETs.

[0034] Each of the transistors PG-1, PG-2, PU-1, PU-2, PD-1, and PD-2 has an active region. In the illustrated embodiment, the SRAM cell has 100 active regions 320A, 320B, 320C, and 320D (collectively referred to as the active regions 320) arranged on a semiconductor substrate. The active regions 320 extend lengthwise along the X-direction and are arranged substantially parallel to each other. In some implementations, the active regions 320 are a portion of the semiconductor substrate (such as a portion of a material layer of the semiconductor substrate). For example, if the semiconductor substrate contains silicon, the active regions 320 have fins and project upwards and continuously from the semiconductor substrate, and the transistors PG-1, PG-2, PU-1, PU-2, PD-1, and PD-2 are FinFET transistors.Alternatively, in some implementations, the active regions 320 are defined in one or more semiconductor material layers arranged above the semiconductor substrate. For example, the active regions 320 may comprise a stack of nanostructures (nanowires or nanosheets) stacked vertically above the semiconductor substrate, and the transistors PG-1, PG-2, PU-1, PU-2, PD-1, and PD-2 are GAA transistors.

[0035] Different active regions in different transistors of the SRAM cell 100 can have the same width or different widths (for example, dimensions measured in the Y direction) to optimize device performance. In the illustrated embodiment, the active region 320A of the PD-1 and PG-1 transistors and the active region 320D of the PD-2 and PG-2 transistors have a first width, while the active region 320B of the PU-1 transistor and the active region 320C have a second width, which is smaller than the first width. The first and second widths are measured in the sections of the respective active regions below the gate structures 330. In other words, these sections of the active regions (from which the first and second widths are measured, respectively) are the channel regions (for example, the vertically stacked nanostructures of GAA devices) of the transistors.Since the PG-1 transistor and the PD-1 transistor (as well as the PG-2 transistor and the PD-2 transistor) are formed on the same active region, these two transistors have the same channel width. If the discharge metal in the 330 gate structures is also the same, the PG-1 transistor and the PD-1 transistor (as well as the PG-2 transistor and the PD-2 transistor) have essentially the same threshold voltage (Vt) and current-driving capabilities. Accordingly, the beta ratio would be 1. How the discharge metal in the respective gate structure of the PG-1 transistor (as well as the PG-2 transistor) can be adjusted separately to achieve a beta ratio greater than 1 will be described in more detail below.

[0036] Various gate structures (also referred to as gate stacks or simply gates) are arranged over the active regions 320, such as gate structures 330A, 330B, 330C, and 330D (collectively referred to as the gate structures 330). The gate structures 330 extend lengthwise along the Y-direction (for example, substantially perpendicular to the active regions 320). The gate structures 330 enclose at least portions of the active regions 320, arranged such that the gate structures are positioned between the respective source / drain regions of the active regions 320. Gate structure 330A is arranged over active region 320A; gate structure 330C is arranged over active regions 320A, 320B, and 320C. The gate structure 330B is arranged above the active areas 320B, 320C, 320D; and the gate structure 330D is arranged above the active area 320D.A gate of the forward-gate transistor PG-1 is formed from the gate structure 330A, a gate of the pull-down transistor PD-1 is formed from the gate structure 330C, a gate of the pull-up transistor PU-1 is formed from the gate structure 330C, a gate of the pull-up transistor PU-2 is formed from the gate structure 330B, a gate of the pull-down transistor PD-2 is formed from the gate structure 330B and a gate of the forward-gate transistor PG-2 is formed from the gate structure 330D.

[0037] A gate via 360A (also referred to as gate contact 360A) electrically connects a gate of the forward-gate transistor PG-1 (formed by the gate structure 330A) to a word line WL, and a gate via 360L (also referred to as gate contact 360L) electrically connects a gate of the forward-gate transistor PG-2 (formed by the gate structure 330D) to the word line WL. A source / drain contact 360K electrically connects a drain region of the pull-down transistor PD-1 (formed on the active region 320A (which may have epitaxial n-source / drain features) and a drain region of the pull-up transistor PU-1 (formed on the active region 320B (which may have epitaxial p-source / drain features)) such that a common drain of the pull-down transistor PD-1 and the pull-up transistor PU-1 forms a storage node SN.A gate via 360B (also referred to as gate contact 360B) electrically connects a gate of the pull-up transistor PU-2 (formed by the gate structure 330B) and a gate of the pull-down transistor PD-2 (also formed by the gate structure 330B) to the memory node SN. A source / drain contact 360C electrically connects a drain region of the pull-down transistor PD-2 (formed on the active region 320D (which may exhibit epitaxial n-source / drain features)) and a drain region of the pull-up transistor PU-2 (formed on the active region 320C (which may exhibit epitaxial p-source / drain features)) such that a common drain of the pull-down transistor PD-2 and the pull-up transistor PU-2 forms a memory node SNB.A gate via 360D (also called gate contact 360D) electrically connects a gate of the pull-up transistor PU-1 (formed by the gate structure 330C) and a gate of the pull-down transistor PD-1 (also formed by the gate structure 330C) to the storage node SNB.

[0038] A source / drain contact 360E and a source / drain contact via 380E, which is located on it, electrically connect a source region of the pull-up transistor PU-1 (formed on the active region 320B (which may have epitaxial p-source / drain features)) to a supply voltage VDD, and a source / drain contact 360F and a source / drain contact via 380F, which is located on it, electrically connect a source region of the pull-up transistor PU-2 (formed on the active region 320C (which may have epitaxial p-source / drain features)) to the supply voltage VDD.A source / drain contact 360G and a source / drain contact via 380G, which is located on it, electrically connect a source region of the pull-down transistor PD-1 (formed on the active region 320A (which may have epitaxial n-source / drain features)) to a ground voltage VSS, and a source / drain contact 360H and a source / drain contact via 380H electrically connect a source region of the pull-down transistor PD-2 (formed on the active region 320D (which may have epitaxial n-source / drain features)) to the ground voltage VSS.The source / drain contact 360G, the source / drain contact via 380G, the source / drain contact 360H and the source / drain contact via 380H can be component-level contacts and contact vias shared by adjacent SRAM cells 100 (for example, four SRAM cells 100 located at the same corner can share a source / drain contact 360G and a source / drain contact via 380G that lands on it). A source / drain contact 360I electrically connects a source region of the pass-through gate transistor PG-1 (formed on the fin 320A (which may have epitaxial n-source / drain features)) to a bit line BL, and a source / drain contact 360J electrically connects a source region of the pass-through gate transistor PG-2 (formed on the fin 320D (which may have epitaxial n-source / drain features)) to a complementary bit line BLB.In this context, a source / drain contact that electrically connects a source area can also be referred to as a source contact, and a source / drain contact that electrically connects a drain area can also be referred to as a drain contact.

[0039] Further referring to Fig. 4. The SRAM cell 100 further comprises a plurality of dielectric elements extending lengthwise along the X-direction, including dielectric elements 350A, 350B, 350C, and 350D (which together are referred to as dielectric elements 350 or insulating elements 350). In the illustrated embodiment, dielectric element 350B is arranged between active area 320A and active area 320B and is in contact with gate structure 330A and gate structure 330B. Dielectric element 350B divides an otherwise continuous gate structure into two insulated segments, corresponding to gate structure 330A and gate structure 330B. The dielectric element 350C is located between the active area 320C and the active area 320D and is adjacent to the gate structure 330C and the gate structure 330D.The dielectric element 350C divides an otherwise continuous gate structure into two insulated segments, corresponding to gate structure 330C and gate structure 330D. The dielectric element 350A is located near one edge of the SRAM cell 100 and abuts gate structure 330C. The dielectric element 350A separates gate structure 330C from an adjacent gate structure of a neighboring SRAM cell. The dielectric element 350D is located near another edge of the SRAM cell 100 and abuts gate structure 330B. The dielectric element 350D separates gate structure 330B from an adjacent gate structure of a neighboring SRAM cell. Each of the dielectric elements 350 is formed by filling a corresponding CMG trench at the position of the dielectric element. The dielectric elements 350 are also known as CMB elements.

[0040] In the illustrated embodiment, from a top view, the CMG element 350B is arranged over an interface between the n-tub region 314 and the p-tub region 316A, the CMG element 350C is arranged over an interface between the n-tub region 314 and the p-tub region 316B, the CMG element 350A is arranged entirely over a p-tub region which includes the p-tub region 316A, and the CMG element 350D is arranged entirely over a p-tub region which includes the p-tub region 316B.

[0041] Fig. Figure 5 represents a layout 500-1 of a section of the component layer DL and the front-facing multilayer interconnect structure FMLI of an SRAM arrangement 400 in accordance with the present disclosure. Referring to Fig. In the 5th dimension, four SRAM cells are arranged in the X and Y directions to form a 2 x 2 array of SRAM cells. Each of the SRAM cells in the array can have the layout of SRAM cell 100 as shown in the diagram. Fig. Figure 4 shows the use of the SRAM cells shown. In the illustrated embodiment, two adjacent SRAM cells in the X-direction are line-symmetric with respect to an intermediate common boundary, and two adjacent SRAM cells in the Y-direction are line-symmetric with respect to an intermediate common boundary. Fig. Section 5 has been simplified for clarity in order to better illustrate the inventive concepts of the present disclosure. For example, certain elements which are in Fig. Figure 4 shows, for example, well areas, CMG elements and certain gate vias which are not intended for pass-through gate transistors, in Fig. Number 5 has been omitted. Furthermore, reference numbers are used for easier understanding. Fig. 4 in Fig. 5 is repeated, however, reference numbers for source / drain contacts have also been omitted for the sake of clarity.

[0042] For ease of reference, a column is defined as extending in the X-direction of an array, and a row as extending in the Y-direction of an array. As shown above, adjacent cells in the array are mirror images along a common boundary between the adjacent cells. Some active areas in an SRAM cell may extend through multiple SRAM cells in a column. Fig. 5. The active region 320A for transistors PG-1 and PD-1 in one SRAM cell extends into the adjacent SRAM cell as the active region for transistors PD-1 and PG-1 in the adjacent SRAM cell. The active region 320B for transistor PU-1 in one SRAM cell extends into the adjacent SRAM cell as the active region for transistor PU-1 in the adjacent SRAM cell. The active region 320D for transistors PG-2 and PD-2 in one SRAM cell extends into the adjacent SRAM cell as the active region for transistors PD-2 and PG-2 in the adjacent SRAM cell. Similarly, certain gate structures can be shared by multiple SRAM cells in a row without being interrupted by a CMG element. For example, the gate structure 330A for transistor PG-1 in one SRAM cell extends into the adjacent SRAM cell as the gate structure for transistor PG-1 in the adjacent SRAM cell.The gate structure 330D for the transistor PG-2 in one SRAM cell extends into the adjacent SRAM cell as the gate structure for the transistor PG-2 in the adjacent SRAM cell.

[0043] Similarly, the source / drain contacts and gate vias located at the boundaries of the SRAM cells can be shared by adjacent SRAM cells. For example, gate via 360A, located at the boundary of two SRAM cells in the same row, can be shared by two adjacent transistors PG-1 of the adjacent SRAM cells, and gate via 360L, located at the boundary of two SRAM cells, can be shared by two adjacent transistors PG-2 of the adjacent SRAM cells. It should be noted that some alternative layouts may have a gate via that is assigned to a corresponding gate of the respective forward-gate transistor. Fig. Figure 6 represents an alternative layout 500-2 of a section of the component layer DL and the front-facing multilayer interconnect structure FMLI of an SRAM array 400. Many aspects of layout 500-2 are the same as those in layout 500-1. One difference is that in layout 500-2, each of the forward-gate transistors PG-1 has its own gate via 360A, and each of the forward-gate transistors PG-2 has its own gate via 360L, without sharing it with any other gate extending from an adjacent SRAM cell.

[0044] In SRAM device design, the power rails and signal lines are not necessarily all located on the front of the integrated circuit structure, but can be distributed across both the front and back sides. For example, the integrated circuit structure may include a front-side multilayer interconnect (FMLI) and a back-side multilayer interconnect (BMLI), located on the front and back sides respectively, which are configured to connect various components such as pull-up transistors, pull-down transistors, and pass-through gate transistors to form the SRAM cells.The design takes into account various factors and parameters, including the sizes of different conductive elements, the packing density, the resistance of the conductive elements, the parasitic capacitances between adjacent conductive elements, the superposition displacement, and machining distances. In the embodiments described below, while one section of the power rails and signal lines is formed on the front of the SRAM device, another section is formed on the rear of the SRAM device. For example, the gate vias for the pass-through transistors can also be formed as rear-side gate vias on the back of the SRAM cells.

[0045] The following refers to Fig. 7. Fig. Figure 7 shows a layout 500-3 of a section of the rear-side multilayer interconnect structure BMLI of the SRAM arrangement 400, which has a rear-side via zero plane (BVo plane). For clarity and to better understand the inventive concepts of the present disclosure, only the rear-side gate vias are shown in the BVo plane, which terminate on the back side of the gate structures of the pass-through gate transistors PG-1 and PG-2. Meanwhile, active areas, gate structures, and source / drain contacts are shown as in Fig. 5 or Fig. Figure 6, which are located on the front of the SRAM array 400, are superimposed in layout 500-3 for greater clarity. Gate vias 360A and 360L as shown in Fig. 5 or Fig. Figure 6, which forms part of the front-facing multilayer interconnect structure FMLI, are shown in Fig. However, number 7 has been omitted.

[0046] The back-side gate via B360A is formed directly below and in direct contact with the gate structure of the forward-gate transistor PG-1, and the back-side gate via B360L is formed directly below and in direct contact with the gate structure of the forward-gate transistor PG-2. Specifically, as shown in Fig. As shown in Figure 7, the rear gate via B360A, which is located at the boundary of two SRAM cells in the same row, is shared by two adjacent forward gate transistors PG-1 of the adjacent SRAM cells, and the rear gate via B360L, which is located at the boundary of two SRAM cells in the same row, is shared by two adjacent forward gate transistors PG-2 of the adjacent SRAM cells.

[0047] Likewise, as above with reference to Fig. As discussed in section 6, some alternative layouts may feature a rear-side gate via, which is assigned to each corresponding gate of the relevant pass-through gate transistor. Fig. Figure 8 shows such an alternative layout 500-4 of a section of the component layer DL and the backside multilayer interconnect structure BMLI of the SRAM array 400. Many aspects of layout 500-4 are the same as those in layout 500-3. One difference is that in layout 500-4, each of the forward-gate transistors PG-1 has its own backside gate via B360A, which is located underneath it, and each of the forward-gate transistors PG-2 has its own backside gate via B360L, which is located underneath it, without sharing it with any other gate extending from an adjacent SRAM cell.

[0048] It should be noted that, depending on certain design considerations, one of the front-side multilayer interconnect structures FMLI, shown in layouts 500-1 and 500-2 respectively, can be used in an SRAM device. Likewise, one of the back-side multilayer interconnect structures BMLI, shown in layouts 500-3 and 500-4 respectively, can also be used independently in the SRAM device. In other words, in an example where one starts with a region that uses gate structure 330A shared by two adjacent forward-gate transistors PG-1, eight different configurations can be implemented based on design considerations: one configuration can have a shared front-side gate via 360A and a shared back-side gate via B360A;A second design may have a shared front-side gate via 360A and two individual back-side gate vias B360A; a third design may have two individual front-side gate vias 360A and a shared back-side gate via B360A; a fourth design may have two individual front-side gate vias 360A and two individual back-side gate vias B360A; a fifth design may have a shared front-side gate via 360A without a back-side gate via; a sixth design may have two individual front-side gate vias 360A without back-side gate vias; a seventh design may have a shared back-side gate via B360A without a front-side gate via;and an eighth design may have two shared back-side gate vias B360A without a front-side gate via.

[0049] Since the forward-gate transistors have associated front- and / or back-side gate vias for electrical connection to word lines, while this is not the case for the pull-down transistors, the creation of these gate vias for the forward-gate transistors provides a way to separately increase the threshold voltage of the forward-gate transistors, thereby achieving a beta ratio greater than 1. The manufacturing process is now described in more detail with reference to the following figures. In this context, Fig. 9 A flowchart illustrating a method 600 for forming a semiconductor device from a workpiece (a work-in-progress or WIP structure) in accordance with embodiments of the present disclosure. Method 600 is only an example and is not intended to limit the present disclosure in any way to what is explicitly shown in method 600. Additional steps may be provided before, during, and after method 600, and some of the described steps may be substituted, omitted, or postponed for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Method 600 is subsequently described in conjunction with the Fig. 10 - 44 described which partial cross-sectional views of a workpiece 700 at different stages of manufacturing in accordance with embodiments of the method 600 of Fig. 9 are. Since the workpiece 700 under processing is being processed into a semiconductor device or a semiconductor structure, the workpiece 700 can be referred to herein as a semiconductor device (a semiconductor component) 700 or a semiconductor structure 700, depending on the context.

[0050] Referring to the Fig. 9 and Fig. 10. Method 600 comprises a block 602 in which a stack 704 of alternating semiconductor layers is formed over the workpiece 700. As in Fig. As shown in Figure 10, workpiece 700 has a substrate 702. In some embodiments, the substrate 702 can be a semiconductor substrate, such as a silicon substrate (Si substrate). Depending on the design requirements, the substrate 702 can have various doping configurations, as is known in the art. In embodiments where the semiconductor device is of type p, an n doping profile (i.e., a well of type n or n-well) can be formed on the substrate 702. In some implementations, the n dopant for forming the n-well can contain phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor device is of type n, a p doping profile (i.e., a well of type p or p-well) can be formed on the substrate 702. In some reactions, the p-doping agent for forming the p-well can contain boron (B) or gallium (Ga).The appropriate doping can involve ion implantation of dopants and / or diffusion processes. Substrate 702 can also contain other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon-germanium (SiGe), germanium-tin (GeSn), or diamond. Alternatively, substrate 702 can contain a compound semiconductor and / or an alloy semiconductor. Furthermore, substrate 702 can optionally have an epitaxial layer (epi-layer), can be stressed to improve performance, can have a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or can have other suitable enhancement features.

[0051] In some embodiments, the stack 704 above the substrate 702 has channel layers 708 of a first semiconductor composition with sacrificial layers 706 of a second semiconductor composition inserted between them. The channel layers 708 can also be said to be inserted between the sacrificial layers 706. The first semiconductor composition and the second semiconductor composition can be different. In some embodiments, the sacrificial layers 706 contain silicon germanium (SiGe) or germanium tin (GeSn), and the channel layers 708 contain silicon (Si). It should be noted that three (3) layers of the sacrificial layers 706 and three (3) layers of the channel layers 708 are arranged alternately, as shown in Fig. Figure 10 is shown, this being solely for illustrative purposes and in no way intended to limit what is stated in the claims. It is therefore understood that any number of epitaxial layers can be formed in the stack 704. The number of layers depends on the desired number of channel elements for the semiconductor device 700. In some embodiments, the number of channel layers 708 is between 2 and 10.

[0052] The sacrificial layers 706 and the channel layers 708 in the stack 704 can be deposited using a molecular beam epitaxy (MBE) process, a vapor deposition (VDE) process, and / or other suitable epitaxial growth processes. As stated above, in at least some examples, the sacrificial layers 706 have an epitaxially grown silicon-germanium (SiGe) layer, and the channel layers 708 have an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layers 706 and the channel layers 708 are essentially dopant-free (i.e., they have an extrinsic dopant concentration of approximately 0 atoms / cm²). 3 up to approximately 1 × 10 17 atoms / cm² 3 (on), for example, if no deliberate doping is carried out during the epitaxial growth processes for stack 704.

[0053] Referring to the Fig. 9 and Fig. In 11, the process 600 comprises a block 604 in which fin-shaped structures 712 are formed from the stack 704 and the substrate 702. In some implementations, the two fin-shaped structures 712 represent, as in Fig. Figure 11 shows the two active areas 320A (or 320D) in the Fig. 5-8. To structure the stack 704, a hard mask layer can be applied over the stack 704 to form an etching mask. The hard mask layer can be a single layer or a multiple layer. For example, the hard mask layer can have a contact oxide layer and a contact nitride layer arranged over the contact oxide layer. The fin-shaped structure 712 can be structured from the stack 704 and the substrate 702 using a lithography process and an etching process. The lithography process can include photoresist coating (for example, spin coating), soft firing, mask alignment, exposure, post-exposure firing, photoresist development, rinsing, drying (for example, spin drying and / or hard firing), other suitable lithography techniques, and / or combinations thereof.In some embodiments, the etching process may include dry etching (for example, RIE etching), wet etching, and / or other etching methods. As in . Fig. As shown in Figure 11, the etching process at block 604 forms trenches that extend vertically through the stack 704 and a section of the substrate 702. The trenches define the fin-shaped structures 712. In some implementations, double- or multiple-structuring processes can be used to define fin-shaped structures that, for example, have spacing dimensions smaller than those achievable using a simple, direct photolithography process. For example, in one embodiment, a layer of material is formed over a substrate and structured using a photolithography process. Spacing elements are formed along the structured layer of material using a self-aligning process.The material layer is then removed, and the remaining spacers or mandrels can be used to structure the fin-shaped structure 712 by etching the stack 704 and a section of the substrate 702. As shown in . Fig. As shown in Figure 11, the fin-shaped structure 712, which includes the sacrificial layers 706 and the channel layers 708, extends vertically along the Z-direction and lengthwise along the X-direction. Each of the fin-shaped structures 712 has a base fin structure 712B structured from the substrate 702 and the structured stacks 704 arranged directly above the base fin structure 712B.

[0054] Referring to the Fig. 9 and Fig. 11. Method 600 comprises a block 606 in which an insulating element 714 is formed around a base fin structure 712B of the fin-shaped structures 712. In some embodiments, which are described in Fig. As shown in Figure 11, the insulating element 714 is arranged on the side walls of the base fin structure 712B. In some embodiments, the insulating element 714 can be formed in the trenches to insulate the fin-shaped structures 712 from an adjacent fin-shaped structure. The insulating element 714 can also be referred to as a flat trench insulating element (STI element) 714. By way of example, in some embodiments, a dielectric layer is first applied over the substrate 702, with the trenches being filled with the dielectric layer. In some embodiments, the dielectric layer can comprise silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a dielectric with a low K-value, combinations thereof, and / or other suitable materials.In various examples, the dielectric layer can be applied by a CVD process, a subatmospheric CVD process (SACVC process), a flowable CVD process (FCVD process), a spin coating process, and / or another suitable process. The applied dielectric material is then thinned and planarized, for example, by a chemical-mechanical polishing (CMP) process. The planarized dielectric layer is then further deepened or retracted by a dry etching process, a wet etching process, and / or a combination thereof to form the STI elements 714, which are described in [reference missing]. Fig. Figure 11 shows that the fin-shaped structure 712 protrudes beyond the STI element 714 after deepening, while the base fin structure 712B is embedded or “buried” in the STI element 714.

[0055] Referring to the Fig. 9 and Fig. In section 12, the method 600 comprises a block 608 in which a hard mask layer 715 is formed over the STI element 714 and around an upper portion of the base fin structure 712B. The composition of the hard mask layer 715 differs from the composition of the STI element 714 to ensure that each of these two elements can be selectively etched, essentially without damaging the other. In some embodiments, the STI element 714 contains an oxide, and the hard mask layer 715 contains a nitride (for example, silicon nitride) or an oxynitride (for example, silicon oxynitride). By way of example, in some embodiments, a nitride-containing material is first applied over the STI element 714 to fill the grooves with nitride.In various examples, the nitride-containing material can be applied by a CVD process, a subatmospheric CVD process (SACVC process), a flowable CVD process (FCVD process), a rotational coating process, and / or another suitable process. The applied nitride-containing material is then thinned and planarized, for example, by a chemical-mechanical polishing (CMP) process. The planarized nitride-containing material is then further recessed or retracted by a dry etching process, a wet etching process, and / or a combination thereof to form the hard mask layer 715. The fin-shaped structure 712 protrudes above the hard mask layer 715 after recession, while the base fin structure 712B is embedded or "buried" in the combination of the STI element 714 and the hard mask layer 715.

[0056] Referring to the Fig. In sections 9 and 13-14, the process 600 comprises a block 610 in which a dummy gate stack 720 is formed above a channel area 712C of the fin-shaped structure 712. The dummy gate stack 720 serves as a placeholder for carrying out various processes and is to be removed and replaced by a functional gate structure. In some implementations, the functional gate structure to be formed is gate structure 330A (or gate structure 330D) in the Fig. 5 - 8. In some embodiments, which are in Fig. 14, which shows a cross-sectional view cut along line A - A in Fig. As shown in Figure 13, the dummy gate stack 720 is formed above the fin-shaped structure 712, and the fin-shaped structure 712 can be divided into channel regions 712C, which are arranged below the dummy gate stacks 720, and source / drain regions 712SD, which are not arranged below the dummy gate stacks 720. The channel regions 712C are arranged adjacent to the source / drain regions 712SD. As shown in Fig. As shown in Figure 14, the channel area 712C is arranged along the X direction between two source / drain areas 712SD.

[0057] The formation of the dummy gate stack 720 can include the deposition of layers in the dummy gate stack 720 and the structuring of these layers. Referring to Fig. 13. A dielectric dummy layer 716, a dummy electrode layer 718, and a hard mask layer can be applied to the top surface of the gate 722, covering the entire workpiece 700. The dielectric dummy layer 716 can be formed on the fin-shaped structure 712 using a chemical vapor deposition (CVD) process, an aqueous local deposition (ALD) process, an oxygen plasma oxidation (OSA) process, or other suitable processes. In some cases, the dielectric dummy layer 716 may contain silicon oxide. Subsequently, the dummy electrode layer 718 can be applied over the dielectric dummy layer 716 using a CVD process, an ALD process, or other suitable processes. In some cases, the dummy electrode layer 718 may contain polysilicon.For structuring purposes, the hard mask layer on the top of gate 722 can be applied to the dummy electrode layer 718 using a CVD process, an ALD process, or other suitable processes. Then, the hard mask layer on the top of gate 722, the dummy electrode layer 718, and the dielectric dummy layer 716 can be structured to form the dummy gate stack 720, as shown in [Figure]. Fig. Figure 13 shows the structuring process. The structuring process may, for example, comprise a lithography process (e.g., photolithography or electron beam lithography) and an etching process. The lithography process may further comprise photoresist coating (e.g., spin coating), soft firing, mask alignment, exposure, post-exposure firing, photoresist development, rinsing, drying (e.g., spin drying and / or hard firing), other suitable lithography techniques, and / or combinations thereof. The photolithography process forms a structured photoresist layer. The structured photoresist layer is then used in the etching process as an etching mask to structure the hard mask layer on the top of gate 722, the dummy electrode layer 718, and the dielectric dummy layer 716. In some embodiments, the etching process may comprise dry etching (e.g., RIE etching), wet etching, and / or other etching methods.In some embodiments, the hard mask layer on the top of the gate 722 can have a silicon oxide layer 723 and a silicon nitride layer 724 over the silicon oxide layer 723. As shown in . Fig. As shown in Figure 14, the dummy gate stack 720 is structured such that it is arranged only over the channel area 712C, but not over the source / drain area 712SD.

[0058] Referring to the Fig. 9 and Fig. In Section 15, the method 600 comprises a block 612 in which a gate spacer layer 726 is applied over the workpiece 700 and also over the dummy gate stack 720. In some embodiments, the gate spacer layer 726 is applied conformally over the workpiece 700, as well as over the top and side surfaces of the dummy gate stack 720. The term "conformally" can be used here to simply describe a layer that has a substantially uniform thickness over different areas. The gate spacer layer 726 can be a single layer or a multiple layer. The at least one layer in the gate spacer layer 726 can contain silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride.The gate spacer layer 726 can be applied over the dummy gate stack 720 using processes such as a CVD process, a subatmospheric CVD process (SACVC process), an ALD process or any other suitable process.

[0059] Referring to the Fig. 9 and Fig. In section 16, the process 600 comprises a block 614 in which source / drain regions 712SD of the fin-shaped structure 712 are anisotropically deepened to form source / drain trenches 728. The anisotropic etching can include dry etching or a suitable etching process that etches the source / drain regions 712SD and a section of the substrate 202. The resulting source / drain trench 728 extends vertically through the depth of the stack 704 and partially into the substrate 702. An example dry etching process for Block 614 can employ an oxygen-containing gas, a fluorine-containing gas (for example, CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (for example, Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (for example, HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. As in Fig. As shown in Figure 16, the source / drain areas 712SD of the fin-shaped structure 712 are deepened to expose sidewalls of the sacrificial layers 706 and the channel layers 708. Since the source / drain trenches 728 extend under the stack 704 into the substrate 702, the source / drain trenches 728 have lower surfaces and lower sidewalls that are defined in the substrate 702.

[0060] Referring to the Fig. 9 and Fig. In the process 600, a block 616 is included in which the majority of channel layers 708 in the channel regions are released as channel elements 7080. Depending on the design, the channel elements 7080 can take the form of nanowires, nanosheets, or other nanostructures. After the formation of the source / drain trench 728, the sacrificial layers 706 between the channel layers 708 in the channel region 712C are selectively removed. The selective removal of the sacrificial layers 706 releases the channel layers 708 to form the channel elements 7080, as shown in Fig. Figure 17 shows that the selective removal of the sacrificial layers 706 creates spaces between and around adjacent channel elements 7080. The selective removal of the sacrificial layers 706 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective dry etching process may involve the use of one or more fluorine-based etchants, such as fluorine gas or fluorocarbons. An exemplary selective wet etching process may involve APM etching (for example, using an ammonium hydroxide-hydrogen peroxide-water mixture).

[0061] Referring to the Fig. 9 and Fig. In section 18, process 600 comprises a block 618 in which a dielectric dummy layer 730 is formed around the channel elements 7080 and over the source / drain grooves 728. The dummy layer 730 can contain silicon oxide and can be applied using plasma-enhanced chemical vapor deposition (PECVD) or ALD. The dummy layer 730 fills the space between the channel elements 7080 and covers the end sidewalls of the channel elements 7080. Furthermore, the dummy layer 730 is in direct contact with a sidewall of the gate spacer layer 726 and an upper surface of the substrate 702.

[0062] Referring to the Fig. 9 and Fig. In section 19, the method 600 comprises a block 620 in which internal spacer recesses 732 are formed. The dummy layers 730 are selectively and partially recessed to form internal spacer recesses 732, while the gate spacer layer 726, the dummy gate stack 720, the exposed portion of the substrate 702, and the channel layers 708 remain essentially unetched. In an embodiment in which the channel layers 708 consist essentially of silicon (Si) and the dummy layers 730 are formed of silicon oxide, the selective recessing of the dummy layer 730 can be carried out using a selective wet etching process or a selective dry etching process. An example of a selective dry etching process may include the use of carbon tetrafluorocarbon (CF4), nitrogen trifluoride (NF3), hydrogen (H2), or a mixture thereof.An example of a selective wet etching process may include the use of hydrofluoric acid, ammonium fluoride, or a mixture thereof.

[0063] Referring to the Fig. 9 and Fig. In Figure 20, Method 600 comprises a block 622 in which an inner spacer layer 734 is deposited over the inner spacer recesses 732. The composition of the inner spacer layer 734 differs from the composition of the dielectric dummy layer 730 to ensure that each of these two elements can be selectively etched, essentially without damaging the other. In some embodiments, the inner spacer layer 734 may contain silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon nitride (SiN), silicon oxycarbide (SiOC), or silicon oxynitride (SiON). In some implementations, the inner spacer layer 734 may be deposited using CVD or ALD.

[0064] Referring to the Fig. 9 and Fig. In Figure 21, the method 600 comprises a block 624 in which the inner spacer layer 734 is back-etched to form inner spacers 736 over the inner spacer recesses 732. In some embodiments, the back-etching of block 624 may involve the use of a dry etching process, such as a reactive ion etching (RIE) process assisted by plasma. An example of a dry etching process may involve the use of boron trichloride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), methane (CH4), nitrogen trifluoride (NF3), carbon tetrafluorocarbon (CF4), sulfur hexafluoride (SF6), nitrogen (N2), or a combination thereof. In the illustrated embodiment, the inner spacers 736 extend laterally to a position directly below the dummy gate stack 720.Alternatively, the inner spacer elements 736 can essentially remain below the gate spacer layer 726 without extending to a position directly below the dummy gate stack 720.

[0065] Referring to the Fig. 9 and Fig. In Figure 22, the process 600 comprises a block 628 in which a source / drain element 750 is formed above the source / drain region 212SD. Although not explicitly shown, the process 600 may include a cleaning process to clean the surfaces of the workpiece 700 before any of the epitaxial layers are formed. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, the wet cleaning may include the use of a mixture of deionized water (DI water), ammonium hydroxide, and hydrogen peroxide; a mixture of DI water, hydrochloric acid, and hydrogen peroxide; SPM (a sulfur peroxide mixture); and / or hydrofluoric acid for oxide removal. The dry cleaning process may include treatment with helium (He) and hydrogen (H2). The hydrogen treatment may convert silicon on the surface to silane (SiH4), which can be pumped out for removal.

[0066] In some embodiments, a source / drain element 750 has a lower epitaxial element 752 and a main epitaxial element 754 above the lower epitaxial element 752. The source / drain element 750 can be of type n or type p. In particular, when the source / drain element 750 is part of the pass-through gate transistors PG-1 and PG-2, as in Fig. As shown in Figures 5-8, the source / drain element 750 can be of type n. If the source / drain element 750 is of type n, the lower epitaxial element 752 can contain undoped silicon (Si) or undoped silicon germanium (SiGe), and the main epitaxial element 754 can contain silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. If the source / drain element 750 is of type p, the lower epitaxial element 752 can contain undoped silicon (Si) or undoped silicon germanium (SiGe), and the main epitaxial element 754 can contain silicon germanium (SiGe) and a p-type dopant, such as boron (B), boron difluoride (BF₂), or a combination thereof. As used herein, undoped semiconductor material is considered undoped if it has not been intentionally doped.In some alternative embodiments, the lower epitaxial element 752 can contain a counter-doper to reduce the input into the base substrate 702. For example, the lower epitaxial element 752 in the n-source / drain element 750 can contain a p-type dopant, such as boron (B). In another example, the lower epitaxial element 752 in the p-source / drain element 750 can contain an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). The source / drain element 750 can be formed using vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE). Doping of the source / drain elements 750 can be achieved by in-situ doping.

[0067] Referring to the Fig. In Figures 1 and 23-28, the process 600 comprises a block 630 in which the dummy gate stack 720 and the dummy layer 730 are replaced by a gate structure 760 (also referred to as a metal gate structure 760). Operations at block 630 can include the application of a contact etch stop layer (CESL) 756 over the source / drain elements 750 (shown in Figure 1). Fig. 23), the application of a dielectric intermediate layer 758 over the CESL 756 (shown in Fig. 23), removing the dummy gate stack 720 (shown in Fig. 24), the removal of the dummy layer 730 (shown in Fig. 25 and Fig. 26) and the application of gate structure 760, so that each of the channel elements 7080 (shown in the Fig. 27 and Fig. 28) envelop, encompass. Referring to Fig. 23. The CESL 756 is deposited over the workpiece 700, as well as over the source / drain element 750. The CESL 756 can contain silicon nitride or aluminum nitride. In some embodiments, the CESL 756 can be deposited using CVD or atomic layer deposition (ALD). Subsequently, the ILD layer 758 is deposited over the CESL 756. In some embodiments, the ILD layer 758 contains materials such as tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass, or doped silicon oxide, such as boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 758 can be deposited using CVD, flowable CVD (FCVD), spin coating, or another suitable deposition technique.After the application of the ILD layer 758, the workpiece 700 can be planarized by a planarization process to expose the dummy gate stack 720. The planarization process can, for example, include a chemical-mechanical planarization process (CMP process). Exposing the dummy gate stack 720 allows for its removal. The removal of the dummy gate stack 720 can involve one or more etching processes that are selective for the material of the dummy gate stack 720. For example, the removal of the dummy gate stack 720 can be performed using selective wet etching, selective dry etching, or a combination thereof that is selective for the dummy gate stack 720.

[0068] After removal of the dummy gate stack 720, the dummy layer 730 in channel area 712C is exposed. A separate etching process can be performed to selectively remove the dummy layer 730 in channel area 712C. For example, a selective wet etching process or a selective dry etching process can be performed to remove the dummy layer 730. An example of a selective wet etching process might involve the use of dilute hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). An example of a selective dry etching process might involve the use of anhydrous hydrogen fluoride vapor (HF vapor), trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF6), sulfur hexafluoride (SF6), or a combination thereof.The targeted etching of the dummy layer 730 etches the channel elements 7080 at a significantly lower etch rate, thus preserving the integrity of the channel elements 7080. The hard mask layer 715 also protects the STI element 714 from etch loss during the removal of the dummy layer 730. After the targeted removal of the dummy layer 730, the channel elements 7080 in channel area 712C are again exposed, as shown in the [reference]. Fig. 25 and Fig. 26 shown.

[0069] After the channel elements 7080 are released, the gate structure 760 is formed to enclose each of the channel elements 7080, as shown in the Fig. 27 and Fig. 28 shown. The gate structure 760 has a dielectric gate layer 762, which faces the channel elements 7080, and the substrate 702 in the channel region 712C, as well as a gate electrode layer 764 above the dielectric gate layer 762.

[0070] The dielectric gate layer 762 can have an interface layer and a high-K dielectric layer above the interface layer. The interface layer can contain a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or another suitable process. The high-K dielectric layer can contain a high-K dielectric material such as hafnium oxide.Alternatively, the high K-value dielectric layer can contain other high K-value dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or another suitable material. The high K-value dielectric layer can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The dielectric gate layer 762 also covers the sidewalls of the inner spacer elements 736.

[0071] The gate electrode layer 764 of the gate structure 760 can have a multilayer structure, such as various combinations of a metal layer with a selected work function to improve device performance (referred to as the work function metal layer (WFM layer)), a lining layer, a wetting layer, an adhesion layer, a metal alloy, or a metal silicide. For example, the gate electrode layer 766 can contain titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metallic materials or a combination thereof.In various embodiments, the gate electrode layer 764 can be formed by ALD, PVD, CVD, E-beam evaporation, or another suitable process. In various embodiments, a CMP process can be performed to remove excess metal, providing a substantially planar top surface of the gate structure 760. The gate structure 760 has sections arranged between channel elements 7080 in the channel region 712C. In some embodiments, the gate structure 760 can be an n-gate structure or a p-gate structure. The n-gate structure has an n-exit metal layer arranged closer to the channel elements 7080. The p-gate structure has a p-exit metal layer arranged closer to the channel elements 7080. In some implementations, the Gate Structure 760 is an n-Gate structure, which replaces the Gate Structure 330A (or the Gate Structure 330D) in the . Fig. 5 - 8 represents and has an n-WFM layer that envelops each of the 7080 channel elements.

[0072] Referring to the Fig. 9 and Fig. 29 The method 600 comprises a block 632 in which one or more dielectric layers are formed as part of a front-side multilayer interconnect structure FMLI over the gate structure 760. In the illustrated embodiment, an etch stop layer (ESL) 768 is applied over the gate structure 760, an intermediate dielectric layer (ILD) 770 is applied over the ESL 768, an ESL 772 is applied over the ILD 770, and an ILD 774 is applied over the ESL 772.Each of the ESLs 768 and 772 may contain silicon carbide, silicon oxynitride, silicon carbonitride or the like, and be formed by CVD, PVD, ALD or other suitable deposition processes; each of the ILDs 770 and 774 may contain a material selected from the group comprising PSG, BSG, PBSG, FSG, TEOS and other non-porous dielectric materials with low K-value, and be formed by flowable CVD, PE-CVD, LP-CVD, spin coating or other suitable deposition processes.

[0073] Referring to the Fig. In sections 9 and 30-31, process 600 comprises a block 634 in which a three-layer resist layer 776 is formed over the ILD 774 and then structured to form a gate via opening 784. The three-layer resist layer 776 has a bottom layer 778, a middle layer 780, and an top layer 782. The bottom layer 778 can be a bottom antireflective coating (BARC). The bottom layer 778 can contain organic materials. The middle layer 780 can be formed from or contain an inorganic material, which may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The top layer 782 is a photosensitive material. The middle layer 780 exhibits high etch selectivity with respect to the upper layer 782 and the lower layer 778.Consequently, the upper layer 782 is used as an etching mask for structuring the middle layer 780, and the middle layer 780 is used as an etching mask for structuring the lower layer 778. In some embodiments, the resist layer formed above the ILD 774 can be a different type of photoresist, such as a single-layer photoresist, a double-layer photoresist, or the like.

[0074] In block 634, the upper layer 782 is structured using any photolithography technique to form an opening in it, as in Fig. Figure 30 shows an example of structuring the top layer 782. The top layer 782 can be exposed to a beam of light from a UV laser or an excimer laser, such as a 248 nm beam from a krypton fluoride excimer laser (KrF excimer laser), a 193 nm beam from an argon fluoride excimer laser (ArF excimer laser), or a 157 nm beam from an F2 excimer laser. Exposure of the photosensitive material can be performed using an immersion lithography system to increase the resolution and reduce the minimum achievable distance. A baking or curing process can be carried out to harden the top layer 782, and a developer can be used to remove either the exposed or the non-exposed sections of the top layer 782, depending on whether a positive or a negative varnish is used.Subsequently, the opening defined in the upper layer 782 is transferred to the layers arranged below using one or more suitable etching processes, as shown in . Fig. Figure 31 shows the enlarged opening being referred to as the gate via opening 784. The gate via opening 784 is extended to the gate electrode layer 764 by etching through the middle layer 780, the bottom layer 778, the ILD 774, the ESL 772, the ILD 770, and the ESL 768 using one or more suitable etching processes. The etching processes can over-etch into the gate electrode layer 764 such that the gate via opening 784 extends to a position below a top surface of the gate electrode layer 764.

[0075] Referring to the Fig. 9 and Fig. In section 32, the method 600 comprises a block 636 in which a threshold voltage (Vt) optimizing dopant 800 is introduced into the gate electrode layer 764 through the gate via opening 784. The introduction of the Vt optimizing dopant 800 can involve an implantation process or a soaking process. The Vt optimizing dopant 800 can contain fluorine, oxygen, hydrogen, nitrogen, or a combination thereof. In an example, the Vt optimizing dopant 800 is fluorine, and fluorine atoms are introduced into the gate electrode layer 764 by an implantation process at a temperature between approximately 30°C and approximately 90°C for between approximately 10 seconds and approximately 200 seconds.In another example, the Vt-optimizing dopant 800 is fluorine, and fluorine atoms are introduced into the gate electrode layer 764 by immersing the workpiece 700 in a fluorine-containing gas (for example, F2 and / or NF3) for approximately 4 seconds to approximately 15 minutes at a temperature between approximately 25°C and approximately 550°C. Subsequently, annealing is performed to accelerate the diffusion of the Vt-optimizing dopant 800 into the WFM layer of the gate electrode layer 764. In one example, the annealing is thermal annealing at a temperature between approximately 200°C and approximately 400°C. The Vt-optimizing dopant 800 can further be driven into the dielectric gate layer 762 after annealing. The Vt optimizing dopant 800 increases the threshold voltage of the transistors, such as the forward gate transistors PG-1 and PG-2 in the . Fig. 5 - 8. After the introduction of the Vt optimizing dopant 800, an ashing process and / or an etching process can be carried out to remove the three-layer lacquer layer 776.

[0076] Since the Vt-optimizing dopant 800 is introduced through the underside of the gate via 784 and diffuses to other sections of the gate electrode layer 764, the concentration of the Vt-optimizing dopant 800 reaches its maximum value at a position adjacent to the underside of the gate via 784 and decreases with increasing distance from the gate via 784 both horizontally (along the Y-axis) and vertically (along the Z-axis). A curve of the concentration measured at an upper section of the gate electrode layer 764 along the line B - B in Fig. 32 is in Fig. Figure 45 shows that in some embodiments, the Vt-optimizing dopant 800 has a concentration peak at an atomic percent fraction of approximately 5% directly below the gate via opening 784 (Yo on the Y-axis) and gradually decreases along the Y-axis away from the gate via opening 784 to zero.

[0077] Referring to the Fig. 9 and Fig. In section 33, method 600 comprises a block 638 in which a front-side gate via 786 is formed in the gate via opening 784. In some implementations, the front-side gate via 786 serves as the front-side gate via 360A or 360L in layout 500-1 as shown in Fig. Figure 5 illustrates this. In some embodiments, the front-side gate via 786 is formed by filling the gate via opening 784 with one or more conductive materials and subsequently removing excess conductive material from the front of the workpiece 700 in a planarization process. The front-side gate via 786 can contain tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals and can be deposited by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive material for forming the front-side gate via 786 is fluorine-free, such as fluorine-free tungsten.In some alternative embodiments, the method 600 can optionally omit block 636 but use fluorine-containing conductive material, such as fluorine-containing tungsten, to form the front-side gate via 786 at block 638. In this scenario, the method 600 can further perform annealing at block 638 after forming the front-side gate via 786 so that fluorine atoms diffuse from the fluorine-containing tungsten into the gate electrode layer 764 below, thereby increasing the threshold voltage of the transistors. The concentration curve along the line B - B in . Fig. 33 is similar to the curve that is in Fig. 45 is shown.

[0078] In some alternative embodiments, such as those described above with reference to layout 500-2 as in Fig. As discussed in Figure 6, Method 600 can form two front-side gate vias 786 on each of the forward-gate transistors. In some implementations, the front-side gate via 786 can be represented as the front-side gate vias 360A or 360L in layout 500-2 as shown in Figure 6. Fig. Figure 6 serves as a guide. The resulting workpiece 700 and the concentration of the Vt-optimizing dopant along the line B - B are shown in Fig. 34 respectively Fig. Figure 46 shows the concentration curve. Note that the concentration curve in Fig. 46 has two points which correspond to the positions of the two front-side gate vias 786 (Y1 and Y2 on the Y-axis). The following figures explain the manufacturing processes that are carried out after the structure, which in Fig. 33 is shown, which was formed. However, the same processes can also be applied to the in Fig. The structure shown in section 34 can be applied.

[0079] Referring to the Fig. 9 and Fig. 35. Method 600 comprises a block 640 in which the front-facing multilayer interconnect structure FMLI is completed by forming the remaining higher-ordered interconnect layers 788 before the workpiece 700 is turned over with the other side facing upwards by attaching the front of the workpiece 700 to a carrier 790. This allows access to the device 700 from the rear for further processing. Any suitable fastening processes can be used in block 640 of method 600, such as direct bonding, hybrid bonding, the use of adhesives, or other bonding methods. The carrier 790 can be a silicon wafer in some embodiments. Fig. Figure 35 and the following figures show the “Z” direction from the back of workpiece 700 to the front of workpiece 700, while the “-Z” direction shows from the front of workpiece 700 to the back of workpiece 700.

[0080] Referring to the Fig. 9 and Fig. In section 36, the process 600 comprises a block 642 in which the workpiece 700 is thinned from the rear side until the STI element 714 is exposed from the rear side of the workpiece 700. The thinning process can include a mechanical grinding process and / or a chemical thinning process. A substantial amount of the substrate material can first be removed from the substrate 702 during a mechanical grinding process. Subsequently, a chemical thinning process can apply an etching chemical to the rear side of the substrate 702 to further thin the substrate 702.

[0081] Referring to the Fig. 9 and Fig. 37. Method 600 comprises a block 644 in which one or more backside dielectric layers are formed as part of a backside multilayer interconnect structure BMLI on the backside of the STI element 712 and the base fin structure 712B. In the illustrated embodiment, a backside ESL 768B is applied to the backside of the workpiece 700, a backside ILD 770B is applied over the backside ESL 768B, a backside ESL 772B is applied over the backside ILD 770B, and a backside ILD 774B is applied over the backside ESL 772B.Each of the backside ESLs 768B and 772B may contain silicon carbide, silicon oxynitride, silicon carbonitride or the like, and be formed by CVD, PVD, ALD or other suitable deposition processes; each of the backside ILDs 770B and 774B may contain a material selected from the group comprising PSG, BSG, PBSG, FSG, TEOS and other non-porous dielectric materials with low K-value, and be formed by flowable CVD, PE-CVD, LP-CVD, spin coating or other suitable deposition processes.

[0082] Referring to the Fig. In sections 9 and 38-40, process 600 comprises a block 646 in which a backside three-layer lacquer layer 776B is formed over the backside ILD 774B and then structured to form a backside gate via opening 784B. As in Fig. As shown in Figure 38, the three-layer reverse coating 776B comprises a bottom layer 778B, a middle layer 780B, and a top layer 782B. The bottom layer 778B may be a bottom antireflective coating (BARC). The bottom layer 778B may contain organic materials. The middle layer 780B may be composed of or contain an inorganic material, which may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The top layer 782B is a photosensitive material. The middle layer 780B exhibits high etch selectivity with respect to the top layer 782B and the bottom layer 778B. As a result, the upper layer 782B is used as an etching mask to structure the middle layer 780B, and the middle layer 780B is used as an etching mask to structure the lower layer 778B.In some embodiments, the lacquer layer formed over the rear-side ILD 774B can be a different type of photoresist, such as a single-layer photoresist, a double-layer photoresist, or the like.

[0083] In block 646, the upper layer 782B is structured using any photolithography technique to form an opening in it, as in Fig. Figure 38 shows that, as an example of structuring the top layer 782B, the top layer 782B can be exposed to a beam of light from a UV laser or an excimer laser, such as a 248 nm beam from a krypton fluoride excimer laser (KrF excimer laser), a 193 nm beam from an argon fluoride excimer laser (ArF excimer laser), or a 157 nm beam from an F2 excimer laser. Exposure of the photosensitive material can be performed using an immersion lithography system to increase the resolution and reduce the minimum achievable distance. A baking or curing process can be carried out to harden the top layer 782B, and a developer can be used to remove either the exposed or the non-exposed sections of the top layer 782B, depending on whether a positive or a negative varnish is used.Subsequently, the opening defined in the upper layer 782B is transferred to the layers below using one or more suitable etching processes, as shown in . Fig. Figure 39 shows the enlarged opening being referred to as the back-side gate via opening 784B. The gate via opening 784 is enlarged to the hard mask layer 715 by etching through the middle layer 780B, the bottom layer 778B, the back-side ILD 774B, the back-side ESL 772B, the back-side ILD 770B, and the back-side ESL 768B using one or more suitable etching processes. The hard mask layer 715 protects the gate electrode layer 764 from being directly etched. Subsequently, one or more separate etching processes are performed using a suitable etchant targeting the hard mask layer 715, as shown in Figure 39. Fig. Figure 40 shows that the separate etching processes also extend the backside gate via opening 784B through the dielectric gate layer 762 and expose the gate electrode layer 764. Furthermore, the separate etching processes can over-etch into the gate electrode layer 764 such that the backside gate via opening 784B extends to a position above (along the Z direction) a lower surface of the gate electrode layer 764.

[0084] Referring to the Fig. 9 and Fig. In section 41, the method 600 comprises a block 648 in which a threshold voltage (Vt) optimizing dopant 900 is introduced into the gate electrode layer 764 through the rear gate via opening 784B. The introduction of the Vt optimizing dopant 900 can involve an implantation process or a soaking process. The Vt optimizing dopant 900 can contain fluorine, oxygen, hydrogen, nitrogen, or a combination thereof. The Vt optimizing dopant 900 can be the same as the Vt optimizing dopant 800. Alternatively, the Vt optimizing dopant 900 can be of a different type than the Vt optimizing dopant 800. Depending on the device performance requirements, the dosages of the Vt optimizing dopant 900 can also differ from or be the same as those of the Vt optimizing dopant 800.For example, the dose of the Vt-optimizing dopant 900 can be lower than the dose of the Vt-optimizing dopant 800 because doping from the back of the workpiece 700 provides a shorter path for the Vt-optimizing dopant 900 to reach the WFM layer of the gate electrode layer 764. In one example, the Vt-optimizing dopant 900 is fluorine, and fluorine atoms are implanted into the gate electrode layer 764 by an implantation process at a temperature between approximately 30°C and approximately 90°C for between approximately 10 seconds and approximately 200 seconds. In another example, the Vt optimizing dopant 900 is fluorine, and fluorine atoms are introduced into the gate electrode layer 764 by immersing the workpiece 700 in a fluorine-containing gas (for example, F2 and / or NF3) for approximately 4 seconds to approximately 15 minutes at a temperature between approximately 25°C and approximately 550°C.Subsequently, an annealing process is performed to accelerate the diffusion of the voltage-optimizing dopant 900 into the WFM layer of the gate electrode layer 764. In one example, the annealing is thermal annealing at a temperature between approximately 200°C and approximately 400°C. After annealing, the voltage-optimizing dopant 900 can further be driven into the dielectric gate layer 762. The voltage-optimizing dopant 900 increases the threshold voltage of the transistors, such as the forward-gate transistors PG-1 and PG-2. Fig. 5 - 8. After the introduction of the Vt optimizing dopant 900, an ashing process and / or an etching process can be carried out to remove the reverse three-layer lacquer layer 776B.

[0085] Since the Vt-optimizing dopant 900 is introduced through the underside of the back-side gate via 784B and diffuses to other sections of the gate electrode layer 764, the concentration of the Vt-optimizing dopant 900 reaches its maximum value at a position adjacent to the underside of the back-side gate via 784B and decreases with increasing distance from the back-side gate via 784B in both the horizontal direction (along the Y-axis) and the vertical direction (along the Z-axis). A curve of the concentration measured at a lower section of the gate electrode layer 764 along the line C - C in Fig. 41, is in Fig. Figure 47 illustrates this. In some embodiments, the Vt-optimizing dopant 900 exhibits a concentration peak at an atomic percentage of approximately 5% directly below the back-side gate via 784B (Yo on the Y-axis) and gradually decreases to zero along the Y-axis away from the back-side gate via 784B. Furthermore, in some embodiments, depending on the device performance requirements, the maximum value of the Vt-optimizing dopant 900 may be higher than the maximum value of the Vt-optimizing dopant 800.

[0086] Referring to the Fig. 9 and Fig. In section 42, method 600 comprises a block 650 in which a back-side gate via 786B is formed in the back-side gate via opening 784B. In some implementations, the back-side gate via 786B serves as the back-side gate via B360A or B360L in layout 500-3 as shown in Fig. Figure 7 illustrates this. In some embodiments, the back-gate via 786B is formed by filling the back-gate via opening 784B with one or more conductive materials and subsequently removing excess conductive material from the back of the workpiece 700 in a planarization process. The back-gate via 786B may contain tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals and may be deposited by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive material used to form the back-gate via 786B is fluorine-free, such as fluorine-free tungsten.In some alternative embodiments, the method 600 can optionally omit block 648 but use fluorine-containing conductive material, such as fluorine-containing tungsten, to form the back-side gate via 786B at block 650. In this scenario, the method 600 can further perform annealing at block 650 after forming the back-side gate via 786B so that fluorine diffuses from the fluorine-containing tungsten into the gate electrode layer 764 below, thereby increasing the threshold voltage of the transistors. The concentration curve along the line C - C in . Fig. 42 is similar to the curve that is in Fig. 47 is shown.

[0087] In some alternative embodiments, such as those described above with reference to layout 500-4 as in Fig. As discussed in Figure 8, Method 600 can form two back-gate vias 786B under each of the forward-gate transistors. In some implementations, the back-gate vias 786B serve as the back-gate vias B360A or B360L in layout 500-4 as shown in Figure 8. Fig. Figure 8 shows the resulting workpiece 700 and the concentration of the Vt-optimizing dopant along the line C - C. Fig. 43 respectively Fig. Figure 48 shows that in this scenario, the base fin structure 712B can be removed by an etching process and replaced by a backside dielectric element 792 before the deposition of the backside ESL 768B, so that the backside gate vias 786B extend through the backside dielectric element 792 and the dielectric gate layer 762 and further into the gate electrode layer 764. The concentration curve in Fig. 48 has two points, which correspond to the positions of the two rear-side gate vias 786B (Y1 and Y2 on the Y-axis). In the following Fig. 44 explains the manufacturing processes that are carried out after the structure, which is in Fig. 42 is shown, which was formed. However, the same processes can also be applied to the in Fig. The structure shown in section 43 can be applied.

[0088] The following refers to Fig. 44. The process 600 can be continued to complete the rear-side multilayer interconnect structure BMLI by forming the remaining lower interconnect layers 788B before the workpiece 700 is turned back to complete further processes of the manufacturing sequence, such as the formation of passivation layers, the formation of bond pads, parting, and packaging. The embodiment shown in Fig. Figure 44 shows a front-side gate via 786, which is shared by the two transistors, and a rear-side gate via 786B, which is shared by the two transistors, with the concentration of the Vt-optimizing dopant in the upper section of the gate electrode layer (for example, along the line B - B) as shown in Fig. 45 shown, and the concentration of the Vt-optimizing dopant in the lower section of the gate electrode layer (for example, along the line C - C) as in Fig. 47 shown. As above with regard to the different embodiments in the Fig.As discussed in sections 5-8, the workpiece 700 can have one or two front-facing gate vias 786 and, independently of this, one or two rear-facing gate vias 786B, or the workpiece 700 can have no front-facing gate vias but one or two rear-facing gate vias 786B, or the workpiece 700 can have one or two front-facing gate vias but no rear-facing gate vias 786B. Furthermore, depending on the requirements of the fixture performance, the Vt-optimizing dopant can be applied only to the front of the workpiece 700, only to the rear of the workpiece 700, or to both the front and rear of the workpiece 700.

[0089] The SRAM cells and corresponding layouts, which are illustrated in various embodiments of this disclosure, represent front-gate vias and back-gate vias as a means of further optimizing the threshold voltages of the forward-gate transistors in the SRAM cells to achieve a higher beta ratio. The increased beta ratio enlarges the read-through operating window and improves memory performance. Furthermore, embodiments of this disclosure can be readily integrated into existing semiconductor manufacturing processes without modifying the front-end-of-line (FEOL) operations.

[0090] In one exemplary aspect, the present disclosure relates to a method for manufacturing a semiconductor device. The method comprises forming a stack over a substrate, the stack having channel layers between which sacrificial layers are arranged, structuring the stack to form a fin-shaped structure, forming a dummy gate stack over a channel region of the fin-shaped structure, applying a gate spacer layer over the dummy gate stack, after applying the gate spacer layer, deepening a source / drain region of the fin-shaped structure, selectively removing the sacrificial layers in the channel region to expose the channel layers as channel elements, applying a dummy layer in the space between the channel elements, and selectively and partially deepening the dummy layer to form internal spacer recesses.forming inner spacer elements in the inner spacer element recesses, forming a source / drain element over the source / drain area, removing the dummy gate stack, removing the dummy layer, forming a gate structure to enclose each of the channel elements, the gate structure comprising a dielectric gate layer and a gate electrode layer, applying a backside dielectric layer to a rear side of the semiconductor device, structuring the backside dielectric layer to form a backside gate via directly beneath the gate structure, and doping a threshold voltage-optimizing dopant into the gate electrode layer of the gate structure through the backside gate via.and, after doping with the threshold voltage-optimizing dopant, the formation of a back-side gate via in the back-side gate via hole. In some embodiments, the semiconductor device is a memory device comprising at least one first memory cell and a second memory cell adjacent to the first memory cell, and the gate structure is a component of a first forward-gate transistor in the first memory cell. In some embodiments, the gate structure is shared with a second forward-gate transistor in the second memory cell. In some embodiments, the threshold voltage-optimizing dopant is selected from a group comprising fluorine, oxygen,Hydrogen and nitrogen. In some embodiments, a concentration peak of the threshold voltage-optimizing dopant is located directly above the back-side gate via. In some embodiments, the method further comprises performing an annealing step to allow the threshold voltage-optimizing dopant to diffuse into a work-work metal layer of the gate electrode layer. In some embodiments, the method further comprises applying an insulating element to the sidewalls of the fin-shaped structure, applying a hard mask layer over the insulating element, enlarging the back-side gate via opening through the insulating element in a first etching process, and enlarging the back-side gate via opening through the hard mask layer in a second etching process.which differs from the first etching process. In some embodiments, the method further comprises, after enlarging the back-side gate via opening through the hard mask layer, enlarging the back-side gate via opening through the dielectric gate layer to expose the gate electrode layer of the gate structure. In some embodiments, the method further comprises depositing a front-side dielectric layer on a front face of the semiconductor device, structuring the front-side dielectric layer to form a front-side gate via opening directly above the gate structure,and the formation of a front-side gate via in the front-side gate via opening. In some embodiments, the method further comprises, prior to the formation of the front-side gate via, the introduction of the threshold voltage-optimizing dopant through the front-side gate via opening into the gate electrode layer of the gate structure.

[0091] In another exemplary aspect, the present disclosure relates to a method for manufacturing a semiconductor device.The process comprises forming a first active region and a second active region protruding from a substrate, applying a first gate across the first active region and the second active region to form a first transistor and a second transistor, applying a second gate across the first active region to form a third transistor, applying a third gate across the second active region to form a fourth transistor, applying a dielectric layer covering the first gate, the second gate and the third gate, forming a gate via opening through the dielectric layer and exposing the first gate, doping a threshold voltage-optimizing dopant through the gate via opening into the first gate, and forming a gate via in the gate via opening.In some embodiments, the first transistor is a forward-gate transistor of a first memory cell, the second transistor is a pull-down transistor of the first memory cell, the third transistor is a forward-gate transistor of a second memory cell connected to the first memory cell, and the fourth transistor is a pull-down transistor of the second memory cell. In some embodiments, after the gate via is formed, either the third or the fourth transistor lacks an electrically connected gate via. In some embodiments, the dielectric layer is deposited on a front face of the semiconductor device, and the gate via opening exposes a top surface of the first gate.In some embodiments, the dielectric layer is applied to a rear side of the semiconductor device, and the gate via exposes a lower surface of the first gate. In some embodiments, the gate via is a first gate via and the gate via is a first gate via, and the method further comprises forming a second gate via through the dielectric layer and exposing the first gate, doping a threshold-optimizing dopant through the second gate via into the first gate, and forming a second gate via in the second gate via.In some embodiments, after doping with the dopant material that optimizes the threshold voltage, the threshold voltage of the first transistor and the second transistor is higher than that of the third transistor and the fourth transistor.

[0092] In yet another exemplary aspect, the present disclosure relates to a storage device. The storage device comprises a plurality of first vertically stacked nanostructures, a plurality of second vertically stacked nanostructures spaced laterally from the first nanostructures, a gate structure enclosing the first and second nanostructures, a gate via electrically connected to the gate structure, and a threshold-optimizing dopant distributed in a gate electrode layer of the gate structure, wherein a concentration peak of the threshold-optimizing dopant is vertically oriented towards the gate via.In some embodiments, the gate via is a first gate via, and the storage device further comprises a second gate via which is electrically connected to the gate structure. The first gate via is located on a lower face of the gate structure, and the second gate via is located on an upper face of the gate structure. In some embodiments, the gate via is a first gate via, and the storage device further comprises a second gate via which is electrically connected to the gate structure.The first gate via and the second gate via are arranged on the same side of the gate structure, the concentration peak of the threshold voltage optimizing dopant is a first peak, and a second concentration peak of the threshold voltage optimizing dopant is vertically aligned to the second gate via.

[0093] The foregoing description presents features / elements of various embodiments in such a way that skilled persons may better understand the aspects of the present disclosure. Skilled persons should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein. Skilled persons should also recognize that such equivalent designs do not deviate from the concept and scope of the present disclosure, and that they can make a wide variety of changes, substitutions, and adaptations to them without deviating from the concept and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 652,956

[0001]

Claims

[1] Method for manufacturing a semiconductor device, the method comprising: Forming a stack, which has channel layers and sacrificial layers arranged between them, over a substrate; Structuring the stack to form a fin-shaped structure; Forming a dummy gate stack over a channel area of ​​the fin-shaped structure; Applying a gate spacer layer over the dummy gate stack; After applying the gate spacer layer, deepening a source / drain area of ​​the fin-shaped structure; selective removal of sacrificial layers in the canal area to expose the canal layers as canal elements; Applying a dummy layer in the space between the channel elements; Selective and partial deepening of the dummy layer to form internal spacer element recesses; Forming inner spacer elements in the inner spacer element recesses; Forming a source / drain element over the source / drain area; Remove the dummy gate stack; Removing the dummy layer; Forming a gate structure to enclose each of the channel elements, wherein the gate structure comprises a dielectric gate layer and a gate electrode layer; Applying a backside dielectric layer to the rear side of the semiconductor device; Structuring the backside dielectric layer to form a backside gate via opening directly beneath the gate structure; Doping a threshold voltage-optimizing dopant through the rear gate via opening into the gate electrode layer of the gate structure; and After doping with the threshold voltage optimizing dopant, a backside gate via is formed in the backside gate via opening. [2] Method according to claim 1, wherein the semiconductor device is a storage device comprising at least a first storage cell and a second storage cell adjacent to the first storage cell, and the gate structure is a component of a first pass-through gate transistor in the first storage cell. [3] Method according to claim 2, wherein the gate structure is shared with a second pass-through gate transistor in the second memory cell. [4] Method according to any of the preceding claims, wherein the dopant optimizing the threshold voltage is selected from the group comprising fluorine, oxygen, hydrogen and nitrogen. [5] Method according to one of the preceding claims, wherein a concentration peak of the threshold voltage optimizing dopant is arranged directly above the backside gate via. [6] Method according to any of the foregoing claims, further comprising: Performing a tempering process to introduce the dopant material, which optimizes the threshold voltage, into an exit metal layer of the gate electrode layer. [7] Method according to any of the foregoing claims, further comprising: Applying an insulating element to the side walls of the fin-shaped structure; Applying a hard mask layer over the insulating element; Enlarging the rear-side gate via opening through the insulating element in a first etching process; and Enlarging the rear gate via opening through the hard mask layer in a second etching process, which differs from the first etching process. [8] Method according to claim 7, further comprising: After widening the backside gate via opening through the hard mask layer, widening the backside gate via opening through the dielectric gate layer to expose the gate electrode layer of the gate structure. [9] Method according to any of the foregoing claims, further comprising: Application of a front-side dielectric layer to a front face of the semiconductor device; Structuring the front-side dielectric layer to form a front-side gate via directly above the gate structure; and Forming a front-side gate via in the front-side gate via opening. [10] The method of claim 9, further comprising: Before forming the front-side gate via, the dopant material optimizing the threshold voltage is introduced through the front-side gate via opening into the gate electrode layer of the gate structure. [11] Method for manufacturing a semiconductor device, the method comprising: Formation of a first active area and a second active area from a substrate; Applying a first gate across the first active area and the second active area to form a first transistor and a second transistor; Adding a second gate across the first active area to form a third transistor; Adding a third gate across the second active area to form a fourth transistor; Applying a dielectric layer covering the first gate, the second gate, and the third gate; Forming a gate via opening through the dielectric layer and exposing the first gate; Doping with a threshold voltage-optimizing dopant through the gate via opening into the first gate; and Forming a gate via in the gate via opening. [12] Method according to claim 11, wherein the first transistor is a pass-through gate transistor of a first memory cell, the second transistor is a pull-down transistor of the first memory cell, the third transistor is a pass-through gate transistor of a second memory cell connected to the first memory cell, and the fourth transistor is a pull-down transistor of the second memory cell. [13] Method according to claim 11 or 10, wherein after forming the gate via either the third transistor or the fourth transistor does not have a gate via electrically connected to it. [14] Method according to any one of claims 11 to 13, wherein the dielectric layer is applied to a front face of the semiconductor device and the gate via opening exposes an upper surface of the first gate. [15] Method according to any one of claims 11 to 13, wherein the dielectric layer is applied to a rear side of the semiconductor device and the gate via opening exposes a lower surface of the first gate. [16] Method according to any one of claims 11 to 15, wherein the gate via opening is a first gate via opening, and the gate via is a first gate via, the method further comprising: Forming a second gate via opening through the dielectric layer and exposing the first gate; Doping with a threshold voltage-optimizing dopant through the second gate via opening into the first gate; and Forming a second gate via in the second gate via opening. [17] Method according to any one of claims 11 to 16, wherein after doping with the threshold voltage optimising dopant, the threshold voltage of the first transistor and the second transistor is higher than that of the third transistor and the fourth transistor. [18] Storage device comprising: a plurality of first vertically stacked nanostructures; a plurality of second vertically stacked nanostructures, which are laterally spaced from the first nanostructures; a gate structure that encloses the first nanostructures and the second nanostructures; a gate via which is electrically connected to the gate structure; and a threshold voltage-optimizing dopant distributed in a gate electrode layer of the gate structure, wherein a concentration peak of the threshold voltage-optimizing dopant is vertically aligned with the gate via. [19] Storage device according to claim 18, wherein the gate via is a first gate via, the storage device further comprising: a second gate via which is electrically connected to the gate structure, wherein the first gate via is located on a lower surface of the gate structure, and the second gate via is located on an upper surface of the gate structure. [20] Storage device according to claim 18, wherein the gate via is a first gate via, the storage device further comprising: a second gate via which is electrically connected to the gate structure, wherein the first gate via and the second gate via are arranged on the same side of the gate structure, the concentration peak of the threshold voltage optimizing dopant is a first peak, and a second concentration peak of the threshold voltage optimizing dopant is vertically aligned to the second gate via.

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