CELL AREA WITH VG- AND VD-FREE CONDUCTOR PATHWAYS AND METHOD FOR ITS PROCESSING

Abstract

A cell region (of a device) comprises: active regions; gate segments and metal source / drain region (MD) contacts mixed together; via-hole gate contacts (VG contacts); via-hole MD contact contacts (VD contacts), the VG contacts and VD contacts being oriented accordingly to alpha traces extending in the first direction; first trace segments (RTE segments) being oriented accordingly to the alpha traces; and first buried power grid segments. A first and a second alpha trace are adjacent to a first and a second boundary of the cell region. At least a third alpha trace is located between the first and second alpha traces. The first alpha trace has no VG contacts oriented toward it, and the second alpha trace has no VD contacts oriented toward it.

Description

priority claim

[0001] The present application claims priority over the preliminary US patent application filed on September 27, 2024, under file number 63 / 700.309, which is incorporated by reference into the present application. background

[0002] The IC industry (IC: integrated semiconductor circuit) manufactures a wide variety of analog and digital devices to address problems in several different fields. Advances in semiconductor process technology have continuously reduced component sizes and spacing, resulting in ever-increasing transistor density. ICs have become smaller. Brief description of the drawings

[0003] The figures in the accompanying drawings illustrate one or more embodiments by way of example and without limitation, whereby elements with the same reference numerals consistently represent similar elements. The drawings are not to scale unless otherwise indicated. Fig. Figure 1 is a block diagram according to some embodiments. The Fig. 2A to 2E are corresponding layout diagrams according to some embodiments. The Fig. 3A to 3C are corresponding layout diagrams according to some embodiments. The Fig. 4A and Fig. 4B are sectional views according to some embodiments. Fig. 5A is a layout diagram according to some embodiments. The Fig. 5B and Fig. 5C are corresponding block diagrams according to some embodiments. The Fig. 6, Fig. 7A and Fig. 7B are flowcharts of corresponding procedures according to some embodiments. Fig. Figure 8 is a block diagram of an EDA system (EDA: Design Automation of Electronic Systems) according to some embodiments. Fig. Figure 9 is a block diagram of an IC manufacturing plant and an associated IC manufacturing process according to some embodiments. Detailed description

[0004] The following description provides many different embodiments or examples for implementing various elements of the subject matter. Examples of components, materials, values, steps, operations, arrangements, or the like are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, or the like are also considered. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact.Furthermore, reference numbers and / or letters may be repeated in the various examples in this disclosure. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here may be interpreted accordingly. In some embodiments, the term "standard cell structure" refers to a standardized building block contained in a library of various standard cell structures.In some embodiments, various standard cell structures are selected from a library and used as components in a layout diagram that represents a circuit.

[0006] In some embodiments, a cell region (of a device) comprises: active regions extending in a first direction; gate segments and metal source / drain region contacts (MD contacts) extending in a second direction perpendicular to the first direction, intermingled and having portions over areas of the active regions; via-hole gate contacts (VG contacts) over areas of the gate segments; via-hole MD contact contacts (VD contacts) over areas of the MD contacts, the VG contacts and the VD contacts being oriented accordingly to alpha traces extending in the first direction; in a first metallization layer on a first side of the active regions, first trace segments (RTE segments) extending in the first direction, being oriented accordingly to the alpha traces and arranged accordingly over the VG contacts or the VD contacts;and in a first buried metallization layer on a second side of the active areas, first buried power grid segments extending in the first direction. A first (e.g., upper) alpha trace and a second (e.g., lower) alpha trace of the alpha traces are adjacent to a first (e.g., upper) boundary and a second (e.g., lower) boundary of the cell area. At least a third (e.g., inner) alpha trace of the alpha traces is located between the first and the second alpha trace, the first alpha trace having no VG contacts aligned with it and the second alpha trace having no VD contacts aligned with it. Such a cell area is an example of a backside power distribution grid (BSPD) architecture.

[0007] According to another approach to manufacturing a device with a BSPD architecture, a minimum pendant distance for each of several spatial relationships (e.g., pendant-VG distance, pendant-VD distance, pendant-Vo structure distance, or the like) requires the use of two ELTVL masks (ELTVL: Extreme Ultraviolet Lithography) to generate the spatial relationship. In contrast, at least some embodiments use a larger minimum distance for each of the corresponding spatial relationships. In some embodiments, at least partly due to one or more design rules disclosed herein, a single EUVL mask is sufficient to generate the spatial relationship in a device with a BSPD architecture. By omitting one EUVL mask, these embodiments are cheaper and / or faster to manufacture than the other approach.

[0008] Fig. Figure 1 is a block diagram of a cell area 104 of a device 100 according to some embodiments.

[0009] Device 100 is an example of an integrated circuit (IC). In some embodiments, device 100 is referred to as a semiconductor device. Device 100 includes a macro-area 102. In some embodiments, the macro-area 102 consists of one or more functional areas, such as circuit areas, or the like. In some embodiments, the macro-area 102 includes: a memory, a power grid, one or more cells, an inverter, a latch, a buffer, a driver, analog devices such as a digital-to-analog converter (DAW) or an analog-to-digital converter (ADW), or the like, clock trees, phase-locked loops (PLLs), interfaces, and / or another type of circuit arrangement.Examples of memory types include static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), solid-state memory (ROM), or the like.

[0010] Macro area 102 can be digitally represented in a library of standard cells. In some embodiments, macro area 102 is to be understood in connection with an analogy to the architectural hierarchy of modular programming, in which subroutines / procedures are called by a main program (or by other subroutines) to perform a given computational function. In this context, the device 100 uses macro 102 to execute one or more given functions. Accordingly, in this context and with respect to the architectural hierarchy, the device 100 is analogous to the main program, and macro area 102 is analogous to the subroutines / procedures. In some embodiments, macro area 102 is a soft macro. In some embodiments, macro area 102 is a hard macro.In some embodiments, the macro area 102 is a soft macro digitally represented in an RTL code (RTL: Register Transfer Level). In some embodiments, synthesis, placement, and tracing still need to be performed on the macro area 102 so that the soft macro can be synthesized, placed, and traced for different process technology nodes. In some embodiments, the macro area 102 is a hard macro digitally represented in a binary file format, such as a GDSII stream format (GDSII: Graphic Database System II), wherein the binary file format represents planar geometric shapes, text labels, other information, and the like of one or more layouts of the macro area 102 in a hierarchical form. In some embodiments, the binary file format is referred to as a non-text file format.In some embodiments, the synthesis, placement and routing at the macro area 102 have already been carried out, so that the hard macro is specific for a particular process technology node.

[0011] In Fig. 1. Macro area 102 contains a cell function area 104, which represents a functional circuit. The cell function area 104 contains at least one active device, such as a transistor or the like. In some embodiments, the cell function area 104 contains one or more logic gates. In some embodiments, the cell function area 104 is, or contains, a buffer, a driver, an inverter, or the like. Examples of logic gates / circuits include circuits configured to perform logical AND, OR, NAND, NOR, XOR, INV, AND-OR-INVERT functions (AOI functions) (see, for example, Fig. 5A) or OR-AND-INVERTE functions (OAI functions) or the like. Examples of other function circuits include a multiplexer (MUX), a flip-flop, a buffer (BUFF), a driver (DRV), a latch, a delay circuit, a clock circuit, a memory circuit, or the like.

[0012] Cell functional area 104 contains corresponding segments in one or more metallization layers (see e.g. Fig. 4A and Fig. 4B). In the figures of this disclosure, a Cartesian coordinate system is assumed (unless otherwise specified) in which a first, a second, and a third direction are, for example, parallel to the x-axis, the y-axis, and the z-axis, respectively. In some embodiments, the first to third directions correspond to directions other than the x-axis, the y-axis, and the z-axis. In some embodiments, the long and short axes of the segments extend accordingly in the first and second directions in even-numbered metallization layers, and in these embodiments, the long and short axes of the segments extend accordingly in the first and second directions in odd-numbered metallization layers. In these embodiments, the boundaries of the cell functional area 104 are described by means of the first and second directions.

[0013] In some embodiments, the cell functional area 104 corresponds to a transistor component layer (see e.g. Fig. 4A and Fig. 4B) with circuit components, e.g., transistors, which are manufactured on it in a FEOL (Front End of Line) manufacturing process. In the cell functional area 104, above and / or below an active area layer (AR layer; see e.g. Fig. 4A and Fig. 4B) different metal layers (see e.g. Fig. 4A and Fig. 4B) with corresponding connection layers (see e.g. Fig. 4A and Fig. 4B) are interlocked, and they are stacked over and / or under insulating layers in a BEOL (Back End of Line) manufacturing process. During BEOL manufacturing, a power grid and / or a routing for circuits of the device 100 is provided, which includes the macro area 102 and the cell functional area 104.

[0014] In some embodiments, the cell functional area 104 contains one or more active devices, passive devices, or the like. Examples of active devices or elements include, but are not limited to, transistors, diodes, or the like. Examples of passive elements include, but are not limited to, capacitors, inductors, resistors, or the like.

[0015] Fig. 2A is a layout diagram of a macro area 202A according to some embodiments.

[0016] Macro area 202A is an example of macro area 102 from Fig. 1. The macro-area 202A is arranged with respect to alpha conductor tracks a0 to α21, which extend parallel to the x-axis. In Fig. In Figure 2A and other layout diagrams disclosed herein, it is assumed that the first and second directions are parallel to the x-axis and y-axis, respectively. In some embodiments, it is assumed that the first and second directions have orientations other than being parallel to the x-axis and y-axis, respectively. Fig. In 2A and other layout diagrams revealed here, rows are collinear with the alpha traces.

[0017] Macro area 202A contains cell function areas (FN areas) 206A(1) and 206A(2), as well as 208A(1) and 208A(2), which are stacked with respect to the y-axis. Cell function area 206A(2) is stacked on top of cell function area 208A(2). Cell function area 208A(1) is stacked on top of cell function area 206A(2). Cell function area 206A(1) is stacked on top of cell function area 208A(1). Cell function areas 206A(1) and 206A(2), as well as 208A(1) and 208A(2), are also referred to as interlocking areas with respect to the y-dimension.

[0018] Each of the cell function areas 206A(1) and 206A(2) as well as 208A(1) and 208A(2) is set up to perform a given function, e.g. an AOI (see e.g. Fig. 5A). That is, each of the cell function ranges 206A(1) and 206A(2) as well as 208A(1) and 208A(2) is set up to perform the same function.

[0019] The components (see e.g. Fig. 2B to 2E), which are contained in each of the cell functional areas 206A(1) and 206A(2) as well as 208A(1) and 208A(2), include the following: Gate segments (see e.g. Fig. 2C to 2E) in a gate / MD layer (see e.g. Fig. 4A and Fig. 4B); Metal source / drain contacts (MD contacts) (see e.g. Fig. 2C to 2E) in the gate / MD layer; via-gate contacts (VG contacts) (see e.g. Fig. 2C to 2E) in a VG / VD layer (see e.g. Fig. 4A and Fig. 4B); Through-hole MD contact contacts (VD contacts) (see e.g. Fig. 2B and 2C to 2E) in the VG / VD layer; and first routing segments (RTE segments) in a first metallization layer (see e.g. Fig. 4A and Fig. 4B). In some embodiments, VG is an abbreviation for "via on gate". In some embodiments, VD is an abbreviation for "via on source / drain".

[0020] In some embodiments, depending on the numbering rule of the corresponding process technology node with which a device is located on a front side (see e.g. Fig. 4A and Fig. 4B) of the active area layer (see e.g. Fig. 4A and Fig. 4B) is to be produced, the first metallization layer is either a metallization layer zero (METo) (see e.g. Fig. 4A and Fig. 4B) or a metallization layer one (MET1), and accordingly, a first compound layer on the first metallization layer is either a compound layer zero (VIA0) (see e.g. Fig. 4A and Fig. 4B) or a link layer one (VIA1).

[0021] In these embodiments, the numbering again depends on the numbering rule of the corresponding process technology node on a reverse side (see e.g. Fig. 4A and Fig. 4B) of the active area layer (see e.g. Fig. 4A and Fig. 4B) the first buried metallization layer either a buried metallization layer zero (BMETo) (see e.g. Fig. 4A and Fig. 4B) or a buried metallization layer one (BMET1), and accordingly, a first buried compound layer below the first metallization layer is either a compound layer zero (VIA0) (see e.g. Fig. 4A and Fig. 4B) or a link layer one (VIA1).

[0022] In Fig. In Figure 2A and other figures disclosed herein, the following designations are used: the first metallization layer is MET0, the first interconnect layer is VIA0, the second metallization layer is MET1, the second interconnect layer is VIA1, and the third metallization layer is MET2. Metallization segments in layer MET0 are referred to as Mo segments. Via structures in layer VIA0 are referred to as Vo structures. Metallization segments in layer MET1 are referred to as M1 segments. Via structures in layer VIA1 are referred to as V1 structures. Metallization segments in layer MET2 are referred to as M2 segments.

[0023] In the Fig. 2D and Fig. For 2E, 4A, 4B, or the like, the following technical designations are used: the first buried metallization layer is BMETo, the first buried interconnect layer is BVIAo, the second buried metallization layer is BMET1, the second buried interconnect layer is BVIA1, and the third buried metallization layer is BMET2. Metallization segments in layer BMETo are designated as BMo segments. Via structures in layer BVIAo are designated as BVo structures. Metallization segments in layer BMET1 are designated as BM1 segments. Via structures in layer BVIA1 are designated as BV1 structures. Metallization segments in layer BMET2 are designated as BM2 segments.

[0024] Now let's move on to... Fig. 2A back.

[0025] In Fig. In Figure 2A and other figures revealed herein, the gate segments and MD contacts are aligned to corresponding Beta traces, and the VG contacts and VD contacts are aligned to corresponding Alpha and Beta traces.

[0026] Cell function areas 206A(1) and 206A(2) are instances of a first arrangement of components configured to perform the given function. Cell function areas 208A(1) and 208A(2) are instances of a second arrangement of components configured to perform the given function. The first and second arrangements support interlocked / mixed stacking of cell function areas 206A(1) and 206A(2) and 208A(1) and 208A(2) with respect to the y-axis.

[0027] In some embodiments, the first and second arrangements refer to corresponding arrangements of the gate segments, MD contacts, VG contacts, and VD contacts. In some embodiments, the first and second arrangements refer to corresponding arrangements of the gate segments, MD contacts, VG contacts, and VD contacts plus routing segments of the Mo segments (Mo_rte segments) (see, e.g., Fig. 2D and Fig. 5A) and the Vo structures.

[0028] Examples of differences between the first and second arrangements are discussed below, including differences that arise in the Fig. 2D and Fig. 2E shows differences between cell function areas 506 and 508. Fig. 5A or similar. While the first and second arrangements are different, they do share some characteristics. One such characteristic is that the gate segments and VG contacts correspond to odd-numbered beta traces (e.g., beta traces β3 to β9 of the Fig. 2D and Fig. 2E). A second property that the first and second arrangements have in common is that the MD contacts and the VD contacts correspond to even-numbered beta traces (e.g., beta traces β2 to β10 of the Fig. 2D and Fig. 2E) are aligned. A third property that the first and second arrangements have in common is in the Fig. 2B and Fig. 2C shown.

[0029] The Fig. 2B and Fig. 2C are layout diagrams of corresponding cell function areas 210B and 210C according to some embodiments.

[0030] The layout diagrams of Fig. 2B and 2C, and other layout diagrams disclosed herein, are typical for a transistor-based device. Structures in the device are represented by patterns (also called shapes) in the layout diagram. For the sake of simplicity, elements in the layout diagrams of Fig. 2B and 2C (and also in other layout diagrams revealed here) are described as if they were structures rather than patterns. For example, shapes in Fig. 2B, which represent instances of M0_rte segments, are simply referred to as M0_rte segments rather than as patterns.

[0031] A layout diagram is a top view. Shapes in the layout diagram are two-dimensional, e.g., with respect to the x-axis and y-axis, while the device being depicted is three-dimensional. Therefore, a shape in these layout diagrams is described as having a width / length with respect to the x-axis and a height with respect to the y-axis. With respect to the z-axis, for example, the bottom / back side of a first component shown in the layout diagram is stacked on top of a device with a second component shown in the layout diagram, or the top / front side of the first component is stacked underneath a bottom / back side of the second component.

[0032] Normally, with respect to the z-axis, the device is organized as a stack of layers in which corresponding structures are arranged, i.e., to which corresponding structures belong. Each shape in the layout diagram specifically represents a component in a corresponding layer of the corresponding device. Furthermore, the layout diagram typically represents the relative depth, i.e., positions along the z-axis, of shapes and corresponding layers by overlapping a first shape with a second shape, such that the second shape at least partially overlaps the first. For the sake of clarity, some structures that have a first stacking order along the z-axis in the device are represented in the layout diagram using a second stacking order along the z-axis, i.e., a different / distorted stacking order, as shown in Fig. 2I is shown (Translator's note: a Fig. 2I is not available).

[0033] Layout diagrams vary in the scope of detail shown. In some embodiments, selected layers of a layout diagram are combined / abstracted into a single layer for simplification. Alternatively and / or additionally, in some cases, not all layers of the corresponding device are shown for simplification; that is, selected layers of the layout diagram are omitted. Alternatively and / or additionally, in some cases, not all elements of a given depicted layer of the corresponding device are shown for simplification; that is, selected elements of the given depicted layer of the layout diagram are omitted. Fig. 2B and Fig. 2C and the other layout diagrams disclosed here are examples of layout diagrams in which selected layers and / or selected elements of given depicted layers have been omitted.

[0034] In the Fig. 2B and Fig. 2C are cell function areas 210B and 210C, each an example of the cell function areas 206A(1) and 206A(2) as well as 208A(1) and 208A(2) of Fig. 2A.

[0035] Cell function areas 210B and 210C are representations of a corresponding first and second design rule (DR) that correspond to the first and second arrangement of Fig. 2A, which are discussed below.

[0036] In the Fig. 2A and Fig. 2B refers to the first design rule of the alpha traces, e.g., the alpha trace adjacent to the lower boundary of cell function area 210B with respect to the y-axis and which overlaps cell function area 210B. This relates to cell function areas 206A(1) and 206A(2) as well as 208A(1) and 208A(2) of Fig. 2A and with the cell function area 210B of Fig. 2B refers to the first alpha trace as the lower alpha trace. In the Fig. Let 2A to 2C be the lower alpha traces α5, α10, α15, and α20. The first design rule specifies that the lower alpha trace has no VD contact aligned with it. In some embodiments, the first design rule is referred to as a VD-undesired-trace design rule.

[0037] In the Fig. 2A and Fig. 2C refers to the second design rule for a second alpha trace, e.g., the alpha trace adjacent to the upper boundary of cell function area 210C with respect to the y-axis and which overlaps cell function area 210C. This relates to cell function areas 206A(1) and 206A(2) as well as 208A(1) and 208A(2) of Fig. 2A and with the cell functional area 210C from Fig. 2C refers to the second alpha trace as the upper alpha trace. In the Fig. In embodiments 2B to 2C, the upper alpha traces are alpha traces α1, α6, α11, and α16. The second design rule specifies that the upper alpha trace does not have a VG contact aligned with it. In some embodiments, the second design rule is referred to as a VG-undesired-trajectory design rule.

[0038] In the cell function areas 206A(1) and 206A(2) as well as 208A(1) and 208A(2) of Fig. 2A and in the cell functional area 210C of Fig. 2C VD contacts are permitted in the upper alpha trace and in each of the inner alpha traces located between the upper and lower traces. For example, the inner alpha traces α2 to α4 are each in the Fig. 2B and Fig. 2C. In other words, in the cell function areas 206A(1) and 206A(2) as well as 208A(1) and 208A(2) of Fig. 2A and in the cell functional area 210C of Fig. 2B each of the alpha conductors α1 to α4 is a VD-permissible alpha conductor.

[0039] In the cell function areas 206A(1) and 206A(2) as well as 208A(1) and 208A(2) of Fig. 2A and in the cell functional area 210C of Fig. 2C VG contacts are permitted in the lower alpha trace and in each of the inner alpha traces. In other words, in cell functional areas 206A(1) and 206A(2) as well as 208A(1) and 208A(2) of Fig. 2A and in the cell functional area 210C of Fig. 2C, each of the alpha conductor tracks α2 to α5 is a VG-approved alpha conductor track.

[0040] The third common characteristic of the first and second arrangements, which was discussed above in the discussion of Fig. 2A has been mentioned, is (again) in the Fig. 2B and Fig. 2C is shown. In each of the cell functional areas 210B and 210C, VG contacts are located in each of the inner alpha traces, specifically in alpha traces α2 to α4, in each of the Fig. 2B and Fig. 2C is permitted. In each of the cell functional areas 210B and 210C, VD contacts are located in each of the inner alpha conductors, specifically (again) in the alpha conductors α2 to α4, in each of the Fig. 2B and Fig. 2C permissible. Thus, the common third property of the first and the second arrangement is that the VG contacts and / or the VD contacts in each of the alpha conductor tracks α2 to α4 in each of the Fig. 2B and Fig. 2C are permissible. In other words, the common third property of the first and second arrangements is that each of the alpha traces α2 to α4 is a VD-permitted alpha trace and a VG-permitted alpha trace, as shown in the Fig. 2B and Fig. 2C is shown.

[0041] Fig. 2D is a layout diagram of a macro area 202D according to some embodiments.

[0042] Macro area 202D is an example of macro area 102 from Fig. 1. The macro area 202D contains cell function areas (FN areas) 206D(1) and 206D(2) as well as 208D(1), which are stacked with respect to the y-axis. In Fig. In 2D, a section line 4A - 4A' runs parallel to the x-axis. In some embodiments, the section line 4A - 4A' corresponds to Fig. 2D of a section view 420A of Fig. 4A.

[0043] Cell function area 208D(1) is stacked on cell function area 206D(2). Cell function area 206D(1) is stacked on cell function area 208D(1). Cell function areas 206D(1) and 206D(2), as well as 208D(1), are also referred to as interlocked regions with respect to the y-dimension.

[0044] Each of the cell function areas 206D(1), 206D(2), and 208D(1) is configured to perform a given function. That is, each of the cell function areas 206D(1), 206D(2), and 208D(1) is configured to perform the same function. However, there are differences in the arrangement of components in cell function areas 206D(1) and 206D(2) compared to the arrangement of components in cell function area 208D(1), as explained below.

[0045] The components contained in each of the cell functional areas 206D(1) and 206D(2) and 208D(1) include the following: active areas (ARs), gate segments, MD contacts, VG contacts, VD contacts, M0_rte segments, Vo structures, M1 segment routing segments (M1_rte segments), dummy isolation gates (discussed later) and BMo segment power grid segments (PG segments) (BM0_PG segments).

[0046] Through the integration of the BM0_PG segments, each of the cell functional areas 206D(1), 206D(2), and 208D(1) is an example of a backside power supply architecture (BSPD architecture). Fig. In 2D, it is assumed that none of the cell functional areas 206D(1) and 206D(2) as well as 208D(1) contain Mo segments that are PG segments. Advantages of a BSPD architecture include a reduced accumulation of Mo_rte segments on the front face, or the like. In some embodiments, selected Mo segments are PG segments (M0_PG segments).

[0047] In some embodiments, where the first and second arrangements refer to corresponding arrangements of the gate segments, MD contacts, VG contacts and VD contacts, the cell functional areas 206D(1) and 206D(2) are instances of a first arrangement of components configured to perform the given function; and the cell functional area 208D(1) is an instance of a second arrangement of components configured to perform the given function.

[0048] In Fig. In cell functional area 206D(2), unlike cell functional area 206D(1), cell functional area 2D contains a Vo structure and an M1_rte segment. In some embodiments where the first and second arrangements refer to corresponding arrangements of the gate segments, MD contacts, VG contacts, and VD contacts, the following applies to the Vo structures and the M1_rte segments: cell functional area 206D(2) is an instance of a first arrangement of components configured to perform the given function; cell functional area 208D(1) is an instance of a second arrangement of components configured to perform the given function; and the cell function area 206D(1) is a minor modification of the cell function area 206D(2), and thus the cell function area 206D(1) is considered a minor modification of the first arrangement of components.

[0049] In the macro area 202D of Fig. With respect to the x-axis, the left and right boundaries of cell functional areas 206D(1) and 206D(2), as well as 208D(1), each correspond to a dummy isolation gate (IDG) instead of corresponding gate segments. In some embodiments, a dummy isolation gate is a dielectric structure containing one or more dielectric materials and functioning as an electrical isolation structure. Accordingly, a dummy isolation gate is not an electrically conductive structure that functions, for example, as an active gate of a transistor. A dummy isolation gate contains one or more dielectric materials and functions as an electrical isolation structure. In some embodiments, a dummy isolation gate is based on a gate structure as a precursor. In some embodiments, a dummy gate structure includes a gate conductor, a gate isolation layer, (optionally) one or more spacers, or the like.In some embodiments, a dummy isolation gate is manufactured as follows: first, a gate structure, e.g., a dummy gate structure, is fabricated; sacrifice / remove (e.g., by etching) the gate conductor of the gate structure to create a trench; (optionally) remove a portion of a substrate that was previously located beneath the gate conductor to deepen the trench; and subsequently, fill the trench with one or more dielectric materials such that the physical dimensions of the resulting electrical isolation structure, i.e., the dummy isolation gate, are similar to the dimensions of the sacrificed dummy gate conductor, namely the gate conductor or the combination of the gate conductor and the portion of the substrate. In some embodiments, a dummy isolation gate is a dielectric structural element comprising one or more dielectric materials (e.g.,a dummy insulation gate contains an oxide, a nitride, an oxide nitride, or other suitable materials) and functions as an insulating element. In some embodiments, a dummy insulation gate is a continuous polysilicon-on-oxide diffusion edge structure and is referred to as a CPODE structure.

[0050] In Fig. In 2D, the boundaries of each of the cell functional areas 206D(1) and 206D(2) as well as 208D(1) in a corresponding device with one or more structural elements can be identified as follows. In some embodiments, an upper boundary of each of the cell functional areas 206D(1) and 206D(2) as well as 208D(1) is defined by a first reference line extending parallel to the x-axis and close to and parallel to a line representing the upper ends of a first majority of the gate segments, e.g., all gate segments in the example of Fig. 2D, intersects. In some embodiments, a lower boundary of each of the cell functional areas 206D(1) and 206D(2) as well as 208D(1) is defined by a second reference line extending parallel to the x-axis and close to and parallel to a line representing a second majority of the gate segments, e.g., all gate segments in the example of Fig. 2D, cuts. In some embodiments, such as in Fig. In 2D, a left and a right boundary of each of the cell function areas 206D(1) and 206D(2) as well as 208D(1) are defined by corresponding parts of the IDGs. In some embodiments, a left boundary of each of the cell function areas 206D(1) and 206D(2) as well as 208D(1) is defined by a third reference line extending parallel to the y-axis and close to and parallel to a line that defines the left ends of a first majority of the M0_rte segments, e.g., all M0_rte segments in the example of Fig. 2D, intersects; and a right boundary of each of the cell function areas 206D(1) and 206D(2) as well as 208D(1) is defined by a fourth reference line extending parallel to the y-axis and close to and parallel to a line that defines the right ends of a second majority of the M0_rte segments, e.g., all M0_rte segments in the example of Fig. 2D, intersects. In some embodiments, cell area boundaries are identified using dummy source / drain areas and / or dummy conductors. In some embodiments, cell area boundaries are identified using operating voltage lines (e.g., VDD rails or ground rails). In some embodiments, cell area boundaries are identified by locating positions that do not have certain types of interconnects. In some embodiments, boundaries are identified by empty spaces or dummy areas.

[0051] With respect to the y-axis, the lower boundary of the cell function range 208D(1) is also the upper boundary of the cell function range 206D(2). Fig. 2D is assumed to be the following: the upper alpha trace of cell functional area 208D(1) is alpha trace α6; the lower alpha trace of cell functional area 208D(1) is alpha trace α10; the upper alpha trace of cell functional area 206D(2) is alpha trace α11; and the lower alpha trace of cell functional area 206D(2) is alpha trace α15.

[0052] In Fig. In 2D, the gate segments are spaced apart with a uniform distance / pitch p_gate relative to the x-axis. The value for the pitch p_gate depends on the corresponding semiconductor process technology node. In some embodiments, the pitch p_gate represents a contacted polysilicon pitch (CPP) for the corresponding semiconductor process technology node. Here, the word "poly" in the term CPP does not necessarily mean that the gate structures in semiconductor devices corresponding to this are made of polysilicon. Fig. 2D or similar, must be made from polysilicon, but "poly" represents a historical convenience, i.e., "poly" is used because gate structures in ICs manufactured according to a predecessor semiconductor process technology node were often made from polysilicon.

[0053] In Fig. In 2D, the M0_rte segments are spaced apart from each other with a uniform distance / pitch p_M0_rte with respect to the y-axis. The value for the pitch p_M0_rte depends on the corresponding semiconductor process technology node. Fig. In 2D as well as in other layout diagrams disclosed herein, M0_rte segments that are aligned to one and the same of the alpha traces are referred to as alpha-co-aligned M0_rte segments.

[0054] In Fig. In 2D and other layout diagrams disclosed herein, VG contacts aligned with one and the same beta conductor track are referred to as beta-co-aligned VG contacts. With respect to the y-axis, adjacent beta-co-aligned VG contacts are spaced apart by a minimum gap_VG. In one embodiment, gap_VG is approximately equal to or greater than a smaller value of p_gate or twice p_M0_rte, such that min{≈(p_gate), ≈(2*p_M0_rte) ≤ gap_VG. In another approach to fabricating a device with a BSPD architecture, a minimum pendant gap (OA_gap_VG) between adjacent beta-co-aligned VG contacts is approximately equal to a pendant M0_rte gap (OA_p_M0_rte).The minimum pendant gap OA_gap_VG is so small that the other approach requires the use of two ELTVL masks to produce adjacent beta-co-aligned VG contacts of a corresponding device, where EUVL is an abbreviation for "Extreme Ultraviolet Lithography". In contrast, at least some embodiments, at least partly due to one or more of the design rules disclosed herein, use a relatively larger minimum gap between adjacent beta-co-aligned VG contacts, namely gap_VG, where a single EUVL mask is sufficient to produce adjacent beta-co-aligned VG contacts of a corresponding device, and accordingly, by omitting one EUVL mask, these embodiments are at least cheaper and / or faster to manufacture than with the other approach.

[0055] In Fig. In 2D and other layout diagrams disclosed herein, VD contacts aligned with one and the same beta conductor track are referred to as beta-co-aligned VD contacts. With respect to the y-axis, adjacent beta-co-aligned VD contacts are spaced apart by a minimum gap_VD. In one embodiment, gap_VD is approximately equal to or greater than a smaller value of p_gate or twice p_M0_rte, such that min{≈(p_gate), ≈(2*p_M0_rte) ≤ gap_VD. In another approach to fabricating a device with a BSPD architecture, a minimum pendant gap (OA_gap_VD) between adjacent beta-co-aligned VD contacts is approximately equal to a pendant M0_rte gap (OA_p_M0_rte). The minimum pendant gap OA_gap_VD is so small that the other approach requires the use of two ELTVL masks to create adjacent beta-co-aligned VD contacts of a corresponding device.In contrast, at least partly due to one or more of the design rules disclosed herein, at least some embodiments use a relatively larger minimum distance between adjacent beta-co-aligned VD contacts, namely gap_VD, where a single EUVL mask is sufficient to produce adjacent beta-co-aligned VD contacts of a corresponding device, and accordingly, by omitting an EUVL mask, these embodiments are at least cheaper and / or faster to manufacture than with the other approach.

[0056] In Fig. In 2D and other layout diagrams disclosed herein, Vo structures aligned with one and the same beta traces are referred to as beta-co-aligned Vo structures. With respect to the y-axis, adjacent beta-co-aligned Vo structures are spaced apart by a minimum gap_V0. In one embodiment, gap_V0 is approximately equal to or greater than a smaller value of p_gate or twice p_M0_rte, such that min{≈(p_gate), ≈(2*p_M0_rte) ≤ gap_V0. In another approach to fabricating a device with a BSPD architecture, a minimum pendant gap (OA_gap_V0) between adjacent beta-co-aligned Vo structures is approximately equal to a pendant M0_rte gap (OA_p_M0_rte). The pendant minimum distance OA_gap_V0 is so small that the other approach requires the use of two ELTVL masks to create adjacent beta-co-aligned Vo structures of a corresponding device.In contrast, at least partly due to one or more of the design rules disclosed herein, at least some embodiments use a relatively larger minimum distance between adjacent beta-co-aligned Vo structures, namely gap_V0, where a single EUVL mask is sufficient to produce adjacent beta-co-aligned Vo structures of a corresponding device, and accordingly, by omitting an EUVL mask, these embodiments are at least cheaper and / or faster to produce than with the other approach.

[0057] In Fig. In 2D and other layout diagrams disclosed herein, M1_rte segments aligned with the same beta conductor track are referred to as beta-co-aligned M1_rte segments. With respect to the y-axis, adjacent beta-co-aligned M1_rte segments are spaced apart by a minimum gap_M1_E2E. In one embodiment, gap_M1_E2E is significantly larger than p_M0_rte. In some embodiments, gap_M1_E2E is approximately twice p_M0_rte, such that ≈(2*p_M0_rte) ≤ gap_M1_E2E. In another approach to manufacturing a device with a BSPD architecture, a minimum pendant spacing (OA_gap_M1_E2E) is approximately equal to a minimum pendant spacing (OA_gap_M0) between adjacent M0_rte segments with respect to the y-axis.Regarding segments in a metallization layer, it generally becomes more difficult to divide / separate a longer precursor segment into two parts with adjacent ends spaced apart by a corresponding minimum E2E distance as end-to-end distances (E2E distances) decrease. At least partly due to one or more of the design rules disclosed herein, at least some embodiments employ a minimum distance between adjacent ends of beta-co-aligned M1_rte segments, namely gap_M1_E2E, to produce adjacent ends of beta-co-aligned M1_rte segments, where gap_M1_E2E is significantly larger than the counterpart minimum distance OA_gap_M1_E2E. Consequently, adjacent ends of beta-co-aligned M1_rte segments are at least easier and / or cheaper to produce than with the other approach.

[0058] In Fig. In 2D as well as in other layout diagrams disclosed herein, it is assumed that with respect to the y-axis, each cell function range (e.g., 206D(1) in Fig. 2D) has a height equal to six alpha traces, so that each cell functional area has five alpha traces (e.g., α1 to α5 in Fig. 2D), i.e., five rows of M0_rte segments overlap. In some embodiments, cell functional areas have a height equal to or greater than four alpha traces, such that each cell functional area overlaps at least three alpha traces.

[0059] Assuming a substantially uniform pitch for alpha traces, in another approach to fabricating a device with a BSPD architecture, a pendant cell functional area with a height equal to six alpha traces overlaps only four rows of pendant M0_rte segments. At least partially due to one or more of the design rules disclosed herein, in some embodiments a cell functional area with a height equal to six alpha traces overlaps five rows of M0_rte segments, thereby realizing an additional row of M0_rte segments compared to the other approach.Regarding the gate density of transistors fabricated in a given cell functional area, in some embodiments with the cell functional area having a height of six alpha traces and overlapping five rows of M0_rte segments, a gate density G_dens in the range of (≈1.04) ≤ G_dens ≤ (≈1.06) is achieved compared to the counterpart cell functional area in the other approach, which has a height of six alpha traces and overlaps only four rows of M0_rte segments, representing an improvement of about 4% to about 6%.

[0060] Between the first and second arrangement of Fig. In 2D, the following differences exist. All VD contacts and half of the VG contacts in cell functional areas 208D(1) and 206D(2) exhibit mirror symmetry with respect to a reference line 214(1) extending parallel to the x-axis. Exceptions to the VG / VD mirror symmetry between cell functional areas 208D(1) and 206D(2) include: the position of the VG contact at the intersection of alpha trace α10 and beta trace β7 in cell functional area 208D(1), and the position of the VG contact at the intersection of alpha trace α12 and beta trace β7 in cell functional area 206D(2). and the position of the VG contact at the intersection of the alpha conductor α9 and the beta conductor β9 in the cell functional area 208D(1) and the position of the VG contact at the intersection of the alpha conductor α14 and the beta conductor β9 in the cell functional area 206D(2).The Vo structures and the M1_rte segments show mirror symmetry with respect to a reference line 214(2) that extends parallel to the x-axis.

[0061] The differences between the first and second arrangements of Fig. 2D further includes the following: relative positions in cell functional areas 208D(1) and 206D(2) are relative with respect to the upper and lower boundaries in cell functional areas 208D(1) and 206D(2), respectively. Two alpha traces in each of cell functional areas 208D(1) and 206D(2) contain alpha-co-aligned M0_rte segments, but the relative positions of the two alpha traces (α7 and α9) in cell functional area 208D(1) are different from the relative positions of the two alpha traces (α12 and α13) in cell functional area 206D(2).Although the gap between the alpha-co-aligned M0_rte segments of the alpha conductor α7 in the cell function area 208D(1) and the gap between the alpha-co-aligned M0_rte segments of the alpha conductor α13 in the cell function area 206D(2) are each aligned to the beta conductor β5 and the gap between the alpha-co-aligned M0_rte segments of the alpha conductor α9 in the cell function area 208D(1) is aligned to the beta conductor β8, the gap between the alpha-co-aligned M0_rte segments of the alpha conductor α12 in the cell function area 206D(2) is aligned to the beta conductor β6.

[0062] Fig. 2E is a layout diagram of a macro area 202E according to some embodiments.

[0063] Macro area 202E is a variant of macro area 202D. Macro area 202E is an example of macro area 102. Fig. 1. In Fig. In 2E, a section line 4B - 4B' runs parallel to the x-axis. In some embodiments, the section line 4B - 4B' corresponds to Fig. 2E of a sectional view 420B of Fig. 4B.

[0064] For the sake of simplicity, macro 202E does not contain the active regions (ARs), the Vo structures, or the M1_rte segments, unlike macro 202D. Furthermore, macro 202E does contain cut-gate segment shapes (CG shapes) and cut-MD contact shapes (CMD shapes), unlike macro 202D.

[0065] In Fig. In Figure 2E, as well as in other layout diagrams disclosed herein, gate segments aligned with one and the same beta traces are referred to as beta-co-aligned gate segments. Adjacent beta-co-aligned gate segments result from subdividing / splitting a longer precursor segment into two parts with adjacent ends spaced apart by an appropriate minimum distance, with CG shapes serving to indicate where a longer precursor segment (not shown) would be subdivided / split.

[0066] With respect to the y-axis, adjacent ends of beta-co-aligned gate segments are spaced apart by a minimum distance h_CG, where h_CG also represents a height of the CG shape. In some embodiments, h_CG is approximately equal to p_M0_rte, so h_CG ≈ p_M0_rte. According to another approach to fabricating a device with a BSPD architecture, a minimum pendant distance (OA_h_CG) between adjacent ends of beta-co-aligned pendant gate segments is approximately equal to the minimum pendant distance (OA_gap_M0) between adjacent pendant Mo_rte segments with respect to the y-axis. In general, for segments in a metallization layer with decreasing end-to-end distances (E2E distances), the difficulty of subdividing / separating a longer precursor segment into two parts that have adjacent ends spaced apart by a corresponding minimum E2E distance increases.In at least some embodiments, a minimum distance between adjacent ends of beta-co-aligned gate segments, namely h_CG, is used to fabricate adjacent ends of beta-co-aligned gate segments, where h_CG is significantly larger than the counterpart minimum distance OA_h_CG. This makes it at least easier and / or cheaper to fabricate adjacent ends of beta-co-aligned gate segments than with the other approach.

[0067] In Fig. In Figure 2E and other layout diagrams disclosed herein, MD contacts aligned with one and the same beta traces are referred to as beta-co-aligned MD contacts. Adjacent beta-co-aligned MD contacts result from subdividing / splitting a longer precursor segment into two parts with adjacent ends spaced apart by an appropriate minimum distance, with CMD shapes serving to indicate where a longer precursor segment (not shown) would be subdivided / split.

[0068] With respect to the y-axis, adjacent ends of beta-co-aligned MD contacts are spaced apart by a minimum distance h_CMD, where h_CMD also represents a height of the CMD shape. In some embodiments, h_CMD is approximately equal to p_M0_rte, so h_CMD ≈ p_M0_rte. According to another approach to fabricating a device with a BSPD architecture, a minimum pendant distance (OA_h_CMD) between adjacent ends of beta-co-aligned MD contacts is approximately equal to the minimum pendant distance (OA_gap_M0) between adjacent pendant M0_rte segments with respect to the y-axis. In general, for segments in a metallization layer with decreasing end-to-end distances (E2E distances), the difficulty of subdividing / separating a longer precursor segment into two parts that have adjacent ends spaced apart by a corresponding minimum E2E distance increases.In at least some embodiments, a minimum distance between adjacent ends of beta-co-aligned MD contacts, namely h_CMD, is used to manufacture adjacent ends of beta-co-aligned MD contacts, where h_CMD is significantly larger than the pendant minimum distance OA_h_CMD. This makes manufacturing adjacent ends of beta-co-aligned MD contacts at least easier and / or cheaper than with the other approach.

[0069] In Fig. 2E is a macro area, a representation of a third and a fourth design rule (DR) that belong to macro area 202D of Fig. 2D, as outlined below.

[0070] In Fig. In 2E, the third design rule applies to the first alpha trace of each of the cell functional areas 206D(1) and 206D(2), as well as 208D(1). In connection with cell functional areas 206D(1) and 206D(2), as well as 208D(1), the first alpha traces are referred to as the lower alpha traces. In cell functional areas 206D(1) and 206D(2), as well as 208D(1), the lower alpha traces are alpha traces α5, α10, and α15. The third design rule specifies that the lower alpha trace must not have a CMD-oriented shape. In some embodiments, the third design rule is referred to as a CMD-undesired trace design rule.

[0071] In Fig. In 2E, the fourth design rule applies to the second alpha trace of each of the cell functional areas 206D(1) and 206D(2), as well as 208D(1) and 208D(2). In connection with cell functional areas 206D(1) and 206D(2), as well as 208D(1), the first alpha traces are referred to as upper alpha traces. In cell functional areas 206D(1) and 206D(2), as well as 208D(1) and 208D(2), the upper alpha traces are alpha traces α1, α6, and α11. The fourth design rule specifies that the upper alpha trace must not have a CG-oriented shape. In some embodiments, the fourth design rule is referred to as a CG-undesired trace design rule.

[0072] Fig. 3A is a layout diagram of a macro area 302A according to some embodiments.

[0073] Macro area 302A is an example of macro area 102 from Fig. 1.

[0074] Macro area 302A contains cell function areas (FN areas) 306A(1) and 306A(2), as well as 308A(1) and 308A(2), which are stacked with respect to the y-axis. Cell function area 306A(2) is stacked on top of cell function area 308A(2). Cell function area 308A(1) is stacked on top of cell function area 306A(2). Cell function area 306A(1) is stacked on top of cell function area 308A(1). Cell function areas 306A(1) and 306A(2), as well as 308A(1) and 308A(2), are also referred to as interlocking cell function areas with respect to the y-axis.

[0075] Each of the cell function areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) is set up such that it can perform a given function, e.g. AOI (see e.g. Fig. 5A). That is, each of the cell function ranges 306A(1) and 306A(2) as well as 308A(1) and 308A(2) is set up to perform the same function.

[0076] The components (see e.g. Fig. 3B and Fig. 3C), which are contained in each of the cell functional areas 306A(1) and 306A(2) and 308A(1) and 308A(2), include the following: Gate segments (see e.g. Fig. 3B and Fig. 3C); MD contacts (see e.g. Fig. 2B and Fig. 2E); VG contacts (see e.g. Fig. 2C to 2E); VD contacts (see e.g. Fig. 2B, Fig. 2D and Fig. 2E); Mo_rte segments; some of the M0_rte segments that are input / output pin Mo segments (Mo_pin segments); and Vo structures. In Fig. In 3A and other figures revealed here, the Vo structures are aligned to corresponding alpha and beta traces.

[0077] Cell function areas 306A(1) and 306A(2) are instances of a third arrangement of components configured to perform the given function. Cell function areas 308A(1) and 308A(2) are instances of a fourth arrangement of components configured to perform the given function.

[0078] In some embodiments, the third and fourth arrangements refer to corresponding arrangements of the gate segments, MD contacts, Vo contacts, and Mo_pin segments. In some embodiments, the third and fourth arrangements refer to corresponding arrangements of the gate segments, MD contacts, Vo contacts, and Mo_pin segments, as well as non-pin Mo_rte segments.

[0079] Examples of differences between the third and fourth arrangements are discussed below. Although the third and fourth arrangements are different, they also share common properties. One such property is that the VD structures correspond to even-numbered beta traces (e.g., beta traces β2 to β10 of the Fig. 3D and Fig. 3E) are aligned. A second property that the third and fourth arrangements have in common is in the Fig. 3B and Fig. 3C shown.

[0080] The Fig. 3B and Fig. 3C are layout diagrams of corresponding cell function areas 310B and 310C according to some embodiments.

[0081] In the Fig. 3B and Fig. 3C is each of the cell function areas 310B and 310C, an example of the cell function areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) of Fig. 3A. Cell function areas 310B and 310C are representations of a corresponding fifth and sixth design rule, which correspond to the third and fourth arrangement of Fig. 3A, as set out below.

[0082] In the Fig. 3A and Fig. 3B refers to the fifth design rule on the first alpha trace of each of the cell functional areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) of Fig. 3A and cell functional area 310B of Fig. 3B. In connection with the cell functional areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) of Fig. 3A and the cell functional area 310B of Fig. In cell 3B, the first alpha traces are referred to as lower alpha traces. In cell functional areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) of Fig. 3A and the cell functional area 310B of Fig. In 3B, the lower alpha traces are alpha traces α5, α10, and α20. The fifth design rule specifies that the lower alpha trace must not have a V0 structure aligned with it. In some embodiments, the fifth design rule is referred to as a Vo-structure-undesired-trace design rule.

[0083] In the Fig. 3A and Fig. 3C refers to the sixth design rule on the second alpha trace of each of the cell functional areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) of Fig. 3A and cell functional area 310C of Fig. 3C. In connection with the cell functional areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) of Fig. 3A and the cell functional area 310B of Fig. In cell 3C, the second alpha traces are referred to as upper alpha traces. This applies to cell functional areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2). Fig. 3A and the cell functional area 310B of Fig. Let 3C be the upper alpha traces α1, α11, and α16. The sixth design rule specifies that the upper alpha trace must not contain any Mo_pin segments aligned with it. In some embodiments, the sixth design rule is referred to as an M0_pin undesired trace design rule.

[0084] In the cell function areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) of Fig. 3A and the cell functional area 310B of Fig. 3B Vo structures are permitted in the upper alpha trace and in each of the inner alpha traces located between the upper and lower alpha traces. For example, the inner alpha traces are alpha traces α2 to α4 in each of the Fig. 3B and Fig. 3C. In other words, in the cell function areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) of Fig. 3A, in the cell functional area 310C of Fig. 3C and the cell functional area 310B of Fig. 3B, each of the alpha conductor paths α1 to α4 is a Vo-permissible alpha conductor path.

[0085] In the cell function areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) of Fig. 3A, in the cell functional area 310C of Fig. 3C and the cell functional area 310B of Fig. 3B, Mo_pin segments are allowed in the lower alpha trace and in each of the inner alpha traces. In other words, in the cell function areas 306A(1) and 306A(2) as well as 308A(1) and 308A(2) of Fig. 3A, in the cell functional area 310C of Fig. 3C and the cell functional area 310B of Fig. 3B each of the alpha traces α2 to α5 is a Mo_pin-permissible alpha trace.

[0086] The second common characteristic of the third and fourth arrangements, which was discussed above in the discussion of Fig. 3A have been named, is in the Fig. 3B and Fig. 3C shown.

[0087] In each of the cell functional areas 310B and 310C, Vo structures are present in each of the inner alpha pathways, specifically in alpha pathways α2 to α4 in each of the Fig. 3B and Fig. 3C, permissible. In each of the cell functional areas 310B and 310C, M0_pin segments are present in each of the inner alpha traces, specifically (also) in the alpha traces α2 to α4 in each of the Fig. 3B and Fig. 3C, permissible. Thus, the third common property of the third and fourth arrangements is that the Vo structures and / or the M0_pin segments in each of the alpha traces α2 to α4 in each of the Fig. 3B and Fig. 3C are permissible. In other words, as in the Fig. 3B and Fig. As shown in Figure 3C, the third common property of the third and fourth arrangements is that each of the alpha traces α2 to α4 is a Vo-permissible alpha trace and an M0_pin-permissible alpha trace.

[0088] The Fig. 4A and Fig. 4B are corresponding cross-sections 420A or 420B of a part of a device according to some embodiments.

[0089] In some embodiments, the part of the device that Fig. 4A and Fig. 4B is an example of a part of a device shown in the layout diagrams of the Fig. 2D and Fig. 2E based. The device of the Fig. 4A and Fig. 4B is an example of device 100 from Fig. 1. In some embodiments, the cross-section 420A corresponds to a section line 4A - 4A' of Fig. 2D. In some embodiments, the cross-section 420B corresponds to a section line 4B - 4B' of Fig. 2E.

[0090] Fig. 5A is a compilation of three layout diagrams according to some embodiments. Fig. 5B and Fig. 5C are corresponding block diagrams according to some embodiments.

[0091] Fig. 5A contains cell functional areas 506 and 508 and an intermediate cell area 516. Fig. 5B represents a spatial reorganization in the intermediate cell 516 in comparison to the cell functional area 506. Fig. 5C represents a spatial reorganization in the cell functional area 506 compared to the intermediate cell 516.

[0092] Each of the cell function ranges 506 and 508 is configured to execute a given function. In the example of Fig. In cell 5A, each of the cell function ranges 506 and 508 is configured to execute the logical AND-OR-INVERT function (AOI function). That is, each of the cell function ranges 506 and 508 is configured to execute the same function, namely AOI.

[0093] In some embodiments, each of the cell functional areas 506 and 508 is configured as an AOI22D1 cell area. In some embodiments, AOI22DX is an alphanumeric text sequence intended to imply that the corresponding cell area is an AOI cell area for which the drive strength is DX, where X is a multiple of a unit drive strength D. Fig. 5A assumes that X equals one (X = 1).

[0094] Cell function area 506 is an instance of a first arrangement of components configured to perform the AOI function. Cell function area 508 is an instance of a second arrangement of components configured to perform the AOI function. The first and second arrangements allow for an interlocking / mixed stacking of these cell function areas with respect to the y-axis.

[0095] Let us remember that Fig. Figure 5B represents a spatial rearrangement in the intermediate cell 516 compared to the cell functional area 506. An axis of symmetry is represented as a reference line 214(3) running parallel to the x-axis. The reference line 214(3) is located essentially midway between the alpha traces α3 and α4 with respect to the y-axis. Considering that the symbol ρ represents the Greek letter Rho, lines ρ0 to ρ4 of the cell functional area 506 are rotated around the reference line 214(3), resulting in lines ρ0' to ρ4' in the intermediate cell area 516.

[0096] Let us remember that Fig. 5C represents a spatial rearrangement in cell function area 508 compared to the intermediate cell 516. The VG contact at the intersection of row ρ4' and beta trace β7 is shifted to the intersection of row ρ2' and beta trace β7. The gap between the alpha-co-aligned M0_rte segments in row ρ3' (between beta traces β7 and β9) is shifted to the intersection of row ρ2' and beta trace β6. The line ρ4' is moved from a position where it is collinear with the alpha trace α0 to its original position where it is collinear with the alpha trace α0, resulting in a line ρ4". The VG contact at the intersection of line ρ3' and beta trace β9 is moved to the intersection of line ρ4" and beta trace β9.

[0097] Fig. Figure 6 is a flowchart of a method 600 for manufacturing a system or device according to some embodiments.

[0098] According to some embodiments, the method 600 can be used, for example, with an EDA system 800 ( Fig. 8; will be discussed later) and an IC manufacturing plant 900 ( Fig. 9; discussed later) implementable. Examples of an FNCR embedded with an FTCR that can be fabricated by Method 600 include the FTCR-embedded FNCRs disclosed herein, or the like.

[0099] In Fig. Section 6 comprises method 600 blocks 602 and 604. In block 602, a layout diagram is generated which includes, among other things, one or more layout diagrams corresponding to one or more of the cell function areas disclosed herein, one or more of the cell macro areas disclosed herein, or the like. According to some embodiments, block 602 can be used, for example, with the EDA system 800 ( Fig. 8; discussed later) implementable. From block 602, the process continues to block 604.

[0100] In block 604, based on the layout diagram, at least one of the following operations is performed: (A) performing one or more photolithographic exposures; (B) producing one or more photolithographic masks; and (C) producing one or more components in a layer of a device, e.g., manufacturing a fixture. See the later discussion of IC manufacturing plant 900 in Fig. 9.

[0101] The Fig. 7A and Fig. 7B are corresponding parts of a flowchart of a method 700 for manufacturing a device according to some embodiments.

[0102] Procedure 700 is an example of block 604 (see Fig. 6, which has been discussed above). For example, process 700 is compatible with IC manufacturing plant 900 (see Fig. 9 (discussed later) can be implemented according to some embodiments. Examples of devices that can be manufactured using Method 700 include devices that contain one or more of the cell functional areas disclosed herein, one or more of the cell macro areas disclosed herein, or the like. Method 700 comprises Blocks 710 to 744.

[0103] Block 710 contains active areas (see e.g. Fig. 2D, Fig. 4A and Fig. 4B) is generated, which extend in a first direction (e.g., parallel to the x-axis). From block 710, the process continues to block 712.

[0104] In block 712, gate segments are used (see e.g. Fig. 2A to 2E, 4A and 4B), extending in a second direction perpendicular to the first direction (e.g., parallel to the y-axis), were manufactured and inserted, with the gate segments having portions over areas of the active regions. The process continues from block 712 to block 714.

[0105] Block 714 contains MD contacts (see e.g. Fig. 2E, Fig. 4A and Fig. 4B), extending in the second direction, were manufactured and inserted, with the MD contacts having parts over areas of the active regions. From block 714, the process continues to block 716.

[0106] Block 716 contains VG contacts (see e.g. Fig. 2C to 2E, 4A and 4B) are produced via areas of the gate segments. From block 716, the process continues to block 718.

[0107] In block 718, VG contacts are arranged so that they are aligned with the corresponding alpha traces, with the exception that the first alpha trace (see, for example, alpha traces α1, α6, α11, and α16) is located in the Fig. 2A to 2C) does not have a VG contact aligned with this. The process continues from block 718 to block 720.

[0108] In block 720, adjacent beta-co-aligned VG contacts are spaced apart by a gap_VG (see e.g. Fig. 2D). From block 720, the process continues to block 722.

[0109] In block 722, VD contacts are used (see e.g. Fig. 2C to 2E, 4A and 4B) via areas of the MG contacts. Block 722 comprises blocks 724 and 726. In block 722, the process continues to block 724.

[0110] In block 724, VD contacts are arranged so that they are aligned with the corresponding alpha traces, with the exception that the last alpha trace (see, for example, alpha traces α5, α10, α15, and α20) is aligned accordingly in the Fig. 2A to 2E) does not have a VD contact aligned for this purpose. From block 724, the process continues to block 726.

[0111] In block 726, adjacent beta-co-aligned VD contacts are spaced apart by a gap_VD (see e.g. Fig. 2D). After block 726, the sequence leaves block 722 and continues to block 728.

[0112] In block 728, a first metallization layer (see e.g. METo in the Fig. 4A and Fig. 4B) M0_rte segments (see e.g. Fig. 2B to 2E, 3B, 3C, 4A and 4B), extending in the first direction (e.g., parallel to the x-axis), are manufactured, aligned according to the alpha conductors (see, e.g., α0, α1, ...) and arranged accordingly over the VG contacts or the VD contacts. Block 728 comprises blocks 730 and 732. The process continues from block 728 to block 730.

[0113] In block 730, adjacent M0_rte segments are spaced apart from each other with a pitch p_M_rte with respect to the y-axis (see e.g. Fig. 2D). From block 730, the process continues to block 732.

[0114] In block 732, M0_pins, i.e., pins of the M0_rte segments, are arranged so that they are aligned with corresponding alpha traces, except that the first alpha trace (see, for example, alpha trace α1 of Fig. 3C) does not have a Mo_pin segment contact aligned for this purpose. After block 732, the sequence leaves block 728 and continues to a terminal block 733. From terminal block 733 of Fig. 7A the process continues to a connection block 733 in Fig. Continue to 7B.

[0115] In Fig. 7B continues the process from terminal block 733 to block 734.

[0116] In block 734, a first buried metallization layer (e.g., BMET0 in the Fig. 4A and Fig. 4B) BM0_PG segments (see e.g. Fig. 2D, Fig. 2E, Fig. 4A and Fig. 4B) are produced, extending in the first direction (e.g., parallel to the x-axis). The process continues from block 734 to block 736.

[0117] Block 736 contains Vo structures (see e.g. Fig. 2D, Fig. 3B and Fig. 4A) is produced over areas of the M0_rte segments and aligned to the corresponding beta conductor tracks (see e.g. β4). Block 736 comprises blocks 738 and 740. The process continues from block 736 to block 738.

[0118] In block 738, Vo structures are arranged so that they are aligned with the corresponding alpha traces, with the exception that the last alpha trace (see, for example, alpha traces α5, α10, α15, and α20) is positioned accordingly in the Fig. 2D and 3A to 3C) do not have a Vo structure that is aligned with this. From block 738, the process continues to block 740.

[0119] In block 740, adjacent beta-co-aligned Vo structures are spaced apart by a gap_V0 (see e.g. Fig. 2D). After block 740, the sequence leaves block 736 and continues to block 742.

[0120] In block 742, a second metallization layer (see e.g. MET1 in the Fig. 4A and Fig. 4B) M1_rte segments (see e.g. Fig. 2D and Fig. 4A), extending in the second direction (e.g., parallel to the y-axis), are manufactured, aligned with the beta traces (see, e.g., β4), and arranged accordingly above the Vo structures. Block 742 contains a block 744. The process continues from block 742 to block 744.

[0121] In block 744, adjacent ends of M1_rte segments are spaced apart with a gap_M1_E2E relative to the y-axis (see e.g. Fig. 2D). From block 730, the process continues to block 732.

[0122] Fig. Figure 8 is a block diagram of an EDA system 800 (EDA: Design Automation of Electronic Systems) according to some embodiments.

[0123] In some embodiments, the EDA system 800 is an APR system (APR: automatic placement and tracing). In some embodiments, the EDA system 800 is a general-purpose computing device with a processor 802 (e.g., a hardware processor) and a non-volatile, machine-readable storage medium 804. The storage medium 804 is encoded, among other things, with computer program code 806, i.e., a set of executable instructions. The execution of the instructions 806 with the processor 802 is carried out (at least partially) by an EDA tool that implements, for example, part or all of one or more methods for generating layout diagrams according to the layout diagrams disclosed herein or the like, according to one or more embodiments (hereinafter: "the specified processes and / or methods").

[0124] The 804 storage medium stores, among other things, layout diagrams 811, such as the layout diagrams revealed here, or the like.

[0125] The processor 802 is electrically connected to the machine-readable storage medium 804 via a bus 808. The processor 802 is also electrically connected to an I / O interface 810 via the bus 808. Furthermore, a network interface 812 is electrically connected to the processor 802 via the bus 808. The network interface 812 is connected to a network 814, enabling the processor 802 and the machine-readable storage medium 804 to connect to external elements via the network 814. The processor 802 is configured to execute the computer program code 806, which is encoded in the machine-readable storage medium 804, so that the EDA system 800 can be used to perform some or all of the specified processes and / or procedures.In one or more embodiments, the 802 processor is a main processor (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or another suitable processing unit.

[0126] In one or more embodiments, the machine-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device). The storage medium 804 comprises, for example, a semiconductor or solid-state memory, a magnetic tape, a removable disk, a random-access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments in which optical disks are used, the storage medium 804 comprises a compact disc read-only memory (CD-ROM), a compact disc read / write (CD-R / W), and / or a digital video disk (DVD).

[0127] In one or more embodiments, the storage medium 804 stores computer program code 806 configured such that the EDA system 800 (where processing is at least partially carried out by the EDA tool) can be used to perform some or all of the specified processes and / or procedures. In one or more embodiments, the storage medium 804 also stores information enabling the performance of some or all of the specified processes and / or procedures. In one or more embodiments, the storage medium 804 stores a library 807 of standard cells comprising standard cells corresponding to components of the layout diagrams disclosed herein.The storage medium 804 stores one or more layout diagrams 816, such as one or more layout diagrams corresponding to the layout diagrams disclosed herein, one or more compiled macros based on layout diagrams comprising one or more of the layout diagrams disclosed herein, or the like.

[0128] The EDA system 800 has an I / O interface 810. The I / O interface 810 is connected to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor keys for sending information and commands to the processor 802.

[0129] The EDA System 800 also features the Network Interface 812, which is connected to the Processor 802. The Network Interface 812 allows the EDA System 800 to communicate with the Network 814, to which one or more other computer systems are connected. The Network Interface 812 includes wireless network interfaces, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or wired network interfaces, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the specified processes and / or procedures are implemented in two or more EDA Systems 800.

[0130] The EDA system 800 is configured to receive information via the I / O interface 810. The information received via the I / O interface 810 includes commands, data, design rules, libraries of standard cells, and / or other parameters for processing by the processor 802. This information is sent to the processor 802 via the bus 808. The EDA system 800 is also configured to receive user interface (UI) information via the I / O interface 810. This information is stored on the machine-readable medium 804 as a UI 842.

[0131] In some embodiments, some or all of the specified processes and / or procedures are implemented as an independent software application for execution by a processor. In some embodiments, some or all of the specified processes and / or procedures are implemented as a software application that is part of another software application. In some embodiments, some or all of the specified processes and / or procedures are implemented as a plug-in for a software application. In some embodiments, at least one of the specified processes and / or procedures is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the specified processes and / or procedures are implemented as a software application used by the EDA System 800. In some embodiments, a layout containing standard cells is created using a tool such as VIRTUOSO.® , which is supplied by CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0132] In some embodiments, the processes are implemented as functions of a program stored on a non-volatile, machine-readable recording medium. Examples of non-volatile, machine-readable recording media include external / removable and / or internal / built-in storage units, such as an optical disc like a DVD, a magnetic disk like a hard drive, a semiconductor memory like a ROM, RAM, and / or a memory card, or the like.

[0133] Fig. Figure 9 is a block diagram of an IC manufacturing plant 900 (IC: integrated circuit) and an associated IC manufacturing process according to some embodiments.

[0134] In some embodiments, the IC manufacturing system 900 implements the technology based on the one described in block 602 of Fig. The layout diagram 6 generated block 604 of Fig. 6, in which (A) one or more semiconductor masks and / or (B) at least one component in a layer of an unfinished integrated semiconductor circuit are fabricated using the fabrication system 900. In some embodiments, the IC fabrication system 900 implements the flowcharts of the Fig. 7A and Fig. 7B or the like.

[0135] In Fig. Figure 9 of the IC manufacturing facility 900 comprises units, such as a design house 920, a mask house 930, and an IC manufacturer (“microchip factory”) 950, which interact with each other in the design, development, and manufacturing cycles and / or in the services associated with the manufacture of an IC device 960. The units in the facility 900 are connected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network comprises many different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each unit interacts with one or more of the other units, providing services to and / or receiving services from one or more of the other units.In some embodiments, two or more of the units Design House 920, Mask House 930, and IC Factory 950 are owned by a single larger company. In some embodiments, two or more of the units Design House 920, Mask House 930, and IC Factory 950 exist side-by-side in a shared facility and utilize common resources.

[0136] Design House (or Design Team) 920 creates an IC design layout 922. The IC design layout 922 contains various geometric structures designed for an IC device 960. These geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 960 to be manufactured. The different layers together form various IC structural elements. For example, part of the IC design layout 922 includes various IC structural elements, such as an active region, a gate terminal, a source and drain, metal traces or vias of an interlayer connection, and openings for bond pads to be fabricated in a semiconductor substrate (such as a silicon wafer) and various material layers arranged on the semiconductor substrate.Source / drain areas can, depending on the context, individually or collectively designate a source or a drain. Design House 920 implements a suitable design process for generating the IC design layout 922. This design process includes a logic design, a physical design, or placement and routing. The IC design layout 922 is represented in one or more data files containing information about the geometric structures. For example, the IC design layout 922 is represented in a GDSII or DFII file format.

[0137] In the mask house 930, data preparation 932 and mask fabrication 934 are performed. The mask house 930 uses the IC design layout 922 to fabricate one or more masks 935, which are to be used for fabricating the various layers of the IC device 960 according to the IC design layout 922. The mask house 930 performs data preparation 932, in which the IC design layout 922 is translated into a representative data file (RDF). During mask data preparation 932, the RDF is made available for mask fabrication 934. A mask writer is used in mask fabrication 934. A mask writer converts the RDF into an image on a substrate, such as a mask (reticule) or a semiconductor wafer. The design layout is manipulated during mask data preparation 932 so that it corresponds to certain properties of the mask writer and / or meets the requirements of the IC factory 950. In Fig.Figure 9 shows the mask data preparation 932, the mask production 934, and the mask 935 as separate elements. In some embodiments, the mask data preparation 932 and the mask production 934 can be referred to collectively as mask data preparation.

[0138] In some embodiments, the mask data preparation 932 includes optical proximity correction (OPC), for which lithographic enhancement methods are used to compensate for image defects such as those that may arise from diffraction, interference, other process effects, and the like. The IC design layout 922 is adapted by the OPC. In some embodiments, the mask data preparation 932 includes further resolution enhancement methods (RETs), such as off-axis exposure, partial resolution adjustment elements, phase-shift masks, other suitable methods, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats the OPC as an inverse imaging problem.

[0139] In some embodiments, during mask data preparation 932, a mask rule checker (MRC) verifies the IC design layout 922, which has undergone processes in the OPC, against a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to accommodate variability in semiconductor manufacturing processes and the like. To comply with the mask generation rules, in some embodiments the MRC modifies the IC design layout 922 to compensate for constraints encountered during mask fabrication 934 that may undo some of the modifications made by the OPC.

[0140] In some embodiments, the mask data preparation 932 includes a lithography process check (LPC) that simulates the machining operations implemented by the IC factory 950 to manufacture the IC fixture 960. In the LPC, this machining is simulated based on the IC design layout 922 to produce a simulated manufactured fixture, such as the IC fixture 960. The machining parameters in the LPC simulation may include: parameters associated with various processes of the IC manufacturing cycle; parameters associated with tools used to manufacture ICs; and / or other aspects of the manufacturing process. The LPC considers various factors, such as intermediate image contrast, depth of field (DOF), mask defect improvement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, if, after the fabrication of a simulated manufactured device by LPC, the simulated device deviates too much from compliance with the design rules with regard to its shape, the OPC and / or the MRC must be repeated to further improve the IC design layout 922.

[0141] The preceding description of the mask data preparation 932 has been simplified for clarity. In some embodiments, the mask data preparation 932 includes further elements, such as a logical operation (LOP), to modify the IC design layout 922 according to the manufacturing rules. Furthermore, the processes used for the IC design layout 922 during the mask data preparation 932 can be performed in many different sequences.

[0142] Following mask data preparation 932 and during mask fabrication 934, a mask 935 or a group of masks 935 is fabricated based on the modified IC design layout. In some embodiments, an electron beam or a multi-electron beam mechanism is used to generate a structure on a mask (photomask or reticule) based on the modified IC design layout. The masks are fabricated using various technologies. In some embodiments, the mask is fabricated using binary technology. In some embodiments, a mask structure has opaque and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose a photosensitive material layer (e.g., photoresist) deposited on a wafer, is blocked by the opaque region and passes through the transparent regions.In one example, a binary mask has a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) applied to the opaque areas of the mask. In another example, the mask is fabricated using phase-shift technology. In a phase-shift mask (PSM), various elements in the structure created on the mask are configured to have a phase difference suitable for improving resolution and image quality. In various examples, the phase-shift mask can be a mask with a reduced phase shift or a mask with a variable phase shift. The masks produced by the 934 mask fabrication process are used in many different processes.Such masks are used, for example, in an ion implantation process to create different doped areas in the semiconductor wafer, in an etching process to create different etched areas in the semiconductor wafer and / or in other suitable processes.

[0143] IC Factory 950 is an IC manufacturing company that has one or more production facilities for manufacturing many different IC products. In some embodiments, IC Factory 950 is a semiconductor manufacturing facility. For example, there might be one production facility for the front-end manufacturing of multiple IC products [front-end-of-line manufacturing (FEOL manufacturing)], while a second production facility might handle the back-end manufacturing for connecting and packaging the IC products [back-end-of-line manufacturing (BEOL manufacturing)], and a third production facility might provide other services for the manufacturing operation.

[0144] In IC Factory 950, one or more masks 935 produced by Mask House 930 are used to manufacture IC Device 960 using manufacturing tools 952. Thus, IC Factory 950 uses, at least indirectly, the IC design layout 922 to manufacture IC Device 960. In some embodiments, the semiconductor wafer 953 is produced by IC Factory 950 using one or more masks 935 to manufacture IC Device 960. The semiconductor wafer 953 has a silicon substrate or other suitable substrate on which layers of material are produced. The semiconductor wafer 953 further has one or more different doped regions, dielectric structural elements, multi-layer interconnects, and the like (which are produced in later manufacturing steps).

[0145] In some embodiments, a cell region (of a device) comprises: active regions extending in a first direction; gate segments and metal source / drain region contacts (MD contacts) extending in a second direction perpendicular to the first direction, intermingled and having portions over areas of the active regions; via-hole gate contacts (VG contacts) over areas of the gate segments; via-hole MD contact contacts (VD contacts) over areas of the MD contacts, the VG contacts and the VD contacts being oriented accordingly to alpha traces extending in the first direction; in a first metallization layer on a first side of the active regions, first trace segments (RTE segments) extending in the first direction, being oriented accordingly to the alpha traces and arranged accordingly over the VG contacts or the VD contacts;and in a first buried metallization layer on a second side of the active areas, first buried power grid segments extending in the first direction. A first and a second of the alpha traces are adjacent to a first and a second boundary of the cell area. At least a third of the alpha traces is located between the first and the second alpha trace. The first alpha trace has no VG contacts aligned with it, and the second alpha trace has no VD contacts aligned with it.

[0146] In some embodiments, the gate segments are aligned with beta traces extending in the second direction. With respect to the first direction, adjacent gate segments are spaced apart by a first pitch. With respect to the second direction, adjacent first RTE segments are spaced apart by a second pitch. Regarding some of the VD contacts aligned with the same beta traces (beta-co-aligned VD contacts), adjacent beta-co-aligned VD contacts are spaced apart by a gap approximately equal to or greater than a smaller value of the first pitch or twice the second pitch.

[0147] In some embodiments, the gate segments are aligned with beta traces extending in the second direction. With respect to the first direction, adjacent gate segments are spaced apart by a first pitch. With respect to the second direction, adjacent first RTE segments are spaced apart by a second pitch. Regarding some of the VG contacts aligned with the same beta traces (beta-co-aligned VG contacts), adjacent beta-co-aligned VG contacts are spaced apart by a gap approximately equal to or greater than a smaller value of the first pitch or twice the second pitch.

[0148] In some embodiments, the cell area further comprises the following: in a first interconnect layer, first contacts that are aligned with the alpha traces and arranged accordingly over the first RTE segments. One or more of the first RTE segments are first input / output (pin) segments. The first alpha trace does not have any of the first pin segments aligned with it, and the second alpha trace does not have any of the first contacts aligned with it.

[0149] In some embodiments, the gate segments are aligned with beta traces extending in the second direction. With respect to the first direction, adjacent gate segments are spaced apart by a first pitch. With respect to the second direction, adjacent first RTE segments are spaced apart by a second pitch. Regarding some of the first contacts aligned with the same beta traces (beta-co-aligned first contacts), adjacent beta-co-aligned first contacts are spaced apart by a gap approximately equal to or greater than a smaller value of the first pitch or twice the second pitch.

[0150] In some embodiments, the cell area further comprises: in a second metallization layer, second RTE segments extending in the second direction, aligned with beta conductors, and positioned over the first contacts. With respect to the second direction, adjacent first RTE segments are spaced apart by a first pitch. Regarding some of the second RTE segments aligned with the same direction as the beta conductors (beta-co-aligned second RTE segments), adjacent ends of beta-co-aligned second RTE segments are spaced apart by a first gap equal to or greater than the first pitch.

[0151] In some embodiments, the gate segments, MD contacts, VG contacts and VD contacts of the cell area can be arranged in a first or a second arrangement, wherein, in the case that they are arranged according to the first or the second arrangement, the cell area is configured to perform the same function.

[0152] In some embodiments, if the gate segments, MD contacts, VG contacts and VD contacts of the cell area are arranged in the first or second arrangement, the cell area is configured to perform the same AND-OR-INVERT function (AOI function).

[0153] In some embodiments, a cell region (of a device) comprises: active regions extending in a first direction; gate segments and metal source / drain region contacts (MD contacts) extending in a second direction perpendicular to the first direction, intermingled and having portions over areas of the active regions; via-gate contacts (VG contacts) over areas of the gate segments; via-MD contact contacts (VD contacts) over areas of the MD contacts, the VG contacts and the VD contacts being oriented accordingly to alpha conductor tracks extending in the first direction;in a first metallization layer on a first side of the active areas, first trace segments (RTE segments) extending in the first direction, aligned with the alpha conductors and arranged accordingly over the VG contacts or the VD contacts, as well as one or more of the first RTE segments that are first input / output (pin) segments; in a first interconnection layer, first contacts aligned with the alpha conductors and arranged accordingly over the first RTE segments;and in a first buried metallization layer on a second side of the active areas, first buried power grid segments extending in the first direction. A first and a second of the alpha traces are adjacent to a first and a second boundary of the cell area. At least a third of the alpha traces is located between the first and the second alpha trace. The first alpha trace has none of the VG contacts and none of the first pin segments aligned with it, and the second alpha trace has none of the VD contacts and none of the first contacts aligned with it.

[0154] In some embodiments, the gate segments are aligned with beta traces extending in the second direction. With respect to the first direction, adjacent gate segments are spaced apart by a first pitch. With respect to the second direction, adjacent first RTE segments are spaced apart by a second pitch. Regarding some of the VD contacts aligned with the same beta traces (beta-co-aligned VD contacts), adjacent beta-co-aligned VD contacts are spaced apart by a gap approximately equal to or greater than a smaller value of the first pitch or twice the second pitch.

[0155] In some embodiments, the gate segments are aligned with beta traces extending in the second direction. With respect to the first direction, adjacent gate segments are spaced apart by a first pitch. With respect to the second direction, adjacent first RTE segments are spaced apart by a second pitch. Regarding some of the VG contacts aligned with the same beta traces (beta-co-aligned VG contacts), adjacent beta-co-aligned VG contacts are spaced apart by a gap approximately equal to or greater than a smaller value of the first pitch or twice the second pitch.

[0156] In some embodiments, the gate segments are aligned with beta traces extending in the second direction. With respect to the first direction, adjacent gate segments are spaced apart by a first pitch. With respect to the second direction, adjacent first RTE segments are spaced apart by a second pitch. Regarding some of the first contacts aligned with the same beta traces (beta-co-aligned first contacts), adjacent beta-co-aligned first contacts are spaced apart by a gap approximately equal to or greater than a smaller value of the first pitch or twice the second pitch.

[0157] In some embodiments, the cell area further comprises: in a second metallization layer, second RTE segments extending in the second direction, aligned with beta conductors, and positioned over the first contacts. With respect to the second direction, adjacent first RTE segments are spaced apart by a first pitch. Regarding some of the second RTE segments aligned with the same direction as the beta conductors (beta-co-aligned second RTE segments), adjacent ends of beta-co-aligned second RTE segments are spaced apart by a first gap equal to or greater than the first pitch.

[0158] In some embodiments, the gate segments, MD contacts, VG contacts and VD contacts of the cell area can be arranged in a first or a second arrangement, wherein, in the case that they are arranged according to the first or the second arrangement, the cell area is configured to perform the same function.

[0159] In some embodiments, a method (for generating a cell region of a device) comprises the following: generating active regions extending in a first direction; in a second direction perpendicular to the first direction, generating gate segments having portions over first regions of the active regions; and generating metal source / drain region contacts (MD contacts) with the gate segments interspersed, the MD contacts having portions over second regions of the active regions; generating via-hole gate contacts (VG contacts) over regions of the gate segments; generating via-hole MD contact contacts (VD contacts) over regions of the MD contacts, the VG contacts and the VD contacts being aligned accordingly with alpha conductor tracks extending in the first direction;In a first metallization layer on a first side of the active areas, first trace segments (RTE segments) are produced that extend in the first direction, are aligned according to the alpha conductor tracks and are arranged accordingly over the VG contacts or the VD contacts;In a first buried metallization layer on a second side of the active areas, first buried power grid segments are created that extend in the first direction, wherein a first and a second of the alpha conductors are adjacent to a first and a second boundary of the cell area, and at least a third of the alpha conductors is arranged between the first and the second alpha conductors. Creating the VG contacts comprises the following: arranging the VG contacts such that the first alpha conductor does not have any of the VG contacts aligned with it. Creating the VD contacts comprises the following: arranging the VD contacts such that the second alpha conductor does not have any of the VD contacts aligned with it.

[0160] In some embodiments, the fabrication of gate segments comprises the following: aligning the gate segments with beta traces extending in the second direction; and, with respect to the first direction, spacing adjacent gate segments apart by a first pitch. The fabrication of MD contacts comprises the following: with respect to the second direction, spacing adjacent first RTE segments apart by a second pitch. The fabrication of VD contacts comprises the following: aligning corresponding VD contacts with one and the same beta traces, resulting in beta-co-aligned VD contacts; and spacing adjacent beta-co-aligned VD contacts apart by a gap of a size approximately equal to or greater than a smaller value of the first pitch or twice the second pitch.

[0161] In some embodiments, the fabrication of gate segments comprises the following: aligning the gate segments with beta traces extending in the second direction; and, with respect to the first direction, spacing adjacent gate segments apart by a first pitch. The fabrication of first RTE segments comprises the following: with respect to the second direction, spacing adjacent first RTE segments apart by a second pitch. The fabrication of VG contacts comprises the following: aligning corresponding VG contacts with one and the same beta traces, resulting in beta-co-aligned VG contacts; and spacing adjacent beta-co-aligned VG contacts apart by a gap of a size approximately equal to or greater than a smaller value of the first pitch or twice the second pitch.

[0162] In some embodiments, the method further comprises the following: creating first contacts in a first interconnect layer, which are aligned with the alpha conductors and arranged accordingly over the first RTE segments. Creating first RTE segments comprises the following: creating one or more first input / output (pin) segments, wherein creating one or more first input / output (pin) segments comprises: arranging the one or more first pin segments such that the first alpha conductor does not have any of the first pin segments aligned with it. Creating first contacts comprises the following: arranging the first contacts such that the second alpha conductor does not have any of the first contacts aligned with it.

[0163] In some embodiments, the fabrication of gate segments comprises the following: aligning the gate segments with beta traces extending in the second direction; and, with respect to the first direction, spacing adjacent gate segments apart by a first pitch. The fabrication of first RTE segments comprises the following: with respect to the second direction, spacing adjacent first RTE segments apart by a second pitch. The fabrication of the first contacts comprises the following: aligning corresponding first contacts with the same beta traces, resulting in beta-co-aligned first contacts; and spacing adjacent beta-co-aligned first contacts apart by a gap of a size approximately equal to or greater than a smaller value of the first pitch or twice the second pitch.

[0164] In some embodiments, the method further comprises the following: producing, in a second metallization layer, second RTE segments extending in the second direction, aligned accordingly with beta conductor tracks, and positioned accordingly over the first contacts. The production of first RTE segments comprises the following: with respect to the second direction, spacing adjacent first RTE segments apart by a first pitch. The production of second RTE segments comprises the following: aligning corresponding second RTE segments with one and the same beta conductor track, resulting in beta-co-aligned second RTE segments; and spacing adjacent ends of beta-co-aligned second RTE segments apart by a first gap equal to or greater than the first pitch.

[0165] A person skilled in the art should readily recognize that one or more of the disclosed embodiments offer one or more of the aforementioned advantages. After reading the foregoing patent description, a person skilled in the art should be able to implement various modifications, substitutions of equivalents, and various other embodiments, which are outlined herein. The protection granted therein is therefore to be limited only by the definitions contained in the appended claims and their equivalents. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 700.309

[0001]

Claims

[1] Cell area of ​​a device comprising the following: active areas extending in a first direction; Gate segments and metal source / drain area contacts (MD contacts) extending in a second direction perpendicular to the first direction are intermingled and have parts over areas of the active regions; Through-connect gate contacts (VG contacts) across areas of the gate segments; Through-hole MD contact contacts (VD contacts) over areas of the MD contacts, wherein the VG contacts and the VD contacts are aligned accordingly to alpha conductors extending in the first direction; in a first metallization layer on a first side of the active areas, first trace segments (RTE segments) extending in the first direction are aligned with the alpha conductors and arranged accordingly over the VG contacts or the VD contacts; and in a first buried metallization layer on a second side of the active areas, first buried power grid segments extending in the first direction, wherein a first and a second of the alpha conductors are adjacent to a first and a second boundary of the cell area, at least a third of the alpha conductors is arranged between the first and the second alpha conductors, the first alpha conductor does not have any of the VG contacts aligned for this purpose, and the second alpha conductor does not have any of the VD contacts aligned with it. [2] Cell area according to claim 1, wherein the gate segments are aligned accordingly with beta conductor tracks extending in the second direction, In relation to the first direction, adjacent gate segments are spaced apart from each other by a first pitch. With regard to the second direction, adjacent first RTE segments are spaced apart from each other by a second pitch, and Regarding some of the VD contacts that are aligned to one and the same of the beta conductors (beta-co-aligned VD contacts), adjacent beta-co-aligned VD contacts are separated from each other by a gap of a size approximately equal to or greater than a smaller value of the first pitch or twice the second pitch. [3] Cell area according to claim 1 or 2, wherein the gate segments are aligned accordingly with beta conductor tracks extending in the second direction, In relation to the first direction, adjacent gate segments are spaced apart from each other by a first pitch. With regard to the second direction, adjacent first RTE segments are spaced apart from each other by a second pitch, and Regarding some of the VG contacts that are aligned to one and the same of the beta conductors (beta-co-aligned VG contacts), adjacent beta-co-aligned VG contacts are separated from each other by a gap of a size approximately equal to or greater than a smaller value of the first pitch or twice the second pitch. [4] Cell area according to any of the preceding claims, further comprising: in a first interconnection layer, first contacts are aligned accordingly to the alpha conductor tracks and arranged accordingly over the first RTE segments, wherein one or more of the first RTE segments are the first input / output (pin) segments, the first alpha conductor does not have any of the first pin segments that are aligned for this purpose, and the second alpha conductor does not have any of the first contacts that are aligned for this purpose. [5] Cell area according to claim 4, wherein the gate segments are aligned accordingly with beta conductor tracks extending in the second direction, In relation to the first direction, adjacent gate segments are spaced apart from each other by a first pitch. With regard to the second direction, adjacent first RTE segments are spaced apart from each other by a second pitch, and Regarding some of the first contacts that are aligned to one and the same of the beta conductors (beta-co-aligned first contacts), adjacent beta-co-aligned first contacts are separated from each other by a gap of a size approximately equal to or greater than a smaller value of the first pitch or twice the second pitch. [6] Cell area according to claim 4 or 5, further comprising: in a second metallization layer, second RTE segments extending in the second direction are aligned accordingly to beta conductor tracks and are arranged accordingly over the first contacts, wherein With regard to the second direction, adjacent first RTE segments are spaced apart from each other by a first pitch, and Regarding some of the second RTE segments that are aligned to one and the same of the beta conductor tracks (beta-co-aligned second RTE segments), adjacent ends of beta-co-aligned second RTE segments are separated from each other by a first gap that is equal to or greater than the first pitch. [7] Cell area according to one of the preceding claims, wherein the gate segments, the MD contacts, the VG contacts and the VD contacts of the cell area can be arranged in a first or a second arrangement, and in the event that they are arranged according to the first or the second arrangement, the cell area is set up in such a way that it performs the same function. [8] Cell area according to claim 7, wherein, in the case that they are arranged according to the first or the second arrangement, the cell area is configured to perform the same AND-OR-INVERT function (AOI function). [9] Cell area of ​​a device, wherein the cell area comprises: active areas extending in a first direction; Gate segments and metal source / drain area contacts (MD contacts) extending in a second direction perpendicular to the first direction are intermingled and have parts over areas of the active regions; Through-connect gate contacts (VG contacts) across areas of the gate segments; Through-hole MD contact contacts (VD contacts) over areas of the MD contacts, wherein the VG contacts and the VD contacts are aligned accordingly to alpha conductors extending in the first direction; in a first metallization layer on a first side of the active areas, first trace segments (RTE segments) extending in the first direction are aligned with the alpha conductors and are arranged accordingly over the VG contacts or the VD contacts, as well as one or more of the first RTE segments that are first input / output (pin) segments; in a first interconnection layer, the first contacts are aligned with the alpha conductors and arranged accordingly above the first RTE segments; and in a first buried metallization layer on a second side of the active areas, first buried power grid segments extending in the first direction, wherein a first and a second of the alpha conductors are adjacent to a first and a second boundary of the cell area, at least a third of the alpha conductors is arranged between the first and the second alpha conductors, the first alpha conductor does not have any of the VG contacts aligned with it and none of the first pin segments aligned with it, and the second alpha conductor does not have any of the VD contacts aligned with it and none of the first contacts aligned with it. [10] Cell area according to claim 9, wherein the gate segments are aligned accordingly with beta conductor tracks extending in the second direction, In relation to the first direction, adjacent gate segments are spaced apart from each other by a first pitch. With regard to the second direction, adjacent first RTE segments are spaced apart from each other by a second pitch, and Regarding some of the VD contacts that are aligned to one and the same of the beta conductors (beta-co-aligned VD contacts), adjacent beta-co-aligned VD contacts are separated from each other by a gap of a size approximately equal to or greater than a smaller value of the first pitch or twice the second pitch. [11] Cell area according to claim 9 or 10, wherein the gate segments are aligned accordingly with beta conductor tracks extending in the second direction, In relation to the first direction, adjacent gate segments are spaced apart from each other by a first pitch. With regard to the second direction, adjacent first RTE segments are spaced apart from each other by a second pitch, and Regarding some of the VG contacts that are aligned with the same beta conductors (beta-co-aligned VG contacts), adjacent beta-co-aligned VG contacts are separated from each other by a gap of a size approximately equal to or greater than a smaller value of the first pitch or twice the second pitch. [12] Cell area according to one of claims 9 to 11, wherein the gate segments are aligned accordingly with beta conductor tracks extending in the second direction, In relation to the first direction, adjacent gate segments are spaced apart from each other by a first pitch. With regard to the second direction, adjacent first RTE segments are spaced apart from each other by a second pitch, and Regarding some of the first contacts that are aligned to one and the same of the beta conductors (beta-co-aligned first contacts), adjacent beta-co-aligned first contacts are separated from each other by a gap of a size approximately equal to or greater than a smaller value of the first pitch or twice the second pitch. [13] Cell area according to any one of claims 9 to 12, further comprising: in a second metallization layer, second RTE segments extending in the second direction are aligned accordingly to beta conductor tracks and are arranged accordingly over the first contacts, wherein With regard to the second direction, adjacent first RTE segments are spaced apart from each other by a first pitch, and Regarding some of the second RTE segments that are aligned to one and the same of the beta conductor tracks (beta-co-aligned second RTE segments), adjacent ends of beta-co-aligned second RTE segments are spaced apart from each other by a first gap that is equal to or greater than the first pitch. [14] Cell area according to any one of claims 9 to 13, wherein the gate segments, the MD contacts, the VG contacts and the VD contacts of the cell area can be arranged in a first or a second arrangement, and in the event that they are arranged according to the first or the second arrangement, the cell area is set up in such a way that it performs the same function. [15] Method for generating a cell region of a device comprising the following: Creating active areas that extend in a first direction; in a second direction, perpendicular to the first direction, producing gate segments having parts over first areas of the active regions, and producing metal source / drain region contacts (MD contacts) with the gate segments in between, the MD contacts having parts over second areas of the active regions; Establishing through-hole gate contacts (VG contacts) across areas of the gate segments; Producing via-hole MD contact contacts (VD contacts) over areas of the MD contacts, wherein the VG contacts and the VD contacts are aligned accordingly to alpha conductor tracks extending in the first direction; in a first metallization layer on a first side of the active areas, first trace segments (RTE segments) are produced, extending in the first direction, aligned according to the alpha conductors and arranged accordingly over the VG contacts or the VD contacts; and in a first buried metallization layer on a second side of the active areas, producing first buried power grid segments extending in the first direction, wherein a first and a second of the alpha conductors are adjacent to a first and a second boundary of the cell area, and at least a third of the alpha conductors is arranged between the first and the second alpha conductor, wherein The creation of the VG contacts includes arranging the VG contacts in such a way that the first alpha conductor does not have any of the VG contacts aligned for this purpose, and The creation of the VD contacts includes arranging the VD contacts in such a way that the second alpha conductor does not have any of the VD contacts aligned with it. [16] Method according to claim 15, wherein The manufacturing of gate segments includes the following: Aligning the gate segments according to beta traces extending in the second direction; and Regarding the first direction of spacing adjacent gate segments with an initial pitch from each other, Establishing MD contacts includes the following: Regarding the second direction, spacing adjacent first RTE segments from each other with a second pitch, and Establishing the VD contacts includes the following: Aligning the corresponding VD contacts with one and the same of the beta traces, resulting in beta-co-aligned VD contacts; and Spacing adjacent beta-co-aligned VD contacts apart with a gap that is approximately equal to or greater than a smaller value of the first pitch or twice the second pitch. [17] Method according to claim 15 or 16, wherein The manufacturing of gate segments includes the following: Aligning the gate segments according to beta traces extending in the second direction; and Regarding the first direction of spacing adjacent gate segments with an initial pitch from each other, The creation of initial RTE segments includes the following: Regarding the second direction, spacing adjacent first RTE segments from each other with a second pitch, and Establishing VG contacts includes the following: Aligning the corresponding VG contacts with one and the same of the beta traces, resulting in beta-co-aligned VG contacts; and Spacing adjacent beta-co-aligned VG contacts apart with a gap of a size approximately equal to or greater than a smaller value of the first pitch or twice the second pitch. [18] Method according to any one of claims 15 to 17, further comprising: In a first interconnection layer, initial contacts are established, which are aligned accordingly to the alpha conductor tracks and arranged accordingly over the first RTE segments, wherein The creation of first RTE segments includes the creation of one or more first input / output (pin) segments, wherein the creation of one or more first input / output (pin) segments includes the following: Arranging one or more first pin segments such that the first alpha conductor does not have any of the first pin segments aligned with it, and making first contacts comprises the following: Arrange the first contacts so that the second alpha conductor does not have any of the first contacts aligned with it. [19] Method according to claim 18, wherein The manufacturing of gate segments includes the following: Aligning the gate segments according to beta traces extending in the second direction; and Regarding the first direction of spacing adjacent gate segments with an initial pitch from each other, The creation of initial RTE segments includes the following: Regarding the second direction, spacing adjacent first RTE segments from each other with a second pitch, and Establishing initial contacts includes the following: Aligning the corresponding first contacts with one and the same beta conductor track, resulting in beta-co-aligned first contacts; and Spacing adjacent beta-co-aligned first contacts apart with a gap that is approximately equal to or greater than a smaller value of the first pitch or twice the second pitch. [20] The method of claim 18 or 19, further comprising: in a second metallization layer, producing second RTE segments that extend in the second direction, are aligned accordingly to beta conductor tracks and are arranged accordingly over the first contacts, wherein The creation of initial RTE segments includes the following: Regarding the second direction, spacing adjacent first RTE segments with a first pitch from each other, The creation of second RTE segments includes the following: Aligning corresponding second RTE segments with one and the same beta conductor track, resulting in beta-co-aligned second RTE segments; and Spacing adjacent ends of beta-co-aligned second RTE segments apart by a first gap that is equal to or greater than the first pitch.

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