METHOD, DEVICE AND CIRCUIT FOR HIGH-SPEED STORAGE

Abstract

A storage device comprises multiple memory cells arranged in an array, a first clock generator connected to the multiple memory cells and configured to generate a local clock signal to be output to the multiple memory cells, a second clock generator connected to an input / output interface connected to the multiple memory cells, the second clock generator being configured to generate a global clock signal to be output to the input / output interface; and one or more logic gates connected to the first clock generator and / or the second clock generator, the one or more logic gates allowing the local clock signal and the global clock signal to be output independently.

Description

BACKGROUND

[0001] Modern system-on-a-chip (SoC) designs can contain a large number of memory modules. These modules can occupy most of the SoC's capacity, and any memory failure can disrupt the SoC's operation. Therefore, a design-for-testability (DFT) approach can be used to identify and eliminate defective chips. DFT can be implemented as a segment of a circuit on a chip, a circuit board, or a system, used to test the circuit itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. In fact, the dimensions of the various elements may have been enlarged or reduced as appropriate for clarity of description. Fig. Figure 1 shows a schematic representation of a storage system according to some embodiments. Fig. Figure 2 shows a schematic representation of a circuit in which Fig. 1 storage system shown according to some embodiments. Fig. Figure 3 shows a schematic representation of a circuit in which Fig. 1 storage system shown according to some embodiments. Fig.Figure 4 shows a flowchart of a method for operating a storage system according to some embodiments. DETAILED DESCRIPTION

[0003] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For instance, the forming of a first element above or on top of a second element in the following description may cover embodiments in which the first and second elements are in direct contact, and may also cover embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0004] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of an element or section to one or more other elements or sections, as shown in the figures. These spatially relative terms are intended to cover various orientations of the device used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here can be interpreted accordingly.

[0005] As digital circuits become increasingly complex, existing testing methods may be insufficient to efficiently and effectively detect potential circuit errors or defects. Furthermore, there is a growing need to identify and resolve problems early in the design and manufacturing process to reduce the overall cost of circuit products. To facilitate the testing of memory circuits, DFT functions can be directly integrated into a digital circuit to detect faults. For example, DFT can be implemented as a section of the circuit on a chip, circuit board, or system used for testing the circuit itself. The circuit in DFT mode can include signals, such as DFT enable signals, that activate test functions when required.Using such a signal, a circuit with DFT functionality can test itself and output test responses that allow for analysis of its behavior and fault detection. The circuit may include, or be functionally connected to, a control circuit that manages the activation of the DFT mode (e.g., controlling the start of the test functions by outputting an enable signal).

[0006] In existing storage devices that do not implement the disclosed memory circuit, a storage device typically uses an external or SOC clock to generate an internal clock for performing memory and DFT operations. Thus, the internal clock, which includes a global clock signal and a local clock signal, is generated by a common clock generator. However, this approach has a significant drawback, such as a substantial time delay, because the pathways for the operating mode must be disabled when DFT operation is enabled. For example, read and / or write signals must be disabled during DFT operation, which increases overall setup and hold times and therefore reduces the speed of DFT operation and the device itself.

[0007] The present disclosure provides various embodiments of a memory circuit, a method, and a device for independently generating internal clock signals. In some embodiments, a memory device may include a first clock generator that outputs a local clock signal and a second clock generator that outputs a global clock signal. The memory device may include one or more logic gates that enable independent output of the local clock signal and the global clock signal. This allows clock generation in DFT mode to occur independently of clock generation in operating mode, thereby enabling independent tuning of power consumption, power, and area (PPA) for DFT operation. Likewise, PPA for operating mode can be tuned without affecting DFT operation. This provides a simple and flexible solution for adjusting the operating frequency of the DFT mode in various memory applications (e.g., memory, storage, and memory).to improve (e.g., an SRAM macro) in an efficient way.

[0008] Fig. Figure 1 shows a schematic representation of a storage system 100 according to some embodiments. The storage system 100 can also be referred to as a storage device. The storage system 100 includes a global control circuit (GCTRL) 105. In some embodiments, the GCTRL 105 can independently generate internal clock signals (e.g., a working-mode clock signal and a DFT-mode clock signal). Operation in working mode can also be referred to as normal operation. The GCTRL 105 can be referred to as a control circuit.

[0009] The GCTRL 105 can have several inputs. The GCTRL 105 receives an inverted chip enable signal (CEB) via a CEB line 110. The CEB signal can be configured to enable and / or enable at least one component of the GCTRL 105. The GCTRL 105 receives a clock signal (CLK) via a CLK line 115. The CLK signal can be configured to enable the generation of a clock signal by the GCTRL 105. The GCTRL 105 receives a DFT enable signal via a DFT line 120. The DFT enable signal can be configured to enable the generation of a signal indicating operation in DFT mode. In some embodiments, the DFT enable signal may include a DFT bypass signal and / or a scan enable signal (SE signal).

[0010] The memory system 100 includes a memory bank 150. The memory bank 150 can have a number of memory cells. The memory cells can be operated according to signals for word line, bit line, select line, and read / write. Although only one memory bank 150 is shown, the memory system 100 can have two or more memory banks 150 without this deviating from the scope of this disclosure.

[0011] The GCTRL 105 has several outputs. The GCTRL 105 outputs a local clock signal (GCK signal) via a GCK line 130, which connects the GCTRL 105 to a local control circuit (LCTRL) 135. In some embodiments, the GCK signal may be referred to as the GCK clock (GCKP). In some embodiments, the GCK is enabled in working mode (e.g., for accessing memory bank 150, performing read / write operations, etc.). In some embodiments, the LCTRL 135 can receive the GCK signal via the GCK line 130. In some embodiments, the LIO 155 outputs a data signal from memory bank 150. Although only one LIO 155 is shown, two or more LIOs 155 may be included without deviating from the scope of this disclosure. In some embodiments with two or more LIOs 155, each LIO 155 can perform I / O operations for a corresponding memory bank 150.In some embodiments, the memory bank 150 and / or the LIO 155 receives the GCK signal via the GCK line 130.

[0012] The GCTRL 105 outputs a DFT mode-operating mode switching clock signal (DCK signal) via a DCK line 140. In some embodiments, the DCK signal is referred to as the global clock signal. The DCK signal is enabled in DFT mode (e.g., for testing the memory system 100, etc.) and / or in operating mode. In some embodiments, the DCK signal can be enabled without disabling the GCK and GCK-dependent signals such as word line, bit line, select line, and read / write signals. The DCK signal and the GCK and GCK-dependent signals can be output independently, as described in more detail below. The memory system 100 includes a global input / output interface (GIO interface) 145. The GIO 145 receives the DCK signal via the DCK line 140. In some embodiments, the DCK signal may include a signal to enable a test mode of the circuit.

[0013] The GCTRL 105 can be configured to output the GCK signal and the DCK signal independently. In some embodiments, the GCTRL 105 may have a first clock generator (CKG) 171 that outputs the GCK signal via the GCK line 130. The CKG 171 can generate the GCK signal depending on the CEB signal, the CLK signal, and the DFT enable. In some embodiments, the GCTRL 105 may have a second clock generator (DKG) 172 that outputs the DCK signal via the DCK line 140. The DKG 172 can generate the DCK signal depending on the CEB signal, the CLK signal, and the DFT enable. In some embodiments, the GCTRL 105 may include one or more logic gates or circuits that independently generate the GCK signal and / or the DCK signal depending on the CLK signal, the CEB signal, and the DFT enable signal. The one or more logic gates or circuits...Circuits can be connected to the CKG 171 and / or the DKG 172, allowing the CKG 171 and the DKG 172 to independently output a corresponding clock signal (e.g., the GCK signal or the DCK signal). For example, the CKG 171 and / or the DKG 172 can have or be connected to one or more logic gates or circuits, as shown in the [reference]. Fig. 2 and Fig. 3 shown.

[0014] In some embodiments, the memory system can have 100 tracking bit cells (TRKBL cells) 192, each of which is connected to a TWL_GCK line 190. In some embodiments, a tracking word line of the TRKBL cells 192 can include a (e.g., horizontal) portion extending along the rows of the memory bank 150 (not explicitly shown) and a (e.g., vertical) portion extending along the columns of the memory bank 150 (not explicitly shown). The TRKBL cells 192 can transmit a local tracking word line signal (TWL_GCK signal) that can be output via the TWL_GCK line 190. By transmitting the TWL_GCK signal, the TRKBL cells 192 can emulate the signal propagation delays in a functional memory array (e.g., the memory bank 150).

[0015] In general, TRKBL cells 192 do not function like the (actual) memory bank 150 in terms of data storage and support for read / write operations. Rather, TRKBL cells 192 may originally be a subset of memory bank 150, but may be used or repurposed for timing tracking. For example, TRKBL cells 192 may be bit cells with fixed logic values, configured and interconnected to respond predictably when driven by check or tracking signals. For instance, when the TWL_GCK signal transitions to a logic high state, any of the TRKBL cells 192 may be turned on, and the pre-charged tracking bit lines may begin to discharge to a logic low state. In response to this discharge, the TWL_GCK signal may transition from a logic high state to a logic low state.When the TWL_GCK signal has transitioned to a sufficiently low voltage (e.g., dropped by a predefined ΔV), at least one other signal, e.g., the GCK signal, can be configured to reset it.

[0016] In some embodiments, the CKG 171 can generate the TWL_GCK signal, which can be output via the TWL_GCK line 190 and passes through the GIO 145. The TWL_GCK signal can discharge a bit line of the TRKBL cells 192. In some embodiments, a discharged bit line can generate a reset signal that resets the GCK signal based on one or more logic gates or circuits 194. In some embodiments, a reset of the GCK signal can be triggered in response to an inverted GCK signal (GCKPB signal) being in a logic low state. For example, the GCK signal can be reset when the GCKPB signal goes low. In some embodiments, such a reset signal can determine a pulse width of the GCK signal for a read or write operation.

[0017] In some embodiments, the DKG 172 can generate a global tracking word line signal (TWL_DCK signal) that can be output via a TWL_DCK line 180 and passes through the GIO 145. The TWL_DCK signal can be used to access the GIO 145. In some embodiments, after accessing the GIO 145, the TWL_DCK signal can be used to generate a reset signal to reset the DCK signal. In some embodiments, such a reset signal can determine a pulse width of the DCK signal.

[0018] Fig. Figure 2 shows a schematic representation of a circuit 200 in which in Fig. 1. Storage system 100 shown according to some embodiments. More precisely, the circuit 200 may be the CKG 171 or a part thereof. As in Fig.As shown in Figure 2, the circuit 200 can include one or more logic gates or circuits that output a GCK (or GCKP) signal 230 depending on the input signals (e.g., a CEB signal 210, a CLK signal 215, a DFT enable signal 220, etc.). In some embodiments, the one or more logic gates can perform a logical NOR operation on the DFT enable signal 220 and the CEB signal 210 to generate an enable signal EN 205, which enables the generation of the GCK signal 230.

[0019] Table 1 shows an example combination of signals that can enable GCK signal 230. In some embodiments, "1" represents enable and "0" represents block. Table 1 CLK CEB DFT A GCK 1 0 0 1 1 1 0 1 0 0 1 1 0 0 0 1 1 1 0 0

[0020] In some embodiments, the storage system 100 can be operated in working mode in response to the EN signal 205 (e.g., the "NOR" operation on the CEB signal 210 and the DFT enable signal 220) being in a first logical state (e.g., "1"), and the GCK signal 230 generated by the GCTRL 105 (e.g., the CKG 171) can be output.

[0021] In some embodiments, the GCK signal 230 may include a TWL_GCK signal. The TWL_GCK signal may discharge a bit line of TRKBL cells. In some embodiments, a discharged bit line may generate a reset signal RESET 225, which resets the generation of the GCK signal 230. In some embodiments, a reset of the GCK signal 230 may be triggered in response to an inverted GCK signal (GCKPB) being in a logic low state. For example, the generation of the GCK signal 230 may be reset when the GCKPB signal goes low. In some embodiments, the reset signal RESET 225 may determine a pulse width of the GCK signal 230.

[0022] Fig. Figure 3 shows a schematic representation of a circuit 300 in which in Fig.1 storage system 100 shown according to some embodiments. More precisely, the circuit 300 may be the DKG 172 or a part thereof. As in Fig. As shown in Figure 3, the circuit 300 can have one or more logic gates that output a DCK signal 280 depending on input signals (e.g., a CEB signal 260, a CLK signal 265, a DFT enable signal 270, etc.). In some embodiments, the one or more logic gates can perform a logic NOT operation on the DFT enable signal 270 and a logic NAND operation on a result of the logic NOT operation and the CEB signal 260 to generate an enable signal EN 255, which enables the generation of the DCK signal 280.

[0023] Table 2 shows an example combination of signals that can activate the DCK signal. In some embodiments, "1" represents enable and "0" represents disable. Table 2 CLK CEB DFT A DCK 1 0 0 1 1 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1

[0024] In some embodiments, the memory system 100 can, in response to the EN signal 255 (e.g., the "NAND" operation on a CEB signal 260 and a result of the "NOT" operation on a DFT enable signal 270) being in a first logical state (e.g., "1"), perform a DFT mode operation, and the DCK signal 280, generated by the GCTRL 105 (e.g., the DKG 172), can be output. This allows clock generation in DFT mode independent of clock generation in operating mode.

[0025] In some embodiments, the DCK signal 280 may include a TWL_DCK signal. The TWL_DCK signal can be used to access a GIO interface. In some embodiments, after accessing the GIO interface, the TWL_DCK signal can be used to generate a reset signal RESET 275, which resets the DCK signal 280. In some embodiments, the reset signal RESET 275 can determine a pulse width of the DCK signal 280.

[0026] Referring to Table 1 and Table 2, the memory system 100 can be configured to output a local signal (e.g., GCK) and a global signal (e.g., DCK) independently. In some embodiments, the GCTRL 105 (containing, for example, one or more logic gates) can be configured to cause the first clock generator 171 and the second clock generator 172 to generate the GCK signal and the DCK signal, respectively, in a first state (e.g., when CEB is in a second logic state, such as logic low or "0", and when DFT is in a second logic state, such as logic low or "0"). For example, as shown, an enable signal EN with a logic high state (e.g., "1") can be generated for both the GCK signal and the DCK signal. The GCTRL 105 can be configured to operate in a second state (e.g., when CEB is in the second logical state, such as logically low or...).The GCTRL 105 can be configured to prevent the first clock generator 171 and the second clock generator 172 from generating the GCK signal and the DCK signal, respectively, in a third state (e.g., when CEB is in a first logical state, such as logical high or "1", and when DFT is in a second logical state, such as logical low or "0"). In this case, the first clock generator 171 can be prevented from generating the GCK signal. For example, as shown, an enable signal EN can be generated in a logical high state (e.g., "1") only for the DCK signal. The GCTRL 105 can be configured to operate in a fourth state (e.g.,If CEB is in the first logic state (e.g., logic high or "1") and DFT is also in the first logic state (e.g., logic high or "1"), the second clock generator 172 is caused to generate the DCK signal. In this case, the first clock generator 171 can be prevented from generating the GCK signal. For example, as shown, an enable signal EN in a logic high state (e.g., "1") can be generated only for the DCK signal.

[0027] In some embodiments, the configuration can be such that if at least either the DFT enable signal (e.g., DFT in Table 1 and Table 2) is in the first logical state (e.g., high or "1") or the CEB signal (e.g., CEB in Table 1 and Table 2) is in the second logical state (e.g., low or "0"), the generation of the DCK signal is triggered.

[0028] By generating a local clock signal and a global clock signal independently, as described above, the techniques described herein enable clock generation in DFT mode independently of clock generation in operating mode. This allows for independent tuning of power consumption, power, and area (PPA) for DFT operation, while PPA for operating mode can be tuned without affecting DFT operation.

[0029] Fig. Figure 4 shows a flowchart of a method 400 for operating a storage system according to some embodiments. It is noted that method 400 serves only as an example and is not intended to limit the present disclosure. Accordingly, it is understood that more, fewer, or other operations in method 400 may be performed by Fig. 4 may be present, additional processes before, during and after the procedure 400 of Fig.4 may be provided for and that some other processes are only briefly described here. In some embodiments, method 400 is executed by a global control circuit (e.g., the GCTRL 105).

[0030] In summary, Procedure 400 can begin with Operation 410, in which an input clock signal, an inverted chip enable signal (CEB signal), and a design-for-testability enable signal (DFT enable signal) are received. Procedure 400 can proceed to Operation 420, in which a first enable signal is generated, causing a first clock generator to produce a local clock signal based on a logic high state of a first set of signals from the input clock signal, the CEB signal, and the DFT enable signal. Procedure 400 can proceed to Operation 430, in which a second enable signal is generated, causing a second clock generator to produce a global clock signal based on a logic high state of a second set of signals from the input clock signal, the CEB signal, and the DFT enable signal.

[0031] In process 410, a global control circuit (e.g., GCTRL 105) receives an input clock signal (e.g., the CLK signal via CLK line 115), a chip enable signal (e.g., the CE signal via CEB line 110), and a DFT enable signal (e.g., the DFT enable signal via DFT line 120). The DFT enable signal may include a signal to enable operation of the circuit in a test mode.

[0032] In operation 420, the global control circuit can generate a first enable signal (e.g., the enable signal EN 205) that causes a first clock generator (e.g., the first clock generator 171) to generate a local clock signal (e.g., the GCK signal) based on a logic high state of a first set of signals consisting of the input clock signal, the CEB signal, and the DFT enable signal. In some embodiments, the first set of signals can consist of or include the input clock signal (e.g., CLK in Table 1). Thus, if the input clock signal is output when the CEB signal and the DFT enable signal are in a logic low state (e.g., "0"), an enable signal EN for the GCK signal can be output to enable the generation of the GCK signal.

[0033] In operation 430, the global control circuit can generate a second enable signal (e.g., the enable signal EN 255) that causes a second clock generator (e.g., the second clock generator 172) to generate a global clock signal (e.g., the DCK signal) based on a logic high state of a second set of signals consisting of the input clock signal, the CEB signal, and the DFT enable signal. In some embodiments, the second set of signals can consist of or include the input clock signal (e.g., CLK in Table 2), the DFT enable signal (e.g., DFT in Table 2), etc. In some embodiments, the global control circuit can generate the second enable signal to cause the second clock generator to generate the global clock signal based on a logic low state of a third set of signals consisting of the input clock signal, the CEB signal, and the DFT enable signal.The third set of signals can, for example, consist of or contain the CEB signal (e.g., CEB in Table 2). If the input clock signal is output when the DFT enable signal is in a logic high state (e.g., "1") and / or if the input clock signal is output when the CEB signal is in a logic low state (e.g., "0"), an enable signal EN for the DCK signal can thus be output, thereby enabling the generation of the DCK signal. In some embodiments, the first enable signal (and thus the GCK signal) and the second enable signal (and thus the DCK signal) can be generated independently. In a first state (e.g., the first row of Table 1 and Table 2), for example, both the first enable signal and the second enable signal can be generated. In a second state (e.g.,In a third state (e.g., the second row of Table 1 and Table 2), the second enable signal can be generated, while the first enable signal is not. In a third state (e.g., the third row of Table 1 and Table 2), neither the first nor the second enable signal is generated.

[0034] One aspect of this description concerns a storage device. The storage device comprises multiple memory cells arranged in an array, a first clock generator connected to the multiple memory cells and configured to generate a local clock signal to be output to the multiple memory cells, a second clock generator connected to an input / output interface that is also connected to the multiple memory cells, the second clock generator being configured to generate a global clock signal to be output to the input / output interface, and one or more logic gates connected to the first clock generator and / or the second clock generator, the one or more logic gates allowing the local clock signal and the global clock signal to be output independently.

[0035] One aspect of this description concerns a circuit. The circuit comprises a first clock generator that produces a local clock signal depending on an input clock signal, an inverted chip enable signal (CEB signal), and a design-for-testability enable signal (DFT enable signal); a second clock generator that produces a global clock signal depending on the input clock signal, the CEB signal, and the DFT enable signal; and one or more logic gates that independently generate the local clock signal or the global clock signal depending on the input clock signal, the CEB signal, and the DFT enable signal, the configuration being such that when at least either the DFT enable signal is in a logic high state or the CEB signal is in a logic low state, the generation of the global clock signal is triggered, which includes a signal enabling test-mode operation of the circuit.

[0036] One aspect of this description concerns a method. The method comprises receiving an input clock signal, an inverted chip enable signal (CEB signal), and a design-for-testability enable signal (DFT enable signal); generating, based on a logic high state of a first set of signals from the input clock signal, the CEB signal, and the DFT enable signal, a first enable signal that causes a first clock generator to generate a local clock signal; and generating, based on a logic high state of a second set of signals from the input clock signal, the CEB signal, and the DFT enable signal, a second enable signal that causes a second clock generator to generate a global clock signal, wherein the generation of the first enable signal and the second enable signal are independent.

[0037] The foregoing describes features of various embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should recognize that they can easily use the present disclosure as a basis for designing or modifying further processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments introduced herein. They should also recognize that such equivalent designs do not deviate from the spirit and scope of the present disclosure and that they can make various changes, substitutions, and modifications here without deviating from the spirit and scope of the present disclosure.

Claims

[1] Storage device comprising: multiple memory cells arranged in an array; a first clock generator that is connected to the multiple memory cells and configured to generate a local clock signal to be output to the multiple memory cells; a second clock generator connected to an input / output interface that is connected to the multiple memory cells, the second clock generator being configured to generate a global clock signal that is output to the input / output interface; and one or more logic gates connected to the first clock generator and / or the second clock generator, wherein the one or more logic gates allow the local clock signal and the global clock signal to be output independently of each other. [2] Storage device according to claim 1, wherein the one or more logic gates perform a logical NOR operation to generate the local clock signal. [3] Storage device according to claim 1 or 2, wherein the one or more logic gates perform a logical NOT operation and a logical NAND operation to generate the global clock signal. [4] Storage device according to one of the preceding claims, wherein a reset of the local clock signal is triggered in response to an inverted local clock signal being in a logic low state. [5] Storage device according to one of the preceding claims, wherein the first clock generator produces a local tracking word line signal that discharges a bit line of tracking bit cells. [6] Storage device according to claim 5, wherein a discharged bit line serves to generate a reset signal that resets the local clock signal. [7] Storage device according to claim 6, wherein the reset signal serves to determine a pulse width of the local clock signal. [8] Storage device according to one of the preceding claims, wherein the second clock generator produces a global tracking word line signal that accesses the input / output interface, and wherein, after accessing the input / output interface, the global tracking word line signal is to produce a reset signal that resets the global clock signal. [9] Storage device according to claim 8, wherein the reset signal serves to determine a pulse width of the global clock signal. [10] Storage device according to any of the preceding claims, wherein the one or more logic gates are configured to: To cause, in a first state, the first clock generator and the second clock generator to generate the local clock signal and the global clock signal, respectively; Causing, in a second state, the second clock generator to produce the global clock signal; and In a third state, prevent the first clock generator and the second clock generator from generating the local clock signal and the global clock signal, respectively. [11] Circuit comprising: a first clock generator configured to generate a local clock signal depending on an input clock signal, an inverted chip enable signal (CEB signal) and a design-for-testability enable signal (DFT enable signal); a second clock generator configured to generate a global clock signal depending on the input clock signal, the CEB signal, and the DFT enable signal; and one or more logic gates configured to cause the first clock generator and the second clock generator to independently generate the local clock signal and the global clock signal according to the input clock signal, the CEB signal and the DFT enable signal, wherein the configuration is such that if at least either the DFT enable signal is in a logic high state or the CEB signal is in a logic low state, the generation of the global clock signal is triggered, which includes a signal that enables test mode operation of the circuit. [12] Circuit according to claim 11, wherein the one or more logic gates perform a logical NOR operation on the DFT enable signal and the CEB signal to generate the local clock signal. [13] Circuit according to claim 11 or 12, wherein the one or more logic gates perform a logical NOT operation on the DFT enable signal and a logical NAND operation on a result of the logical NOT operation and the CEB signal to generate the global clock signal. [14] Circuit according to one of claims 11 to 13, wherein the first clock generator generates a local tracking word line signal that discharges a bit line of tracking bit cells. [15] Circuit according to claim 14, wherein a discharged bit line serves to generate a reset signal that resets the local clock signal. [16] Circuit according to claim 15, wherein the reset signal serves to determine a pulse width of the local clock signal. [17] Circuit according to one of claims 11 to 16, wherein the second clock generator generates a global tracking word line signal that accesses the input / output interface, and wherein, after accessing the input / output interface, the global tracking word line signal is to generate a reset signal that resets the global clock signal. [18] Circuit according to any one of claims 11 to 17, wherein: In a first state, in which the DFT enable signal is in a logic low state and the CEB signal is in a logic low state, the first clock generator and the second clock generator generate the local clock signal and the global clock signal, respectively; in a second state, in which the DFT enable signal is in the logic high state and the CEB signal is in the logic low state, the second clock generator generates the global clock signal; and In a third state, in which the DFT enable signal is in the logic low state and the CEB signal is in the logic high state, the first clock generator and the second clock generator are prevented from generating the local clock signal and the global clock signal, respectively. [19] Procedures, including: Receiving an input clock signal, an inverted chip enable signal (CEB signal), and a design-for-testability enable signal (DFT enable signal); Generating, based on a logically high state of a first set of signals from the input clock signal, the CEB signal, and the DFT enable signal, a first enable signal that causes a first clock generator to generate a local clock signal; and Based on a logic high state of a second set of signals from the input clock signal, the CEB signal and the DFT enable signal, generate a second enable signal that causes a second clock generator to generate a global clock signal. where the generation of the first enable signal and the second enable signal are independent. [20] Method according to claim 19, wherein: In a first state, both the first release signal and the second release signal are generated; In a second state, the second enable signal is generated and the first enable signal is not generated; and In a third state, the first release signal is not generated and the second release signal is not generated.

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