Neural network for controlling autonomous machines

Abstract

Devices, systems, and techniques for performing actions by an autonomous machine in a previously unknown environment. In at least one embodiment, one or more neural networks are trained based at least in part on images of one or more automatically generated training actions.

Description

TECHNICAL AREA

[0001] At least one embodiment relates to processing resources used to execute and facilitate artificial intelligence. For example, at least one embodiment relates to processors or computer systems used to train neural networks to perform task and motion planning tasks as described herein. BACKGROUND

[0002] Training robots to perform actions can be very expensive and requires a high degree of human interaction. For example, a human operator must guide the robot to perform specific tasks so the robot can learn and reward the robot for correctly performed tasks. Furthermore, even after training, information about the environment is needed for a trained robot to perform actions correctly. Therefore, better ways are needed to train an autonomous device to perform actions better. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a block diagram of a neural network training system according to at least one embodiment; Fig. 2 shows a flowchart illustrating a method for training a neural network according to at least one embodiment; Fig. 3 shows an example of an environment in which an autonomous task is to be executed, according to at least one embodiment; Fig. 4 shows an example of a group of stacked objects to be handled according to a motion planning task according to at least one embodiment; Fig. 5 shows an example of a planning module instructing an autonomous device to perform a task and motion planning (“TAMP”) task according to at least one embodiment; Fig. 6 shows an example process for performing a motion planning task according to at least one embodiment; Fig. 7A shows logic according to at least one embodiment; Fig. 7B shows logic according to at least one embodiment; Fig. 8 shows the formation and use of a neural network according to at least one embodiment; Fig. 9 shows an example of a data center system according to at least one embodiment; Fig. 10A shows an example of an autonomous vehicle according to at least one embodiment; Fig. Figure 10B shows an example of camera locations and fields of view for the autonomous vehicle of Fig. 10A according to at least one embodiment; Fig. Figure 10C is a block diagram showing an example system architecture for the autonomous vehicle of Fig. 10A according to at least one embodiment; Fig. 10D is a diagram illustrating a system for communication between one or more cloud-based servers and the autonomous vehicle of Fig. 10A according to at least one embodiment; Fig. 11 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 12 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 13 shows a computer system according to at least one embodiment; Fig. 14 shows a computer system according to at least one embodiment; Fig. 15A shows a computer system according to at least one embodiment; Fig. 15B shows a computer system according to at least one embodiment; Fig. 15C shows a computer system according to at least one embodiment; Fig. 15D shows a computer system according to at least one embodiment; Fig. 15E and Fig. 15F illustrate a common programming model according to at least one embodiment; Fig. 16 shows exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. 17A-17B illustrate exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. 18A-18B illustrate additional exemplary graphics processor logic according to at least one embodiment; Fig. 19 shows a computer system according to at least one embodiment; Fig. 20A shows a parallel processor according to at least one embodiment; Fig. 20B shows a partition unit according to at least one embodiment; Fig. 20C shows a processing cluster according to at least one embodiment; Fig. 20D shows a graphics multiprocessor according to at least one embodiment; Fig. 21 shows a system with multiple graphics processing units (GPU) according to at least one embodiment; Fig. 22 shows a graphics processor according to at least one embodiment; Fig. 23 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Fig. 24 shows a deep learning application processor according to at least one embodiment; Fig. 25 is a block diagram illustrating a neuromorphic processor according to at least one embodiment; Fig. 26 shows at least portions of a graphics processor according to one or more embodiments; Fig. 27 shows at least portions of a graphics processor according to one or more embodiments; Fig. 28 shows at least portions of a graphics processor according to one or more embodiments; Fig. 29 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Fig. 30 is a block diagram of at least portions of a graphics processor core according to at least one embodiment; Fig. 31A-31B illustrate thread execution logic including an arrangement of processing elements of a graphics processor core according to at least one embodiment; Fig. 32 illustrates a parallel processing unit ("PPU") according to at least one embodiment; Fig. 33 illustrates a general processing cluster ("GPC"), according to at least one embodiment; Fig. 34 illustrates a memory partition unit of a parallel processing unit ("PPU"), according to at least one embodiment; Fig. 35 illustrates a streaming multiprocessor, according to at least one embodiment; Fig. 36 is an example data flow diagram for an advanced computing pipeline according to at least one embodiment; Fig. 37 is a system diagram for an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline according to at least one embodiment; Fig. 38 includes an example illustration of an advanced computer pipeline 3910A for processing image data in accordance with at least one embodiment; Fig. 39A includes an example data flow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment; Fig. 39B includes an example data flow diagram of a virtual instrument supporting a CT scanner, according to at least one embodiment; Fig. 40A shows a data flow diagram for a process for training a machine learning model according to at least one embodiment; and Fig. 40B is an exemplary illustration of a client-server architecture for enhancing annotation tools with pre-trained annotation models, according to at least one embodiment. Fig. 41 shows components of a system for accessing a large language model according to at least one embodiment. DETAILED DESCRIPTION

[0003] Fig. 1 shows a block diagram of a neural network training system 100 ("System 100") according to at least one embodiment. It should be understood that these and other arrangements described herein are examples only. Other arrangements and elements (e.g., engines, interfaces, functions, instructions, functional groups, etc.) may be used in addition to or in place of those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional units that may be implemented as discrete or distributed components, or in conjunction with other components, and in any suitable combination and location. Various functions described herein as being performed by entities may be performed by hardware, firmware, and / or software.For example, various functions can be performed by a processor that executes instructions stored in memory.

[0004] In at least one embodiment, a module comprises any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. In at least one embodiment, a module comprises one or more circuits that are part of a larger system (e.g., an integrated circuit (IC), a system-on-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc.). In at least one embodiment, a controller comprises any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described.In at least one embodiment, software includes software packages, code, programming languages, drivers, instructions, instruction sets, or a combination thereof. In at least one embodiment, hardware includes hard-wired circuits, programmable circuits, state machine circuits, fixed-function circuits, execution unit circuits, firmware with stored instructions executed by programmable circuits, or a combination thereof.

[0005] In at least one embodiment, a logic unit comprises firmware logic, hardware logic, or a combination thereof, configured to provide any function as further described herein. In at least one embodiment, a logic unit comprises circuitry that is part of a larger system (e.g., IC, SoC, CPU, GPU, DPU). In at least one embodiment, a logic unit comprises logic circuitry for implementing firmware and / or hardware.

[0006] In at least one embodiment, an engine comprises a module and / or a logic unit, as further described herein. In at least one embodiment, a component comprises a module and / or a logic unit, as further described herein. In at least one embodiment, an engine comprises software logic, firmware logic, hardware logic, or a combination thereof, configured to provide any function, as further described herein. In at least one embodiment, a component comprises software logic, firmware logic, hardware logic, or a combination thereof, configured to provide any function, as further described. In at least one embodiment, operations performed by hardware and / or firmware may alternatively be implemented via a software module, which may be embodied as a software package, code, and / or instruction set.In at least one embodiment, a logic unit may also use a portion of software to implement its function.

[0007] In at least one embodiment, as used in any implementation described herein, terms such as "module" and nominalized verbs (e.g., scheduling module 106 and / or other terms), unless the context indicates otherwise or explicitly stated otherwise, each refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein.In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, individually or in any combination, hard-wired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by programmable circuitry. In at least one embodiment, modules may be embodied collectively or individually as circuits that are part of a larger system, such as an integrated circuit (IC), system-on-chip (SoC), etc.

[0008] In at least one embodiment, human teleoperation of an autonomous device uses behavioral cloning. In at least one embodiment, behavioral cloning collects data from human operators performing a particular task and uses the data to train a neural network used by an autonomous device to perform the same tasks. In at least one embodiment, a human controls an autonomous device to perform actions in the teleoperation. In at least one embodiment, a human records camera images of an autonomous device and what a human has done. In at least one embodiment, images are used to train an automated policy. In at least one embodiment, a human is replaced by a training action generator (e.g., TAMP) that generates training actions for an autonomous device.In at least one embodiment, a training action generator replaces cloning of behavior instead of requiring human intervention.

[0009] In at least one embodiment, a planning module 106 receives an initial state of an environment 102. In at least one embodiment, the planning module 106 receives an initial state of an autonomous device 104 (e.g., a robot or other autonomous or semi-autonomous machine). In at least one embodiment, the planning module 106 generates training actions 108 for an autonomous device. In at least one embodiment, the autonomous device 114 executes training actions 112 generated by the planning module 106. In at least one embodiment, the actions 116 executed by an autonomous device are provided to a neural network 118. In at least one embodiment, an image sensor 122 generates images of performed training actions 116 executed by the autonomous device 114 (e.g., to effect changes to the initial state of an environment).In at least one embodiment, images of performed actions 120 generated using the image sensor 122 are provided to or otherwise retrieved by the neural network 118. In at least one embodiment, the neural network 118 is trained using performed training actions 116 performed by the autonomous device 114 and / or images of performed actions 120. In at least one embodiment, the neural network 118 is trained to provide information used by one or more control inputs to control an autonomous device, such as the autonomous device 114 and / or the vehicle 1000 of FIG. Fig. 10A-D, to perform tasks in an environment (e.g., an unknown and / or previously unseen environment).

[0010] In at least one embodiment, the neural network training system 100 is used to generate motion planning tasks as described in Fig. 6. In at least one embodiment, the planning module 106 is to access the initial state of an environment 102. In at least one embodiment, the planning module 106 is to access, for example, an initial state of a known environment. In at least one embodiment, the initial state of an environment 102 includes information indicating a state of one or more objects in an environment. In at least one embodiment, an environment may include, for example, an object such as a cup, for which information indicating a state of that cup may indicate a pose and / or position of that cup on a table in that environment. In at least one embodiment, the initial state of the environment 102 includes a group of parts, as in Fig. 3. In at least one embodiment, the initial state of the environment 102 comprises a group of stacked objects, as shown in Fig. 4. In at least one embodiment, the initial state of the environment 102 includes an initial state of an autonomous device 104, as described below.

[0011] In at least one embodiment, the planning module 106 receives an initial state of an autonomous device 114, for example, a robot. In at least one embodiment, for example, an initial state of an autonomous device 104 may include information indicating a position of a robot relative to a cup or certain joint angles of a robot. In at least one embodiment, the initial state of the autonomous device 104 is part of the initial state of the environment 102. In at least one embodiment, the initial state of the autonomous device 104 includes a position of a gripper of the autonomous device relative to an object in the environment, such as a cup on a table, as in Fig. 4. In at least one embodiment, the initial state of the autonomous device 104 includes a position of angles of various movable joints of the autonomous device 104, as shown in Fig. 4. In at least one embodiment, the initial state of the autonomous device 104 includes joints of the autonomous device 104, including an elbow joint, a pivot joint, and a wrist joint, as shown in Fig. 4 shown.

[0012] In at least one embodiment, the planning module 106 includes one or more components configured to generate one or more training actions 108. In at least one embodiment, the planning module 106 generates one or more training actions 108 used to train an autonomous device 114. In at least one embodiment, the training actions 108 may include joint trajectories of an autonomous device. In at least one embodiment, joint trajectories of an autonomous device include trajectories of joints of the autonomous device 114. For example, in at least one embodiment, joint trajectories of an autonomous device include trajectories of joints of the autonomous device that grasp an object and move the object from a first position to a second position.In at least one embodiment, joint trajectories of an autonomous device are mapped to a joint space. In at least one embodiment, a joint space may specify a coordinate space of a joint of an autonomous device 114. In at least one embodiment, joint trajectories are executed on an autonomous device. In at least one embodiment, a joint state of an autonomous device and training actions performed by an autonomous device are recorded for each point in time. For example, in at least one embodiment, a joint state of an autonomous device and training actions performed by an autonomous device are recorded every second.In at least one embodiment, the planning module 106 outputs one or more training actions 108 represented by one or more common control commands used to control one or more control inputs that control or otherwise influence one or more angles of one or more joints of the autonomous device 114. For example, in at least one embodiment, common control commands may be used to control one or more joints of a robot (e.g., a robot arm).

[0013] In at least one embodiment, the planning module 106 is to access a state of an environment in one or more simulations. In at least one embodiment, the planning module 106 may access information indicative of a state of an environment without performing object detection (e.g., detecting objects in images). In at least one embodiment, the planning module 106 uses one or more guided tasks, resulting in planning going hand in hand with gathering visual information about an environment. In at least one embodiment, the planning module 106 may gather essentially everything from the environment. For example, in at least one embodiment, the planning module 106 may gather an initial state of the environment, such as the positions of all objects and / or the attitude of all objects.For example, in at least one embodiment, the planning module 106 may capture the initial state of an autonomous device, such as position, attitude, joint positions of the autonomous device.

[0014] In at least one embodiment, the planning module 106 is intended to simulate an initial state of an environment. In at least one embodiment, the planning module 106 utilizes privileged latent information about a state of an environment to select an executable action for an autonomous device.

[0015] In at least one embodiment, the planning module 106 is to use one or more TAMP (Input / Output Contract) policies to generate training actions 108. In at least one embodiment, object detection and / or other processing of an image is performed to understand a state of an environment and / or actions performed.

[0016] In at least one embodiment, training actions 108 include one or more actions to change an initial state of an environment, such as the initial state of environment 102. For example, in at least one embodiment, performing a training action is to move a cup from a first position on a table to a second position on the table. In at least one embodiment, in such an example, a final state of an environment is a cup in a second position (different from a first position) on a table. In at least one embodiment, training actions 108 are continuous actions relative to a position where an autonomous device should be located.

[0017] In at least one embodiment, the training actions 108 include a position and / or orientation of a portion of the autonomous device 114. In at least one embodiment, the training action 108 may include, for example, a position (e.g., x, y, z), a position change (e.g., Δx, Δy, Δz), and / or a rotation angle command corresponding to a hand of a robot. In at least one embodiment, a training action may, for example, specify a grasp of a robot hand, represented as a discrete indicator variable of zero, one, or minus one. In at least one embodiment, the training actions are high-level and / or low-level training actions. In at least one embodiment, high-level training actions relate to selecting an action, for example, based on the color or shape of an object.In at least one embodiment, low-level training actions relate to the execution of an action, for example, the position of an object. In at least one embodiment, a pose of an object may be estimated. For example, in at least one embodiment, the planning module 106 estimates the position of an object, for example, a handle of a cup. In at least one embodiment, an estimated pose is constructed from a perspective of the autonomous device 114. For example, in at least one embodiment, the planning module 106 estimates the position of an object relative to the position of a gripper of the autonomous device 114. In at least one embodiment, generated low-level training actions may be transmitted at a high rate.

[0018] In at least one embodiment, the training actions include one or more motor commands of the autonomous device 114. In at least one embodiment, the training actions include one or more algorithms for planning one or more movements of the autonomous device 114.

[0019] In at least one embodiment, the training actions 108 are filtered. In at least one embodiment, the training actions 108 are filtered to improve a selection of the data generated by the planning module 106. For example, in at least one embodiment, the training actions 108 may be filtered such that filtered training actions are easier to perform for a simulation. For example, in at least one embodiment, training actions 108 may have values that lie outside a preferred distribution when generated with the planning module 108 (for example, when the planning module 108 uses randomized algorithms for motion planning). In at least one embodiment, the training actions 108 are filtered based on a workspace constraint and a trajectory length constraint to provide more optimal actions for learning.

[0020] In at least one embodiment, post-processing is applied to the training action 108. For example, in at least one embodiment, one or more post-processing operations may be performed to generate a training action 108 suitable for training the neural network 118. In at least one embodiment, the training actions 108 are generated such that the cost of clean training actions is minimized. In at least one embodiment, the training actions 108 are selected by screening out bad training actions. In at least one embodiment, the screening out of bad training actions is performed by a human.

[0021] In at least one embodiment, software (e.g., one or more software programs) may receive training actions generated by the planning module. In at least one embodiment, software may modify the training actions generated by the planning module. In at least one embodiment, the modified training actions may be received by an autonomous device. In at least one embodiment, the autonomous device may perform modified training actions. In at least one embodiment, a simulated autonomous device performs training actions according to one or more rules (e.g., under one or more parameters that specify how the simulation should proceed). In at least one embodiment, the training actions include one or more actions that an autonomous device is permitted to perform.In at least one embodiment, a permitted training action for the autonomous device may include, for example, moving so that it does not collide with other objects and / or rules for grasping and / or releasing objects.

[0022] In at least one embodiment, the planning module 106 includes an open-loop plan (a series of waypoints) defined in joint space. In at least one embodiment, an open-loop plan includes positions where a robot arm with a gripper can move, such as gripper actions for grasping or releasing. In at least one embodiment, an open-loop plan encodes waypoints and grasp points. In at least one embodiment, the planning module 106 does not change an open-loop plan when an environment changes. In at least one embodiment, the planning module 106 changes an open-loop plan during replanning. In at least one embodiment, the planning module 106 provides an open-loop plan with waypoints during training.In at least one embodiment, the goal of an autonomous device is to reach waypoints, regardless of the current position of the autonomous device. In at least one embodiment, commands given to an autonomous device to reach waypoints are recorded sequentially.

[0023] In at least one embodiment, the autonomous device 114 includes one or more components configured to perform one or more autonomous tasks. In at least one embodiment, the autonomous device 114 is equipped with the planning module 106. In at least one embodiment, the autonomous device 114 interacts with objects in an environment. For example, in at least one embodiment, the autonomous device 114 picks up and places items or opens a door. In at least one embodiment, a video of these interactions is recorded at specific times. In at least one embodiment, images of the autonomous device 114 and training actions 108 of the autonomous device 114 at specific times are determined.In at least one embodiment, a training policy may only match a behavior if a training policy has access to a camera and not to an actual state of an environment.

[0024] In at least one embodiment, image sensor 122 includes one or more components configured to generate one or more images. In at least one embodiment, image sensor 122 observes images 120 of training actions performed by autonomous device 114. In at least one embodiment, a virtual image sensor may observe changes in a state of the environment during the simulation. An example of a change in a state of the environment is moving a cup from a first position to a second position on a table. In at least one embodiment, a virtual image sensor may render images of a state of the environment.

[0025] In at least one embodiment, training actions are modified to include images obtained from an image sensor to enhance training of a neural network. In at least one embodiment, an autonomous device performs actions observed over a history of frames in the video.

[0026] In at least one embodiment, a neural network does not change a state of an environment during training because a neural network does not have access to exact positions of objects in an environment during training. In at least one embodiment, a neural network uses images as a proxy to attempt to infer the state of the environment during training and therefore uses previous video frames to infer the state of the environment during training. In at least one embodiment, previous video frames are input to a neural network during training. In at least one embodiment, a video is a surrogate for a state of the environment. In at least one embodiment, observed states of the environment or images are used to detect a state of the environment.

[0027] In at least one embodiment, an image sensor may be a camera. In at least one embodiment, images are captured by an image sensor at any given time. In at least one embodiment, images are not a complete substitute for a state of an environment, but rather, images are a proxy for a state of the environment. In at least one embodiment, a series of images is required for a complete state of an environment.

[0028] In at least one embodiment, an image of how an autonomous device reached a next waypoint is recorded when a waypoint is reached. In at least one embodiment, the images at each waypoint are input into a neural network at specific times. In at least one embodiment, the actions are determined by a planning module based on the images. In at least one embodiment, the actions and images are stored.

[0029] In at least one embodiment, the neural network 118 is a transformer neural network. In at least one embodiment, the neural network 118 receives training actions 104 performed with images 120 of an environment 108. In at least one embodiment, the neural network 118 replicates training actions that a planning module 106 would generate if it had full access to an environment. In at least one embodiment, the neural network 118 is pre-trained to mimic a planning module. In at least one embodiment, the neural network 118 uses a visual machine learning model.

[0030] In at least one embodiment, the performed actions 108 are input to the neural network 118. In at least one embodiment, images of performed actions 116 and joint angles of a robot are input to the neural network 118. In at least one embodiment, the actions are regressed to expert actions for the autonomous device 114.

[0031] In at least one embodiment, a trained neural network replaces a planning module to better predict training actions based on newly generated or additional actions that leverage previous training actions generated by a planning module. In at least one embodiment, a neural network has less information than a planning module.

[0032] In at least one embodiment, the neural network 118 treats performed actions as a supervised learning problem. In at least one embodiment, the neural network 118 has an explicit history.

[0033] In at least one embodiment, the neural network 118 for an autonomous device 114 is trained to perform actions using automatically generated training actions 108 instead of human interactions, meaning that the neural network 118 is trained without human supervision or interaction.

[0034] In at least one embodiment, the neural network 118 associates each image with the corresponding action. In at least one embodiment, the neural network 118 acquires images of an environment 108 and modifies training actions 108. In at least one embodiment, the neural network is trained with modified training actions 108.

[0035] In at least one embodiment, the neural network 118 outputs robot actions. However, in at least one embodiment, the system 100 does not need to rely on the training actions 108 generated by the planning module 106 because the training actions 108 generated by a planning module 106 are modified with images 120.

[0036] In at least one embodiment, neural network 118 outputs a command to control an inductor. In at least one embodiment, neural network 118 enables high-frequency controls that command multiple actions simultaneously. In at least one embodiment, neural network 118 is trained to recognize strategies for performing future tasks. In at least one embodiment, a training action is predicted at a specific time. In at least one embodiment, a training action is a delta Δx, Δy, Δz (e.g., a change in position) that an autonomous device performs to accomplish a task.

[0037] In at least one embodiment, neural network 118 includes an output layer that uses a Gaussian mixture model. In at least one embodiment, a planning module executes in a cost minimization mode, wherein a planning module is configured to find a low-cost solution relative to minimizing time. In at least one embodiment, a motion planning policy is executed for a budget until a motion planning policy finds a lowest-cost solution.

[0038] In at least one embodiment, neural network 118 may be trained by training actions performed by an autonomous device 114 and by images 120 of performed training actions. In at least one embodiment, neural network 118 may be trained using performed training actions and a change in a state of the environment.

[0039] In at least one embodiment, observed changes in a known state are used to predict training actions in an unknown environment. In at least one embodiment, a neural network outputs robot actions for an unknown environment. In at least one embodiment, a trained neural network can be used to control an autonomous device in an unknown environment. In at least one embodiment, an unknown environment is a real environment. In at least one embodiment, an unknown environment is a simulated environment. In at least one embodiment, a neural network is connected to an autonomous device. In at least one embodiment, a neural network receives images of an unknown environment. In at least one embodiment, a neural network predicts actions based on received images.For example, in at least one embodiment, a neural network detects a cup on a washing machine and creates a plan to retrieve the cup. In at least one embodiment, a neural network stores actions that were executable in a simulation and creates a plan to execute those same actions. In at least one embodiment, a neural network repeats a process until a final state of the environment is reached or repeats steps until a certain condition is met.

[0040] In at least one embodiment, the autonomous device 114 equipped with a neural network 118 can be deployed in an unknown environment without human supervision because the neural network 118 automatically generates training actions. In at least one embodiment, the neural network 118 learns and performs tasks that involve manipulating multiple objects in a sequence of different action types. In at least one embodiment, the autonomous device 114 is intended to perform actions in an unknown environment using the neural network 118. In at least one embodiment, the autonomous device 114 can use one or more sensors (e.g., an image sensor for collecting images) and a neural network 118 to perform one or more actions in a previously seen / unseen environment.In at least one embodiment, images collected during training and included in modified training actions enable deployment of the autonomous device 114 with the neural network 118 in one or more environments to perform one or more robot control tasks.

[0041] In at least one embodiment, neural network 118 is trained to predict an action based on a transformer policy. In at least one embodiment, an autonomous device captures an image, and a transformer policy predicts an action for that image at any time.

[0042] In at least one embodiment, the autonomous device detects only portions of the environment that can be captured by cameras of the autonomous device. In at least one embodiment, an autonomous device can see less than the planning module 106.

[0043] In at least one embodiment, neural network 118 predicts actions for an autonomous device in an unknown environment. In at least one embodiment, neural network 118 predicts one action at each point in time.

[0044] In at least one embodiment, an autonomous device captures a single image of an environment using a camera. In at least one embodiment, a single image represents a snapshot of a state of an environment. In at least one embodiment, an autonomous device requires a series of images to obtain a complete state of an environment.

[0045] In at least one embodiment, each block of the method 200 described herein comprises a computational process that may be performed using any combination of hardware, firmware, and / or software. For example, in at least one embodiment, various functions may be performed by a processor executing instructions stored in memory. In at least one embodiment, the method 200 may also be executed as computer-readable instructions stored on a computer storage medium. In at least one embodiment, the method 200 may be provided by a standalone application, service, or hosted service (standalone or in combination with another hosted service), or a plug-in for another product, to name a few. In at least one embodiment, the method 200 is additionally described, by way of example, with respect to the system 100 of Fig. 1. In at least one embodiment, these methods may additionally or alternatively be performed by any system or combination of systems, including, but not limited to, those described herein.

[0046] Fig. Figure 2 shows a flowchart illustrating a method 200 for training a neural network according to at least one embodiment. In at least one embodiment, the method 200 for training a neural network includes a process that causes a planning module to perform a motion planning task, as shown in Fig. 6 shown.

[0047] In at least one embodiment, the method 200 includes, in step 202, accessing an initial state of an environment and an initial state of an autonomous device. For example, in at least one embodiment, the planning module 106 is to access the initial state of the environment 102 and the initial state of the autonomous device 104.

[0048] In at least one embodiment, method 200 includes, in step 204, generating training actions for training an autonomous device. For example, in at least one embodiment, planning module 106 is to use the initial state of environment 102 and the initial state of autonomous device 104 to generate one or more training actions 108.

[0049] In step 208, an autonomous device executes training actions generated by a planning module according to at least one embodiment. For example, in at least one embodiment, the planning module generates training actions to be executed by an autonomous device.

[0050] In step 210, an image sensor observes training actions performed by an autonomous device, according to at least one embodiment. For example, in at least one embodiment, the autonomous device performs actions observed by an image sensor.

[0051] In step 212, a camera outputs images of training actions, according to at least one embodiment. For example, in at least one embodiment, the camera outputs images to a neural network for further processing.

[0052] In step 214, a neural network is trained using performed training actions and images of performed training actions. In at least one embodiment, the neural network receives, for example, training actions performed by an autonomous device and images of performed training actions from a camera for training.

[0053] Fig. 3 shows an example of an environment 300 in which an autonomous task is to be performed, in at least one embodiment. In at least one embodiment, an environment 302 is monitored using one or more devices, such as a camera, a radar array, and / or a laser exposure device. In at least one embodiment, the devices acquire one or more images to be processed by an image processing system that is to detect and / or identify one or more objects in the environment 302 and to estimate a 6D pose for one or more objects. In at least one embodiment, the environment 302 includes a first component 304, a second component 306, a third component 308, a fourth component 310, and a fifth component 312. In at least one embodiment, the components 304, 306, 308, 310, and 312 are to be assembled by performing an autonomous task.In at least one embodiment, state and relationship information includes information describing when individual objects are connected, attached, or in an incorrect mounting position. In at least one embodiment, an autonomous task is to identify a sequence of intermediate states reached by a motion planner as described above.

[0054] Fig. 4 shows an example of a group of stacked objects to be manipulated according to a motion planning task, according to at least one embodiment. In at least one embodiment, an autonomous device 402 or another autonomous device manipulates a set of objects in an environment as part of performing a motion planning task. In at least one embodiment, an autonomous device 402 manipulates objects using an autonomous device gripper 410. In at least one embodiment, the robot 402 includes a number of distinct joints capable of movement, including an elbow joint 404, a pivot joint 406, and a wrist 408. In at least one embodiment, the joints of the robot 402 are driven by electric servomotors equipped with position feedback.In at least one embodiment, a control system as described above modifies the position of the gripper 410 by specifying the angles of the various joints.

[0055] In at least one embodiment, the objects manipulated by robot 402 include a book 418, a can 416, a ruler 414, and a metal can 412. In at least one embodiment, a geometric graph stores location and rotation information for each of the objects, and a symbolic graph stores state information associated with the objects. In at least one embodiment, state information may include information such as ruler 414 resting on metal can 412, can 416 resting on book 418, or metal can 412 resting on book 418.In at least one embodiment, an autonomous device planning module examines information in the symbolic scene graph to determine a state representing progress toward a goal of the motion planning task, and a motion planner uses information in the geometric scene graph to modify a state of objects such that a state of objects matches that of the identified state. In at least one embodiment, by repeating the above process, the position of objects is gradually changed until the position of objects matches the goal of the motion planning task.

[0056] Fig. 5 shows an example of a planning module 502 that instructs an autonomous device to execute a task and motion planning task ("TAMP") according to at least one embodiment. In at least one embodiment, the planning module 502 is a Fig. 1. In at least one embodiment, an autonomous device may be a robot, an articulated robot, an autonomous or semi-autonomous vehicle, an automated welder, or a warehouse or assembly line robot. In at least one embodiment, an autonomous device is an excavator for moving material, and a task is an earthmoving task such as digging a trench. In at least one embodiment, a planning module 502 implements a control algorithm that solves a task and motion planning task. In at least one embodiment, the planning module 502 includes a processor and instructions for storage in memory that, when executed by the processor, cause the planning module 502 to generate instructions that cause an autonomous device 514 to execute a motion planning task. In at least one embodiment, the autonomous device 514 is the Fig. 1 and Fig. 4. In at least one embodiment, the planning module 502 obtains position and attitude information 504, which includes information about objects in an environment, such as 6D attitude information and object type information. In at least one embodiment, the position and attitude information 504 is collected by acquiring images of objects in an environment, determining a type for each object, and determining an attitude for each object. In at least one embodiment, the images may be RGB images, infrared images, laser images, radar images, or medical images.

[0057] In at least one embodiment, the position and attitude information 504 is received by the planning module 502 and used to generate a geometric scene graph 506. In at least one embodiment, the geometric scene graph 506 includes information stored on computer-readable media that describes the position and attitude of each object in an observed scene. In at least one embodiment, the geometric scene graph 506 includes three-dimensional position and three-dimensional rotation information for each object. In at least one embodiment, the planning module 502 uses information in the geometric scene graph 506 to generate a symbolic scene graph 508. In at least one embodiment, the symbolic scene graph 508 includes information stored on a computer-readable medium that describes one or more relationships between objects in the geometric scene graph 506.In at least one embodiment, information in symbolic scene graph 508 may describe, for example, that a first object is on top of a second object, that a first object is inside a second object, that a first object is attached to a second object, or that a first object is touching a second object. In at least one embodiment, symbolic scene graph 508 may include information describing a state of an object, such as state information indicating that an object is upside down, stationary, or moving.

[0058] In at least one embodiment, the planning module 502 implements a task scheduler 510. In at least one embodiment, the task scheduler 510 implements task scheduling as described elsewhere herein. In at least one embodiment, the task scheduler 510 plans backward from a goal until it identifies a series of object states reachable from the states of objects identified in the symbolic graph 508. In at least one embodiment, the planning module 502 implements a motion scheduler 512 that uses information from the geometric scene graph 506 to plan a series of motions that transition objects from states represented in the symbolic scene graph 508 to the states identified by the task scheduler 510. In at least one embodiment, training actions are transmitted to an autonomous device 514, which executes the instructions.In at least one embodiment, training actions are transmitted to an autonomous device 514, as shown in . Fig. 1. In at least one embodiment, after the autonomous device 514 executes a command sequence from the motion planner 512, raw position information is obtained from the state of the environment 516. In at least one embodiment, raw position information is obtained from the state of the environment 516, as shown in Fig. 1. In at least one embodiment, position information is obtained from one or more cameras, radar imaging devices, laser imaging devices, or medical imaging devices. In at least one embodiment, medical imaging devices may include two-dimensional or three-dimensional imaging devices, such as x-ray imaging devices, magnetic resonance imaging devices, or computed tomography devices. In at least one embodiment, raw position information is provided to a posture system that generates position and attitude information, and the above process is repeated. In at least one embodiment, the above cycle is repeated until a state of the environment representing the position and attitude of objects and represented in a symbolic scene graph matches a target state of a motion planning task.

[0059] At least one embodiment provides a hierarchical structure of scene graphs for motion planning. In at least one embodiment, abstract symbolic scene graphs are referred to as symbolic scene graphs for simplicity of notation, and 3D scene graphs are referred to as geometric scene graphs. In at least one embodiment, notations for representing scene graphs are specified, and a method for generating both geometric and symbolic scene graphs is provided.

[0060] Fig. 6 shows an example of a process 600 for performing a motion planning task according to at least one embodiment. In at least one embodiment, process 600 is performed using a training system as shown in Fig. 1. In at least one embodiment, the process 600 for training a neural network is performed according to Fig. 2. In at least one embodiment, process 600 may be performed by a scheduling module comprising one or more processors and computer-readable memory. In at least one embodiment, the computer-readable memory stores executable instructions that, when executed by the one or more processors, cause a scheduling module to generate instructions that control an arm of an autonomous device to perform a task.

[0061] In at least one embodiment, a planning module receives the initial state of an environment in block 602. In at least one embodiment, position data may be images collected by a camera, radar, laser imaging device, or medical imaging device. In at least one embodiment, a planning module identifies objects in the environment based on the position data in block 604. In at least one embodiment, a planning module identifies each object by type. In at least one embodiment, a planning module processes the position data in block 606 to determine a six-degree-of-freedom position for each identified object. In at least one embodiment, the position information includes a three-dimensional position and a three-dimensional rotation of each object.In at least one embodiment, in block 608, type and position information is used to generate a geometric graph, such as a geometric graph as described above. In at least one embodiment, in block 610, a planning module uses information in the geometric object graph to determine relationships between the objects identified above. In at least one embodiment, the relationships may include objects being attached to one another, stacked on top of one another, or in a symbolic orientation, such as right-side-up or right-side-down.

[0062] In at least one embodiment, in block 612, information in a symbolic object graph is updated with relationships identified in block 610. In at least one embodiment, some relationship information in the symbolic object graph remains unchanged, and only the information determinable from the position data is updated. In at least one embodiment, in block 614, a planning module uses the information in the symbolic object graph to perform backward planning of tasks. In at least one embodiment, a planning module identifies a state reachable from a state represented in the symbolic object graph, which drives execution of a motion planning task.In at least one embodiment, in block 616, a planning module uses information in the geometric object graph to generate a sequence of training actions that, when sent to an autonomous device, cause an autonomous device to position the objects into a state determined in block 614.

[0063] In at least one embodiment, a planning module determines in block 618 whether a current state of objects matches a desired end state of a motion planning task. In at least one embodiment, if a current state of objects matches a desired state of a motion planning task, the motion planning task is completed, and execution proceeds to block 620. In at least one embodiment, if a current state of objects does not match that of a motion planning task, a task is not completed, and execution returns to block 602 and the above process is repeated.

[0064] In at least one embodiment, the generation of motion planning tasks requires information about the environment (e.g., the geometry of the space in which the robot is located) in order for an autonomous device to correctly perform actions. One way to train an autonomous device is described in the flowchart of Fig. 7 shown. LOGIC

[0065] Fig. 7A shows logic 715, which, as described elsewhere herein, may be used in one or more devices to perform operations as discussed herein according to at least one embodiment. In at least one embodiment, logic 715 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 715 is inference and / or training logic. Details of logic 715 are described below in connection with Fig. 7A and / or 7B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functions or operations described herein, where the logic may be embodied collectively or individually as circuitry that is part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0066] In at least one embodiment, logic 715 may include, without limitation, a code and / or data memory 701 for storing feedforward and / or output weights and / or input / output data and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 715 may include or be coupled to a code and / or data memory 701 for storing graph code or other software for controlling the timing and / or order into which weight and / or other parameter information is to be loaded to configure the logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).In at least one embodiment, code, such as graph code, loads weighting or other parameter information into processor ALUs based on a neural network architecture to which such code corresponds. In at least one embodiment, code and / or data storage 701 stores weighting parameters and / or input / output data of each layer of a neural network trained or used in connection with one or more embodiments during forward propagation of input / output data and / or weighting parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0067] In at least one embodiment, any portion of code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 701 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the decision as to whether the code and / or code and / or data storage 701 is, for example, internal or external to a processor or comprises DRAM, SRAM, flash, or another type of memory may depend on the available on-chip or off-chip memory, the latency requirements of the training and / or inference functions performed, the batch size of the data used in the inference and / or training of a neural network, or a combination of these factors.

[0068] In at least one embodiment, logic 715 may include, without limitation, a code and / or data storage 705 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 705 stores weighting parameters and / or input / output data of each layer of a neural network trained or used in connection with one or more embodiments during backpropagation of input / output data and / or weighting parameters during training and / or inference using aspects of one or more embodiments.In at least one embodiment, logic 715 may include or be coupled to code and / or data memory 705 to store graph code or other software for controlling the timing and / or order into which weight and / or other parameter information is to be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0069] In at least one embodiment, code, such as graph code, causes weight or other parameter information to be loaded into processor ALUs based on a neural network architecture to which such code corresponds. In at least one embodiment, each portion of code and / or data memory 705 may include other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, each portion of code and / or data memory 705 may be internal to or external to one or more processors or other hardware logic devices or circuitry. In at least one embodiment, code and / or data memory 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the decision as to whether the code and / or data storage 705 is, for example, internal or external to a processor, or comprises DRAM, SRAM, flash memory, or another type of memory, may depend on the available on-chip or off-chip memory, the latency requirements of the training and / or inference functions performed, the batch size of the data used in the inference and / or training of a neural network, or a combination of these factors.

[0070] In at least one embodiment, code and / or data memory 701 and code and / or data memory 705 may be separate memory structures. In at least one embodiment, code and / or data memory 701 and code and / or data memory 705 may be a combined memory structure. In at least one embodiment, code and / or data memory 701 and code and / or data memory 705 may be partially combined and partially separate. In at least one embodiment, each portion of code and / or data memory 701 and code and / or data memory 705 may be included in other on-chip or off-chip data storage, including the L1, L2, or L3 cache or system memory of a processor.

[0071] In at least one embodiment, logic 715 may include, without limitation, one or more arithmetic logic unit(s) ("ALU(s)") 710, including integer and / or floating point units, to perform logical and / or mathematical operations based on, at least in part on, or indicated by, training and / or inference code (e.g., code for graphs), a result of which generate activations (e.g., output values of layers or neurons within a neural network) stored in an activation memory 720 and which are functions of input / output and / or weight parameter data stored in a code and / or data memory 701 and / or a code and / or data memory 705.In at least one embodiment, activations stored in activation memory 720 are generated according to linear algebraic and / or matrix-based mathematics performed by ALU(s) 710 in response to the execution of instructions or other code, using weights stored in code and / or data memory 705 and / or data memory 701 as operands, along with other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, some or all of which may be stored in code and / or data memory 705 or code and / or data memory 701 or other on-chip or off-chip memory.

[0072] In at least one embodiment, ALU(s) 710 are included in one or more processors or other logical hardware devices or circuits, while in another embodiment, ALU(s) 710 may be external to a processor or other logical hardware device or circuit that utilizes them (e.g., a coprocessor). In at least one embodiment, ALU(s) 710 may comprise the execution units of a processor or otherwise comprise a bank of ALUs accessible by the execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed-function units, etc.).In at least one embodiment, code and / or data memory 701, code and / or data memory 705, and enablement memory 720 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be located in different processors or other hardware logic devices or circuitry, or a combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, each portion of enablement memory 720 may include other on-chip or off-chip data memory, including a processor's L1, L2, or L3 cache or system memory.Additionally, derivation and / or training code may be stored along with other code accessible to a processor or other hardware logic or circuitry, and retrieved and / or processed using fetch, decode, scheduling, execution, retire, and / or other logic circuitry of a processor.

[0073] In at least one embodiment, the activation memory 720 may be a cache memory, a DRAM, an SRAM, a non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the activation memory 720 may be located entirely or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the decision as to whether the activation memory 720 is located, for example, within or external to a processor, or comprises DRAM, SRAM, flash memory, or another type of memory, may depend on the available on-chip or off-chip memory, the latency requirements of the training and / or inference functions performed, the batch size of the data used in the inference and / or training of a neural network, or a combination of these factors.

[0074] In at least one embodiment, the Fig. 7A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor (e.g., “Lake Crest”) from Intel Corp. In at least one embodiment, the logic 715 shown in Fig. 7A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate arrays (“FPGAs”).

[0075] Fig. 7B shows logic 715 according to at least one embodiment. In at least one embodiment, logic 715 is inference and / or training logic. In at least one embodiment, logic 715 may comprise hardware logic in which computational resources are dedicated or otherwise used exclusively in connection with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, the logic shown in Fig. 7B may be used in conjunction with an application-specific integrated circuit (ASIC), such as Google's TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or a Nervana® processor (e.g., "Lake Crest") from Intel Corp. In at least one embodiment, the logic 715 shown in Fig. 7B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as field-programmable gate arrays (FPGAs). In at least one embodiment, logic 715 includes, without limitation, code and / or data storage 701 and code and / or data storage 705, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, pulse values, and / or other parameter or hyperparameter information. In at least one embodiment, shown in Fig. 7B, each code and / or data memory 701 and code and / or data memory 705 is coupled to a dedicated computing resource, such as computer hardware 702 and computer hardware 706, respectively. In at least one embodiment, each computer hardware 702 and computer hardware 706 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in the code and / or data memory 701 and code and / or data memory 705, respectively, the result of which is stored in the activation memory 720.

[0076] In at least one embodiment, each of the code and / or data storage 701 and 705 and the corresponding computer hardware 702 and 706 corresponds to different layers of a neural network, such that the resulting activation from one memory / computing pair 701 / 702 of code and / or data storage 701 and computer hardware 702 is provided as input to a next memory / computing pair 705 / 706 of code and / or data storage 705 and computer hardware 706 to reflect a conceptual organization of a neural network. In at least one embodiment, each of the memory / computing pairs 701 / 702 and 705 / 706 may correspond to more than one layer of a neural network. In at least one embodiment, additional memory / compute pairs (not shown) following or parallel to memory / compute pairs 701 / 702 and 705 / 706 may be included in logic 715. TRAINING AND DEPLOYMENT OF NEURAL NETWORKS

[0077] Fig. 8 illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, an untrained neural network 806 is trained using a training dataset 802. In at least one embodiment, the training framework 804 is a PyTorch framework, while in other embodiments, the training framework 804 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 804 trains an untrained neural network 806 and enables it to be trained using the processing resources described herein to generate a trained neural network 808. In at least one embodiment, weights may be selected randomly or by pre-training using a deep belief network.In at least one embodiment, the training may be conducted either supervised, partially supervised, or unsupervised.

[0078] In at least one embodiment, an untrained neural network 806 is trained using supervised learning, where the training data set 802 includes an input paired with a desired output for an input, or where the training data set 802 includes an input having a known output, and an output of the neural network 806 is manually evaluated. In at least one embodiment, an untrained neural network 806 is trained in a supervised manner and processes inputs from the training data set 802 and compares the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 806. In at least one embodiment, the training framework 804 adjusts the weights that govern the untrained neural network 806.In at least one embodiment, the training framework 804 includes tools to monitor how well the untrained neural network 806 converges to a model, such as a trained neural network 808, capable of generating correct answers, such as in result 814, based on input data such as a new data set 812. In at least one embodiment, the training framework 804 repeatedly trains an untrained neural network 806 while adjusting the weights to refine an output of the untrained neural network 806 using a loss function and an adaptation algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 804 trains the untrained neural network 806 until the untrained neural network 806 achieves a desired accuracy.In at least one embodiment, the trained neural network 808 may then be used to implement any number of machine learning operations.

[0079] In at least one embodiment, the untrained neural network 806 is trained using unsupervised learning, where the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the training dataset 802 for unsupervised learning comprises input data without associated output data, or "ground truth data." In at least one embodiment, an untrained neural network 806 can learn groupings within the training dataset 802 and determine how individual inputs are related to the untrained dataset 802. In at least one embodiment, the unsupervised training can be used to generate a self-organizing map in a trained neural network 808 capable of performing operations useful for reducing the dimensionality of a new dataset 812.In at least one embodiment, unsupervised training may also be used for anomaly detection, which may identify data points in a new data set 812 that deviate from the normal patterns of the new data set 812.

[0080] In at least one embodiment, semi-supervised learning may be used, which is a technique in which the training data set 802 includes a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 804 may be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 808 to adapt to a new data set 812 without forgetting the knowledge imparted to the trained neural network 808 during initial training.

[0081] In at least one embodiment, the training framework 804 is a framework processed in conjunction with a software development toolkit, such as an OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, an OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 715 or uses logic 715 to perform operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform operations described herein.

[0082] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, particularly neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variations thereof.

[0083] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose determination (e.g., of humans and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or variations thereof.

[0084] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as model optimizers. In at least one embodiment, a model optimizer is a command-line tool that facilitates transitions between training and deploying neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processing units, such as a GPU, CPU, PPU, GPGPU, and / or variants thereof. In at least one embodiment, a model optimizer generates an internal representation of a model and optimizes the model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model used for training.In at least one embodiment, a model optimizer performs various neural network operations, such as modifying inputs to a model (e.g., changing the size of inputs to a model), modifying a size of inputs of a model (e.g., modifying a batch size of a model), modifying a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof.

[0085] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, an inference engine is a C++ library or any library in a suitable programming language. In at least one embodiment, an inference engine is used to infer input data. In at least one embodiment, an inference engine implements various classes to infer input data and produce one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, specify input and / or output formats, and / or execute a model on one or more devices.

[0086] In at least one embodiment, OpenVINO provides various capabilities for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that use one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to execute a first portion of the code on a CPU and a second portion of the code on a GPU and / or an FPGA.In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0087] In at least one embodiment, OpenVINO includes various functionalities similar to functionalities associated with a CUDA programming model, such as various neural network operations associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more operations of the CUDA programming model are performed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO. DATA CENTER

[0088] Fig. Figure 9 shows an example of a data center 900 in which at least one embodiment may be used. In at least one embodiment, the data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0089] In at least one embodiment, as in Fig. 9, the data center infrastructure layer 910 may include a resource orchestrator 912, clustered compute resources 914, and node compute resources (“node CRs”) 916(1)-916(N), where “N” represents a positive integer (which may be a different integer “N” than that used in other figures). In at least one embodiment, the node computing resources 916(1)-916(N) may include any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), storage devices 918(1)-918(N) (e.g., dynamic read-only memory, solid-state storage, or hard disk drives), network input / output devices ("NW I / O"), network switches, virtual machines ("VMs"), power modules and cooling modules, etc.In at least one embodiment, one or more of the node computing resources 916(1)-916(N) may be a server having one or more of the above-mentioned computing resources.

[0090] In at least one embodiment, grouped computing resources 914 may include separate groupings of node computing resources housed in one or more racks (not shown) or in many racks housed in data centers in different geographic locations (also not shown). In at least one embodiment, separate groupings of node computing resources within grouped computing resources 914 may include grouped computing, networking, storage, or memory resources that may be configured or allocated to support one or more workloads. In at least one embodiment, multiple node computing resources, including CPUs or processors, may be grouped in one or more racks to provide computing resources to support one or more workloads.In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and switches in any combination.

[0091] In at least one embodiment, resource orchestrator 912 may configure or otherwise control one or more node CRs 916(1)-916(N) and / or clustered computing resources 914. In at least one embodiment, resource orchestrator 912 may include a software design infrastructure ("SDI") management entity for data center 900. In at least one embodiment, resource orchestrator 912 may include hardware, software, or a combination thereof.

[0092] In at least one embodiment, as in Fig. 9, the framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, the framework layer 920 may comprise a framework for supporting software 932 of the software layer 930 and / or one or more applications 942 of the application layer 940. In at least one embodiment, the software 932 or the application(s) 942 may each comprise web-based service software or applications such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be a free and open source software web application framework such as, but not limited to, Apache Spark™ (hereinafter "Spark"), which may utilize a distributed file system 928 for processing large amounts of data (e.g., "Big Data").In at least one embodiment, job scheduler 922 may include a Spark driver to facilitate scheduling workloads supported by different layers of data center 900. In at least one embodiment, configuration manager 924 may be capable of configuring different layers, such as software layer 930 and framework layer 920, including Spark and distributed file system 928 to support large-scale computing. In at least one embodiment, resource manager 926 may be capable of managing clustered or grouped compute resources associated with or assigned to support distributed file system 928 and job scheduler 922. In at least one embodiment, clustered or grouped compute resources may include grouped compute resources 914 on data center infrastructure layer 910.In at least one embodiment, the resource manager 926 may coordinate with the resource orchestrator 912 to manage these allocated or assigned computing resources.

[0093] In at least one embodiment, the software 932 included in software layer 930 may include software used by at least portions of node CRs 916(1)-916(N), clustered computing resources 914, and / or distributed file system 928 of framework layer 920. In at least one embodiment, one or more types of software may include, but are not limited to, web page scanning software, email virus scanning software, database software, and streaming video content software.

[0094] In at least one embodiment, applications 942 included in application layer 940 may include one or more types of applications used by at least portions of node compute resources 916(1)-916(N), clustered compute resources 914, and / or distributed file system 928 of framework layer 920. In at least one embodiment, one or more types of applications may include any number of genomic applications, cognitive computing applications, and machine learning applications, including, but not limited to, training or inference software, machine learning frameworks (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

[0095] In at least one embodiment, each of configuration manager 924, resource manager 926, and resource orchestrator 912 may implement any number and type of self-modifying actions based on any amount and type of data collected in any technically feasible manner. In at least one embodiment, self-modifying actions may relieve a data center operator 900 from potentially making poor configuration decisions and potentially avoiding underutilized and / or underperforming portions of a data center.

[0096] In at least one embodiment, data center 900 may include tools, services, software, or other resources to train one or more machine learning models or to predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computational resources as described above with respect to data center 900.In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 900 by using weighting parameters calculated by one or more training techniques described herein.

[0097] In at least one embodiment, the data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform the training and / or inference using the resources described above. Furthermore, one or more of the software and / or hardware resources described above may be configured as a service to enable users to train or infer information, such as image recognition, speech recognition, or other artificial intelligence services.

[0098] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with the Fig. 7A and / or 7B. In at least one embodiment, logic 715 may be used in data center 900 for inferences or predictions based at least in part on weighting parameters calculated using neural network training procedures, neural network functions and / or architectures, or neural network use cases described herein.

[0099] In at least one embodiment, at least one with respect to Fig. 9 is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 9 to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 9 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, wherein training actions 204 are generated and / or the neural network is generated using performed training actions and images of performed training actions of Fig. 2, the surrounding area 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6. AUTONOMOUS VEHICLE

[0100] Fig. 10A shows an example of an autonomous vehicle 1000 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1000 (alternatively referred to herein as "vehicle 1000") may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, the vehicle 1000 may be a semi-trailer truck used to transport cargo. In at least one embodiment, the vehicle 1000 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0101] Autonomous vehicles may be described using automation levels defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers ("SAE") in the "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Highway Vehicles" (e.g., Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and prior and future versions of that standard). In at least one embodiment, the vehicle 1000 may be capable of operating according to one or more of Levels 1 through 5 of autonomous driving capabilities. For example, in at least one embodiment, the vehicle 1000 may be capable of operating in a conditionally automated (Level 3), highly automated (Level 4), and / or fully automated (Level 5) manner, depending on the embodiment.

[0102] In at least one embodiment, vehicle 1000 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1000 may include, without limitation, a propulsion system 1050, such as an internal combustion engine, a hybrid electric power unit, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be connected to a drivetrain of vehicle 1000, which may include, without limitation, a transmission, to enable propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving signals from a gas pedal / accelerator (1052).

[0103] In at least one embodiment, a steering system 1054, which may include, among other things, a steering wheel, is used to steer the vehicle 1000 (e.g., along a desired path or route) when the propulsion system 1050 is operating (e.g., when the vehicle 1000 is in motion). In at least one embodiment, the steering system 1054 may receive signals from steering actuators 1056. In at least one embodiment, a steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 1046 may be used to apply vehicle brakes in response to receiving signals from brake actuators 1048 and / or brake sensors.

[0104] In at least one embodiment, controllers (1036) comprising, without limitation, one or more systems-on-a-chip (“SoCs”) (in Fig. 10A not shown) and / or graphics processing units ("GPU(s)"), provide signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1000. For example, in at least one embodiment, controllers 1036 may send signals to apply vehicle brakes via brake actuators 1048, to apply the steering system 1054 via steering actuators 1056, to apply the propulsion system 1050 via gas pedal / accelerator 1052. In at least one embodiment, the controllers 1036 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and issue operational commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in operating the vehicle 1000.In at least one embodiment, the controller(s) 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for emergency redundancy, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof.

[0105] In at least one embodiment, controller(s) 1036 provide signals to control one or more components and / or systems of vehicle 1000 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received, for example and without limitation, from one or more Global Navigation Satellite Systems (GNSS) sensors (e.g., GPS sensor(s)), one or more RADAR sensors 1060, one or more ultrasonic sensors 1062, one or more LIDAR sensors 1064, one or more Inertial Measurement Unit (IMU) sensors 1066 (e.g., accelerometers, gyroscopes, a magnetic compass(es), magnetometers, etc.).), microphone(s) 1096, stereo camera(s) 1068, wide-angle camera(s) 1070 (e.g., fisheye cameras), infrared camera(s) 1072, environmental camera(s) 1074 (e.g., 360-degree cameras), long-range cameras (not in . Fig. 10A), medium-range camera(s) (not shown in Fig. 10A), speed sensor(s) 1044 (e.g., for measuring the speed of vehicle 1000), vibration sensor(s) 1042, steering sensor(s) 1040, brake sensor(s) (e.g., as part of brake sensor system 1046), and / or other types of sensors.

[0106] In at least one embodiment, one or more controllers 1036 may receive inputs (e.g., represented by input data) from an instrument cluster 1032 of the vehicle 1000 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, an audible chime, a speaker, and / or via other components of the vehicle 1000. In at least one embodiment, the outputs may include information such as vehicle speed, velocity, time, map data (e.g., a high-resolution map (not shown) Fig. 10A), location data (e.g., location of vehicle 1000, e.g., on a map), direction, location of other vehicles (e.g., a grid for occupancy), information about objects and the status of objects as perceived by controller(s) 1036, etc. For example, in at least one embodiment, HMI display 1034 may display information about the presence of one or more objects (e.g., a road sign, a warning sign, a traffic light turning green or red, etc.) and / or information about maneuvers the vehicle has performed, is performing, or will perform (e.g., change lanes now, take exit 34B in two miles, etc.).

[0107] In at least one embodiment, the vehicle 1000 further includes a network interface 1024 that may utilize wireless antenna(s) 1026 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, the network interface 1024 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communication ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, wireless antenna(s) 1026 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks (LANs), such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low-power wide-area networks (LPWANs), such as LoRaWAN, SigFox, etc.

[0108] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 may be used in a vehicle 1000 to infer or predict events based at least in part on weighting parameters calculated using neural network training procedures, neural network functions and / or architectures, or neural network use cases described herein.

[0109] In at least one embodiment, at least one with respect to Fig. 10A is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 10A to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 10A illustrates at least one aspect related to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the environment 300 of FIG. 3, group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0110] Fig. 10B shows an example of camera locations and fields of view for the autonomous vehicle 1000 of Fig. 10A according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are an example of an embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be arranged at different locations on the vehicle 1000.

[0111] In at least one embodiment, camera types may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of the vehicle 1000. In at least one embodiment, camera(s) may operate at Vehicle Safety Integrity Level (“ASIL”) B and / or another ASIL level. In at least one embodiment, camera types may achieve any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another shutter type, or a combination thereof.In at least one embodiment, the color filter array may include a red-clear-clear-clear color filter array ("RCCC"), a red-clear-clear-blue color filter array ("RCCB"), a red-blue-green-clear color filter array ("RBGC"), a Foveon X3 color filter array, a Bayer sensor color filter array ("RGGB"), a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear-pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used to increase light sensitivity.

[0112] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multifunction mono camera may be installed to provide functions such as lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may capture and provide images (e.g., videos) simultaneously.

[0113] In at least one embodiment, one or more cameras may be mounted in a mounting arrangement, such as a custom-designed (three-dimensionally ("3D") printed) arrangement, to eliminate stray light and reflections from inside the vehicle 1000 (e.g., reflections from the dashboard reflected in the windshield mirrors) that could impair the camera's ability to capture images. With respect to mounting exterior mirrors, in at least one embodiment, exterior mirror assemblies may be custom 3D printed so that a camera mounting plate conforms to the shape of an exterior mirror. In at least one embodiment, cameras may be integrated into exterior mirrors. In at least one embodiment, for side-facing cameras, cameras may also be integrated into four pillars at each corner of a cab.

[0114] In at least one embodiment, cameras with a field of view encompassing portions of an environment in front of the vehicle 1000 (e.g., forward-facing cameras) may be used for surround vision to assist in identifying forward paths and obstacles, and to provide, with the aid of one or more controllers 1036 and / or control SoCs, information useful for establishing an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, forward-facing cameras may be used to perform many similar ADAS functions as LIDAR, including, but not limited to, emergency braking, pedestrian detection, and collision avoidance.In at least one embodiment, forward-facing cameras may also be used for ADAS features and systems, including but not limited to lane departure warnings (“LDW”), autonomous cruise control (“ACC”), and / or other features such as traffic sign recognition.

[0115] In at least one embodiment, a plurality of cameras may be used in a forward-facing configuration, including, for example, a monocular camera platform comprising a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1070 may be used to perceive objects coming into view from a periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. 10B shows only one wide-angle camera 1070, in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 1000. In at least one embodiment, any number of long-range cameras 1098 (e.g., a long-range stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, long-range cameras 1098 may also be used for object detection and classification, as well as basic object tracking.

[0116] In at least one embodiment, any number of stereo cameras (1068) may also be included in a forward-facing configuration. In at least one embodiment, one or more of the stereo cameras (1068) may include an integrated control unit comprising a scalable processing unit that may provide a field-programmable logic (“FPGA”) and a multi-core processor with an integrated controller area network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to create a 3D map of the environment of the vehicle 1000, including a range estimate for all points in an image.In at least one embodiment, one or more stereo cameras 1068 may include, without limitation, a compact stereo vision sensor(s), which may include, without limitation, two camera lenses (one each on the left and right) and an image processing chip that can measure the distance from the vehicle 1000 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1068 may be used in addition to, or alternatively to, those described herein.

[0117] In at least one embodiment, cameras with a field of view that includes portions of the environment to the sides of the vehicle 1000 (e.g., side cameras) may be used for a surround view that provides information used to create and update an occupancy grid and to generate side impact collision warnings. For example, in at least one embodiment, surround camera(s) 1074 (e.g., four surround cameras, as in Fig. 10B) may be positioned on the vehicle 1000. In at least one embodiment, the surround camera(s) 1074 may include, without limitation, any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras may be positioned on a front, a rear, and sides of the vehicle 1000. In at least one embodiment, the vehicle 1000 may utilize three surround cameras (e.g., left, right, and rear) and utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround camera.

[0118] In at least one embodiment, cameras with a field of view encompassing portions of an environment behind the vehicle 1000 (e.g., rearview cameras) may be used for parking assistance, surround view, forward collision warnings, and the creation and updating of a vehicle occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras that are also suitable as front-facing cameras (e.g., long-range camera(s) 1098 and / or mid-range camera(s) 1076, stereo camera(s) 1068, infrared camera(s) 1072, etc.), as described herein.

[0119] In at least one embodiment, at least one with respect to Fig. 10B is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 10B to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 10B illustrates at least one aspect related to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the environment 300 of FIG. 3, group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0120] Fig. 10C is a block diagram illustrating an example system architecture for the autonomous vehicle 1000 of Fig. 10A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1000 is Fig. 10C as if connected via a bus 1002. In at least one embodiment, bus 1002 may include, without limitation, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, a CAN may be a network within vehicle 1000 used to support the control of various features and functions of vehicle 1000, such as brake application, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1002 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1002 may be read to determine steering wheel angle, vehicle speed, engine speeds ("RPMs"), button positions, and / or other vehicle status information.In at least one embodiment, bus 1002 may be a CAN bus that is ASIL B compliant.

[0121] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or alternatively to CAN. In at least one embodiment, bus 1002 may consist of any number of buses, which may include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other bus types using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 1002 may communicate with each of the components of vehicle 1000, and two or more buses of bus 1002 may communicate with corresponding components.In at least one embodiment, any system on chip(s) ("SoC(s)") 1004 (such as SoC 1004(A) and SoC 1004(B)), controller 1036, and / or computer within the vehicle may have access to the same input data (e.g., inputs from sensors of vehicle 1000) and may be connected to a common bus, such as a CAN bus.

[0122] In at least one embodiment, the vehicle 1000 may include one or more controllers 1036 as described herein with respect to Fig. 10A. In at least one embodiment, the controller(s) 1036 may be used for a variety of functions. In at least one embodiment, the controller(s) 1036 may be coupled to any of various other components and systems of the vehicle 1000 and may be used to control the vehicle 1000, artificial intelligence of the vehicle 1000, infotainment for the vehicle 1000, and / or other functions.

[0123] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of SoCs 1004 may include, without limitation, central processing units ("CPU(s)") 1006, graphics processing units ("GPU(s)") 1008, processor(s) 1010, cache(s) 1012, accelerator(s) 1014, data storage(s) 1016, and / or other components and functions not shown. In at least one embodiment, SoC(s) 1004 may be used to control vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1004 may be combined in a system (e.g., system of vehicle 1000) with a high definition (“HD”) map 1022 that may receive map updates and / or updates via a network interface 1024 from one or more servers (in Fig. 10C not shown).

[0124] In at least one embodiment, CPU(s) 1006 may comprise a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, CPU(s) 1006 may comprise multiple cores and / or Level 2 caches ("L2 caches"). For example, in at least one embodiment, CPU(s) 1006 may comprise eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU(s) 1006 may comprise four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2-megabyte (MB) L2 cache). In at least one embodiment, CPU(s) 1006 (e.g., CCPLEX) may be configured to support concurrent cluster operations, allowing any combination of clusters of CPU(s) 1006 to be active at any one time.

[0125] In at least one embodiment, one or more of the CPU(s) 1006 may implement power management features, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clocked when idle to dynamically conserve power; each core clock may be clocked when that core is not actively executing instructions due to the execution of Wait for Interrupt (WFI) / Wait for Event (WFE) instructions; each core may be independently powered; each core cluster may be independently clocked when all cores are clocked or powered; and / or each core cluster may be independently powered when all cores are powered.In at least one embodiment, CPU(s) 1006 may further implement an improved state management algorithm, specifying permissible states and expected wake-up times, and hardware / microcode determining which state is most appropriate for the core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified state entry sequences in software, offloading work to microcode.

[0126] In at least one embodiment, GPU(s) 1008 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, GPU(s) 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU(s) 1008 may use an extended Tensor instruction set. In at least one embodiment, GPU(s) 1008 may include one or more streaming microprocessors, where each streaming microprocessor may include a Level 1 cache ("L1 cache", e.g., an L1 cache with at least 96 KB of memory capacity) and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512 KB of memory capacity). In at least one embodiment, GPUs 1008 may include at least eight streaming microprocessors.In at least one embodiment, GPUs 1008 may utilize one or more application programming interfaces (APIs). In at least one embodiment, GPUs 1008 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0127] In at least one embodiment, one or more of the GPU(s) 1008 may be power-optimized for optimal performance in automotive and embedded systems use cases. For example, in at least one embodiment, the GPU(s) 1008 may be constructed on a fin field-effect transistor ("FinFET") circuit. In at least one embodiment, each streaming microprocessor may include a number of mixed-precision processing cores divided into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 FP64 cores could be divided into four processing blocks.In at least one embodiment, each processing block could be assigned 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level zero ("L0") instruction cache, a scheduler (e.g., warp scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to enable efficient execution of workloads with a mix of computations and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grained synchronization and collaboration between parallel threads.In at least one embodiment, streaming microprocessors may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0128] In at least one embodiment, one or more GPUs 1008 may include high-bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem to provide, in some examples, a peak memory bandwidth of approximately 900 GB / second. In at least one embodiment, in addition to or as an alternative to HBM memory, synchronous graphics RAM ("SGRAM") may be used, such as double data rate type 5 ("GDDR5") synchronous graphics RAM.

[0129] In at least one embodiment, the GPU(s) 1008 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to enable the GPU(s) 1008 to directly access the page tables of the CPU(s) 1006. In at least one embodiment, when a GPU of the memory management unit ("MMU") of the GPU(s) 1008 detects a fault, an address translation request may be transmitted to the CPU(s) 1006. In response, two CPUs of the CPU(s) 1006 may look up a virtual-to-physical mapping for an address in their page tables and transmit the translation back to the GPU(s) 1008, in at least one embodiment.In at least one embodiment, unified memory technology may enable a single unified virtual address space for the memory of both the CPU(s) 1006 and the GPU(s) 1008, thereby simplifying programming of the GPU(s) 1008 and porting applications to the GPU(s) 1008.

[0130] In at least one embodiment, the GPU(s) 1008 may include any number of access counters that can track the frequency of access by the GPU(s) 1008 to the memory of other processors. In at least one embodiment, access counters can help ensure that memory pages are moved to the physical memory of a processor that accesses pages most frequently, thereby improving efficiency for memory regions shared by multiple processors.

[0131] In at least one embodiment, one or more SoC(s) 1004 may include any number of cache(s) 1012, including those described herein. For example, in at least one embodiment, cache(s) 1012 may include a Level 3 ("L3") cache available to both CPU(s) 1006 and GPU(s) 1008 (i.e., connected to CPU(s) 1006 and GPU(s) 1008). In at least one embodiment, cache(s) 1012 may include a write-back cache that may track line states, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache may include 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may also be used.

[0132] In at least one embodiment, one or more SoC(s) 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s) 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM) may enable a hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware acceleration cluster may be used to supplement the GPU(s) 1008 and offload some of the tasks of the GPU(s) 1008 (e.g., to free up more cycles of the GPU(s) 1008 to perform other tasks).In at least one embodiment, accelerators 1014 could be used for targeted workloads (e.g., perception, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.) that are stable enough to be accelerated. In at least one embodiment, a CNN may include a region-based or regional convolutional neural network ("RCNNs") and fast RCNNs (e.g., as used for object detection), or another CNN type.

[0133] In at least one embodiment, accelerators 1014 (e.g., hardware acceleration clusters) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, DLA(s) may include, without limitation, one or more tensor processing units ("TPUs") that can be configured to provide an additional tens of trillion operations per second for deep learning applications and inferences. In at least one embodiment, TPUs may be accelerators configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, DLA(s) may be further optimized for a particular set of neural network types and floating-point operations, as well as inferences.In at least one embodiment, the design of DLA(s) can provide more performance per millimeter than a typical general-purpose GPU, typically far exceeding the performance of a CPU. In at least one embodiment, TPU(s) can perform multiple functions, including a single-instance convolution function, supporting, for example, INT8, INT16, and FP16 data types for both features and weights, as well as postprocessor functions.In at least one embodiment, DLA(s) can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for a variety of functions, including, but not limited to: a CNN for object identification and recognition using data from camera sensors; a CNN for range estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and recognition using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for safety-related events.

[0134] In at least one embodiment, DLA(s) may perform any function of GPU(s) 1008, and by using an inference accelerator, for example, a designer may target either DLA(s) or GPU(s) 1008 for each function. For example, in at least one embodiment, a designer may focus the processing of CNNs and floating-point operations on DLA(s) and leave other functions to GPU(s) 1008 and / or accelerator(s) 1014.

[0135] In at least one embodiment, the accelerator(s) 1014 may comprise a programmable image accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS"), autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may comprise, for example and without limitation, any number of reduced instruction set computer (RISC) cores, direct memory access (DMA), and / or any number of vector processors.

[0136] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of cameras described herein), image processors, etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, RISC cores may use one of several protocols, depending on the embodiment. In at least one embodiment, RISC cores may execute a real-time operating system ("RTOS"). In at least one embodiment, RISC cores may be implemented using one or more integrated circuits, application-specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, RISC cores may include an instruction cache and / or tightly coupled RAM.

[0137] In at least one embodiment, DMA may enable components of PVA to access system memory independently of CPU(s) 1006. In at least one embodiment, DMA may support any number of features used to optimize a PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0138] In at least one embodiment, vector processors may be programmable processors that may be configured to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may operate as the primary processing engine of a PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM").In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction multiple data ("SIMD") or very long instruction word ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may increase throughput and speed.

[0139] In at least one embodiment, each of the vector processors may include an instruction cache and be coupled to dedicated memory. In at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to use data parallelism. For example, in at least one embodiment, a plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image.In at least one embodiment, vector processors included in a particular PVA may concurrently execute different computer vision algorithms on an image, or even different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, PVA may include additional error correction code ("ECC") memory to increase the overall security of the system.

[0140] In at least one embodiment, accelerators 1014 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high-bandwidth, low-latency SRAM for accelerator 1014. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, including, for example, and without limitation, eight field-configurable memory blocks accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (APB) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, a PVA and a DLA may access the memory via a backbone that provides high-speed access to the memory to a PVA and a DLA.In at least one embodiment, a backbone may comprise a computer vision network on a chip that enables interconnection of a PVA and a DLA with the memory (e.g., using APB).

[0141] In at least one embodiment, an on-chip computer vision network may include an interface that determines that both a PVA and a DLA are providing ready and valid signals before transmitting a control signal / address / data. In at least one embodiment, an interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, an interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0142] In at least one embodiment, one or more of the SoC(s) 1004 may include a real-time ray tracing hardware accelerator. In at least one embodiment, a real-time ray tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model) to generate real-time visualization simulations, for radar signal interpretation, for sound propagation synthesis and / or analysis, for simulation of sonar systems, for general wave propagation simulation, for comparison with lidar data for localization and / or other functions, and / or for other purposes.

[0143] In at least one embodiment, accelerators (1014) may have a variety of applications for autonomous driving. In at least one embodiment, a PVA may be used for critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of a PVA are a good fit for algorithmic domains that require predictable, low-power, and low-latency processing. In other words, a PVA is well-suited for semi- or fully dense regular computations, even on small datasets, which might require predictable, low-latency, and low-power runtimes. In at least one embodiment, such as in vehicle 1000, PVAs could be designed to execute classical computer vision algorithms because they can be efficient at object detection and integer arithmetic processing.

[0144] For example, according to at least one embodiment of the technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, Level 3-5 autonomous driving applications utilize on-the-fly motion estimation / stereo matching (e.g., structure from motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions for inputs from two monocular cameras.

[0145] In at least one embodiment, a PVA may be used to perform dense optical flow. For example, in at least one embodiment, a PVA may process raw radar data (e.g., using a 4D Fast Fourier Transform) to provide processed radar data. In at least one embodiment, a PVA is used for depth-of-flight processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0146] In at least one embodiment, a DLA may be used to power any type of network to improve control and driving safety, including, for example, and without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be represented or interpreted as a probability, or as the relative "weight" of each detection compared to other detections. In at least one embodiment, a confidence measure further enables a system to make decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, a system may set a confidence threshold and consider only detections that exceed the threshold to be true positives.In an embodiment using an automatic emergency braking ("AEB") system, false positive detections would cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections may be considered triggers for AEB. In at least one embodiment, a DLA may run a neural network to regress the confidence value.In at least one embodiment, the neural network may use as input at least a subset of parameters, such as the dimensions of the bounding box, the obtained ground plane estimate (e.g., from another subsystem), the output of IMU sensors 1066 correlated with the orientation of the vehicle 1000, the distance, the estimates of the 3D position of the object obtained from the neural network and / or other sensors (e.g., LIDAR sensors 1064 or RADAR sensor(s) 1060), among others.

[0147] In at least one embodiment, one or more SoC(s) 1004 may include storage 1016 (e.g., memory). In at least one embodiment, storage 1016 may be on-chip memory of SoC(s) 1004, which may store neural networks to be executed on GPU(s) 1008 and / or a DLA. In at least one embodiment, storage 1016 may be large enough to store multiple neural network instances for redundancy and security purposes. In at least one embodiment, storage 1016 may include L2 or L3 caches.

[0148] In at least one embodiment, SoCs (1004) may include any number of processors (1010) (e.g., embedded processors). In at least one embodiment, processor(s) 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and associated security enforcement. In at least one embodiment, a boot and power management processor may be part of a boot sequence of SoC(s) 1004 and provide runtime power management services.In at least one embodiment, a processor may provide for boot and power programming, clock and voltage programming, assistance with system transitions to a low-power state, management of the thermal and temperature sensors of the SoC(s) 1004, and / or management of the power supply states of the SoC(s) 1004. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and SoC(s) 1004 may use ring oscillators to sense the temperatures of CPU(s) 1006, GPU(s) 1008, and / or accelerator(s) 1014.In at least one embodiment, when temperatures are determined to exceed a threshold, a boot and power management processor may invoke a temperature fault routine and place the SoC(s) 1004 into a lower power state and / or place the vehicle 1000 into a chauffeur-to-safe-stop mode (e.g., bring the vehicle 1000 to a safe stop).

[0149] In at least one embodiment, the processor(s) 1010 may further comprise a set of embedded processors that may serve as an audio processing engine, which may be an audio subsystem enabling full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processing core including a digital signal processor with dedicated RAM.

[0150] In at least one embodiment, the processor(s) 1010 may further include an always-on processor engine that may provide the necessary hardware functions to support low-power sensor management and sleep mode use cases. In at least one embodiment, an always-on processor engine may include, among other things, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0151] In at least one embodiment, the processor(s) 1010 may further comprise a security cluster engine, including, without limitation, a dedicated processor subsystem for handling security management for automotive applications. In at least one embodiment, a security cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a security mode, two or more cores, in at least one embodiment, may operate in a lockstep mode, acting as a single core with comparison logic to detect any differences between their operations.In at least one embodiment, processor(s) 1010 may further comprise a real-time camera engine, which may include, without limitation, a dedicated processor subsystem for real-time camera management. In at least one embodiment, processor(s) 1010 may further comprise a high dynamic range signal processor, which may include, without limitation, an image processor that is a hardware engine that is part of a camera processing pipeline.

[0152] In at least one embodiment, processor(s) 1010 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on wide-angle camera(s) 1070, surround camera(s) 1074, and / or cabin surveillance camera sensor(s). In at least one embodiment, the cabin surveillance camera(s) sensors are preferably monitored by a neural network running on another instance of SoC 1004 and configured to detect and respond to events in the cabin.In at least one embodiment, a system in the vehicle interior may perform, without limitation, lip reading to activate cellular service and place a call, dictate emails, change a vehicle's destination, activate or change a vehicle's infotainment system and settings, or enable voice-activated web browsing. In at least one embodiment, certain functions are available to a driver when a vehicle is operating in an autonomous mode and are disabled otherwise.

[0153] In at least one embodiment, a video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment where motion occurs in a video, the noise reduction appropriately weights the spatial information, reducing the weight of information provided by adjacent images. In at least one embodiment where an image or a portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from a previous image to reduce noise in a current image.

[0154] In at least one embodiment, a video image compositor may also be configured to perform stereo rectification on input stereo lens frames. In at least one embodiment, a video image compositor may further be used for interface composition when an operating system desktop is used and GPU(s) 1008 are not required to continuously render new surfaces. In at least one embodiment, a video image compositor may be used to offload the GPU(s) 1008 when the GPU(s) 1008 are turned on and active and performing 3D rendering to improve performance and responsiveness.

[0155] In at least one embodiment, one or more of SoC(s) 1004 may further include a mobile processor serial interface ("MIPI"), a camera serial interface for receiving video and inputs from cameras, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functions. In at least one embodiment, one or more SoC(s) 1004 may further include one or more input / output controllers that may be controlled by software and may be used to receive I / O signals that are not associated with a particular role.

[0156] In at least one embodiment, one or more of SoC(s) 1004 may further include a variety of interfaces to peripherals to enable communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, SoC(s) 1004 may be used to receive data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1064, RADAR sensor(s) 1060, etc., which may be connected via Ethernet channels), data from bus 1002 (e.g., vehicle speed 1000, steering wheel position, etc.), data from GNSS sensor(s) 1058 (e.g., connected via an Ethernet bus or a CAN bus), etc.In at least one embodiment, one or more of SoC(s) 1004 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used to free CPU(s) 1006 from routine data management tasks.

[0157] In at least one embodiment, SoC(s) 1004 may be an end-to-end platform with a flexible architecture spanning automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and efficiently deploys computer vision and ADAS techniques for diversity and redundancy, and provides a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, SoC(s) 1004 may be faster, more reliable, and even more power and space efficient than conventional systems. For example, in at least one embodiment, accelerators (1014) in combination with CPU(s) (1006), GPU(s) (1008), and data storage(s) (1016) may provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0158] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using a high-level programming language, such as C, to execute a variety of processing algorithms on a variety of images. However, in at least one embodiment, CPUs are often unable to meet the performance requirements of many computer vision applications, such as execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex real-time object detection algorithms such as those used in in-vehicle ADAS applications and practical Level 3-5 autonomous vehicles.

[0159] The embodiments described herein enable multiple neural networks to be executed simultaneously and / or sequentially and the results to be combined to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 1020) may include text and word recognition that enables the reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network capable of identifying, interpreting, and semantically understanding a sign and passing this semantic understanding to planning modules running on a CPU complex.

[0160] In at least one embodiment, multiple neural networks may be executed simultaneously, such as when driving at Level 3, 4, or 5. For example, in at least one embodiment, a warning sign indicating the condition "Caution: Flashing lights indicate icy conditions," along with an electric light, may be interpreted independently or jointly by multiple neural networks. In at least one embodiment, such a warning sign may itself be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "Flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which informs a vehicle's path planning software (preferably running on a CPU complex) that icy conditions exist upon detection of flashing lights.In at least one embodiment, a turn signal may be identified by the operation of a third deployed neural network across multiple frames, which informs a vehicle's path planning software of the presence (or absence) of turn signals. In at least one embodiment, all three neural networks may run concurrently, for example, within a DLA and / or on one or more GPUs 1008.

[0161] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify the presence of an authorized driver and / or owner of vehicle 1000. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle when an owner approaches a driver's door and turns on the lights, and to disable such a vehicle in a security mode when an owner exits such a vehicle. In this way, SoC(s) 1004 provide security against theft and / or carjacking.

[0162] In at least one embodiment, a CNN for detecting and identifying emergency vehicles may use data from microphones 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 1004 use a CNN to classify ambient and urban noise, as well as to classify images. In at least one embodiment, a CNN running on a DLA is trained to identify a relative approach speed of an emergency vehicle (e.g., by using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to an area in which a vehicle is operating, as identified by GNSS sensor(s) 1058.In at least one embodiment, when operating in Europe, a CNN will attempt to detect European sirens, and when operating in North America, a CNN will attempt to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine in which a vehicle is slowed down, pulled over to the side of the road, parked, and / or idled using ultrasonic sensor(s) 1062 until emergency vehicles have passed.

[0163] In at least one embodiment, the vehicle 1000 may include one or more CPUs 1018 (e.g., a discrete CPU(s) or a dCPU(s)) that may be connected to one or more SoC(s) 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the CPU(s) 1018 may comprise, for example, an x86 processor. CPU(s) 1018 may be used to perform a variety of functions, including reconciling potentially inconsistent results between ADAS sensors and SoC(s) 1004 and / or monitoring the status and functionality of controllers 1036 and / or an infotainment system on a chip (“infotainment SoC”) 1030, for example. In at least one embodiment, SoC(s) 1004 include one or more interconnects, and an interconnect may include a Peripheral Component Interconnect Express (PCIe).

[0164] In at least one embodiment, the vehicle 1000 may include one or more GPUs 1020 (e.g., discrete GPU(s) or dGPU(s)) that may be connected to the SoC(s) 1004 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the GPU(s) 1020 may provide additional artificial intelligence functionality, for example, by executing redundant and / or distinct neural networks, and may be used to train and / or update neural networks based at least in part on inputs (e.g., sensor data) from sensors of a vehicle 1000.

[0165] In at least one embodiment, vehicle 1000 may further include a network interface 1024, which may include, among other things, wireless antenna(s) 1026 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1024 may be used to enable wireless connection to internet cloud services (e.g., to one or more servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., passenger client devices). In at least one embodiment, a direct connection may be established between vehicle 1000 and another vehicle and / or an indirect connection (e.g., via networks and via the internet) may be established to communicate with other vehicles.In at least one embodiment, direct connections may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide vehicle 1000 with information about vehicles in the vicinity of vehicle 1000 (e.g., vehicles in front of, beside, and / or behind vehicle 1000). In at least one embodiment, such aforementioned functionality may be part of a cooperative adaptive cruise control functionality of vehicle 1000.

[0166] In at least one embodiment, the network interface 1024 may include an SoC that provides modulation and demodulation functionality and enables one or more controllers 1036 to communicate over wireless networks. In at least one embodiment, the network interface 1024 may include a radio frequency front end for upconversion from baseband to radio frequency and downconversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible manner. For example, frequency conversions could be performed by known processes and / or using super-heterodyne processes. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip.In at least one embodiment, network interfaces may include wireless functionality for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0167] In at least one embodiment, the vehicle 1000 may further include one or more data stores 1028, which may include, without limitation, off-chip memory (e.g., off-SoC memory 1004). In at least one embodiment, the data stores 1028 may include, without limitation, one or more memory elements, including RAM, SRAM, DRAM (Dynamic Random Access Memory), VRAM (Video Random Access Memory), flash memory, hard drives, and / or other components and / or devices capable of storing at least one bit of data.

[0168] In at least one embodiment, the vehicle 1000 may further include one or more GNSS sensors 1058 (e.g., GPS and / or Assisted GPS sensors) to support mapping, sensing, grid generation for occupancy detection, and / or path planning functions. In at least one embodiment, any number of GNSS sensors (1058) may be used, including, for example, and without limitation, a GPS using a USB port with an Ethernet-to-serial bridge (e.g., RS-232).

[0169] In at least one embodiment, vehicle 1000 may further include radar sensors 1060. In at least one embodiment, radar sensors 1060 may be used by vehicle 1000 for vehicle detection over long distances, even in darkness and / or extreme weather conditions. In at least one embodiment, the radar functional safety levels may be ASIL B. In at least one embodiment, radar sensors 1060 may use a CAN bus and / or bus 1002 (e.g., for transmitting data generated by radar sensors 1060) for control and access to object tracking data, with some examples allowing access to Ethernet channels for accessing raw data. In at least one embodiment, a variety of radar sensor types may be used. For example, and without limitation, radar sensors 1060 may be suitable for front-, rear-, and side-mounted radar deployments.In at least one embodiment, one or more of RADAR sensors 1060 is a pulse Doppler RADAR sensor.

[0170] In at least one embodiment, the RADAR sensor(s) 1060 may include different configurations, such as long-range narrow field of view, short-range wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control. In at least one embodiment, long-range RADAR systems may provide a wide field of view realized by two or more independent scans, for example, within a range of 250 m (meters). In at least one embodiment, RADAR sensors 1060 may assist in distinguishing between static and moving objects and may be used by the ADAS system 1038 for emergency braking and forward collision warning.In at least one embodiment, the sensors 1060(s) included in a long-range RADAR system may include, without limitation, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and a high-speed CAN and FlexRay interface. In at least one embodiment, with six antennas, a central four-antenna design may produce a focused beam pattern designed to record the surroundings of the vehicle 1000 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, two additional antennas may expand the field of view, making it possible to quickly detect vehicles entering or exiting a lane of the vehicle 1000.

[0171] For example, in at least one embodiment, medium-range radar systems may include a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range radar systems may include, without limitation, any number of radar sensors 1060 designed to be installed at either end of a rear bumper. When installed at either end of a rear bumper, a radar sensor system may, in at least one embodiment, create two beams that continuously monitor blind spots to the rear and side of a vehicle. In at least one embodiment, short-range radar systems may be used in an ADAS system 1038 for blind spot detection and / or lane change assistance.

[0172] In at least one embodiment, the vehicle 1000 may further include one or more ultrasonic sensors 1062. In at least one embodiment, one or more ultrasonic sensors 1062, which may be positioned at a front, rear, and / or side position of the vehicle 1000, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a plurality of ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 1062 may operate at functional safety levels of ASIL B.

[0173] In at least one embodiment, the vehicle 1000 may include one or more LIDAR sensors 1064. In at least one embodiment, the LIDAR sensor(s) 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 1064 may operate at the ASIL B functional safety level. In at least one embodiment, the vehicle 1000 may include multiple LIDAR sensors 1064 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to deliver data to a Gigabit Ethernet switch).

[0174] In at least one embodiment, LIDAR sensors 1064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensors 1064 may have a stated range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1064 may comprise a small device that may be embedded in a front, rear, side, and / or corner location of the vehicle 1000.In at least one embodiment, the LIDAR sensor(s) 1064 in such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of up to 35 degrees with a range of 200 m, even for low-reflectivity objects. In at least one embodiment, front-mounted LIDAR sensors 1064 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0175] In at least one embodiment, LIDAR technologies such as 3D flash LIDAR may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1000 up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receiver that records the time of flight of the laser pulse and the reflected light at each pixel, which in turn corresponds to a range from the vehicle 1000 to objects. In at least one embodiment, flash LIDAR may enable the generation of highly accurate and distortion-free images of the surroundings with each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 1000.In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D star array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per image and collect reflected laser light as a 3D range point cloud and co-registered intensity data.

[0176] In at least one embodiment, vehicle 1000 may further include one or more IMU sensors 1066. In at least one embodiment, IMU sensors 1066 may be disposed in the center of a rear axle of vehicle 1000. In at least one embodiment, IMU sensors 1066 may include, for example, and without limitation, accelerometers, magnetometers, gyroscopes, a magnetic compass, magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in six-axis applications, IMU sensor(s) 1066 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, IMU sensor(s) 1066 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0177] In at least one embodiment, IMU sensors 1066 can be implemented as a miniaturized, high-performance GPS-based inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor(s) 1066 can enable the vehicle 1000 to estimate its heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from a GPS to the IMU sensor(s) 1066. In at least one embodiment, the IMU sensor(s) 1066 and GNSS sensor(s) 1058 can be combined into a single integrated unit.

[0178] In at least one embodiment, the vehicle 1000 may include one or more microphones 1096 disposed in and / or around the vehicle 1000. In at least one embodiment, the microphone(s) 1096 may be used, among other things, for detecting and identifying emergency vehicles.

[0179] In at least one embodiment, the vehicle 1000 may further include any number of camera types, including stereo camera(s) 1068, wide-angle camera(s) 1070, infrared camera(s) 1072, surround camera(s) 1074, long-range camera(s) 1098, medium-range camera(s) 1076, and / or other camera types. In at least one embodiment, cameras may be used to capture images around the entire perimeter of the vehicle 1000. In at least one embodiment, the type of cameras used depends on the vehicle 1000. In at least one embodiment, any combination of camera types may be used to provide the required coverage around the vehicle 1000. In at least one embodiment, the number of cameras employed may vary depending on the embodiment.For example, in at least one embodiment, vehicle 1000 could include six cameras, seven cameras, ten cameras, twelve cameras, or any other number of cameras. In at least one embodiment, cameras can support, for example, and without limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, each camera can be configured as previously described with respect to [ ]. Fig. 10A and Fig. 10B will be described in more detail.

[0180] In at least one embodiment, vehicle 1000 may further include vibration sensor(s) 1042. In at least one embodiment, vibration sensor(s) 1042 may measure vibrations of components of vehicle 1000, such as axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 1042 are used, differences between vibrations may be used to determine friction or slippage of the road surface (e.g., when there is a difference in vibration between a driven axle and a free-spinning axle).

[0181] In at least one embodiment, the vehicle 1000 may include an ADAS system 1038. In at least one embodiment, the ADAS system 1038 may include, without limitation, in some examples, an SoC. In at least one embodiment, the ADAS system 1038 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control ("ACC") system, a cooperative adaptive cruise control ("CACC") system, a forward collision warning ("FCW") system, an automatic emergency braking ("AEB") system, a lane departure warning ("LDW") system, a lane keep assist ("LKA") system, a blind spot warning ("BSW") system, a rear cross traffic warning ("RCTW") system, a forward collision warning ("CW") system, a lane centering ("LC") system, and / or other systems, features, and / or functions.

[0182] In at least one embodiment, the ACC system may use RADAR sensors (1060), LIDAR sensors (1064), and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1000 and automatically adjusts the speed of the vehicle 1000 to maintain a safe distance from preceding vehicles. In at least one embodiment, a lateral ACC system performs follow-through and commands the vehicle 1000 to change lanes if necessary. In at least one embodiment, lateral ACC is connected to other ADAS applications such as LC and CW.

[0183] In at least one embodiment, a CACC system utilizes information from other vehicles, which may be received via a network interface 1024 and / or one or more wireless antennas 1026 from other vehicles over a wireless connection or indirectly via a network connection (e.g., over the Internet). In at least one embodiment, direct connections may be provided by a vehicle-to-vehicle ("V2V") communication link, while indirect connections may be provided by an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communication provides information about immediately preceding vehicles (e.g., vehicles immediately ahead of vehicle 1000 in the same lane), while I2V communication provides information about traffic further afield.In at least one embodiment, a CACC system may include either one or both I2V and V2V information sources. In at least one embodiment, a CACC system may be more reliable given information about vehicles ahead of vehicle 1000 and has the potential to improve traffic flow and reduce congestion on the road.

[0184] In at least one embodiment, an FCW system is configured to alert a driver to a hazard so that the driver can take corrective action. In at least one embodiment, an FCW system utilizes a forward-facing camera and / or one or more radar sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, an FCW system may provide a warning, such as a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0185] In at least one embodiment, an AEB system detects an impending head-on collision with another vehicle or other object and can automatically initiate braking if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system can utilize forward-facing camera(s) and / or RADAR sensor(s) 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when an AEB system detects a hazard, it will typically first alert a driver to take corrective action to avoid a collision, and if that driver does not take corrective action, that AEB system can automatically apply the brakes to prevent or at least mitigate the impact of a predicted collision.In at least one embodiment, an AEB system may include techniques such as dynamic brake assistance and / or imminent braking.

[0186] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1000 crosses lane markings. In at least one embodiment, an LDW system is not activated when a driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, an LDW system may utilize forward-facing cameras coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, such as via a display, speaker, and / or vibration component. In at least one embodiment, an LKA system is a variation of an LDW system.In at least one embodiment, an LKA system provides a steering or braking input to correct the vehicle 1000 when the vehicle 1000 begins to depart from its lane.

[0187] In at least one embodiment, a BSW system detects vehicles in a motor vehicle's blind spot and warns the driver of them. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile alert to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system may provide an additional warning when a driver activates a turn signal. In at least one embodiment, a BSW system may utilize rear-facing camera(s) and / or RADAR sensor(s) 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0188] In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside the range of a rearview camera while the vehicle 1000 is reversing. In at least one embodiment, an RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a crash. In at least one embodiment, an RCTW system may utilize one or more rear-facing RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration component.

[0189] In at least one embodiment, conventional ADAS systems may be prone to false positives, which may be annoying and distracting for a driver, but are typically not catastrophic because conventional ADAS systems warn a driver and allow that driver to decide whether a safety condition actually exists and act accordingly. In at least one embodiment, even in the presence of conflicting results, the vehicle 1000 decides whether to follow the result of a primary computer or a secondary computer (e.g., a first controller or a second controller of controls 1036). For example, in at least one embodiment, the ADAS system 1038 may be a backup and / or secondary computer that provides perception information to a rationality module of a backup computer.In at least one embodiment, a backup computer rationality monitor may execute redundant, different software on hardware components to detect errors in perception and dynamic driving tasks. In at least one embodiment, outputs of the ADAS system 1038 may be provided to a monitoring MCU. In at least one embodiment, a monitoring MCU determines how to resolve a conflict to ensure safe operation when outputs of a primary computer and outputs of a secondary computer conflict.

[0190] In at least one embodiment, a primary computer may be configured to provide a monitoring MCU with a confidence score indicating the primary computer's confidence in a selected result. In at least one embodiment, if that confidence score exceeds a threshold, that monitoring MCU may follow that primary computer's instruction, regardless of whether that secondary computer provides a conflicting or inconsistent result. In at least one embodiment, if a confidence score does not meet a threshold and if primary and secondary computers indicate different results (e.g., a conflict), a monitoring MCU may arbitrate between the computers to determine an appropriate result.

[0191] In at least one embodiment, a monitoring MCU may be configured to execute one or more neural networks trained and configured to determine, based at least in part on outputs from a primary computer and outputs from a secondary computer, conditions under which that secondary computer will provide false alarms. In at least one embodiment, neural networks in a monitoring MCU may learn when the output of a secondary computer is trustworthy and when it is not. For example, in at least one embodiment, if that secondary computer is a radar-based FCW system, one or more neural networks in that monitoring MCU may learn when an FCW system identifies metallic objects that do not actually pose a threat, such as a drainage grate or manhole cover, which triggers an alarm.In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a supervising MCU may learn to override LDW when cyclists or pedestrians are present and lane departure is actually the safest maneuver. In at least one embodiment, a supervising MCU may include at least one DLA or a GPU capable of operating one or more neural networks with associated memory. In at least one embodiment, a supervising MCU may include and / or be included as a component of SoC(s) 1004.

[0192] In at least one embodiment, ADAS system 1038 may include a secondary computer that executes ADAS functionality using traditional computer vision rules. In at least one embodiment, this secondary computer may use classic computer vision rules (if-then), and the presence of one or more neural networks in a supervising MCU may improve reliability, safety, and performance. For example, in at least one embodiment, different implementations and intentional non-identity make an overall system more fault-tolerant, particularly against errors caused by software (or software-hardware interface) functionality.For example, in at least one embodiment, a monitoring MCU may have greater assurance regarding the correctness of an overall result when there is a software bug or error in software executing on a primary computer and non-identical software code executing on a secondary computer produces a consistent overall result, and a bug in the software or hardware on that primary computer does not cause a significant error.

[0193] In at least one embodiment, an output of the ADAS system 1038 may be fed into the perception block of a primary computer and / or the dynamic task block of a primary computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a forward crash warning due to an object immediately ahead of the vehicle, a perception block may use this information in identifying objects. In at least one embodiment, a secondary computer may have its own neural network trained, thus reducing the risk of false alarms as described herein.

[0194] In at least one embodiment, the vehicle 1000 may further include an infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment SoC 1030 may not be an SoC and may include, without limitation, two or more discrete components. In at least one embodiment, the infotainment SoC 1030 may include, without limitation, a combination of hardware and software configured to provide audio (e.g., music, a personal digital assistant, navigation commands, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.).) and / or information services (e.g., navigation systems, parking assistance, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fluid level, oil level, door open / close, air filter information, etc.) to vehicle 1000. For example, the infotainment SoC 1030 could include radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car computers, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a head-up display (“HUD”), an HMI display 1034, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, functions, and / or systems), and / or other components. or systems), and / or other components.In at least one embodiment, the infotainment SoC 1030 may be further used to provide information (e.g., visual and / or audible) to the user(s) of the vehicle 1000, such as information from the ADAS system 1038, autonomous driving information such as planned vehicle maneuvers, travel routes, environmental information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0195] In at least one embodiment, the infotainment SoC 1030 may include any amount and type of GPU functionality. In at least one embodiment, the infotainment SoC 1030 may communicate with other devices, systems, and / or components of the vehicle 1000 via the bus 1002. In at least one embodiment, the infotainment SoC 1030 may be coupled to a supervisory MCU so that a GPU of an infotainment system may perform some self-driving functions if the primary controller(s) 1036 (e.g., primary and / or backup computers of the vehicle 1000) fail. In at least one embodiment, the infotainment SoC 1030 may place the vehicle 1000 into a chauffeur-to-safe-stop mode, as described herein.

[0196] In at least one embodiment, the vehicle 1000 may further include an instrument cluster 1032 (e.g., a digital instrument cluster, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, the instrument cluster 1032 may include, without limitation, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer).In at least one embodiment, instrument cluster 1032 may include, without limitation, any number and combination of a variety of instruments, such as a speedometer, a fuel level gauge, an oil pressure gauge, a tachometer, an odometer, turn signals, a gear shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or exchanged between infotainment SoC 1030 and instrument cluster 1032. In at least one embodiment, instrument cluster 1032 may be included as part of infotainment SoC 1030 or vice versa.

[0197] In at least one embodiment, at least one with respect to Fig. 10C is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 10C to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 10C illustrates at least one aspect related to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the environment 300 of FIG. 3, group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0198] Fig. 10D is a diagram of a system for communication between one or more cloud-based servers and an autonomous vehicle 1000 of Fig. 10A according to at least one embodiment. In at least one embodiment, the system may include, without limitation, servers (1078), networks (1090), and any number and type of vehicles, including vehicle 1000. In at least one embodiment, servers (1078) may include, without limitation, a plurality of GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPUs 1080). In at least one embodiment, GPUs 1084, CPUs 1080, and PCIe switches 1082 may be interconnected using high-speed interconnects such as, without limitation, NVLink interfaces 1088 developed by NVIDIA and / or PCIe interconnects 1086.In at least one embodiment, GPUs 1084 are connected via an NVLink and / or NVSwitch SoC, and GPUs 1084 and PCIe switches 1082 are connected via PCIe interconnects. Although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, this is not intended to be limiting. In at least one embodiment, each server 1078 may include, without limitation, any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination. For example, in at least one embodiment, servers (1078) could each include eight, sixteen, thirty-two, and / or more GPUs (1084).

[0199] In at least one embodiment, servers (1078) may receive, over networks (1090) and from vehicles, image data representing images depicting unexpected or changed road conditions, such as recently commenced road work. In at least one embodiment, servers (1078) may transmit, over networks (1090) and to vehicles, neural networks (1092), updated or otherwise, and / or map information (1094), including, but not limited to, information about traffic and road conditions. In at least one embodiment, updates to map information 1094 may include updates to HD maps 1022, such as information about construction, potholes, detours, flooding, and / or other obstacles.In at least one embodiment, neural networks 1092 and / or map information 1094 may result from new training and / or new experience represented in data received from any number of vehicles in an environment and / or may be based at least in part on training performed in a data center (e.g., using server(s) 1078 and / or other servers).

[0200] In at least one embodiment, servers (1078) may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated by vehicles and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., if the associated neural network benefits from supervised learning) and / or subjected to other preprocessing. In at least one embodiment, any amount of training data is unlabeled and / or preprocessed (e.g., if the associated neural network does not require supervised learning).In at least one embodiment, machine learning models, once trained, may be used by vehicles (e.g., transmitted to vehicles over a network(s)) 1090, and / or machine learning models may be used by one or more servers 1078 to remotely monitor vehicles.

[0201] In at least one embodiment, servers (1078) may receive data from vehicles and apply data to real-time neural networks to enable intelligent inference in real-time. In at least one embodiment, servers (1078) may include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) (1084), such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, servers (1078) may include a deep learning infrastructure using CPU-powered data centers.

[0202] In at least one embodiment, the deep learning infrastructure of server(s) 1078 may be capable of performing fast, real-time inferences and may utilize this capability to evaluate and verify the state of processors, software, and / or associated hardware in vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as a sequence of images and / or objects that vehicle 1000 includes in that sequence of images (e.g., via computer vision and / or other machine learning methods for object classification).In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to objects identified by vehicle 1000, and if the results do not match and the deep learning infrastructure concludes that the AI in vehicle 1000 is not functioning properly, servers 1078 may send a signal to vehicle 1000 instructing a fail-safe computer of vehicle 1000 to take control, notify passengers, and perform a safe parking maneuver.

[0203] In at least one embodiment, servers (1078) may include graphics processors (1084) and one or more programmable accelerators for inference (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, a combination of graphics processor-powered servers and inference acceleration may enable real-time responsiveness. In at least one embodiment, for example, when performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware structure(s) 715 are used to implement one or more embodiments. Details of hardware structure(s) 715 are described herein in connection with Fig. 7A and / or 7B. COMPUTER SYSTEMS

[0204] Fig. 11 is a block diagram illustrating an example computer system, which may be a system having an interconnection of devices and components, a system-on-a-chip (SOC), or a combination thereof, formed with a processor that may include execution units for executing an instruction in accordance with at least one embodiment. In at least one embodiment, a computer system 1100 may include, without limitation, a component, such as a processor 1102, for employing execution units including logic to execute algorithms for processing data in accordance with the present disclosure, such as in the embodiment described herein.In at least one embodiment, computer system 1100 may include processors such as PENTIUM® family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including personal computers having other microprocessors, technical workstations, set-top boxes, and the like) may also be used. In at least one embodiment, computer system 1100 may run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical interfaces may also be used.

[0205] Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices are mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0206] In at least one embodiment, computer system 1100 may include, without limitation, a processor 1102, which may include, without limitation, one or more execution units 1108 to perform model training and / or inference for machine learning models according to the techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system; however, in another embodiment, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, without limitation, a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other device, such as a digital signal processor.In at least one embodiment, the processor 1102 may be coupled to a processor bus 1110 that may transmit data signals between the processor 1102 and other components in the computer system 1100.

[0207] In at least one embodiment, processor 1102 may include, without limitation, an internal level 1 cache ("cache") 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache may be external to processor 1102. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and needs. In at least one embodiment, a register file 1106 may store different data types in various registers, including, but not limited to, integer registers, floating-point registers, status registers, and an instruction register.

[0208] In at least one embodiment, execution unit 1108, which includes, among other things, logic for performing integer and floating-point operations, is also located in processor 1102. In at least one embodiment, processor 1102 may also include microcode read-only memory ("ROM") ("ucode") that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1108 may include logic for processing an instruction set 1109. In at least one embodiment, by including instruction set 1109 in an instruction set of a general-purpose processor, along with associated instruction execution circuitry, operations used by many multimedia applications may be performed using packed data in processor 1102.In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by using the full width of the processor data bus to perform operations on packed data, thereby eliminating the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0209] In at least one embodiment, execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1100 may include, without limitation, a memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or another storage device. In at least one embodiment, memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0210] In at least one embodiment, a system logic chip may be coupled to processor bus 1110 and memory 1120. In at least one embodiment, a system logic chip may include, without limitation, a memory control hub ("MCH") 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage and for the storage of graphics instructions, data, and textures. In at least one embodiment, MCH 1116 may route data signals between processor 1102, memory 1120, and other components in computer system 1100, and may bridge data signals between processor bus 1110, memory 1120, and a system I / O interface 1122. In at least one embodiment, a system logic chip may provide a graphics port for coupling to a graphics controller.In at least one embodiment, MCH 1116 may be coupled to memory 1120 via a high-bandwidth memory path 1118, and a graphics / video card 1112 may be coupled to MCH 1116 via an Accelerated Graphics Port ("AGP") interconnect 1114.

[0211] In at least one embodiment, computer system 1100 may use system I / O interface 1122 as a proprietary hub interface bus to couple MCH 1116 to an I / O control hub ("ICH") 1130. In at least one embodiment, ICH 1130 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, among other things, a high-speed I / O bus for connecting peripherals to memory 1120, a chipset, and a processor 1102. Examples may include, without limitation, an audio controller 1129, a firmware hub (“Flash BIOS”) 1128, a wireless transceiver 1126, a data store 1124, a legacy I / O controller 1123 containing user input and keyboard interfaces 1125, a serial expansion port 1127, such as a Universal Serial Bus (“USB”) port, and a network controller 1134.In at least one embodiment, data storage 1124 may include a hard disk, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0212] In at least one embodiment, Fig. 11 a system comprising interconnected hardware devices or “chips”, while in other embodiments Fig. 11 may show an exemplary SoC. In at least one embodiment, the Fig. 11 may be connected to proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of computer system 1100 are interconnected using Compute Express Link (CXL) interconnects.

[0213] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 715 are described herein in connection with the Fig. 7A and / or 7B. In at least one embodiment, logic 715 may be used in a computer system 1100 for inferences or predictions based at least in part on weighting parameters calculated using neural network training operations, functions, and / or architectures or neural network use cases described herein.

[0214] In at least one embodiment, at least one with respect to Fig. 11 is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 11 is used to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 11 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, by generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, surroundings 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0215] Fig. 12 is a block diagram illustrating an electronic device 1200 for using a processor 1210 according to at least one embodiment. In at least one embodiment, the electronic device 1200 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop computer, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0216] In at least one embodiment, the electronic device 1200 may include, without limitation, a processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1210 is coupled via a bus or interface, such as an I2C bus, a System Management Bus ("SMBus"), a Low Pin Count (LPC) bus, a Serial Peripheral Interface ("SPI"), a High Definition Audio ("HDA") bus, a Serial Advance Technology Attachment ("SATA") bus, a Universal Serial Bus ("USB") (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Fig. 12 a system comprising interconnected hardware devices or “chips”, while in other embodiments Fig. 12 may show an exemplary SoC. In at least one embodiment, the Fig. 12 may be connected to proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Fig. 12 interconnected using Compute Express Link (CXL) interconnects.

[0217] In at least one embodiment, Fig. 12 a display 1224, a touchscreen 1225, a touchpad 1230, a near field communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, an Express Chipset (“EC”) 1235, a Trusted Platform Module (“TPM”) 1238, BIOS / Firmware / Flash Memory (“BIOS, FW Flash”) 1222, a DSP 1260, a drive 1220 such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), a WLAN unit (“WLAN”) 1250, a Bluetooth unit 1252, a WWAN unit (“WWAN”) 1256, a GPS unit (Global Positioning System) 1255, a camera (“USB 3.0 Camera”) 1254, such as a USB 3.0 Camera, and / or a LPDDR (“Low Power Double Data Rate,” “LPDDR”) (“LPDDR3”) memory unit 1215, implemented, for example, in an LPDDR3 standard. These components can each be implemented in any suitable manner.

[0218] In at least one embodiment, other components may be communicatively coupled to processor 1210 via components described herein. In at least one embodiment, an accelerometer 1241, an ambient light sensor ("ALS") 1242, a compass 1243, and a gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, a thermal sensor 1239, a fan 1237, a keyboard 1236, and a touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speakers 1263, headphones 1264, and a microphone ("Microphone") 1265 may be communicatively coupled to an audio unit ("Audio Codec and Class-D Amplifier") 1262, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, the audio unit 1262 may include, for example and without limitation, an audio encoder / decoder ("codec") and a Class D amplifier.In at least one embodiment, a SIM card ("SIM") 1257 may be communicatively coupled to the WWAN unit 1256. In at least one embodiment, components such as the WLAN unit 1250 and the Bluetooth unit 1252, as well as the WWAN unit 1256, may be implemented in a Next Generation Form Factor ("NGFF").

[0219] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in electronic device 1200 may be used for inferences or predictions based at least in part on weighting parameters calculated using neural network training procedures, neural network functions and / or architectures, or neural network use cases described herein.

[0220] In at least one embodiment, at least one with respect to Fig. 12 is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 12 is used to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 12 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the surrounding area 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0221] Fig. Figure 13 illustrates a computer system 1300 according to at least one embodiment. In at least one embodiment, the computer system 1300 is configured to implement various processes and methods described in this disclosure.

[0222] In at least one embodiment, computer system 1300 includes, without limitation, at least one central processing unit ("CPU") 1302 connected to a communications bus 1310 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communications protocols. In at least one embodiment, computer system 1300 includes, without limitation, main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1304, which may take the form of random access memory ("RAM").In at least one embodiment, a network interface subsystem ("network interface") 1322 provides an interface to other computing devices and networks to receive data from and transmit data to other systems with the computing system 1300.

[0223] In at least one embodiment, computer system 1300 includes, without limitation, input devices 1308, a parallel processing system 1312, and display devices 1306, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light-emitting diode ("LED"), a plasma display, or other suitable display technology. In at least one embodiment, inputs are received from input devices 1308 such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be arranged on a single semiconductor platform to form a processing system.

[0224] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of the inference and / or training logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 may be used in a computer system 1300 for inference or prediction operations based at least in part on weighting parameters calculated using training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0225] In at least one embodiment, at least one with respect to Fig. 13 is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 13 is used to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 13 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, wherein training actions 204 are generated and / or the neural network is trained using the training actions performed and the images of the training actions performed by Fig. 2, the surrounding area 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0226] Fig. 14 shows a computer system 1400 according to at least one embodiment. In at least one embodiment, the computer system 1400 includes, without limitation, a computer 1410 and a USB flash drive 1420. In at least one embodiment, the computer 1410 may include, without limitation, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1410 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0227] In at least one embodiment, the USB flash drive 1420 includes, without limitation, a processing unit 1430, a USB interface 1440, and logic for the USB interface 1450. In at least one embodiment, the processing unit 1430 may be any system, apparatus, or device for executing instructions capable of executing instructions. In at least one embodiment, the processing unit 1430 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1430 includes an application-specific integrated circuit ("ASIC") optimized to perform any number and type of machine learning-related operations.For example, in at least one embodiment, processing unit 1430 is a tensor processing unit ("TPC") optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1430 is a video processing unit ("VPU") optimized to perform computer vision and machine learning inference operations.

[0228] In at least one embodiment, USB interface 1440 may be any type of USB plug or receptacle. For example, in at least one embodiment, USB interface 1440 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1440 is a USB 3.0 Type-A plug. In at least one embodiment, the logic of USB interface 1450 may include any number and type of logic that enables processing unit 1430 to interface with devices (e.g., computer 1410) via USB port 1440.

[0229] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in computer system 1400 may be used for inferences or predictions based at least in part on weighting parameters calculated using neural network training procedures, neural network functions and / or architectures, or neural network use cases described herein.

[0230] In at least one embodiment, at least one with respect to Fig. 14 is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 14 is used to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 14 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the surrounding area 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0231] Fig. 15A illustrates an example architecture in which a plurality of GPUs 1510(1)-1510(N) are communicative with a plurality of multi-core processors 1505(1)-1505(M) via high-speed interconnects 1540(1)-1540(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, high-speed interconnects 1540(1)-1540(N) support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, various protocols may be used for interconnection, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, "N" and "M" represent positive integers, the values of which may vary from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1510(1)-1510(N) includes one or more graphics cores (also referred to simply as “cores”) 1800, as shown in the Fig. 18A and Fig. 18B. In at least one embodiment, one or more graphics cores 1800 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context refers to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or scheduler).

[0232] Additionally, and in at least one embodiment, two or more GPUs 1510 are interconnected via high-speed interconnects 1529(1)-1529(2), which may be implemented using similar or different protocols / connections than those for high-speed interconnects 1540(1)-1540(N). Likewise, two or more multi-core processors 1505 may be interconnected via a high-speed interconnect 1528, which may be symmetric multiprocessor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, all communication between various system components implemented in Fig. 15A, using similar protocols / connections (e.g., via a common interconnection structure).

[0233] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to a processor memory 1501(1)-1501(M) via memory interconnects 1526(1)-1526(M), and each GPU 1510(1)-1510(N) is communicatively coupled to a GPU memory 1520(1)-1520(N) via GPU memory interconnects 1550(1)-1550(N), respectively. In at least one embodiment, memory interconnects 1526 and 1550 may use similar or different memory access technologies. For example, and not by way of limitation, the processor memories 1501(1)-1501(M) and the GPU memories 1520 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or non-volatile memories such as 3D XPoint or Nano-Ram.In at least one embodiment, a portion of processor memory 1501 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level hierarchy (2LM)).

[0234] As described herein, various multi-core processors 1505 and GPUs 1510 may be physically coupled to a particular memory 1501 or 1520, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address") is distributed across different physical memories. For example, processor memories 1501(1)-1501(M) may each comprise 64 GB of system memory address space, and GPU memories 1520(1)-1520(N) may each comprise 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M=2 and N=4. Other values for N and M are possible.

[0235] Fig. 15B shows additional details for an interconnect between a multi-core processor 1507 and a graphics acceleration module 1546 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1546 may include one or more GPU chips integrated on a line card connected to the processor 1507 via a high-speed interconnect 1540 (e.g., a PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, the graphics acceleration module 1546 may be integrated on a package or die with the processor 1507.

[0236] In at least one embodiment, processor 1507 includes a plurality of cores 1560A-1560D (which may be referred to as "execution units"), each with a translation lookaside buffer ("TLB") 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, cores 1560A-1560D may include various other components for executing instructions and processing data, not shown. In at least one embodiment, caches 1562A-1562D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 1556 may be included in caches 1562A-1562D and shared by sets of cores 1560A-1560D. For example, one embodiment of processor 1507 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches.In this embodiment, one or more L2 and L3 caches are shared between two adjacent cores. In at least one embodiment, processor 1507 and graphics acceleration module 1546 are coupled to system memory 1514, which includes processor memories 1501(1)-1501(M) of FIG. Fig. 15A may include.

[0237] In at least one embodiment, coherency for data and instructions stored in various caches 1562A-1562D, 1556, and system memory 1514 is maintained via inter-core communication over a coherency bus 1564. For example, in at least one embodiment, each cache may have associated cache coherency logic / circuitry to communicate over the coherency bus 1564 in response to detected reads or writes to specific cache lines. In at least one embodiment, a cache snooping protocol is implemented over the coherency bus 1564 to monitor cache accesses.

[0238] In at least one embodiment, a proxy circuit 1525 communicatively couples the graphics acceleration module 1546 to the coherence bus 1564, allowing the graphics acceleration module 1546 to participate in a cache coherence protocol as a peer of cores 1560A-1560D. Specifically, in at least one embodiment, an interface 1535 connects to a proxy circuit 1525 via a high-speed interconnect 1540, and an interface 1537 connects the graphics acceleration module 1546 to the high-speed interconnect 1540.

[0239] In at least one embodiment, an accelerator integration circuit 1536 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546. In at least one embodiment, graphics processing engines 1531(1)-1531(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, a plurality of graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546 include one or more graphics cores 1800, as described in connection with the Fig. 18A and Fig. 18B. In at least one embodiment, graphics processing engines 1531(1)-1531(N) may alternatively comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1546 may be a graphics processor having a plurality of graphics processing engines 1531(1)-1531(N), or graphics processing engines 1531(1)-1531(N) may be individual graphics processors integrated on a common package, board, or die.

[0240] In at least one embodiment, accelerator integration circuitry 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1514. In at least one embodiment, MMU 1539 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1538 may store instructions and data for efficient access by graphics processing engines 1531(1)-1531(N).In at least one embodiment, the data stored in cache 1538 and graphics memories 1533(1)-1533(M) is kept coherent with core caches 1562A-1562D, 1556, and system memory 1514, possibly using a fetch unit 1544. As previously mentioned, this may be done via proxy circuitry 1525 on behalf of cache 1538 and memories 1533(1)-1533(M) (e.g., sending updates to cache 1538 related to changes / accesses to cache lines in processor caches 1562A-1562D, 1556 and receiving updates from cache 1538).

[0241] In at least one embodiment, a set of registers 1545 stores context data for threads executed by graphics processing engines 1531(1)-1531(N), and context management circuitry 1548 manages thread contexts. For example, context management circuitry 1548 may perform save and restore operations to save and restore contexts of different threads during context switches (e.g., when saving a first thread and saving a second thread so that a second thread can be executed by a graphics processing engine). For example, upon a context switch, context management circuitry 1548 may save current register values to a specific location in memory (e.g., identified by a context pointer). Upon returning to a context, it may then restore the register values.In at least one embodiment, an interrupt management circuit 1547 receives and processes interrupts received from system devices.

[0242] In at least one embodiment, virtual / effective addresses from a graphics processing engine 1531 are translated into real / physical addresses in system memory 1514 by an MMU 1539. In at least one embodiment, accelerator integration circuitry 1536 supports multiple (e.g., 4, 8, 16) graphics acceleration modules 1546 and / or other accelerator devices. In at least one embodiment, graphics acceleration module 1546 may be associated with a single application executing on processor 1507 or shared among multiple applications. In at least one embodiment, a virtualized environment for graphics execution is depicted in which resources from graphics processing engines 1531(1)-1531(N) are shared with multiple applications or virtual machines (VMs).In at least one embodiment, resources may be divided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0243] In at least one embodiment, accelerator integration circuitry 1536 acts as a bridge to a system for graphics acceleration module 1546 and provides address translation and system memory caching services. Additionally, in at least one embodiment, accelerator integration circuitry 1536 may provide virtualization facilities to a host processor to manage the virtualization of graphics processing engines 1531(1)-1531(N), interrupts, and memory management.

[0244] In at least one embodiment, each host processor can directly access these resources via an effective address because the hardware resources of graphics processing engines 1531(1)-1531(N) are explicitly mapped to a real address space seen by host processor 1507. In at least one embodiment, a function of accelerator integration circuitry 1536 is to physically separate graphics processing engines 1531(1)-1531(N) so that they appear to a system as independent entities.

[0245] In at least one embodiment, one or more graphics memories 1533(1)-1533(M) are coupled to each of the graphics processing engines 1531(1)-1531(N), where N=M. In at least one embodiment, graphics memories 1533(1)-1533(M) store instructions and data processed by each of the graphics processing engines 1531(1)-1531(N). In at least one embodiment, the graphics memories 1533(1)-1533(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or non-volatile memories such as 3D XPoint or Nano-RAM.

[0246] In at least one embodiment, biasing techniques may be used to reduce data traffic over high-speed interconnect 1540 and ensure that the data stored in graphics memories 1533(1)-1533(M) is the data most frequently used by graphics processing engines 1531(1)-1531(N) and preferably not used (at least not frequently) by cores 1560A-1560D. In at least one embodiment, a biasing mechanism attempts to keep data needed by cores (and preferably not by graphics processing engines 1531(1)-1531(N)) in caches 1562A-1562D, 1556, and system memory 1514.

[0247] Fig. 15C shows another exemplary embodiment in which accelerator integration circuitry 1536 is integrated with processor 1507. In this embodiment, graphics processing engines 1531(1)-1531(N) communicate directly over a high-speed interconnect 1540 with accelerator integration circuitry 1536 via an interface 1537 and an interface 1535 (which may again be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuitry 1536 may perform similar operations as described with respect to Fig. 15B, but possibly with higher throughput due to its proximity to the coherence bus 1564 and caches 1562A-1562D, 1556. In at least one embodiment, an accelerator integration circuit supports different programming models, including a dedicated process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models controlled by the accelerator integration circuit 1536 and programming models controlled by the graphics acceleration module 1546.

[0248] In at least one embodiment, graphics processing engines 1531(1)-1531(N) are associated with a single application or process under a single operating system. In at least one embodiment, a single application can forward other application requests to graphics processing engines 1531(1)-1531(N), thereby providing virtualization within a VM / partition.

[0249] In at least one embodiment, graphics processing engines 1531(1)-1531(N) may be shared between multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize graphics processing engines 1531(1)-1531(N) to provide access by any operating system. In at least one embodiment, for systems with a partition without a hypervisor, graphics processing engines 1531(1)-1531(N) are owned by an operating system. In at least one embodiment, an operating system may virtualize graphics processing engines 1531(1)-1531(N) to provide access to any process or application.

[0250] In at least one embodiment, the graphics acceleration module 1546 or an individual graphics processing engine 1531(1)-1531(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1514 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when it registers its context with the graphics processing engine 1531(1)-1531(N) (i.e., calls system software to add a process element to a process element linked list). In at least one embodiment, the lower 16 bits of a process handle may be an offset of a process element within a process element linked list.

[0251] Fig. 15D illustrates an exemplary accelerator integration slice 1590. In at least one embodiment, a "slice" comprises a particular portion of the processing resources of accelerator integration circuitry 1536. In at least one embodiment, an application is effective addresses 1582 within system memory 1514 in which process elements 1583 are stored. In at least one embodiment, process elements 1583 are stored in response to GPU calls 1581 from applications 1580 executing on processor 1507. In at least one embodiment, a process element 1583 contains process state for a corresponding application 1580. In at least one embodiment, a work description (WD) 1584 contained in a process element 1583 may be a single job requested by an application or may contain a pointer to a queue of jobs.In at least one embodiment, WD 1584 is a pointer to a job request queue at the effective address 1582 of an application.

[0252] In at least one embodiment, the graphics acceleration module 1546 and / or individual graphics processing engines 1531(1)-1531(N) may be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for establishing states of processes and sending a WD 1584 to a graphics acceleration module 1546 to start a job in a virtualized environment may be included.

[0253] In at least one embodiment, a dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a graphics acceleration module 1546 or a single graphics processing engine 1531 is owned by a single process. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, a hypervisor initializes the accelerator integration circuit 1536 for an owning partition, and an operating system initializes the accelerator integration circuit 1536 for an owning process when the graphics acceleration module 1546 is allocated.

[0254] In at least one embodiment, a WD fetch unit 1591 in an accelerator integration slice 1590 fetches the next WD 1584, which contains an indication of the work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. In at least one embodiment, data from WD 1584 may be stored in registers 1545 and used by MMU 1539, interrupt management circuitry 1547, and / or context management circuitry 1548, as shown. For example, one embodiment of MMU 1539 includes segment / page walk circuitry for accessing segment / page tables 1586 within an operating system virtual address space 1585. In at least one embodiment, interrupt management circuitry 1547 may process interrupt events 1592 received from graphics acceleration module 1546.In at least one embodiment, when performing graphics operations, an effective address 1593 generated by a graphics processing engine 1531(1)-1531(N) is translated into a real address by the MMU 1539.

[0255] In at least one embodiment, registers 1545 are duplicated for each graphics processing engine 1531(1)-1531(N) and / or each graphics acceleration module 1546 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included in an accelerator integration slice 1590. Example registers that may be initialized by a hypervisor are listed in Table 1. Table 1 - Registers initialized by a hypervisor Register # Beschreibung 1 Slice-Steuerregister (Slice-Steuerregister) 2 Reale Adresse (RA) Zeiger auf den Bereich für geplante Prozesse 3 Authority mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry boundary 6 Condition register 7 Logical partition ID 8 Real Address (RA) pointer to Hypervisor Accelerator Utilization Record 9 Memory description register

[0256] Table 2 lists example registers that can be initialized by an operating system. Table 2 - Initialized operating system registers Register # Description 1 Process and thread identification 2 Effective Address (EA) Context Store / Restore Pointer 3 Virtual Address (VA) pointer for the accelerator utilization set 4 Virtual Address (VA) Pointer to the memory segment table 5 Authority mask 6 Job description

[0257] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engines 1531(1)-1531(N). In at least one embodiment, it contains all the information a graphics processing engine 1531(1)-1531(N) needs to perform its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be performed.

[0258] Fig.15E shows additional details for an exemplary embodiment of a shared model. This embodiment includes a real hypervisor address space 1598 in which a process element list 1599 is stored. In at least one embodiment, the real hypervisor address space 1598 is accessible via a hypervisor 1596 that virtualizes graphics acceleration engine engines for the operating system 1595.

[0259] In at least one embodiment, shared programming models enable all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1546. In at least one embodiment, there are two programming models where the graphics acceleration module 1546 is shared among multiple processes and partitions: time-shared and graphics-shared.

[0260] In at least one embodiment, in this model, the graphics acceleration module 1546 belongs to the system hypervisor 1596 and provides its functionality to all operating systems 1595. In at least one embodiment, in order to support virtualization by the system hypervisor 1596, a graphics acceleration module 1546 may meet certain requirements, such as (1) the job request of an application must be autonomous (i.e.the state does not need to be maintained between jobs), or the graphics acceleration module 1546 must provide a mechanism for saving and restoring the context, (2) an application's job request is guaranteed by the graphics acceleration module 1546 to complete in a certain time, including any translation errors, or the graphics acceleration module 1546 provides the ability to interrupt the processing of a job, and (3) the graphics acceleration module 1546 must ensure fairness between processes when operating in a directed joint programming model.

[0261] In at least one embodiment, application 1580 is required to execute an operating system system call 1595 with a graphics acceleration module type, a work description (WD), an authority mask register (AMR) value, and a context save / restore region (CSRP) pointer. In at least one embodiment, the graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value.In at least one embodiment, WD is specifically formatted for the graphics acceleration module 1546 and may be in the form of an instruction of the graphics acceleration module 1546, a pointer to an effective address of a user-defined structure, a pointer to an effective address of a queue of instructions, or any other data structure to describe the work to be performed by the graphics acceleration module 1546.

[0262] In at least one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. In at least one embodiment, if the implementations of accelerator integration circuitry 1536 (not shown) and graphics acceleration module 1546 do not support a user authority mask override register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1596 may optionally apply a current authority mask override register (AMOR) value before placing an AMR in process element 1583.In at least one embodiment, CSRP is one of the registers 1545 that contains an effective address of a region in an application's effective address space 1582 for the graphics acceleration module 1546 to save and restore context state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or when a job is interrupted. In at least one embodiment, the context save / restore region may be pinned system memory.

[0263] Upon receiving a system call, the operating system 1595 may verify whether the application 1580 is registered and has been granted permission to use the graphics acceleration module 1546. In at least one embodiment, the operating system 1595 then calls the hypervisor 1596 with the information shown in Table 3. Table 3 - Parameters for calling the operating system to the hypervisor Parameters # Description 1 A job description (WD) 2 An authority mask register (AMR) value (possibly masked) 3 An effective address (EA) Context save / restore pointer (CSRP) 4 A process ID (PID) and optionally a thread ID (TID) 5 A virtual address (VA) accelerator utilization set pointer (AURP) 6 Virtual address of the pointer to the memory segment table (SSTP) 7 A logical interrupt service number (LISN)

[0264] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1596 checks whether operating system 1595 is registered and has been granted permission to use graphics acceleration module 1546. In at least one embodiment, hypervisor 1596 then inserts process element 1583 into a process element linked list for a corresponding graphics acceleration module type 1546. In at least one embodiment, a process element may include the information shown in Table 4. Table 4 - Process element information Item # Description 1 A job description (WD) 2 An Authority Mask Register (AMR) value (possibly masked). 3 An effective address (EA) Context save / restore pointer (CSRP) 4 A process ID (PID) and optionally a thread ID (TID) 5 A virtual address (VA) accelerator utilization set pointer (AURP) 6 Virtual address of the pointer to the memory segment table (SSTP) 7 A logical interrupt service number (LISN) 8 Interrupt vector table derived from hypervisor call parameters 9 A status register value (SR) 10 A logical partition ID (LPID) 11 A pointer to the hypervisor's accelerator utilization set with real address (RA) 12 Memory Description Register (SDR)

[0265] In at least one embodiment, the hypervisor initializes a plurality of accelerator integration slice 1590 registers 1545.

[0266] As in Fig.15F, in at least one embodiment, a unified memory addressable via a common virtual memory address space is used to access physical processor memories 1501(1)-1501(N) and GPU memories 1520(1)-1520(N). In this implementation, operations performed on GPUs 1510(1)-1510(N) use the same virtual / effective memory address space to access processor memories 1501(1)-1501(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is assigned to processor memory 1501(1), a second portion is assigned to second processor memory 1501(N), a third portion is assigned to GPU memory 1520(1), and so on.In at least one embodiment, this distributes a total virtual / effective memory space (sometimes referred to as effective address space) across each of the processor memories 1501 and GPU memories 1520, such that each processor or GPU can access each physical memory with a virtual address associated with that memory.

[0267] In at least one embodiment, a bias / coherence management circuit 1594A-1594E in one or more MMUs 1539A-1539E ensures cache coherence between caches of one or more host processors (e.g., 1505) and GPUs 1510 and implements biasing techniques that indicate physical memories in which certain data types should be stored. In at least one embodiment, while multiple instances of bias / coherence management circuits 1594A-1594E in Fig.15F, bias / coherence circuits may be implemented within an MMU of one or more host processors 1505 and / or within an accelerator integration circuit 1536.

[0268] One embodiment enables GPU memory 1520 to be mapped as part of system memory and accessed using Shared Virtual Memory (SVM) technology, but without the performance penalty associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1520 as system memory without burdensome cache coherence overhead provides a beneficial environment for GPU offloading. In at least one embodiment, this arrangement enables host processor 1505 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies include calls to drivers, interrupts, and memory I / O accesses (MMIO), all of which are inefficient compared to simple memory accesses.In at least one embodiment, the ability to access GPU memory 1520 without cache coherence overhead may be critical to the execution time of a paged computation. For example, in at least one embodiment, in cases with significant streaming write memory traffic, the cache coherence overhead may significantly reduce the effective write bandwidth seen by a GPU 1510. In at least one embodiment, operand facility efficiency, result access efficiency, and GPU computation efficiency may play a role in determining the effectiveness of GPU paged computation.

[0269] In at least one embodiment, the selection of the GPU bias and the host processor bias is controlled by a bias tracker data structure. For example, in at least one embodiment, a bias table may be used, which may be a page-granular structure (e.g., controlled at a memory page granularity) comprising 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory region of one or more GPU memories 1520, with or without a bias cache in a GPU 1510 (e.g., to cache frequently / recently used bias table entries). Alternatively, in at least one embodiment, an entire bias table may be maintained within a GPU.

[0270] In at least one embodiment, a bias table entry associated with each access to GPU-attached memory 1520 is accessed prior to the actual GPU memory access, thereby triggering subsequent operations. In at least one embodiment, local requests from a GPU 1510 that find their page in the GPU bias are forwarded directly to a corresponding GPU memory 1520. In at least one embodiment, local requests from a GPU that find their page in the host bias are forwarded to the processor 1505 (e.g., over a high-speed interconnect as described herein). In at least one embodiment, requests from the processor 1505 that find a requested page in the host processor bias complete a request like a normal memory read.Alternatively, requests directed to a GPU-biased page may be forwarded to a GPU 1510. In at least one embodiment, a GPU may then transition a page to host processor bias if it is not currently using a page. In at least one embodiment, a page's bias state may be changed either through a software-based mechanism, a hardware-assisted software-based mechanism, or, in a limited number of cases, a purely hardware-based mechanism.

[0271] In at least one embodiment, a mechanism for changing bias state uses an API call (e.g., OpenCL), which in turn invokes a driver for a GPU, which in turn sends a message (or queues a command descriptor) to a GPU instructing it to change a bias state and, on some transitions, perform a cache flush operation in a host. In at least one embodiment, a cache flush operation is used for a transition from host processor 1505 bias to GPU bias, but not for an opposite transition.

[0272] In at least one embodiment, cache coherence is maintained by temporarily making GPU-biased pages uncacheable by host processor 1505. In at least one embodiment, to access these pages, processor 1505 may request access from GPU 1510, which may or may not grant access immediately. Therefore, in at least one embodiment, to reduce communication between processor 1505 and GPU 1510, it is advantageous to ensure that GPU-biased pages are those required by a GPU but not by host processor 1505, and vice versa.

[0273] Hardware structure(s) 715 are used to carry out one or more embodiments. Details of hardware structure(s) 715 may be described herein in connection with the Fig. 7A and / or 7B are provided.

[0274] Fig.Figure 16 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0275] Fig.16 is a block diagram illustrating an exemplary system on an integrated circuit 1600 that may be manufactured using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic that includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I22S / I22C controller 1640.In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1650 and a mobile industrial processor interface (MIPI) display interface 1655. In at least one embodiment, memory may be provided by a flash memory subsystem 1660 that includes flash memory and a controller for the flash memory. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1670.

[0276] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with the Fig. 7A and / or 7B. In at least one embodiment, logic 715 in integrated circuit 1600 may be used for inferences or predictions based at least in part on weighting parameters calculated using neural network training procedures, neural network functions and / or architectures, or neural network use cases described herein.

[0277] In at least one embodiment, at least one with respect to Fig. 16 is used to implement techniques and / or functions associated with the Fig.1-6. In at least one embodiment, at least one component of Fig. 16 is used to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 16 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, by generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the surrounding area 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0278] Fig. 17A-17B illustrate example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0279] Fig. 17A-17B are block diagrams illustrating example graphics processors for use in an SoC according to the embodiments described herein. Fig. 17A shows an exemplary graphics processor 1710 of a system on an integrated circuit that may be manufactured using one or more IP cores in accordance with at least one embodiment. Fig. 17B shows an additional exemplary graphics processor 1740 of a system on an integrated circuit that may be manufactured using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, the graphics processor 1710 is Fig. 17A, a low-power graphics core. In at least one embodiment, the graphics processor 1740 is Fig. 17B, a higher performance graphics core. In at least one embodiment, each of the graphics processors 1710, 1740 may be a variant of the graphics processor 1610 of Fig. be 16.

[0280] In at least one embodiment, graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D through 1715N-1, and 1715N). In at least one embodiment, graphics processor 1710 may execute different shader programs via separate logic, such that vertex processor 1705 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1705 executes a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, the fragment processor(s) 1715A-1715N use the primitive and vertex data generated by the vertex processor 1705 to generate a frame buffer displayed on a display device. In at least one embodiment, the fragment processor(s) 1715A-1715N are optimized for executing fragment shader programs as provided in an OpenGL API, which can be used to perform similar operations as a pixel shader program as provided in a Direct3D API.

[0281] In at least one embodiment, graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, cache(s) 1725A-1725B, and circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMU(s) 1720A-1720B provide virtual-to-physical address mapping for graphics processor 1710, including vertex processor 1705 and / or fragment processor(s) 1715A-1715N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more cache(s) 1725A-1725B. In at least one embodiment, one or more MMU(s) 1720A-1720B may be synchronized with other MMUs within a system comprising one or more MMUs connected to one or more application processor(s) 1605, image processor(s) 1615, and / or video processor(s) 1620 of Fig.16, so that each processor 1605-1620 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable the graphics processor 1710 to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection.

[0282] In at least one embodiment, the graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F to 1755N-1 and 1755N) as shown in Fig.17B, which provides a unified shader core architecture in which a single core or core type can execute all types of programmable shader code, including shader code implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745 acting as a thread dispatcher to distribute execution threads to one or more shader cores 1755A-1755N and a tiling unit 1758 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are divided in image space, for example, to leverage local spatial coherence within a scene or to optimize the use of internal caches.

[0283] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in graphics processors 1710 and / or 1740 may be used for inferences or predictions based at least in part on weighting parameters calculated using training operations, neural network functions, and / or architectures or neural network use cases as described herein.

[0284] In at least one embodiment, at least one with respect to Fig. 17 is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig.17 is used to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 17 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the surrounding area 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0285] Fig.18A-18B illustrate additional exemplary logic for graphics processors according to the embodiments described herein. In at least one embodiment, the logic shown in Fig. 18A-18B are integrated into a single system, such as a graphics processing unit (GPU), SoC, or other processor type. Fig. 18A shows a graphics core 1800 that, in at least one embodiment, is included in the graphics processor 1610 of Fig. 16 and in at least one embodiment, a unified shader core 1755A-1755N as shown in Fig. 17B can be. Fig.18B shows a highly parallel general-purpose graphics processing unit ("GPGPU," which may also be referred to as a "graphics processing unit") 1830, which in at least one embodiment is suitable for use on a multi-chip module. In at least one embodiment, the graphics processing unit 1830 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1600 includes a graphics core 1800, for example, to form an integrated circuit and / or an SoC, such an integrated circuit and / or SoC performing operations described herein.

[0286] In at least one embodiment, the graphics core 1800 includes a shared instruction cache 1802, a texture unit 1818, and a cache / shared memory 1820 (e.g., including L1, L2, L3, last level cache, or other caches) common to the execution resources within the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N or a partition for each core, and a graphics processor may include multiple instances of the graphics core 1800. In at least one embodiment, each slice 1801A-1801N relates to the graphics core 1800. In at least one embodiment, the slices 1801A-1801N include sub-slices that are part of a slice 1801A-1801N. In at least one embodiment, slices 1801A-1801N are independent of other slices or dependent on other slices.In at least one embodiment, slices 1801A-1801N may include support logic including a local instruction cache 1804A-1804N, a thread scheduler (sequencer) 1806A-1806N, a thread dispatcher 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional functional units (AFUs 1812A-1812N), floating-point units (FPUs 1814A-1814N), integer arithmetic logic units (ALUs 1816A-1816N), address arithmetic units (ACUs 1813A-1813N), double-precision floating-point units (DPFPUs 1815A-1815N), and matrix processing units (MPUs 1817A-1817N). In at least one embodiment, MPUs 1817A-1817N are referred to as matrix engines.

[0287] In at least one embodiment, each slice 1801A-1801N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines for computing a vector (e.g., computing mathematical operations on vectors). In at least one embodiment, a vector engine can compute a vector operation in 16-bit floating point (also referred to as "FP16"), 32-bit floating point (also referred to as "FP32"), or 64-bit floating point (also referred to as "FP64").In at least one embodiment, one or more slices 1801A-1801N include 16 vector engines paired with 16 matrix compute units to compute matrix / tensor operations, where vector engines and compute units are exposed via matrix extensions. In at least one embodiment, a slice is a particular portion of processing resources of a processing unit, for example, 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, the graphics core 1800 includes one or more matrix engines for computing matrix operations, for example, when computing tensor operations.

[0288] In at least one embodiment, one or more slices 1801A-1801N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 1801A-1801N). In at least one embodiment, a ray tracing unit computes ray tracing, triangle intersection, bounding box intersection, or other ray tracing operations.

[0289] In at least one embodiment, one or more slices 1801A-1801N comprise a media slice that encodes, decodes, and / or transcodes data, scales and / or formats data, and / or performs video quality operations on video data.

[0290] In at least one embodiment, one or more slices 1801A-1801N are connected to L2 cache and memory structure, interconnects, high-bandwidth memory (HBM) stacks (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 1801A-1801N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1801A-1801N include one or more L1 caches. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g., corresponding to the instructions; one or more samplers for sampling data;one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in geometry pipelines and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in vector graphic format (e.g., shape) and converting it to a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by shapes); one or more hierarchical depth buffers (Hiz) for caching data; and / or one or more pixel backends. In at least one embodiment, a slice 1801A-1801N includes a memory structure, such as an L2 cache.

[0291] In at least one embodiment, FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while DPFPUs 1815A-1815N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, ALUs 1816A-1816N can perform 8-bit, 16-bit, and 32-bit variable-precision integer operations and can be configured for mixed-precision operations. In at least one embodiment, MPUs 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, MPUs 1817-1817N may perform a variety of matrix operations to accelerate frameworks for machine learning applications, including support for accelerated general matrix-to-matrix multiplication (GEMM).In at least one embodiment, AFUs 1812A-1812N may perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0292] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in graphics core 1800 may be used for inferences or predictions based at least in part on weighting parameters calculated using neural network training procedures, neural network functions and / or architectures, or neural network use cases described herein.

[0293] In at least one embodiment, the graphics core 1800 includes an interconnect and an interconnect fabric sublayer connected to a switch and a GPU-to-GPU bridge that enables multiple graphics processors 1800 (e.g., 8) to be interconnected without gluing together, with load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1800. In at least one embodiment, interconnects include standardized interconnects (e.g., PCIe) or a combination thereof.

[0294] In at least one embodiment, the graphics core 1800 includes multiple tiles. In at least one embodiment, a tile is a single chip or one or more chips, where individual chips may be connected to an interconnect (e.g., an embedded multi-chip interconnect bridge (EMIB)). In at least one embodiment, the graphics core 1800 includes a compute tile, a memory tile (e.g., where a memory tile may be exclusively accessed by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, all of which tiles are packaged together in the graphics core 1800 as part of a GPU. In at least one embodiment, the graphics core 1800 may include multiple tiles in a single package (also referred to as a "multi-tile package").In at least one embodiment, a compute tile may include 8 graphics cores 1800, an L1 cache, and a base tile; a host interface with PCIe 5.0, HBM2e, MDFI, and EMIB; an 8-connect, 8-port interconnect tile with an embedded switch. In at least one embodiment, the tiles are connected by a face-to-face (F2F) chip-on-chip interconnect via closely spaced 36-micrometer microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 1800 includes a memory structure that includes memory and is a tile accessible by multiple tiles.In at least one embodiment, the graphics core 1800 stores, accesses, or loads its own hardware contexts in memory, where a hardware context is a set of data loaded from registers before a process continues, and where a hardware context may indicate a state of the hardware (e.g., the state of a GPU).

[0295] In at least one embodiment, the graphics core 1800 includes a SerDes (serializer / deserializer) circuit that converts a serial data stream to a parallel data stream or converts a parallel data stream to a serial data stream.

[0296] In at least one embodiment, the graphics core 1800 includes a high-speed coherent fabric (GPU to GPU), load / store units, bulk data transfer, and synchronization semantics, and connected GPUs via an embedded switch, with a GPU-GPU bridge controlled by a controller.

[0297] In at least one embodiment, the graphics core 1800 executes an API, where the API abstracts the hardware of the graphics core 1800 and accesses libraries of instructions to perform mathematical operations (e.g., a math kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communication, thread blocks, video processing, a data analysis library, and / or ray tracing operations.

[0298] In at least one embodiment, at least one with respect to Fig. 18A is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig.18A to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 18A illustrates at least one aspect related to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the environment 300 of FIG. 3, group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0299] Fig.18B illustrates GPGPU 1830, which may be configured to enable the execution of highly parallel computational operations by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 1830 may be directly connected to other instances of GPGPU 1830 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 1830 includes a host interface 1832 to enable connection to a host processor. In at least one embodiment, host interface 1832 is a PCI Express interface. In at least one embodiment, host interface 1832 may be a vendor-specific communications interface or communications fabric.In at least one embodiment, GPGPU 1830 receives instructions from a host processor and uses a global scheduler 1834 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to distribute the execution threads associated with those instructions among a group of compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H share a cache 1838. In at least one embodiment, cache 1838 may serve as a higher-level cache for caches within compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H comprise a slice or are referred to as "slices." In at least one embodiment, GPGPU 1830 is part of an SoC, for example, part of an integrated circuit 1600 (. Fig. 16).

[0300] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1844A-1844B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate memory (GDDR).

[0301] In at least one embodiment, the compute clusters 1836A-1836H each include a set of graphics cores, such as the graphics core 1800 of Fig.18A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of floating-point units in each of compute clusters 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of floating-point units may be configured to perform 64-bit floating-point operations.

[0302] In at least one embodiment, multiple instances of GPGPU 1830 can be configured to operate as a compute cluster. In at least one embodiment, the communication used by compute clusters 1836A-1836H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of GPGPU 1830 communicate via host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839 that couples GPGPU 1830 to a GPU interconnect 1840 that enables direct connection to other instances of GPGPU 1830. In at least one embodiment, GPU interconnect 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830.In at least one embodiment, GPU interconnect 1840 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 are located in separate computing systems and communicate via a network interconnect device accessible via host interface 1832. In at least one embodiment, GPU interconnect 1840 can be configured to enable connection to a host processor in addition to, or alternatively to, host interface 1832.

[0303] In at least one embodiment, GPGPU 1830 can be configured to train neural networks. In at least one embodiment, GPGPU 1830 can be used within an inference platform. In at least one embodiment where GPGPU 1830 is used for inference, GPGPU 1830 can include fewer compute clusters 1836A-1836H than in an embodiment where GPGPU 1830 is used for training a neural network. In at least one embodiment, the memory technology associated with memory 1844A-1844B can differ between inference and training configurations, with higher-bandwidth memory technologies provided for training configurations. In at least one embodiment, a inference configuration of GPGPU 1830 can support inference-specific instructions.For example, in at least one embodiment, a derivative configuration may support one or more 8-bit integer dot product instructions that may be used during derivative operations for deployed neural networks.

[0304] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in GPGPU 1830 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0305] In at least one embodiment, at least one with respect to Fig. 18B is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 18B is used to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 18B illustrates at least one aspect related to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig.1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the surrounding area 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0306] Fig.19 is a block diagram illustrating a computer system 1900 according to at least one embodiment. In at least one embodiment, the computer system 1900 includes a processing subsystem 1901 having one or more processors 1902 and a system memory 1904 communicating via an interconnect path that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset component or integrated with one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communications link 1906. In at least one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that may enable the computer system 1900 to receive input from one or more input devices 1908.In at least one embodiment, the I / O hub 1907 may enable a display controller, which may be included in one or more processors 1902, to provide outputs to one or more display devices 1910A. In at least one embodiment, one or more display devices 1910A coupled to the I / O hub 1907 may comprise a local, internal, or embedded display device.

[0307] In at least one embodiment, processing subsystem 1901 includes one or more parallel processors 1912 connected to storage hub 1905 via a bus or other communication link 1913. In at least one embodiment, communication link 1913 may use any number of standards-based communication link technologies or protocols, such as PCI Express, or may be a vendor-specific interface or structure for communication. In at least one embodiment, one or more parallel processors 1912 form a computationally focused parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a many-integrated-core (MIC) processor.In at least one embodiment, some or all of the parallel processors 1912 form a graphics processing subsystem that can output pixels to one or more display devices 1910A coupled via an I / O hub 1907. In at least one embodiment, the parallel processor(s) 1912 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1910B. In at least one embodiment, the parallel processor(s) 1912 include one or more cores, such as the graphics cores 1800 discussed herein.

[0308] In at least one embodiment, a system storage unit 1914 may be connected to an I / O hub 1907 to provide a storage mechanism for the computer system 1900. In at least one embodiment, an I / O switch 1916 may be used to provide an interface enabling connections between the I / O hub 1907 and other components, such as a network adapter 1918 and / or a wireless network adapter 1919, that may be integrated into the platform, and various other devices that may be added via one or more add-in devices 1920. In at least one embodiment, the network adapter 1918 may be an Ethernet adapter or other wired network adapter.In at least one embodiment, the wireless network adapter 1919 may include one or more Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more wireless radios.

[0309] In at least one embodiment, the computer system 1900 may include other components not explicitly shown, including USB or other port connections, optical storage devices, video capture devices, and the like, which may also be connected to the I / O hub 1907. In at least one embodiment, communication paths connecting various components in Fig.19 interconnected, be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect)-based protocols (e.g., PCI Express) or other bus or point-to-point communication interfaces and / or protocols, such as NV-Link high-speed links or interconnect protocols.

[0310] In at least one embodiment, the parallel processor(s) 1912 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and form a graphics processing unit (GPU), i.e., the parallel processor(s) 1912 include a graphics core 1800. In at least one embodiment, the parallel processor(s) 1912 include circuitry optimized for general processing. In at least one embodiment, components of the computer system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor(s) 1912, the memory hub 1905, the processor(s) 1902, and the I / O hub 1907 may be integrated into a system-on-chip (SoC) circuit.In at least one embodiment, components of computer system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 1900 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computer system.

[0311] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig.7A and / or 7B. In at least one embodiment, logic 715 in computer system 1900 may be used for inference or prediction operations based at least in part on weighting parameters calculated using training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0312] In at least one embodiment, at least one with respect to Fig. 19 is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig.19 to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 19 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the surrounding area 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6. PROCESSORS

[0313] Fig. 20A shows a parallel processor 2000 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2000 can be implemented using one or more integrated circuits, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the parallel processor 2000 shown is a variant of one or more parallel processors 1912 implemented in Fig. 19 according to an exemplary embodiment. In at least one embodiment, a parallel processor 2000 includes one or more graphics cores 1800.

[0314] In at least one embodiment, processor 2000 includes a parallel processing unit 2002. In at least one embodiment, parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of parallel processing unit 2002. In at least one embodiment, I / O unit 2004 may be directly connected to other devices. In at least one embodiment, I / O unit 2004 connects to other devices through the use of a hub or switch interface, such as a storage hub 2005. In at least one embodiment, connections between storage hub 2005 and I / O unit 2004 form a communication link 2013.In at least one embodiment, the I / O unit 2004 is coupled to a host interface 2006 and a memory crossbar 2016, wherein the host interface 2006 receives commands directed to perform processing operations and the memory crossbar 2016 receives commands directed to perform memory operations.

[0315] In at least one embodiment, when host interface 2006 receives a command buffer via I / O unit 2004, it may forward work to a front end 2008 to execute those commands. In at least one embodiment, front end 2008 is coupled to a scheduler 2010 (which may also be referred to as a sequencer) configured to dispatch commands or other work items to a processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is properly configured and in a valid state before dispatching tasks to a cluster of processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic executing on a microcontroller.In at least one embodiment, the scheduler 2010 implemented on a microcontroller is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid interruption and context switching of threads executing on the processing array 2012. In at least one embodiment, host software may allocate workloads for scheduling on the processing cluster array 2012 via one of several graphics processing paths. In at least one embodiment, workloads may then be automatically distributed across the processing cluster array 2012 via the logic of the scheduler 2010 within a microcontroller that includes the scheduler 2010.

[0316] In at least one embodiment, the processing cluster array 2012 may include up to "N" processing clusters (e.g., cluster 2014A, cluster 2014B through cluster 2014N), where "N" represents a positive integer (which may be a different integer "N" than that used in other figures). In at least one embodiment, each cluster 2014A-2014N of the processing cluster 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may allocate work to the clusters 2014A-2014N of the processing cluster array 2012 using various scheduling and / or work distribution algorithms, which may vary depending on the workload incurred for each program or computation type.In at least one embodiment, scheduling may be performed dynamically by the scheduler 2010 or may be partially assisted by compiler logic during compilation of the program logic configured for execution by the processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N of the processing cluster array 2012 may be allocated for processing different program types or for performing different computations.

[0317] In at least one embodiment, the processing cluster array 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general parallel computing operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic for performing tasks including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0318] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster 2012 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via the I / O unit 2004 for processing.In at least one embodiment, transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to system memory.

[0319] In at least one embodiment, when parallel processing unit 2002 is used to perform graphics processing, scheduler 2010 may be configured to divide a processing workload into approximately equally sized tasks to enable better distribution of graphics processing operations across multiple clusters 2014A-2014N of processing cluster 2012. In at least one embodiment, portions of processing cluster 2012 may be configured to perform different types of processing.For example, in at least one embodiment, a first section may be configured to perform vertex shading and topology generation, a second section may be configured to perform tessellation and geometry shading, and a third section may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more clusters 2014A-2014N may be stored in buffers to allow intermediate data to be transferred between clusters 2014A-2014N for further processing.

[0320] In at least one embodiment, processing cluster array 2012 may receive processing tasks to be executed via scheduler 2010, which receives commands defining processing tasks from frontend 2008. In at least one embodiment, processing tasks may include indices of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how data is to be processed (e.g., which program is to be executed). In at least one embodiment, scheduler 2010 may be configured to retrieve indices corresponding to tasks or to receive indices from frontend 2008.In at least one embodiment, frontend 2008 may be configured to ensure that processing cluster 2012 is configured to a valid state before initiating a workload indicated by incoming command buffers (e.g., stack buffers, push buffers, etc.).

[0321] In at least one embodiment, each of one or more instances of parallel processing unit 2002 may be coupled to a parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 may be accessed via a memory crossbar 2016, which may receive memory requests from both processing cluster array 2012 and I / O unit 2004. In at least one embodiment, memory crossbar 2016 may access parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, memory interface 2018 may include a plurality of partition units (e.g., partition unit 2020A, partition unit 2020B, through partition unit 2020N), each of which may be coupled to a portion (e.g., memory unit) of parallel processor memory 2022.In at least one embodiment, a number of partition units 2020A-2020N is configured to correspond to a number of storage units, such that a first partition unit 2020A has a corresponding first storage unit 2024A, a second partition unit 2020B has a corresponding storage unit 2024B, and an Nth partition unit 2020N has a corresponding Nth storage unit 2024N. In at least one embodiment, a number of partition units 2020A-2020N may be different than a number of storage units.

[0322] In at least one embodiment, memory units 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate memory (GDDR). In at least one embodiment, memory units 2024A-2024N may also include 3D stack memory, including, but not limited to, high bandwidth memory (HBM), HBM2e, or HDM3. In at least one embodiment, render targets, such as frame buffers or texture maps, may be stored across memory units 2024A-2024N, allowing partition units 2020A-2020N to write portions of each render target in parallel to efficiently utilize the available bandwidth of parallel processor memory 2022.In at least one embodiment, a local instance of parallel processor memory 2022 may be eliminated in favor of a unified memory design that uses system memory in conjunction with a local cache memory.

[0323] In at least one embodiment, each of the clusters 2014A-2014N of the processing cluster 2012 may process data written to one of the storage units 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the storage crossbar 2016 may be configured to transfer an output of each cluster 2014A-2014N to any partition unit 2020A-2020N or to another cluster 2014A-2014N that may perform additional processing on an output. In at least one embodiment, each cluster 2014A-2014N may communicate with the storage interface 2018 via the storage crossbar 2016 to read from or write to various external storage devices.In at least one embodiment, the memory crossbar 2016 has a connection to the memory interface 2018 to communicate with the I / O unit 2004, as well as a connection to a local instance of the parallel processor memory 2022, whereby processing units within different processing clusters 2014A-2014N can communicate with system memory or other memory that is not local to the parallel processing unit 2002. In at least one embodiment, the memory crossbar 2016 can use virtual channels to separate traffic flows between the clusters 2014A-2014N and the partition units 2020A-2020N.

[0324] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate, even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units compared to other instances.In at least one embodiment, systems including one or more instances of the parallel processing unit 2002 or the parallel processor 2000 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld PCs, servers, workstations, game consoles, and / or embedded systems.

[0325] Fig. 20B is a block diagram of a partition unit 2020 according to at least one embodiment. In at least one embodiment, the partition unit 2020 is an instance of one of the partition units 2020A-2020N of Fig. 20A. In at least one embodiment, the partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster operations unit). In at least one embodiment, the L2 cache 2021 is a read / write cache configured to execute load and store operations received from the memory crossbar 2016 and the ROP 2026. In at least one embodiment, read misses and urgent writeback requests are issued from the L2 cache 2021 to the frame buffer interface 2025 for processing. In at least one embodiment, updates may also be sent to a frame buffer via the frame buffer interface 2025 for processing. In at least one embodiment, the frame buffer interface 2025 is connected to one of the memory units in the parallel processor memory, such as the memory units 2024A-2024N of Fig. 20A (for example within the parallel processor memory 2022), as an interface.

[0326] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stencil, Z-test, blend, etc. In at least one embodiment, ROP 2026 then outputs processed graphics data, which is stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic for compressing depth or color data written to memory and for decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic using one or more of several compression algorithms. In at least one embodiment, a type of compression performed by ROP 2026 may vary based on statistical properties of the data to be compressed.For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0327] In at least one embodiment, ROP 2026 is in each processing cluster (e.g., clusters 2014A-2014N of Fig. 20A) instead of partition unit 2020. In at least one embodiment, read and write requests for pixel data instead of pixel fragment data are transmitted via memory crossbar 2016. In at least one embodiment, processed graphics data may be displayed on a display device, for example, on one or more display devices 1910 of Fig. 19, for further processing by one or more processors 1902 or for further processing by one of the processing units within the parallel processor 2000 of Fig. 20A.

[0328] Fig. 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 2014A-2014N of Fig. 20A. In at least one embodiment, the processing cluster 2014 may be configured to execute many threads in parallel, where "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single instruction, multiple data (SIMD) instruction issuing techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction, multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a set of engines within each processing cluster.

[0329] In at least one embodiment, the operation of the processing cluster 2014 may be controlled by a pipeline manager 2032 that dispatches tasks to parallel SIMT processors. In at least one embodiment, the pipeline manager 2032 receives instructions from the scheduler 2010 of Fig. 20A and manages the execution of these instructions via a graphics multiprocessor 2034 and / or a texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included in the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may be included in a processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and a data crossbar 2040 may be used to distribute processed data to one of several possible destinations, including other shader units.In at least one embodiment, the pipeline manager 2032 may facilitate the distribution of processed data by specifying destinations for processed data to be distributed across the data crossbar 2040.

[0330] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may include an identical set of functional execution logic (e.g., arithmetic logic units, load / store units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, in which new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may be present.

[0331] In at least one embodiment, instructions transferred to processing cluster 2014 represent a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program with different input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within a graphics multiprocessor 2034. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within a graphics multiprocessor 2034.In at least one embodiment, if a thread group includes fewer threads than a number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is processing. In at least one embodiment, a thread group may also include more threads than a number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, if a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2034, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute concurrently on a graphics multiprocessor 2034.

[0332] In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2034 may forgo an internal cache and use a cache (e.g., L1 cache 2048) within the processing cluster 2014. In at least one embodiment, each graphics multiprocessor 2034 also has access to L2 caches in partition units (e.g., partition units 2020A-2020N of Fig. 20A) that are shared by all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2034 can also access off-chip global memory, which can include one or more local parallel processor memories and / or system memories. In at least one embodiment, any memory external to parallel processing unit 2002 can be used as global memory. In at least one embodiment, processing cluster 2014 includes multiple instances of graphics multiprocessor 2034 and can share common instructions and data, which can be stored in L1 cache 2048.

[0333] In at least one embodiment, each processing cluster 2014 may include a memory management unit (MMU) 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside within the memory interface 2018 of Fig. 20A. In at least one embodiment, MMU 2045 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU 2045 may include address translation lookaside buffers (TLBs) or caches, which may be located in a graphics multiprocessor 2034 or L1 2048 cache or a processing cluster 2014. In at least one embodiment, a physical address is processed to distribute access to surface data locally to enable efficient interleaving of requests between partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0334] In at least one embodiment, a processing cluster 2014 may be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations, such as determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034 and retrieved as needed from an L2 cache, local parallel processor memory, or system memory.In at least one embodiment, each graphics multiprocessor 2034 issues processed tasks to the data crossbar 2040 to provide processed tasks to another processing cluster 2014 for further processing or to store processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 2016. In at least one embodiment, a preROP 2042 (pre-raster operation unit) is configured to receive data from a graphics multiprocessor 2034 and forward data to ROP units, which may be located in partition units as described herein (e.g., partition units 2020A-2020N of FIG. Fig. 20A). In at least one embodiment, the preROP 2042 unit may perform optimizations for mixing colors, organizing pixel color data, and performing address translations.

[0335] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 may be used in a processing cluster 2014 for inferring or predicting operations based at least in part on weighting parameters calculated using training operations, neural network functions, and / or architectures or neural network use cases as described herein.

[0336] In at least one embodiment, at least one with respect to the Fig. 20A-20C is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of the Fig. 20A-20C to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of the Fig. 20A-20C illustrate at least one aspect related to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, surroundings 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0337] Fig. 20D illustrates a graphics multiprocessor 2034 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2034 is coupled to the pipeline manager 2032 of the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline including, among other things, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general-purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066, where one or more load / store units 2066 may perform load / store operations to load / store instructions corresponding to performing an operation.In at least one embodiment, GPGPU cores 2062 and load / store units 2066 are coupled to a cache memory 2072 and a shared memory 2070 via a memory and cache interconnect 2068. In at least one embodiment, GPGPU cores 2062 are part of an SoC, such as part of integrated circuit 1600 in FIG. Fig. 16.

[0338] In at least one embodiment, instruction cache 2052 receives a stream of instructions to be executed from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and forwarded for execution by an instruction unit 2054. In at least one embodiment, instruction unit 2054 may dispatch instructions as thread groups (e.g., warps, wavefronts, waves), with each thread of the thread group assigned to a different execution unit within GPGPU cores 2062. In at least one embodiment, an instruction may access a local, shared, or global address space by specifying an address within a unified address space.In at least one embodiment, address mapping unit 2056 may be used to translate addresses in a unified address space into a particular memory address accessible by load / store units 2066.

[0339] In at least one embodiment, register file 2058 provides a set of registers for functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands associated with data paths of functional units (e.g., GPGPU cores 2062, load / store units 2066) of graphics multiprocessor 2034. In at least one embodiment, register file 2058 is partitioned between each of the functional units such that each functional unit is assigned a dedicated portion of register file 2058. In at least one embodiment, register file 2058 is partitioned between different warps (which may be referred to as wavefronts and / or waves) executed by graphics multiprocessor 2034.

[0340] In at least one embodiment, GPGPU cores 2062 may each include floating-point units (FPUs) and / or integer arithmetic logic units (ALUs) used to execute instructions of graphics multiprocessor 2034. In at least one embodiment, GPGPU cores 2062 may have a similar architecture or differ in architecture. In at least one embodiment, a first portion of GPGPU cores 2062 includes a single-precision FPU and an integer ALU, while a second portion of GPGPU cores includes a double-precision FPU. In at least one embodiment, FPUs may implement the floating-point arithmetic of the IEEE 754-2008 standard or enable variable-precision floating-point arithmetic.In at least one embodiment, graphics multiprocessor 2034 may additionally include one or more fixed-function or special-purpose functional units to perform specific functions such as copying rectangles or blending pixels. In at least one embodiment, one or more of GPGPU cores 2062 may also include fixed or special-purpose functional logic.

[0341] In at least one embodiment, GPGPU cores 2062 include SIMD logic capable of executing a single instruction on multiple data sets. In at least one embodiment, GPGPU cores 2062 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for SPMD (Single Program Multiple Data) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can execute via a single SIMD instruction.For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

[0342] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network that connects each functional unit of the graphics multiprocessor 2034 to the register file 2058 and the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a crossbar interconnect that enables the load / store unit 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 may operate at the same frequency as the GPGPU cores 2062, so that data transfer between the GPGPU cores 2062 and the register file 2058 may have very low latency.In at least one embodiment, shared memory 2070 may be used to enable communication between threads executing on functional units within graphics multiprocessor 2034. In at least one embodiment, cache 2072 may be used as a data cache, for example, to cache texture data between functional units and texture unit 2036. In at least one embodiment, shared memory 2070 may also be used as a program-managed cache. In at least one embodiment, threads executing on GPGPU cores 2062 may programmatically store data in shared memory in addition to automatically cached data stored in cache 2072.

[0343] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to host processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a graphics processor may be communicatively coupled to a host processor core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, an SoC includes a parallel processor or GPGPU as described herein, with the parallel processor or GPGPU executing on the SoC. In at least one embodiment, a GPU may be integrated on a package or die as cores and communicatively coupled to cores via an internal processor bus / interconnect within a package or die.In at least one embodiment, processor cores, regardless of how a GPU is connected, can assign work to that GPU in the form of command / instruction sequences contained in a work description. In at least one embodiment, that GPU then uses dedicated circuitry / logic to efficiently process those commands / instructions.

[0344] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 715 are described herein in connection with the Fig. 7A and / or 7B. In at least one embodiment, logic 715 may be used in a graphics multiprocessor 2034 for inference or prediction operations based at least in part on weighting parameters calculated using training operations, neural network functions and / or architectures or neural network use cases as described herein.

[0345] In at least one embodiment, at least one with respect to Fig. 20 is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 20 is used to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 20 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, by generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, surroundings 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0346] Fig. 21 illustrates a computer system with multiple graphics processors 2100 according to at least one embodiment. In at least one embodiment, the computer system with multiple graphics processors 2100 may include a processor 2102 connected to a plurality of general-purpose graphics processing units (GPGPUs) 2106A-D via a host interface switch 2104. In at least one embodiment, the host interface switch 2104 is a PCI Express switch device that couples the processor 2102 to a PCI Express bus over which the processor 2102 can communicate with the GPGPUs 2106A-D. In at least one embodiment, the GPGPUs 2106A-D may form an interconnect via a set of high-speed, point-to-point GPU-to-GPU interconnects 2116. In at least one embodiment, the GPU-to-GPU connections 2116 are connected to each of the GPGPUs 2106A-D via a dedicated GPU connection.In at least one embodiment, the P2P GPU connections 2116 enable direct communication between each of the GPGPUs 2106A-D without requiring communication over the host interface bus 2104 to which the processor 2102 is connected. In at least one embodiment where GPU-to-GPU traffic is routed to P2P GPU connections 2116, the host interface 2104 remains available for accessing system memory or for communicating with other instances of the multi-GPU computer system 2100, for example, via one or more network devices. While in at least one embodiment, GPGPUs 2106A-D are connected to processor 2102 via a host interface switch 2104, in at least one embodiment, processor 2102 includes direct support for P2P GPU connections 2116 and can be connected directly to GPGPUs 2106A-D.In at least one embodiment, GPGPUs 2106A-D are part of a SoC, such as part of integrated circuit 1600 in . Fig. 16, wherein GPGPUs 2106A-D perform the operations described herein.

[0347] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 may be used in a computer system 2100 having multiple GPUs for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0348] In at least one embodiment, the multi-graphics processor computer system 2100 includes one or more graphics cores 1800.

[0349] In at least one embodiment, at least one with respect to Fig. 21 component shown or described is used to implement techniques and / or functions that may be used in conjunction with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 21 is used to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 21 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, by generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, surroundings 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0350] Fig. 22 is a block diagram of a graphics processor 2200 according to at least one embodiment. In at least one embodiment, the graphics processor 2200 includes a ring interconnect 2202, a pipelined front end 2204, an engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, the ring interconnect 2202 couples the graphics processor 2200 to other processing units, including other graphics processors or one or more general-purpose processing cores. In at least one embodiment, the graphics processor 2200 is one of many processors integrated into a multi-core processing system. In at least one embodiment, the graphics processor 2200 includes the graphics core 1800.

[0351] In at least one embodiment, graphics processor 2200 receives instruction stacks via a ring interconnect 2202. In at least one embodiment, incoming instructions are interpreted by an instruction streamer 2203 in a pipeline front end 2204. In at least one embodiment, graphics processor 2200 includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s) 2280A-2280N. In at least one embodiment, instruction streamer 2203 provides instructions to geometry pipeline 2236 for 3D geometry processing instructions. In at least one embodiment, instruction streamer 2203 provides instructions for at least some media processing instructions to a video front end 2234 coupled to media engine 2237.In at least one embodiment, the media engine 2237 includes a video quality engine (VQE) 2230 for post-processing videos and images and a multi-format encoder / decoder (MFX) engine 2233 to provide hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate execution threads for threaded execution resources provided by at least one graphics core 2280.

[0352] In at least one embodiment, graphics processor 2200 includes scalable resources for executing threads with graphics cores 2280A-2280N (which may be modular and sometimes referred to as core slices), each having a plurality of sub-cores 2250A-2250N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2200 may include any number of graphics cores 2280A. In at least one embodiment, graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, graphics processor 2200 is a low-performance processor with a single sub-core (e.g., 2250A). In at least one embodiment, the graphics processor 2200 includes a plurality of graphics cores 2280A-2280N, each including a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N.In at least one embodiment, each subcore in the first subcores 2250A-2250N includes at least a first set of execution units 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each subcore in the second subcores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each subcore 2250A-2250N, 2260A-2260N shares a set of common resources 2270A-2270N. In at least one embodiment, the shared resources include a shared cache and pixel operation logic. In at least one embodiment, the graphics processor 2200 includes load / store units in a pipelined front end 2204.

[0353] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 715 are described herein in connection with the Fig. 7A and / or 7B. In at least one embodiment, logic 715 in graphics processor 2200 may be used for inferences or predictions based at least in part on weighting parameters calculated using neural network training procedures, neural network functions and / or architectures, or neural network use cases described herein.

[0354] In at least one embodiment, at least one with respect to Fig. 22 is used to implement techniques and / or functions associated with the Fig. 1-6. In at least one embodiment, at least one component of Fig. 22 is used to use one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations of the one or more tasks. In at least one embodiment, at least one component of Fig. 22 at least one aspect relating to the planning module 106, the autonomous device 114, the neural network 118 and / or the image sensor 122 of Fig. 1, namely generating training actions 204 and / or updating the neural network using performed training actions and images of performed training actions of Fig. 2, the surrounding area 300 from Fig. 3, Group of stacked objects of Fig. 4, Planning module of Fig. 5 and / or process of Fig. 6.

[0355] Fig. 23 is a block diagram illustrating the microarchitecture for a processor 2300 that may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2300 may execute instructions, including x86 instructions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), and so on. In at least one embodiment, the processor 2300 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation, Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point form, may operate on packed data elements accompanying single-instruction, multiple-instruction data ("SIMD"), and streaming SIMD extension ("SSE") instructions.In at least one embodiment, 128-bit XMM registers related to SSE2, SSE3, SSE4, AVX, or beyond (commonly referred to as "SSEx") technology may contain such packed data operands. In at least one embodiment, processor 2300 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0356] In at least one embodiment, processor 2300 includes an in-order frontend ("frontend") 2301 to fetch instructions to be executed and prepare instructions to be used later in a processor pipeline. In at least one embodiment, frontend 2301 may include multiple units. In at least one embodiment, an instruction pre-fetcher 2326 fetches instructions from memory and passes instructions to an instruction decoder 2328, which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2328 decodes a received instruction into one or more operations, referred to as "micro-instructions" or "micro-operations" (also referred to as "micro-ops" or "uOps" or "µ-ops"), that a machine may execute.In at least one embodiment, instruction decoder 2328 decomposes an instruction into operation code and corresponding data and control fields that can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, a trace cache 2330 may assemble decoded uOps into programmed sequences, or traces, in a uOps queue 2334 for execution. In at least one embodiment, when trace cache 2330 encounters a complex instruction, a microcoder ROM 2332 provides uOps needed to complete an operation.

[0357] In at least one embodiment, some instructions may be converted into a single micro-op, while others may require multiple micro-ops to complete the entire operation. In at least one embodiment, instruction decoder 2328 may access microcode ROM 2332 to execute an instruction if more than four micro-operations are required to complete an instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-operations for processing in instruction decoder 2328. In at least one embodiment, an instruction may be stored in microcode ROM 2332 if a number of micro-operations are required to perform such an operation.In at least one embodiment, trace cache 2330 refers to a programmable logic array ("PLA") having an entry point for determining a correct microinstruction pointer for reading microcode sequences to execute one or more instructions from microcode ROM 2332 according to at least one embodiment. In at least one embodiment, after microcode ROM 2332 completes sequencing mi...

Claims

[1] Processor comprising: one or more circuits to use one or more neural networks, to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more performance simulations for the one or more tasks. [2] The processor of claim 1, wherein the one or more execution simulations of the one or more tasks are generated by a task and motion planning module. [3] The processor of claim 2, wherein the task and motion planning module is to access an initial state of an environment. [4] The processor of claim 2, wherein the task and motion planning module is to access an initial state of the autonomous device. [5] The processor of claim 1, wherein the one or more performance simulations of the one or more tasks comprise one or more training actions for the autonomous device. [6] The processor of claim 1, wherein the one or more neural networks are trained using the one or more images and the one or more performance simulations of the one or more tasks. [7] The processor of claim 1, wherein the one or more circuits are to use the one or more neural networks to identify one or more control inputs of the autonomous device to control the autonomous device to perform the one or more tasks. [8] System comprising: one or more processors for using one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more simulations of performance of the one or more tasks. [9] The system of claim 8, wherein the one or more performance simulations of the one or more tasks are generated by a task and motion planning module. [10] The system of claim 9, wherein the task and motion planning is for accessing an initial state of an environment. [11] The system of claim 9, wherein the task and motion planning module is configured to access an initial state of the autonomous device. [12] The system of claim 8, wherein the one or more performance simulations of the one or more tasks comprise one or more training actions for the autonomous device. [13] The system of claim 8, wherein the one or more neural networks are trained using the one or more images and the one or more performance simulations of the one or more tasks. [14] The system of claim 8, wherein the one or more processors are to use the one or more neural networks to identify one or more control inputs of the autonomous device to control the autonomous device to perform the one or more tasks. [15] Method comprising: Using one or more neural networks to control an autonomous device to perform one or more tasks based at least in part on one or more images of one or more simulations of performing the one or more tasks. [16] The method of claim 15, wherein the one or more performance simulations of the one or more tasks are generated by a task and motion planning module. [17] The method of claim 16, wherein the task and motion planning module is to access an initial state of an environment. [18] The method of claim 16, wherein the task and motion planning module is to access an initial state of the autonomous device. [19] The method of claim 15, wherein the one or more simulations of performing the one or more tasks comprise training actions for the autonomous device. [20] The method of claim 15, wherein the one or more neural networks are trained using the one or more images and the one or more performance simulations of the one or more tasks.

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