METHOD FOR INDUCTING THE THRESHOLD VOLTAGE TUNING RANGE FOR SEMICONDUCTOR DEVICES

Abstract

Semiconductor devices and methods are provided. An exemplary method according to the present disclosure comprises: forming a dielectric layer over a section of a substrate, forming a first p-exit layer over the dielectric layer, wherein the first p-exit layer comprises titanium nitride, forming a second p-exit layer over the first p-exit layer, wherein the second p-exit layer comprises titanium nitride with dopants, forming an aluminum-containing N-exit layer over the second p-exit layer, wherein the dopants in the second p-exit layer reduce the aluminum diffusion from the aluminum-containing N-exit layer into the second p-exit layer, and forming a metal layer over the aluminum-containing N-exit layer.

Description

PRIORITY

[0001] This application is a non-provisional application of, and claims priority over, the provisional US patent application with serial number 63 / 655,816, filed on June 4, 2024, the entire disclosure of which is hereby incorporated by reference into the present text. BACKGROUND

[0002] The integrated semiconductor (IC) industry has experienced exponential growth. Technological advances in IC materials and design have led to generations of ICs, each featuring smaller and more complex circuits than the previous one. As ICs evolved, functional density (the number of interconnected components per unit area) has generally increased, while geometric size (the smallest component or trace that can be produced by a manufacturing process) has decreased. This miniaturization process generally delivers benefits by increasing production efficiency and reducing manufacturing costs.

[0003] Such miniaturization has also increased the complexity of processing and manufacturing ICs. Integrated circuits contain a variety of different components, such as transistors. One characteristic of a transistor is its threshold voltage. As transistor sizes continue to decrease, it is desirable to find ways to increase the threshold voltage tuning range without affecting other aspects of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. It is also emphasized that the accompanying drawings illustrate only typical embodiments of this invention and should therefore not be interpreted as limiting the scope of protection, since the invention may equally well be applicable to other embodiments. Fig. Figure 1 is a flowchart illustrating a method for forming a semiconductor structure according to various embodiments of the present disclosure. Fig. Figure 2 illustrates a fragmentary top view of an exemplary structure constructed using the method of Fig. It is to undergo 1 different processing stages, according to different aspects of the revelation. Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21A, Fig. 21B and Fig. Figure 22 illustrates fragmentary cross-sectional views of the structure during various manufacturing stages in the process of Fig. 1 according to various aspects of the revelation. Fig. 14A, Fig. 14B, Fig. 14C, Fig. 14D illustrate fragmentary cross-sectional views of various structures according to different aspects of the revelation. Fig. Figure 15 illustrates a simplified time diagram of a cycle of an atomic layer deposition process according to various aspects of the revelation. Fig. Figure 16 illustrates a simplified time diagram of a cycle of another atomic layer deposition process according to various aspects of the revelation. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or facilities discussed.

[0006] Spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify descriptions and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0007] Furthermore, when a number or range of numbers is described using terms like "about," "approximately," and the like, the term should also include numbers that lie within a meaningful range that accounts for variations inherent in any manufacturing process, as understood by the person skilled in the art. For example, the number or range of numbers includes a meaningful range that contains the stated number plus a span of, for example, ±10% of the stated number, based on known manufacturing tolerances associated with the production of a structural element that has a property linked to the number. For example, a material layer that is "about 5 nm" thick may encompass a dimensional range of 4.25 nm to 5.75 nm if the person skilled in the art knows that the manufacturing tolerances associated with the deposition of the material layer are ±15%.Furthermore, this disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or devices discussed. To avoid any ambiguity, the X, Y, and Z directions in the figures are perpendicular to each other and are used consistently. Unless otherwise specified, throughout this disclosure, identical reference numerals denote identical structural elements.

[0008] A functional gate stack of a transistor comprises a gate electrode above a gate dielectric layer. The gate electrode may have one or more work layers with suitable work functions, such that the corresponding transistor is improved with respect to its device performance (for example, a reduced threshold voltage). As described above, it is desirable to find ways to increase the threshold voltage tuning range without affecting other aspects of the transistor. One way to adjust the threshold voltage is to adjust the thickness of the work layer, which is part of the transistor's gate stack. However, increasing the thickness of the work layer becomes more difficult when smaller circuits are fabricated.

[0009] The present disclosure relates to methods for increasing the threshold voltage tuning range of P-transistors. A first mechanism of the present disclosure can incorporate dopants of a first type into the work function layer of the P-transistor to reduce aluminum diffusion, thereby increasing the work function and decreasing the threshold voltage of the P-transistor; a second mechanism of the present disclosure can incorporate dopants of a second type into the work function layer of the P-transistor to reduce the work function, thereby increasing the threshold voltage of the P-transistor. Thus, the threshold voltage tuning range can be increased without adjusting the thickness of the work function layer. The two mechanisms are described with reference to Fig. 1-22 described in more detail.

[0010] With reference to Fig. In steps 1 and 2-3, procedure 100 includes a block 102 where a structure 200 is received. Fig. Figure 3 shows a fragmentary cross-sectional view of structure 200 along the in Fig. Line AA shown in 2. A fragmentary cross-sectional view of structure 200 along the line shown in Fig. Line CC shown in 2 resembles Fig. 3 and is omitted for the sake of simplicity. In this illustrated embodiment, the structure 200 comprises a first device region 200A for forming N devices (for example, N-gate all-around transistors (GAA transistors)) and a second device region 200B for forming P devices (for example, P-GAA transistors). The structure 200 has a substrate 202 (in Fig. 3). In one embodiment, the substrate 202 is a bulk silicon substrate (that is, it contains single-crystal bulk silicon). In various embodiments, the substrate 202 may also contain other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In some alternative embodiments, the substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate, and comprises a support, an insulator on the support, and a semiconductor layer on the insulator. The substrate 202 can have various doped regions set up according to the design requirements of the semiconductor structure 200.P-doped regions can contain p-doped elements such as boron, indium, other p-doped elements, or combinations thereof. N-doped regions can contain n-doped elements such as phosphorus, arsenic, other n-doped elements, or combinations thereof. In some implementations, substrate 202 contains doped regions formed with a combination of p-type and n-type dopants. The various doped regions can be formed directly on and / or within substrate 202, creating, for example, a p-well structure, an n-well structure, a double-well structure, a raised structure, or combinations thereof. An ion implantation process, a diffusion process, and / or another suitable doping process can be used to form the different doped regions.

[0011] The structure 200 also has several fin-shaped active regions (for example, fin-shaped active regions 205a, 205b) arranged above the substrate 202. In the present embodiments, each of the fin-shaped active regions 205a is located in the first device region 200A (in Fig. (2 shown) of the structure 200, and each of the fin-shaped active regions 205b is formed in the second device region 200B of the structure 200. The fin-shaped active regions 205a, 205b can be referred to separately or collectively as a fin-shaped active region 205 or fin-shaped active regions 205. Each of the fin-shaped active regions 205 extends longitudinally along the X-direction and is subdivided into channel regions 205C and source / drain regions 205SD. “Source / drain region” or “source / drain regions” can refer—individually or collectively, depending on the context—to a source or a drain.

[0012] The fin-shaped active region 205 can consist of an upper section of the substrate 202 and a vertical stack 207 (in Fig. 3) are formed from alternating semiconductor layers 206 and 208 using a combination of lithography and etching steps. In the embodiment shown, the vertical stack 207 of alternating semiconductor layers 206 and 208 has a number of channel layers 208 nested with a number of sacrificial layers 206. Each channel layer 208 can contain a semiconductor material such as silicon, germanium, silicon carbide, silicon-germanium, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, while each sacrificial layer 206 has a different composition than the channel layer 208. In one embodiment, the channel layer 208 contains silicon (Si), and the sacrificial layer 206 contains silicon-germanium (SiGe).The channel layers 208 and the sacrificial layers 206 can be epitaxially deposited on the substrate 202 using molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), and / or other suitable epitaxial growth processes. In some examples, each of the fin-shaped active regions 205 can have a total of three to ten pairs of alternating sacrificial layers 206 and channel layers 208; of course, other methods may be applicable depending on the specific design requirements.

[0013] The structure 200 also features an insulation structure element 204 (in Fig. (11 shown) formed above the substrate 202 to isolate two adjacent fin-shaped active regions. The insulation structural element 204 can also be referred to as a shallow trench insulation (STI) structural element. In some embodiments, the STI structural element 204 may contain silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low k-value dielectric, combinations thereof, and / or other suitable materials. In some embodiments, a top surface of the STI structural element 204 is lower than a top surface of the upper portion of the substrate. The top surface of the STI structural element 204 may be a curved (for example, concave) surface with a lowest point near its center.

[0014] With further reference to Fig. 2-3, the structure 200 also includes dummy gate structures 216, which are formed over channel regions 205C of the fin-shaped active regions 205. The channel regions 205C and the dummy gate structures 216 also define source / drain regions 205SD, which are not vertically overlapped by the dummy gate structures 216. Each of the channel regions 205C is arranged between two source / drain regions 205SD along the X-direction. Two dummy gate structures 216 are in Fig. Figure 2 shows, but structure 200 can also have other numbers of dummy gate structures. In this embodiment, a gate replacement process (or gate load process) is used, with the dummy gate structures 216 serving as placeholders for functional gate stacks (for example, those shown in Figure 2). Fig. 21A and Fig. (21B shown in the functional gate stack 255, 260). Other processes for forming the functional gate stack are also possible. Although not shown separately, in the present embodiments each of the dummy gate structures 216 comprises a dummy gate dielectric layer (for example, silicon oxide) and a dummy gate electrode (for example, polysilicon) arranged over the dummy gate dielectric layer. The structure 200 also has gate spacers 218 extending along side walls of the dummy gate structures 216. In some embodiments, the gate spacers 218 can contain silicon oxide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material. The gate spacer 218 can be a single-layer or a multi-layer structure.

[0015] With reference to Fig. 1 and Fig. In section 4, the method 100 comprises a block 104 where source / drain regions 205SD of the fin-shaped active regions 205 are recessed to form source / drain openings 220. In some embodiments, the source / drain regions 205SD of the fin-shaped active region 205 that are not covered by the dummy gate structures 216 and the gate spacers 218 are anisotropically etched by dry etching or a suitable etching process to form source / drain openings 220. An exemplary dry etching process can implement an oxygen-containing gas, hydrogen, a fluorine-containing gas (for example, CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (for example, Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (for example, HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof.The source / drain openings 220 extend through the stack 207 of channel layers 208 and sacrificial layers 206 and into the substrate 202. As through . Fig. As illustrated in Figure 4, the side walls of the channel layers 208 and the sacrificial layers 206 are exposed in the source / drain openings 220.

[0016] With reference to Fig. In sections 1 and 5-6, procedure 100 comprises a block 106 where the sacrificial layers 206 are replaced by dummy layers 224. With reference to Fig. 5. After the formation of the source / drain openings 220, the sacrificial layers 206, which nest the channel layers 208 in the channel region 205C, are selectively removed. The selective removal of the sacrificial layers 206 exposes the channel layers 208 to form channel elements 208. Depending on the design, the channel elements 208 can take the form of nanowires, nanolayers, or other nanostructures. The selective removal of the sacrificial layers 206 creates spaces 222 between and around adjacent channel elements 208. The selective removal of the sacrificial layers 206 can be implemented by selective dry etching, selective wet etching, or other selective etching processes. An example of a selective dry etching process might involve the use of one or more fluorine-based etchants, such as fluorine gas or fluorocarbons.An example of a selective wet etching process could include APM etching (for example, an ammonia hydroxide-hydrogen peroxide-water mixture).

[0017] With reference to Fig. In an exemplary process, after the selective removal of the sacrificial layers 206, a layer of dielectric material is deposited around the channel elements 208 and over the source / drain openings 220. The dielectric material layer fills the space 222 between the channel elements 208 and covers the end sidewalls of the channel elements 208. After the deposition of the dielectric material layer, an etching process is carried out to selectively etch the dielectric material layer, forming the dummy layers 224 that are nested with the channel elements 208.The layer of dielectric material can contain silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, high K-value dielectric materials (for example, aluminum oxide, hafnium oxide), other suitable materials, or combinations thereof, and can be deposited using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods. In one embodiment, the layer of dielectric material contains silicon oxide.

[0018] With reference to Fig. 1 and Fig. In Figure 7, the process 100 comprises a block 108 where structural elements 226 for internal spacers are formed. After the formation of the dummy layers 224, an etching process is carried out to selectively recess the dummy layers 224 to form recesses for internal spacers (which are now filled by structural elements 226 for internal spacers). The etching process selectively and partially recesses the dummy layers 224 to form recesses for internal spacers, while the exposed channel elements 208 are not etched to a significant extent. In an embodiment where the channel elements 208 consist substantially of silicon (Si) and the dummy layers 224 are formed of silicon oxide, the selective recession of the dummy layer 224 can be carried out using a selective wet etching process or a selective dry etching process. The extent to which the dummy layers 224 are left out is controlled by the duration of the etching process.In an alternative embodiment, the back-etching of the dielectric material layer and the selective and partial recession of the dummy layers 224 are performed by carrying out the same etching process. Internal spacer structural elements 226 are then formed in the internal spacer recesses. In an exemplary process, after the internal spacer recesses have been formed, an internal spacer material layer (not shown) is deposited over the structure 200, including within the internal spacer recesses. The deposited internal spacer material layer is then back-etched to remove excess material, thereby forming the internal spacer structural elements 226.The etching process in block 108 can be a dry etching process similar to the dry etching process used in the formation of the source / drain openings 220. The structural elements 226 for internal spacers follow the shapes of the corresponding recesses for internal spacers. The material layer for internal spacers can contain silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material.

[0019] With reference to Fig. 1 and Fig. In the present embodiment, the method 100 comprises a block 110 where source / drain structural elements are formed adjacent to the channel regions 205C. The source / drain structural elements are formed in and / or above source / drain regions 205SD and coupled to the channel layers 208 in the channel regions 205C. In the present embodiments, N-source / drain structural elements 220N are formed in the first device region 200A, and P-source / drain structural elements (not shown) are formed in the second device region 200B. Exemplary N-source / drain structural elements can contain silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon or another suitable material and can be doped in situ during the epitaxial process by incorporating an n-doping agent such as phosphorus, arsenic or antimony, or can be doped ex situ using a boundary layer implantation process.Exemplary p-source / drain structural elements can contain germanium, gallium-doped silicon germanium, boron-doped silicon germanium or another suitable material and can be doped in situ during the epitaxial process by incorporating a p-doping agent, such as boron or gallium, or can be doped ex situ using an interface implantation process.

[0020] With reference to Fig. In sections 1 and 9-10, the procedure 100 comprises a block 112 where the dummy gate structures 216 are selectively removed to form gate trenches 234. With reference to Fig. 9. After forming the source / drain structural elements, a contact etch stop layer (CESL) 230 and an interlayer dielectric layer (ILD) 232 are formed over the structure 200. The CESL 230 is designed to protect the various underlying components during subsequent manufacturing processes and may contain silicon nitride, silicon oxynitride, and / or other suitable materials. It can be formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. As described in Fig. As shown in Figure 9, the CESL 230 can be formed on the top surfaces of the source / drain structural elements (for example, the N-source / drain structural elements 228N) and on the side walls of the gate spacers 218. The ILD layer 232 is deposited over the structure 200 after the CESL 230 has been deposited by a CVD process, a PECVD process, or another suitable deposition technique. The ILD layer 232 can contain silicon oxide, a low K-value dielectric material, tetraethyl orthosilicate (TEOS), doped silicon oxide (for example, BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or combinations thereof. One or more chemical-mechanical planarization (CMP) processes can be performed to planarize the top surface of structure 200 in order to expose the dummy gate electrode of dummy gate structures 216. With reference to Fig. 10. The dummy gate structures 216 are selectively removed to form gate trenches 234 over the channel regions 205C. The dummy gate structures 216 are selectively removed by an etching process. The etching process for removing the dummy gate structures 216 can include any suitable process, such as a dry etching process, a wet etching process, or combinations thereof, and is designed to selectively remove the dummy gate structures 216.

[0021] With reference to Fig. In sections 1 and 10-11, the procedure 100 includes a block 114 where the dummy layers 224 are selectively removed to form gate openings 236. Fig. Figure 11 shows a cross-sectional view of structure 200 along the in Fig. 2 and Fig. Line B-B' shown in Figure 10. After the removal of the dummy gate structures 216, the dummy layers 224 are selectively removed to form gate openings 236. The selective removal of the dummy layers 224 can be implemented by selective dry etching, selective wet etching, or another selective etching process. An exemplary selective wet etching process may involve the use of dilute hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). An exemplary selective dry etching process may involve the use of anhydrous hydrogen fluoride vapor (HF vapor), trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or a combination thereof. In some embodiments, the selective wet etching includes an APM etching (for example, an ammonia hydroxide-hydrogen peroxide-water mixture).

[0022] With reference to Fig. 1 and Fig. In section 12, the method 100 comprises a block 116 where a gate dielectric layer 238 is formed over the structure 200. In some embodiments, the gate dielectric layer 238 is a multilayer structure comprising an interface layer 238a and a high k-value dielectric layer 238b over the interface layer 238a. In some other implementations, the interface layer 238a can be formed by thermal oxidation and may contain silicon oxide. That is, the interface layer 238a is formed only along exposed surfaces of the semiconductor structure elements (for example, the upper portion of the substrate 202 and the channel elements 208). In some embodiments, the interface layer 238a can be conformally deposited over the substrate 202, including in the gate grooves 234 and the gate openings 236, and on the STI structure element 204.The high-k dielectric layer 238b is then conformally deposited over the structure 200 by performing a deposition process (for example, CVD, ALD) such that it has a generally uniform thickness over the top of the structure 200 to partially fill the gate grooves 234 and the gate openings 236. The term "conformally" can be used in this text for the simpler description of a layer with substantially uniform thickness over different regions. The high-k dielectric layer 238b can incorporate dielectric materials with a high dielectric constant, for example, greater than that of silicon dioxide. Exemplary high-k dielectric materials include hafnium, zirconium, tantalum, titanium, oxygen, nitrogen, other suitable constituents, or combinations thereof.In some implementations, the high k-value dielectric layer 238b may contain a high k-value dielectric material, for example HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, TiO2, Ta2O5, other suitable high k-value dielectric material, or combinations thereof.

[0023] In order to effectively adjust the work function of the gate stack of the P-transistor without significantly influencing other physical or electrical properties (for example, gate resistance Rg, channel resistance Rch) of the gate stack, no single P-work function layer with a thickness T (in Fig. (as shown in Figure 14), but instead, the gate stack of the P-transistor comprises a multilayer P-outflow structure 241 with thickness T. For example, in one embodiment, the multilayer P-outflow structure 241 has a first P-outflow layer 240 and a second P-outflow layer 242 above the first P-outflow layer 240. The second P-outflow layer 242 can be a single-layer outflow layer (with reference to Figure 14). Fig. 14 described) or can have two sublayers (referring to Fig. 17 described).

[0024] In the present embodiments, two different mechanisms can be implemented to increase the threshold voltage tuning range of a P-transistor without changing the overall thickness T of its P-work function structure 241. A first of the two mechanisms involves incorporating dopants of a first type into the first P-work function layer and / or the second P-work function layer 242. The dopants of the first type can reduce or prevent the diffusion of aluminum from an aluminum-containing N-work function layer above the second P-work function layer 242 into the first and / or the second P-work function layers 240 and 242. A reduced degree of aluminum diffusion can lead to an increased work function for the gate stack of the P-transistor and thus achieve a lower threshold voltage for the P-transistor.The dopants of the first type can include tungsten, oxygen, fluorine, or other suitable compositions. The dopants of the first type can be incorporated by an atomic layer deposition process, plasma doping, controlling parameters during the deposition of the first and / or the second phosphorus exit work layer 240 and 242, or other suitable processes. An example of forming the phosphorus exit work layer containing dopants of the first type is given below with reference to [reference missing]. Fig. 16 described in detail.

[0025] A second of the two mechanisms involves the incorporation of second-type dopants into the first P-type output layer 240. The intrinsic output positions of the second-type dopants can be lower than the intrinsic output position of the material of the first P-type output layer 240. Thus, incorporating the second-type dopants into the first P-type output layer 240 can reduce the output position for the first P-type output layer 240, resulting in an increased threshold voltage for the P-type transistor. The second-type dopants can include silicon, aluminum, tantalum, or other suitable compositions. An example of forming the P-type output layer containing second-type dopants is given below with reference to Fig. 16 described in detail.

[0026] With reference to Fig. In sections 1 and 13-15, the process 100 includes a block 118 where a first P exit work layer 240 is deposited above the structure 200. Fig. Figure 14 shows an enlarged section of structure 200. Fig. Figure 15 shows a simplified diagram illustrating an exemplary cycle of an atomic layer deposition (ALD) process 300 for forming the first work function layer 240 of the P work function structure 241.

[0027] With reference to Fig. 13, Fig. 14 and Fig. In embodiment 15, the first P-exit layer 240 is conformally deposited over the substrate 202, including on the high k-value dielectric layer 238b located above the channel layers 208. The first P-exit layer 240 can be deposited using ALD, CVD, PVD, or other suitable processes. The first P-exit layer 240 contains a P-exit material for P-transistors, such as TiN, TaN, TiSiN, TaSiN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, other P-exit materials, or combinations thereof. In some embodiments, the first P-exit layer 240 completely fills any remaining portion of the gate openings 236 between the adjacent channel layers 208. In this illustrated embodiment, the first P-exit working layer 240 does not completely fill a remaining section of the gate openings 236 between the adjacent channel layers 208.In some embodiments, the first P exit working layer 240 has a thickness T1 of about 6 Å to about 18 Å.

[0028] A through Fig. The ALD process 300 shown in Figure 15 can be implemented to form the first P-exit working layer 240. In an initial process, the Fig. The structure 200 shown in Figure 12 is loaded into a process chamber, where the process chamber is prepared for the ALD process 300 to form an exit working layer, such as the first P exit working layer 240, above the gate dielectric layer 238 and the substrate 202. After loading into the process chamber, the structure 200 is brought into contact with a metal-containing precursor (which can be referred to as a pulse process 310 or a metal-containing pulse process 310). Then, a rinsing process 320 is performed to remove any remaining metal-containing precursor and any byproducts from the process chamber. The structure 200 is then brought into contact with a non-metal-containing precursor (which can be referred to as a non-metal-containing pulse process 330 or a pulse process 330).A rinsing process 340 is then performed to remove any remaining non-metallic precursor and byproducts from the process chamber. The pulsed process 310, the rinsing process 320, the pulsed process 330, and the rinsing process 340 constitute a single ALD cycle, comprising two deposition phases (processes 310 and 330) and two rinsing phases (processes 320 and 340). Each ALD cycle is a self-limiting process, with less than or equal to approximately a single monolayer being deposited during each cycle. The ALD cycle is repeated until the first phosphorus exit layer 240 reaches a desired (target) thickness T1.In embodiments where the first P exit layer contains titanium nitride 240, the metal-containing precursor may contain titanium tetrachloride (TiCl4), tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or other suitable materials, and the non-metal-containing precursor may contain NH3, nitrogen, N2H4, or other suitable materials. In one embodiment, the metal-containing precursor contains TiCl4, and the non-metal-containing precursor contains NH3. A carrier gas may be used to direct the precursors into the process chamber. In some embodiments, the carrier gas may be an inert gas, such as an argon-containing gas, a helium-containing gas, another suitable inert gas, or a combination thereof.In some embodiments, each of the first purge process 320 and the second purge process 340 implements an inert gas, such as an argon-containing gas, a helium-containing gas, another suitable inert gas, or combinations thereof.

[0029] We now turn to the Fig. 1, Fig. 13, Fig. 14 and Fig. 16. The process 100 comprises a block 120 where a second P-exit work layer 242 is deposited above the first P-exit work layer 240. Fig. Figure 14 shows the enlarged section of structure 200. Fig. Figure 16 shows a simplified diagram illustrating an exemplary cycle of an atomic layer deposition (ALD) process 350 for forming the second phosphorus exitwork layer 242 of the phosphorus exitwork structure 241. After forming the first phosphorus exitwork layer 240, the second phosphorus exitwork layer 242 is conformally deposited over the substrate 202, including on top of the first phosphorus exitwork layer 240. The second phosphorus exitwork layer 242 can be deposited using ALD, CVD, PVD, or other suitable processes. In the illustrated embodiment, the second phosphorus exitwork layer 242 completely fills a remaining portion of the gate openings 236 between the adjacent channel layers 208. In some other embodiments, the second P-exit working layer 242 does not completely fill a remaining section of the gate openings 236 between the adjacent channel layers 208.The second P-exit layer 242 contains a P-exit metal for P-transistors, such as doped TiN (e.g., TiWN, TiSiN), other P-exit materials (e.g., doped TaN or other doped P-exit materials), or combinations thereof. In some embodiments, the second P-exit layer 242 has a thickness T2 of about 7 Å to about 19 Å.

[0030] According to the first mechanism described above, dopants of the first type (for example, tungsten, oxygen, fluorine) can be incorporated into the first P-exit layer 240 and / or the second P-exit layer 242 to reduce or prevent the diffusion of aluminum from the aluminum-containing N-exit layer into the first and / or the second P-exit layer 240 and 242, in order to achieve a lower threshold voltage for the P-transistor. In a Fig. In the example illustrated in Figure 14A, tungsten (W) is incorporated into the second P exit work layer 242. For example, the second P exit work layer 242 contains tungsten-doped titanium nitride (titanium-tungsten nitride (TiWN)).

[0031] A through Fig. The ALD process 350, shown in Figure 16, is implemented to form the second P exit work layer 242 based on TiWN. The ALD process 350 comprises a first half-cycle 350A for forming one or more monolayers of tungsten nitride (WN), followed by a second half-cycle 350B for forming one or more monolayers of titanium nitride (TiN). Thus, upon completion of the ALD process 350, the second P exit work layer 242 has a laminated structure comprising one or more alternating monolayers of WN and one or more monolayers of TiN. The interdiffusion of elements from the monolayers forms the second P exit work layer 242, which contains tungsten-doped titanium nitride (titanium-tungsten nitride (TiWN)).

[0032] In an initial process, after the formation of the first P-exit working layer 240, the structure 200 is loaded into a process chamber, where the process chamber is prepared for the ALD process 350 to form the second P-exit working layer 242 above the first P-exit working layer 240 and the substrate 202.

[0033] After loading into the process chamber, the structure 200 is brought into contact with a first metal-containing precursor (which can be referred to as a pulse process 360 or a metal-containing pulse process 360). A rinsing process 365 is then performed to remove any remaining first metal-containing precursor and any byproducts from the process chamber. The structure 200 is then brought into contact with a first non-metal-containing precursor (which can be referred to as a non-metal-containing pulse process 370 or a pulse process 370). A rinsing process 375 is then performed to remove any remaining first non-metal-containing precursor and any byproducts from the process chamber. The pulse process 360, the rinsing process 365, the pulse process 370, and the rinsing process 375 constitute the first half-cycle 350A of an ALD cycle of the ALD process 350.Each first half-cycle 350A of the ALD cycle is a self-limiting process, during which less than or equal to approximately a single monolayer is deposited. The first half-cycle 350A is repeated until the tungsten nitride (WN) monolayers reach a desired (target) thickness. For example, within one cycle of the ALD process 350, the first half-cycle 350A can be performed a number A of times before proceeding to the second half-cycle 350B, where A is a positive integer. That is, one cycle of the ALD process 350 can include multiple iterations of the first half-cycle 350A.

[0034] After completing the first half-cycle 350A, the ALD process 350 cycle progresses to the second half-cycle 350B. The structure 200, which has the tungsten nitride (WN) monolayers, is brought into contact with a second metal-containing precursor (which can be referred to as a second metal-containing pulse process 380 or a pulse process 380). A rinsing process 385 is then performed to remove any remaining second metal-containing precursor and any byproducts from the process chamber. The structure 200 is then brought into contact with a second non-metal-containing precursor (which can be referred to as a second non-metal-containing pulse process 390 or a pulse process 390). A rinsing process 395 is then performed to remove any remaining second non-metal-containing precursor and any byproducts from the process chamber.The second metal-containing pulse process 380, the rinsing process 385, the second non-metal-containing pulse process 390, and the rinsing process 395 constitute the second half-cycle 350B of an ALD cycle of the ALD process 350. Every second half-cycle 350B of the ALD cycle is a self-limiting process, whereby less than or equal to approximately a single monolayer is deposited during each second half-cycle 350B. The second half-cycle 350B is repeated until the titanium nitride (TiN) monolayers reach a desired (target) thickness. For example, the second half-cycle 350B can be performed a number B of times before proceeding to the next cycle of the ALD process 350, where B is a positive integer. The entire cycle (including the first half-cycle 350A and the second half-cycle 350B) of the ALD process 350 can be repeated several times until the second P exit working layer 242 reaches the desired (target) thickness T2.In some embodiments, a carrier gas is used to guide the precursors into the process chamber. In some embodiments, the carrier gas is an inert gas, such as an argon-containing gas, a helium-containing gas, another suitable inert gas, or combinations thereof. In some embodiments, each of the purging processes 365, 375, 385, 395 implements an inert gas, such as an argon-containing gas, a helium-containing gas, another suitable inert gas, or combinations thereof.

[0035] In embodiments where the second P exit layer contains titanium tungsten nitride 242, the first metal-containing precursor may contain tungsten hexafluoride (WF6), tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), tungsten carbonyl (for example, W(CO)6), tris(3-hexyn)tungsten carbonyl (W(CO)(CH3CH2C ≡ CCH2CH3)3), bis(tert-butylimino)bis(dimethylamino)tungsten(VI) (((CH3)3CN)2W(N(CH3)2)2), or other suitable tungsten-containing precursors. The second metal-containing precursor may contain titanium tetrachloride (TiCl4), tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or other suitable titanium-containing precursors. The non-metal-containing precursor may contain NH3, nitrogen, N2H4, or other suitable materials.In this present embodiment, both the first half-cycle 350A and the second half-cycle 350B use the same non-metallic precursor, whereas in some other embodiments, the first half-cycle 350A and the second half-cycle 350B may implement different non-metallic precursors. In one embodiment, the atomic percentage of tungsten in the second P exit layer 242, based on TiWN, is in a range between about 5% and about 27%.If the atomic percentage of tungsten in the second P-exit work layer 242 on the TiWN base is less than 5%, the work function of the gate stack 260, and thus the resulting threshold voltage, may not be effectively tuned; and if the atomic percentage of tungsten in the second P-exit work layer 242 on the TiWN base is greater than 27%, the adhesion between the second P-exit work layer 242 and the photoresist formed on the second P-exit work layer 242 on the TiWN base in a subsequent structuring process may not be sufficient, leading to an unsatisfactory structuring result. In one embodiment, a ratio of the number B to the number A is in the range between approximately 3 and 10 to obtain a satisfactory tungsten concentration.This means that one cycle of the ALD process 350 can comprise performing the first half-cycle 350A once and performing the second half-cycle 350B 3 to 10 times. In this illustrated embodiment, the first half-cycle 350A is performed before the second half-cycle 350B. In some alternative embodiments, the second half-cycle 350B is performed before the first half-cycle 350A. Additional steps can be provided before, during, and after the ALD process 350, and some of the described steps can be shifted, replaced, or omitted to obtain additional embodiments of the ALD process 350.

[0036] Various parameters of the ALD 350 process can be adjusted to achieve desired growth characteristics, such as the flow rate of a deposition gas (including titanium-containing precursor gas, tungsten-containing precursor gas, nitrogen-containing precursor gas and / or a carrier gas), the concentration (or dosage) of the titanium-containing precursor gas, the concentration (or dosage) of the tungsten-containing precursor gas, the concentration (or dosage) of the nitrogen-containing precursor gas, the concentration (or dosage) of the carrier gas, the ratio of the concentration of the titanium-containing precursor gas to the concentration of the tungsten-containing precursor gas, and the ratio of the concentration of the metal-containing precursor gas to the concentration of the non-metal-containing precursor gas.a power of a high-frequency (HF) source (used, for example, to generate a plasma during the deposition process), a bias voltage (applied, for example, to excite the plasma during the deposition process), a process chamber pressure, a deposition process duration, other suitable deposition parameters, or combinations thereof. In some embodiments, the ratio of the duration of the second pulse process 370 to the duration of the first pulse process 360 is less than 2.5. In one embodiment, the duration of the first pulse process 360 in the first half-cycle 350A is between approximately 0.5 seconds and 10 seconds. In some embodiments, the temperature maintained in the process chamber during the second metal-containing pulse process 380 is between approximately 300 °C and approximately 400 °C. In some embodiments, each cycle of the ALD 350 has the same ratio of the number B to the number A.and the concentration of tungsten in the second P exit working layer 242 is uniform across the second P exit working layer 242. In some other embodiments, one or more cycles of the ALD process 350 have different ratios of the number B to the number A, and the concentration of tungsten in the second P exit working layer 242 is uneven across the second P exit working layer 242. For example, with reference to , Fig. 14A, the concentration of tungsten in the second P exit working layer 242 has a graded profile that gradually decreases from bottom to top, or can have a stepped profile that decreases from bottom to top. As described above, the concentration of tungsten in the second P exit working layer 242 is in a range between about 5% and about 27%. In one embodiment, a bottom surface of the second P exit working layer 242 has a tungsten concentration of about 27%, and a top surface of the second P exit working layer 242 has a tungsten concentration of about 5%.

[0037] In the above embodiments, tungsten is incorporated as a dopant into the titanium nitride-containing P-work function structure 241. In another embodiment, which is described by Fig. As shown in Figure 14B, oxygen can be incorporated as a dopant into the titanium nitride-containing phosphorus work function structure 241. The oxygen-containing dopant can be incorporated into the first phosphorus work function layer 240 and / or the second phosphorus work function layer 242 by performing oxygen plasma dopant. For example, after incorporation of oxygen as a dopant, both the first phosphorus work function layer 240 and the second phosphorus work function layer 242 can contain oxygen-containing titanium nitride. In some other embodiments, the titanium nitride-based first phosphorus work function layer 240 and / or the second phosphorus work function layer 242 can be subjected to a firing process to increase their respective oxygen concentrations.In some other embodiments, the first P exit working layer 240 contains titanium nitride formed by the ALD process 300, and a temperature maintained in a corresponding process chamber during the first pulse process 310 is about 300 °C to about 400 °C; the second P exit working layer 242 contains titanium nitride formed by the ALD process 300, and a temperature maintained in a corresponding process chamber during the first pulse process 310 is about 300 °C to about 400 °C.For embodiments in which the first P-exit work layer 240 and the second P-exit work layer 242 contain titanium nitride formed by the ALD process 300, and the temperature maintained in a corresponding process chamber during the first pulse process 310 is approximately 300 °C to approximately 400 °C, the oxygen concentration of the titanium nitride-based first P-exit work layer 240 and second P-exit work layer 242 is in a range between approximately 15% and approximately 50%.If the temperature is less than approximately 300 °C, the oxygen concentration of the first phosphorus exit layer 240 and the second phosphorus exit layer 242 may be too high, leading to an increased gate resistance Rg; and if the temperature is higher than approximately 400 °C, the titanium-containing precursor (TiCl4) may be completely consumed, and as a result, the oxygen concentration of the first phosphorus exit layer 240 and the second phosphorus exit layer 242 may be too low to affect the work function of the titanium nitride. In one embodiment, the temperature associated with the ALD process 300 for forming the second phosphorus exit layer 242 may be different (for example, lower) than the temperature associated with the ALD process 300 for forming the first phosphorus exit layer 240.As a result, the first P-exit working layer 240 and the second P-exit working layer can have different oxygen concentrations. For example, in one embodiment, the oxygen concentration in the second P-exit working layer 242 is higher than the oxygen concentration in the first P-exit working layer 240.

[0038] The above embodiments include various combinations of different compositions of the first P-exit working layer 240 and the second P-exit working layer 242. For example, in one embodiment, which is characterized by Fig. Figure 14A shows the first P-exit working layer 240 as oxygen-containing titanium nitride, which is formed at a temperature in a range between about 300 °C and about 400 °C, and a second P-exit working layer 242 as titanium tungsten nitride (TiWN) or tungsten-containing titanium nitride. In another embodiment, which is described by Fig. As shown in Figure 14B, the first P exit working layer 240 contains oxygenated titanium nitride, which is formed at a first temperature in a range between about 300 °C and about 400 °C, and a second P exit working layer 242 contains oxygenated titanium nitride, which is formed at a second temperature in a range between about 300 °C and about 400 °C, wherein the first temperature may be different from the second temperature (for example, lower or higher) or equal to the second temperature, and the oxygen concentration in the second P exit working layer 242 may be higher than, equal to, or lower than the oxygen concentration in the first P exit working layer 240.

[0039] In the above embodiments, which refer to Fig. As described in Figures 14-16, the second P-exit working layer 242 is a single-layer exit working layer 242. In some alternative embodiments, the second P-exit working layer 242 can be a multi-layer exit working layer. With reference to Fig. 17 The second P exit working layer 242 has a first layer 242a and a second layer 242b above the first layer 242a. The first layer 242a and the second layer 242b are P exit working layers having different compositions. In one embodiment, the first P exit working layer 240 contains oxygenated titanium nitride, which is formed at the first temperature in a range between about 300 °C and about 400 °C, the first layer 242a contains tungsten nitride (WN), and the second layer 242b contains titanium tungsten nitride (TiWN). It should be noted that the second TiWN-based layer 242b is formed over the first WN-based layer 242a to provide excellent adhesion between the second P exit layer 242 and the photoresist layer formed in a subsequent process to achieve satisfactory structuring.The thickness T3 of the first layer 242a can be the same as, or different from (for example, greater or less than), the thickness T4 of the second layer 242b, and the combined thickness (that is, T3+T4) of the first layer 242a and the second layer 242b is equal to the thickness T2. In one embodiment, the ratio of thickness T3 to thickness T2 is 0.5. In another embodiment, the ratio of thickness T3 to thickness T2 is 2. In some embodiments, depending on the selection of tungsten-containing precursors, the first layer 242a can contain carbon-containing tungsten nitride (WN) (“WN:C” or “WCN”), and the second layer 242b can contain carbon-containing titanium tungsten nitride (TiWN).

[0040] The above descriptions provide examples of the first mechanism. An example of the second mechanism involves incorporating second-type dopants (for example, silicon, aluminum, tantalum) into the P-work function structure 241 to reduce the work function position for the P-work function structure 241. For example, with reference to Fig. 14C, according to the second mechanism, the first P-exit work layer 240 contains silicon-containing titanium nitride (for example, TiSiN) to reduce the exit work position for the P-exit work structure 241. The dopants of the second type (for example, silicon) can be incorporated in a similar manner to the dopants of the first type (for example, tungsten), with reference to Fig. The processes described in Section 16 can be incorporated. For example, to form a silicon-doped first phosphorus exit layer 240 on a TiN base (e.g., TiSiN), an ALD process similar to ALD process 350, comprising the first half-cycle 350A and the second half-cycle 350B, can be carried out. One of the differences between these two ALD processes may be that, instead of using a tungsten-containing metal precursor to incorporate the first-type dopants, a precursor containing a second-type dopant (e.g., a silicon-containing precursor) is implemented to incorporate the second-type dopants (e.g., silicon) for doping the first phosphorus exit layer 240 on a TiN base. The concentration of silicon in the silicon-doped first phosphorus exit layer 240 on a TiN base is less than approximately 20%.If the silicon concentration is greater than 20%, the gate resistance Rg of the resulting gate stack may be too high, adversely affecting the transistor's performance. The silicon concentration in the first P-work layer 240 can be affected in a manner similar to the tungsten concentration described above. Fig. 16, as described, can be uniform or non-uniform. In embodiments according to the second mechanism, the second P exit working layer 242, which is formed above the silicon-doped first TiN-based P exit working layer 240, can contain titanium nitride, which is formed at a third temperature above 400 °C, and has an oxygen concentration that is lower than that of the titanium- and nitrogen-containing P exit working layer (for example, the first P exit working layer 240 formed according to the first mechanism), which is formed at the first temperature in a range between about 300 °C and 400 °C. In some other embodiments, as described by Fig. As shown in Figure 14D, the dopants of the second type (for example, silicon, aluminum, tantalum) can be incorporated into the second P-work function 242 of the P-work function structure 241. For example, the first P-work function layer can contain titanium nitride, which is formed at the third temperature above 400 °C, and has an oxygen concentration that is lower than that of the titanium- and nitrogen-containing P-work function layer (for example, the P-work function layer 240, which is formed according to the first mechanism), which is formed at the first temperature in a range between about 300 °C and 400 °C; the second P-work function 242 can contain silicon-containing titanium nitride (for example, TiSiN) and can be formed by the ALD process, which is described with reference to Fig. 14C is described.

[0041] In some embodiments, the structure 200 includes a first P-transistor which provides a threshold V T0The structure 200 has a first P-type work layer comprising titanium nitride formed at a temperature above 400 °C, and a second P-type work layer above the first P-type work layer comprising titanium nitride formed at a temperature above 400 °C. The structure 200 also includes a second P-type transistor comprising a threshold V T1 has and the P-exit work structure 241 (for example, an oxygen-containing first P-exit work layer 240 based on TiN and a second P-exit work layer 242 based on TiWN) which is formed according to the first mechanism described above with reference to Fig. The structure 200 also includes a third P-transistor having a threshold voltage VT2 and a P-discharge structure (for example, a first P-discharge layer 240 based on TiSiN and a second P-discharge layer 242 based on TiN) formed according to the second mechanism. The gate stack arrangements of the three P-transistors are essentially the same, except for the different arrangements of the P-discharge structure. Compared to the first P-transistor, different threshold voltages can be achieved by incorporating dopants into the P-discharge structure without changing the thickness of the P-discharge structure. In one embodiment, the threshold voltage V T1 smaller than the threshold voltage V T0 , and the threshold voltage V T2 is greater than the threshold voltage V T0Therefore, the threshold voltage tuning range of the P-transistor can be advantageously increased to meet different design requirements.

[0042] With reference to Fig. 1 and Fig. In section 18, method 100 comprises a block 122 where the P-exit work structure 241 is patterned, thereby removing the section of the P-exit work structure 241 in the first apparatus region 200A. After forming the P-exit work structure 241, the P-exit work structure 241 is patterned. The operations in block 122 can employ a lithography process that includes forming a resist layer (or photoresist layer) over the P-exit work structure 241 by spin coating, performing a pre-exposure firing process, performing an exposure process, performing a post-exposure firing process, and developing the exposed resist layer in a developer solution. After development, the resist layer becomes a resist structure.During the use of the resist structure as an etching mask, an etching process is carried out to remove the section of the P exit work structure 241 that is formed in the first device region 200A.

[0043] With reference to Fig. 1 and Fig. In Figure 19, Method 100 comprises a block 124 where an N-exit work layer 246 is formed over the structure 200. After structuring the P-exit work structure 241, an N-exit work layer 246 is deposited over the gate dielectric layer 238 using suitable processes, such as atomic layer deposition (ALD). In one embodiment, the N-exit work layer 246 is conformally deposited over the structure 200 such that it has a generally uniform thickness over the top of the structure 200 in order to partially fill the gate grooves 234 in the first device region 200A and the gate openings 236 in the first device region 200A. In some embodiments, the N-work function layer 246 can contain a metal with a sufficiently low effective work function such as Ti, Al, TaC, TaCN, TaSiN or combinations thereof.For example, the N-outlet work layer 246 can have an aluminum-containing N-outlet work layer formed from titanium-aluminum (TiAl), titanium-aluminum carbide (TiAlC), tantalum-aluminum (TaAl), or titanium-aluminum nitride (TiAlN), or other suitable materials. In some other embodiments, the aluminum-containing N-outlet work layer 246 (for example, TiAlC) can be formed by an ALD process similar to the ALD process 350 by selecting suitable precursors (titanium-containing precursors, carbon-containing precursors, aluminum-containing precursors), and the aluminum concentration of the aluminum-containing N-outlet work layer 246 can be adjusted by adjusting its corresponding ratio of the number B to the number A, thereby adjusting the work function of the aluminum-containing N-outlet work layer 246 to obtain a larger threshold voltage tuning range for N-transistors.

[0044] With reference to Fig. In steps 1, 20 and 21A-21B, the process 100 includes a block 126 where one or more conductive layers are formed over the substrate 202 to complete the fabrication of functional gate stacks 255 and 260. Fig. Figure 21A shows an enlarged section of the gate stack 255 formed in the gate trench 234 in the first device region 200A, and Fig. Figure 21A shows an enlarged section of the gate stack 260 formed in the gate trench 234 in the second device region 200B. In some embodiments of the present disclosure, the one or more conductive layers comprise a first protective layer 248 and a second protective layer 250 conformally formed over the N exit working layer 246, and a metal electrode layer 252 formed over the second protective layer 250. In one embodiment, the first protective layer 248 contains titanium nitride, and the deposition thickness of the first protective layer 248 can be less than the thickness T1 of the first P exit working layer 240. In another embodiment, both the first protective layer 248 and the first P exit working layer 240 contain oxygenated titanium nitride, and the oxygen concentration of the first protective layer 248 is higher than the oxygen concentration of the first P exit working layer 240.The second protective layer 250 can contain silicon. The metal electrode layer 252 can contain a conductive material such as Al, W, and / or Cu and can be deposited using ALD, CVD, PVD, plating, or other suitable processes such that all remaining sections of the gate grooves 234 are filled. In various embodiments, a planarization process (for example, a chemical-mechanical polishing (CMP) process) can be performed to remove excess sections of the material above the ILD layer 232, thereby completing the structure of the gate stack 255 in the first device region 200A and the gate stack 260 in the second device region 200B.In this illustrated embodiment, the gate stack 255 formed in the gate trench 234 in the first device region 200A contains the metal electrode layer 252, and the gate stack 260 formed in the gate trench 234 in the second device region 200B does not contain the metal electrode layer 252.

[0045] In the above embodiments, the N-exit working layer 246 is formed in both the first device region 200A and the second device region 200B. In some alternative embodiments, as described by Fig. As shown in Figure 22, the section of the N-discharge work layer 246 formed in the second device region 200B is removed. In another alternative embodiment, sections of the first protective layer 248 and the second protective layer 250 formed in the second device region 200B can also be removed. The second mechanism described above (for example, incorporating dopants of the second type to reduce the work function) can be applied to lower the threshold voltage of the P-transistors formed in the Fig. The second device region 200B shown in Figure 22 is to be adjusted.

[0046] After the formation of the gate stacks 255 and 260, further processes are carried out. Such further processes can include the formation of a silicide layer (not shown) over the source / drain structural elements and a multilayer interconnect (MLI) structure (not shown) over the structure 200. The MLI structure can have various interconnect structural elements, for example, vias and conductive traces, source / drain contacts, and gate contacts, which are arranged in dielectric layers such as etch stop layers and ILD layers (such as ILD layer 232).In some embodiments, the vias are vertical interconnect structural elements configured to connect contacts at the device level, such as source / drain contacts formed over the source / drain structural elements and gate contacts (not shown) formed over the gate stacks 255 and 260.

[0047] Without intending any limitation, one or more embodiments of the present disclosure can realize many benefits for semiconductor devices and their construction. In some embodiments, the present disclosure provides methods for increasing the threshold voltage tuning range of P-transistors without adjusting the overall thickness of the P-exit layers.

[0048] The present disclosure provides many different embodiments. Semiconductor structures and methods for their fabrication are disclosed in this text. As an example, the present disclosure relates to a method.The process comprises: forming a dielectric layer over a section of a substrate, forming a first p-exit layer over the dielectric layer, wherein the first p-exit layer comprises titanium nitride, forming a second p-exit layer over the first p-exit layer, wherein the second p-exit layer comprises titanium nitride with dopants, forming an aluminum-containing N-exit layer over the second p-exit layer, wherein the dopants in the second p-exit layer reduce the aluminum diffusion from the aluminum-containing N-exit layer into the second p-exit layer, and forming a metal layer over the aluminum-containing N-exit layer.

[0049] In some embodiments, the atomic percentage of titanium in the second p-work layer is lower than the atomic percentage of titanium in the first p-work layer. In some embodiments, the work function of the second p-work layer is lower than the work function of the first p-work layer. In some embodiments, the dopants in the second p-work layer may contain oxygen, tungsten, or fluorine.In some embodiments, the dopants in the second p-exit work layer can contain tungsten, and the formation of the second p-exit work layer can involve performing an atomic layer deposition (ALD) process. One cycle of the ALD process comprises: performing a number of first loops to form first monolayers of titanium nitride, and after performing the number of first loops, performing a number of second loops to form second monolayers of tungsten nitride over the first monolayers. In some embodiments, the process can also include adjusting the ratio of the number of second loops to the number of first loops to control the concentration of tungsten in the second p-exit work layer.In some embodiments, precursors for forming the first titanium nitride monolayers may comprise ammonia and a titanium-containing precursor, and precursors for forming the second tungsten nitride monolayers may comprise ammonia and a tungsten-containing precursor. In some embodiments, the method may also comprise adjusting the ratio of an ammonia pulse duration to a tungsten-containing precursor pulse duration to adjust the concentration of tungsten in the second p-exit work layer. In some embodiments, the method may further comprise: prior to forming the second p-exit work layer, forming a third p-exit work layer above the first p-exit work layer, wherein the first p-exit work layer may contain titanium nitride, the second p-exit work layer may contain tungsten-containing titanium nitride, and the third p-exit work layer may contain tungsten nitride.In some embodiments, the first p-exit working layer may contain oxygenated titanium nitride.

[0050] In another exemplary aspect, the present disclosure relates to a process.The method comprises: receiving a structure comprising: multiple nanostructures above a substrate, and a source / drain structural element coupled to the multiple nanostructures; forming a gate dielectric layer above and around the nanostructures; and performing an atomic layer deposition process to form a p-work layer above the gate dielectric layer, wherein a cycle of the atomic layer deposition process may comprise a first half-cycle followed by a second half-cycle, and the first half-cycle may comprise the sequential pulsing of a first metal precursor and a first non-metal precursor in a chamber, and the second half-cycle may comprise the sequential pulsing of a second metal precursor and a second non-metal precursor in the chamber, wherein the first metal precursor and the second metal precursor contain different metal elements.

[0051] In some embodiments, the p-work layer may contain TiWN, the first metal precursor may contain titanium, and the second metal precursor may contain tungsten. In some embodiments, the first non-metal precursor and the second non-metal precursor have the same composition. In some embodiments, the second half-cycle of the atomic layer deposition process may include multiple repetitions of the sequential pulsing of the second metal precursor and the second non-metal precursor. In some embodiments, the process may further include: prior to performing the atomic layer deposition process, depositing an additional work layer on the gate dielectric layer, wherein the additional work layer and the second metal precursor contain the same metal element.In some embodiments, the method may also include: after performing the atomic layer deposition process, depositing an n exit work layer over the p exit work layer, and forming a metal layer over the n exit work layer.

[0052] In another exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises: a substrate, a gate dielectric layer over a section of the substrate, a first titanium- and nitrogen-containing exit layer over the gate dielectric layer, a second titanium- and nitrogen-containing exit layer on the first titanium- and nitrogen-containing exit layer, wherein the composition of the second titanium- and nitrogen-containing exit layer differs from the composition of the first titanium- and nitrogen-containing exit layer, and an aluminum-containing exit layer arranged over the second titanium- and nitrogen-containing exit layer, wherein the second titanium- and nitrogen-containing exit layer comprises an element configured toto reduce the aluminum diffusion from the aluminum-containing exit layer into the second titanium- and nitrogen-containing exit layer, and a conductive layer arranged above the aluminum-containing exit layer.

[0053] In some embodiments, the semiconductor device may also include: multiple nanostructures over the substrate, wherein the gate dielectric layer, the first titanium-nitrogen-containing exit layer, and the second titanium-nitrogen-containing exit layer are arranged over and around the multiple nanostructures. In some embodiments, the second titanium-nitrogen-containing exit layer contains oxygen, tungsten, or fluorine. In some embodiments, the second titanium-nitrogen-containing exit layer may contain TiWN.

[0054] The above has outlined features of various embodiments, enabling the person skilled in the art to better understand the following disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure. For example, different resistances for the conductors can be achieved by implementing different thicknesses for the bit line conductor and the word line conductor.However, other techniques can also be used to vary the resistance of the metal conductors. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 655,816

[0001]

Claims

[1] Procedure, encompassing: Forming a dielectric layer over a section of a substrate; Forming a first p-work function layer above the dielectric layer, wherein the first p-work function layer comprises titanium nitride; Forming a second p-exit work layer above the first p-exit work layer, wherein the second p-exit work layer comprises titanium nitride with dopants; Forming an aluminum-containing N-exit layer above the second p-exit layer, wherein the dopants in the second p-exit layer reduce the aluminum diffusion from the aluminum-containing N-exit layer into the second p-exit layer; and Formation of a metal layer above the aluminum-containing N exit working layer. [2] Method according to claim 1, wherein the atomic percentage of titanium in the second p-exit layer is lower than the atomic percentage of titanium in the first p-exit layer. [3] Method according to claim 1 or 2, wherein the output work of the second p-output work layer is less than the output work of the first p-output work layer. [4] Method according to any one of claims 1 to 3, wherein the dopants in the second p-work layer comprise oxygen, tungsten or fluorine. [5] Method according to claim 4, wherein the dopants in the second p-exit work layer comprise tungsten and the formation of the second p-exit work layer comprises carrying out an atomic layer deposition (ALD) process, and a cycle of the atomic layer deposition (ALD) process comprises: Performing a number of first loops to form first monolayers of titanium nitride; and After performing the number of first loops, perform a number of second loops to form second monolayers of tungsten nitride over the first monolayers. [6] Method according to claim 5, further comprising: adjusting a ratio of the number of second loops to the number of first loops to adjust a concentration of tungsten in the second p-exit work layer. [7] Method according to claim 5 or 6, wherein precursors for forming the first titanium nitride monolayers comprise ammonia and a titanium-containing precursor, and precursors for forming the second tungsten nitride monolayers comprise ammonia and a tungsten-containing precursor. [8] Method according to claim 7, further comprising: adjusting a ratio of a pulse duration of ammonia to a pulse duration of the tungsten-containing precursor in order to adjust a concentration of tungsten in the second p-exit work layer. [9] Method according to any one of claims 1 to 8, further comprising: Before the formation of the second p-exit work layer, formation of a third p-exit work layer above the first p-exit work layer, wherein the first p-exit work layer comprises titanium nitride, the second p-exit work layer comprises tungsten-containing titanium nitride, and the third p-exit work layer comprises tungsten nitride. [10] Method according to any one of claims 1 to 9, wherein the first p-exit work layer comprises oxygenated titanium nitride. [11] Procedure, encompassing: Receiving a structure, comprehensive: multiple nanostructures on a substrate, and a source / drain structural element coupled to the multiple nanostructures; Forming a gate dielectric layer over and around the nanostructures; and performing an atomic layer deposition process to form a p-work function layer over the gate dielectric layer, wherein a cycle of the atomic layer deposition process comprises a first half-cycle followed by a second half-cycle, and the first half-cycle comprises the sequential pulsing of a first metal precursor and a first non-metal precursor in a chamber, and the second half-cycle comprises the sequential pulsing of a second metal precursor and a second non-metal precursor in the chamber, wherein the first metal precursor and the second metal precursor contain different metal elements. [12] Method according to claim 11, wherein the p-exit work layer comprises TiWN, the first metal precursor comprises titanium, and the second metal precursor comprises tungsten. [13] Method according to claim 11 or 12, wherein the first non-metallic precursor and the second non-metallic precursor have the same composition. [14] Method according to any one of claims 11 to 13, wherein the second half-cycle of the atomic layer deposition process comprises the multiple repetition of the sequential pulsing of the second metal precursor and the second non-metal precursor. [15] Method according to any one of claims 11 to 14, further comprising: Prior to performing the atomic layer deposition process, a further exit work layer is deposited on the gate dielectric layer, wherein the further exit work layer and the second metal precursor contain the same metal element. [16] Method according to any one of claims 11 to 15, further comprising: After performing the atomic layer deposition process, an n-exit work layer is deposited over the p-exit work layer, and a metal layer is formed over the n-exit work layer. [17] Semiconductor device comprising: a substrate; a gate dielectric layer over a section of the substrate; a first titanium and nitrogen-containing exit layer above the gate dielectric layer; a second titanium- and nitrogen-containing exit layer on top of the first titanium- and nitrogen-containing exit layer, wherein the composition of the second titanium- and nitrogen-containing exit layer differs from the composition of the first titanium- and nitrogen-containing exit layer; an aluminum-containing exit working layer arranged above the second titanium- and nitrogen-containing exit working layer, the second titanium- and nitrogen-containing exit working layer comprising an element configured to reduce aluminum diffusion from the aluminum-containing exit working layer into the second titanium- and nitrogen-containing exit working layer; and a conductive layer that is arranged above the aluminium-containing exit working layer. [18] Semiconductor device according to claim 17, further comprising: multiple nanostructures above the substrate, wherein the gate dielectric layer, the first titanium and nitrogen-containing exit working layer and the second titanium and nitrogen-containing exit working layer are arranged over and around the multiple nanostructures. [19] Semiconductor device according to claim 17 or 18, wherein the second titanium and nitrogen-containing exit working layer comprises oxygen, tungsten or fluorine. [20] Semiconductor device according to claim 19, wherein the second titanium and nitrogen-containing exit working layer comprises TiWN.

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