STORAGE DEVICE AND STORAGE SYSTEM

Abstract

A storage device according to one embodiment comprises strings, bit lines, word lines, a source line, and a controller. Each of the strings contains memory cells. The word lines are each connected to the memory cells in each of the strings. The controller is configured to perform an initial read operation, which includes a first read sequence and a second read sequence. The controller is further configured to: in the first read sequence, increase the voltages of the word lines at the same rate and determine a correction value for each of a plurality of read voltages based on a timing such that a current quantity through the strings changes with an increase in the word line voltages; and in the second read sequence, perform a read operation using the read voltages to which the correction value is applied.

Description

AREA

[0001] The embodiments described here generally relate to a storage device and a storage system. BACKGROUND

[0002] A NAND flash memory that can store data non-volatilely is known. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram illustrating an example of the configuration of a storage system according to a first embodiment. Fig. Figure 2 is a block diagram illustrating an example of a hardware configuration of a memory controller included in the memory system according to the first embodiment. Fig. Figure 3 is a block diagram illustrating an example of a hardware configuration of a storage device included in the storage system according to the first embodiment. Fig. Figure 4 is a diagram illustrating an example of a circuit configuration of a memory cell array included in the storage device according to the first embodiment. Fig. Figure 5 is a diagram illustrating an example of a circuit configuration of a line decoder module included in the memory device according to the first embodiment. Fig. Figure 6 is a diagram illustrating an example of a configuration of a read amplifier module and a data register included in the storage device according to the first embodiment. Fig. Figure 7 is a diagram illustrating an example of a more detailed circuit configuration of the read amplifier module included in the storage device according to the first embodiment. Fig. Figure 8 is a diagram illustrating an example of the arrangement of the read amplifier module and the data register included in the storage device according to the first embodiment. Fig. Figure 9 is a diagram illustrating an example of a circuit configuration of a driver circuit and a detection circuit included in the storage device according to the first embodiment. Fig. Figure 10 is a diagram illustrating an example of the threshold voltage distribution of a memory cell transistor and the data allocation in the storage device according to the first embodiment. Fig. Figure 11 is a diagram illustrating an example of the combined threshold voltage distribution of NAND strings in the storage device according to the first embodiment. Fig. Figure 12 is a flowchart illustrating an example of a processing procedure for the read operation of the storage system according to the first embodiment. Fig. Figure 13 is a diagram illustrating an example of a voltage applied to the NAND strings at a specific time point during a normal read operation of the storage device according to the first embodiment. Fig. Figure 14 is a diagram illustrating an example of an operating waveform of the normal read operation of the storage device according to the first embodiment. Fig. Figure 15 is a flowchart illustrating an example of a processing procedure for a proofreading operation of the storage device according to the first embodiment. Fig. Figure 16 is a diagram illustrating an example of the variation of the combined threshold voltage distribution of NAND strings in the storage device according to the first embodiment. Fig. Figure 17 is a diagram illustrating an example of a voltage applied to the NAND strings at a specific time point during the correction read operation of the storage device according to the first embodiment. Fig. Figure 18 is a diagram illustrating an example of an operating waveform of the proofreading process of the storage device according to the first embodiment. Fig. Figure 19 is a diagram illustrating an example of a command sequence for the proofreading operation of the storage device according to the first embodiment. Fig. Figure 20 is a diagram illustrating an example of an operating waveform of an on-chip tracking process in a comparative example. Fig. Figure 21 is a diagram illustrating an example of an operating waveform of the proofreading process according to a first further embodiment of the first embodiment. Fig. Figure 22 is a diagram illustrating an example of an operating waveform of the proofreading process according to a second further embodiment of the first embodiment. Fig. Figure 23 is a diagram illustrating an example of an operating waveform of the proofreading process according to a third further embodiment of the first embodiment. Fig. Figure 24 is a diagram illustrating an example of the arrangement of bit lines selected at the time of acquisition of a combined threshold voltage distribution during a proofread operation of a storage device according to a second embodiment. Fig. Figure 25 is a diagram illustrating an example of an operating waveform of the proofreading process of the storage device according to the second embodiment. Fig. Figure 26 is a diagram illustrating an example of the state of a block in a memory cell array in a storage device according to a third embodiment. Fig. Figure 27 is a flowchart illustrating an example of a processing operation of a proofreading operation of a storage system according to the third embodiment. Fig. Figure 28 is a diagram illustrating an example of an operating waveform of the proofreading process of the storage device according to the third embodiment. Fig. Figure 29 is a diagram illustrating an example of a configuration of a block contained in a memory cell array contained in a storage device according to a fourth embodiment. Fig. Figure 30 is a diagram illustrating a first example of a block state that is a target of the proofreading operation of the storage system according to the fourth embodiment. Fig. Figure 31 is a diagram illustrating a second example of a block state that is a target of the proofreading operation of the storage system according to the fourth embodiment. Fig. Figure 32 is a diagram illustrating a third example of a block state that is a target of the proofreading operation of the storage system according to the fourth embodiment. Fig. Figure 33 is a diagram illustrating a fourth example of a block state that is a target of the proofreading operation of the storage system according to the fourth embodiment. Fig. Figure 34 is a diagram illustrating a fifth example of a block state that is a target of the proofreading operation of the storage system according to the fourth embodiment. Fig. Figure 35 is a diagram illustrating a first example of the operating waveform of the proofreading process and the method for using the read amplifier module of the storage system according to the fifth embodiment. Fig. Figure 36 is a diagram illustrating an example of a measurement target by three-point reading of the memory system according to the fifth embodiment. Fig. Figure 37 is a diagram illustrating a second example of the operating waveform of the proofreading process and the method for using the read amplifier module of the storage system according to the fifth embodiment. Fig. Figure 38 is a diagram illustrating an example of an operating waveform of the proofreading process according to a further embodiment of the fifth embodiment. Fig. Figure 39 is a block diagram illustrating an example of a hardware configuration of a storage device in a storage system according to a sixth embodiment. Fig. Figure 40 is a diagram illustrating an example of a circuit configuration of a read amplifier module and a capture circuit in the storage device according to the sixth embodiment. Fig. Figure 41 is a flowchart illustrating an example of a processing procedure for a proofreading operation of the storage device according to the sixth embodiment. Fig. Figure 42 is a diagram illustrating an example of an operating waveform of the proofreading process of the storage device according to the sixth embodiment. DETAILED DESCRIPTION

[0003] In general, a storage device according to one embodiment comprises a plurality of strings, a plurality of bit lines, a plurality of word lines, a source line, and a controller. Each string contains a plurality of memory cells connected in series. One end of each string is connected to a different bit line of the bit lines. The plurality of word lines are each connected to the memory cells in each of the strings. The other end of each string is connected to the source line. The controller is configured to perform an initial read operation with a first read sequence and a second read sequence.The controller is further configured to: in the first read sequence, increase the voltages of the word lines at the same rate and determine a correction value for each of a plurality of read voltages based on a timing in which a current magnitude through the strings changes with an increase in the voltages of the word lines; and in the second read sequence, perform a read operation using the read voltages to which the correction value is applied.

[0004] The following descriptions illustrate embodiments with reference to the drawings. These embodiments demonstrate devices and methods for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. Illustrations of the configuration are omitted where appropriate. Components with essentially the same functions and configurations are designated by the same reference numerals. Numbers and the like added to the reference numerals are also designated by the same reference numerals and serve to distinguish similar components. <1> First embodiment

[0005] The MS memory system according to the first embodiment determines a suitable shift value of the read voltage during read operation based on the combined threshold voltage distribution of a plurality of memory cell transistors MT connected in series in the NAND strings NS. In the first embodiment, the lower end of the combined threshold voltage distribution of the multiple memory cell transistors MT connected in series in the NAND strings NS is detected by measuring the change in the current flowing through a source line SL. Details of the MS memory system according to the first embodiment are described below. <1-1> Configuration

[0006] First, a configuration of the MS storage system according to the first embodiment is described. <1-1-1> Configuration of the MS storage system

[0007] Fig. Figure 1 is a block diagram showing an example of a configuration of the MS storage system according to the first embodiment. As shown in Fig. As illustrated in Figure 1, the storage system MS can be connected to an external host device HD (also referred to as the host). The host device HD is an electronic device, such as a personal computer, a personal digital assistant, or a server. The storage system MS is a storage device, such as a memory card or a solid-state drive (SSD). The storage system MS includes, for example, a storage controller 1 and at least one storage device 2.

[0008] Memory controller 1 is, for example, an integrated semiconductor circuit configured as a system-on-a-chip (SoC), application-specific integrated circuit (ASIC), or field-programmable gate array (FPGA). Memory controller 1 is responsible for managing and controlling storage device 2. Memory controller 1 is connected to host device HD via a host bus HB and to storage device 2 via a memory bus MB. Memory controller 1 can control storage device 2 based on a command received from host device HD. For example, memory controller 1 can control storage device 2 to perform read, write, erase, and similar operations.

[0009] Memory Device 2, for example, is a semiconductor memory device configured to store data non-volatilely. Memory Device 2 is, for example, a NAND flash memory. In NAND flash memory, a unit consisting of a data read operation and a data write operation is called a page. Memory Device 2 comprises a plurality of memory cell transistors MT, a plurality of bit lines BL, and a plurality of word lines WL. For example, each memory cell transistor MT is connected to one bit line BL and one word line WL. Each of the bit lines BL is assigned a column address. Each of the word lines WL is assigned a page address. <1-1-2> Hardware configuration of the memory controller 1

[0010] Fig. Figure 2 is a block diagram showing an example of a hardware configuration of the memory controller 1 in the MS storage system according to the first embodiment. As shown in Figure 2, the memory controller 1 includes, for example, a host interface (Host I / F) 10, a memory interface (Memory I / F) 11, a central processing unit (CPU) 12, an error correction code (ECC) circuit 13, a read-only memory (ROM) 14, a random access memory (RAM) 15, and a buffer memory 16. The host I / F 10, the memory I / F 11, the CPU 12, the ECC circuit 13, the ROM 14, the RAM 15, and the buffer memory 16 can be coupled via an internal bus.

[0011] The Host I / F 10 manages communication between the Host Device HD and the Storage Controller 1 according to an interface specification. The Host I / F 10 is connected to the Host Device HD via the Host Bus HB. The Host I / F 10 supports interface specifications such as Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), PCI Express (PCIe™), and Non-Volatile Memory Express™ (NVMe™).

[0012] The memory I / F 11 controls the communication between the memory controller 1 and the storage device 2 according to an interface specification. The memory I / F 11 is connected to the storage device 2 via the memory bus MB. The memory I / F 11 supports an interface specification such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0013] CPU 12 controls the overall operation of memory controller 1. CPU 12 instructs storage device 2 to perform a data write operation via memory I / F 11 in accordance with a write request received via host I / F 10. CPU 12 instructs storage device 2 to perform a data read operation via memory I / F 11 in accordance with a read request received via host I / F 10.

[0014] ECC circuit 13 is a circuit that performs ECC processing. ECC processing includes data encoding and decoding. ECC circuit 13 encodes data to be written to storage device 2 and decodes data to be read from storage device 2.

[0015] ROM 14 is a non-volatile memory. ROM 14 stores, for example, a program such as firmware. ROM 14 is, for example, an electrically erasable programmable read-only memory (EEPROM™). The CPU 12 performs various operations by executing the firmware or similar data stored in ROM 14.

[0016] RAM 15 is volatile memory. RAM 15 is used as the workspace of CPU 12. RAM 15 is, for example, static random access memory (SRAM) or dynamic random access memory (DRAM).

[0017] Buffer memory 16 is, for example, volatile memory. Buffer memory 16 temporarily stores data received via host I / F 10, data received via memory I / F 11, or similar information. Buffer memory 16 is, for example, DRAM or SRAM. Buffer memory 16 can be located on the outside of memory controller 1. <1-1-3> Hardware configuration of storage device 2

[0018] Fig. Figure 3 is a block diagram showing an example of a configuration of storage device 2 in the MS storage system according to the first embodiment. As shown in Fig. As shown in Figure 3, the storage device 2 comprises, for example, a memory cell array 20, an input / output circuit 21, a logic controller 22, a register circuit 23, a sequencer 24, a ready / occupied controller 25, a driver circuit 26, a line decoder module 27, a data register 28, a read amplifier module 29, and a detection circuit 30. Signals transmitted and received between the storage device 2 and the memory controller 1 via the memory bus MB include, for example, the input / output signals I / O0 to I / O7, the control signals CEn, CLE, ALE, WEn, REn, and WPn, as well as a ready / occupied signal RBn.

[0019] The memory cell array 20 is a set of memory cell transistors MT. The memory cell array 20 comprises a plurality of blocks BLKO to BLKn (where "n" is an integer of 1 or greater). The block BLK is a management unit for a memory area of ​​the memory device 2. The data erasure operation, for example, is performed in units of blocks BLK. Each of the blocks BLK is assigned a block address. The memory cell array 20 is equipped with a plurality of bit lines BL0 to BLm (where "m" is an integer of 1 or greater) and a plurality of word lines WL (not shown).

[0020] The input / output circuit 21 controls the transmission and reception (input / output) of the input / output signals I / O0 to I / O7. The input / output signal I / O can contain, for example, data (DAT), status information, an address, and a command. The input / output circuit 21 can input and output the data (DAT) between the data register 28 and the memory controller 1. The input / output circuit 21 can output the status information transmitted by the register circuit 23 to the memory controller 1. The input / output circuit 21 can output both the address and the command transmitted by the memory controller 1 to the register circuit 23.

[0021] Logic controller 22 controls each of the input / output circuits 21 and the sequencer 24 based on various control signals input by memory controller 1. Logic controller 22 enables memory device 2 based on the control signal CEn. Logic controller 22 informs input / output circuit 21 that the input / output signals (I / O) received from memory device 2 are the command and the address, respectively, based on the control signals CLE and ALE. Logic controller 22 instructs input / output circuit 21 to receive the input / output signal (I / O) based on the control signal WEn and instructs input / output circuit 21 to transmit the input / output signal (I / O) based on the control signal REn. Logic controller 22 puts memory device 2 into a protection state based on the control signal WPn.

[0022] The register circuit 23 can temporarily store a status, an address, an instruction, or similar information. The status information indicates the operating state of the storage device 2. This status information is updated based on the control of the sequencer 24 and transmitted to the memory controller 1 via the input / output circuit 21. The address can be a block address, a page address, a column address, and so on. The instructions comprise directions for various operations of the storage device 2.

[0023] Sequencer 24 controls the overall operation of storage device 2. Sequencer 24 can execute a read operation, a write operation, an erase operation, etc., based on the instruction and the address stored in register circuit 23. Furthermore, during a write operation, sequencer 24 can perform a correction read operation, in which a suitable shift value (correction value) of the read voltage is selected according to the state of the page to be read. Details of the correction read operation are described later.

[0024] The ready / occupied controller 25, under the control of the sequencer 24, can generate a ready / occupied signal RBn. The ready / occupied signal RBn informs the memory controller 1 whether the storage device 2 is in a ready state or an occupied state. The ready state is a state in which the storage device 2 can accept a command from the memory controller 1 and is indicated by the ready / occupied signal RBn at a high level. The occupied state is a state in which the storage device 2 cannot accept a command from the memory controller 1 and is indicated by the ready / occupied signal RBn at a low level.

[0025] The driver circuit 26 generates voltages for use in a read operation, a write operation, an erase operation, etc. Then the driver circuit 26 supplies the generated voltages to the memory cell array 20, the line decoder module 27, the read amplifier module 29, and the like.

[0026] The line decoder module 27 is a circuit for selecting block BLK and supplying voltage to connections such as the word line WL. Line decoder module 27 contains a number of line decoders RD0 to RDn. Line decoders RD0 to RDn are each connected to blocks BLKO to BLKn. Each line decoder RD can set the corresponding block BLK as selected or unselected based on the block address.

[0027] Data register 28 can temporarily store DAT data. For example, data register 28 can be used when DAT data is input and output between the input / output circuit 21 and the read amplifier module 29. Data register 28 can be referred to as a data latch, page register, or cache memory.

[0028] The read amplifier module 29 is a circuit for use in supplying a voltage to each bit line BL and for reading data. The read amplifier module 29 comprises a plurality of read amplifier units SAU0 to SAUm. The read amplifier units SAU0 to SAUm are each connected to a plurality of bit lines BL0 to BLm. Each of the read amplifier units SAU can determine the data read by the selected memory cell transistor MT based on the voltage of the associated bit line BL.

[0029] During the proofreading process, the detection circuit 30 recognizes the state of the page to be read based on a change in the current flowing in the memory cell array 20. The detection circuit 30 then outputs the detection result to the sequencer 24. Based on the detection result, the sequencer 24 can determine the shift value of the read voltage used in the proofreading process.

[0030] Note that in the storage device 2, a set consisting of the memory cell array 20, the line decoder module 27, and the read amplifier module 29 can be referred to as a stage. The stage includes at least the memory cell array 20. The storage device 2 can include a plurality of stages. The sequencer 24 can be configured to control each of the multiple stages. <1-1-4> Circuit configuration of memory cell array 20

[0031] Fig. Figure 4 is a diagram illustrating an example of a circuit configuration of the memory cell array 20 according to the first embodiment. Fig. 4 is one of the several BLK blocks illustrated that are contained in memory cell field 20. As in Fig. As illustrated in Figure 4, block BLK is connected to a plurality of bit lines BL0 to BLm, a plurality of word lines WL0 to WL(N-1) (where N is an integer of two or greater), selection gate lines SGDO to SGD4, one selection gate line SGS, and one source line SL. The selection gate lines SGDO to SGD4 and SGS, and the word lines WL0 to WL(N-1) (where N is an integer of two or greater), are provided for each block BLK. The bit lines BL0 to BLm are shared by a plurality of blocks BLK. The source line SL is shared by a plurality of blocks BLK.

[0032] Block BLK, for example, contains five string units SU0 to SU4. Each string unit SU contains a plurality of NAND strings NS. The multiple NAND strings NS are each connected to the bit lines BL0 to BLm. That is, each bit line BL is shared by the NAND string NS that is assigned the same column address among the plurality of blocks BLK. Each NAND string NS is coupled between its associated bit line BL and the source line SL.

[0033] Each NAND string NS comprises, for example, N memory cell transistors MT0 to MT (N-1) and selection transistors STD and STS. Each memory cell transistor MT is a memory cell with a control gate and a charge storage layer and stores data non-volatilely. The threshold voltage of the memory cell transistor MT can be changed depending on the amount of charge injected into the charge storage layer or similar factors. Each of the selection transistors STD and STS is used to select the block BLK and the string unit SU.

[0034] In each NAND string NS, the selector transistor STD, the memory cell transistors MT (N-1) to MT0, and the selector transistor STS are connected in series in that order. Specifically, the drain of selector transistor STD is connected to its corresponding bit line BL. The source of selector transistor STD is connected to the drain of memory cell transistor MT (N-1). Memory cell transistors MT0 to MT (N-1) are connected in series between selector transistors STD and STS. The drain of selector transistor STS is connected to the source of memory cell transistor MT0. The source of selector transistor STS is connected to the source line SL.

[0035] The select gate lines SGDO to SGD4 are each connected to the string units SU0 to SU4. Each select gate line SGD is coupled to the gate of each of the multiple select transistors STD contained in the associated string unit SU. The select gate line SGS is coupled to the gate of each of the multiple select transistors STS contained in the associated block BLK. The word lines WL0 to WL(N-1) are each connected to the control gates of the multiple memory cell transistors MT0 to MT(N-1) in the associated block BLK.

[0036] It should be noted that in memory cell array 20, the number of string units SU in each block BLK and the number of selection transistors STD and STS in each NAND string NS can be chosen arbitrarily. The selection gate line SGS can be provided for each string unit SU.

[0037] In this specification, a set of multiple memory cell transistors MT connected to the common word line WL in a string unit SU is referred to as a cell unit CU. Furthermore, a set of 1-bit data stored in each of the multiple memory cell transistors MT in the cell unit CU is referred to as page data. That is, the "page" is associated with a set of memory cell transistors MT connected to the common word line WL in the same block BLK. The cell unit CU can store two or more pages, depending on the number of data bits stored in each memory cell transistor MT. Thus, the memory controller 1 can manage the memory area of ​​the memory device 2 in units of cell units CU configured by a plurality of memory cell transistors MT, each of which can store a plurality of bit data. <1-1-5> Circuit configuration of the line decoder module 27

[0038] Fig. Figure 5 is a diagram illustrating an example of a circuit configuration of the line decoder module 27 according to the first embodiment. Fig. Figure 5 illustrates a connection relationship between the driver circuit 26 and the memory cell array 20 and the line decoder module 27, as well as a detailed circuit configuration of the line decoder RD0, which corresponds to block BLKO. The circuit configuration of the other line decoders RD is similar to that of line decoder RD0. Fig. Figure 5 illustrates a case where the number of word lines WL is eight.

[0039] As in Fig. As illustrated in Figure 5, each line decoder RD is coupled to the signal lines CG0 to CG7, SGDDO to SGDD4, SGSD, USGD, and USGS, which are connected to the driver circuit 26. Furthermore, each line decoder RD is connected to the word lines WL0 to WL7 of the associated block BLK and the select gate lines SGDO to SGD4 and SGS.

[0040] The line decoder RD0, for example, contains transistors TR0 to TR19, transfer gate lines TG and bTG, and a block decoder BD. Each of transistors TR0 to TR19 is a high-break-voltage n-channel MOS transistor. Transfer gate line TG is coupled to the gates of transistors TR0 to TR13. Transfer gate line bTG is coupled to the gates of transistors TR14 to TR19. The drains of transistors TR0 to TR13 are coupled to signal lines SGSD, CG0 to CG7, and SGDDO to SGDD4, respectively. Sources of transistors TR0 to TR13 are coupled to the select gate line SGS, word lines WL0 to WL7, and select gate lines SGDO to SGD4, respectively, of block BLKO. The drain and source of transistor TR14 are coupled to the signal line USGS and the select gate line SGS, respectively. The drains of transistors TR15 to TR19 are coupled to the signal line USGD.The sources of transistors TR15 to TR19 are coupled to the selection gate lines SGDO to SGD4.

[0041] The block decoder BD decodes the block address and applies a voltage to the transfer gate line TG based on the decoding result. For example, the block decoder BD applies either a high-level or a low-level voltage to the transfer gate line TG and applies the other voltage, i.e., either a high-level or a low-level voltage, to the transfer gate line bTG. Specifically, the block decoder BD of the selected block BLK applies a high-level voltage to the transfer gate line TG and a low-level voltage to the transfer gate line bTG. The block decoder BD of the unselected block BLK applies a low-level voltage to the transfer gate line TG and a high-level voltage to the transfer gate line bTG.As a result, the voltages of the signal lines CG0 to CG7 are applied to the word lines WL0 to WL7 of the selected block BLK, the voltages of the signal lines SGDDO to SGDD4 and SGSD are applied to the selection gate lines SGDO to SGD4 and SGS respectively of the selected block BLK, and the voltages of the signal lines USGD and USGS are applied to the selection gate lines SGD and SGS respectively of the unselected block BLK.

[0042] Note that the number of transistors TR in line decoder module 27 can be changed according to the number of connections of the individual blocks BLK. Since the signal line CG is shared by several blocks BLK, it can be called a global word line. Since the word line WL is provided for each block, it can be called a local word line. Since each of the signal lines SGDD and SGSD is shared by several blocks BLK, they can be called global transfer gate lines. Each of the select gate lines SGD and SGS is provided for each block and can therefore be called a local transfer gate line. <1-1-6> Configuration of the read amplifier module 29 and the data register 28

[0043] Fig. Figure 6 is a diagram showing an example of a configuration of the read amplifier module 29 and the data register 28 according to the first embodiment. As in Fig. As shown in Figure 6, each read amplifier unit SAU contained in the read amplifier module 29 includes, for example, a bit line interconnect section BLHU, a read amplifier section SA, buses DBUS and LBUS, latch circuits SDL, ADL, BDL and CDL, and a transistor T0. The data register 28 comprises a variety of latch circuits XDL0 to XDLm.

[0044] Each of the XDL latch circuits can temporarily hold (store) data. Latch circuits XDL0 to XDLm are each connected to the read amplifier units SAU0 to SAUm. Each XDL latch circuit is configured to send and receive data to and from its associated read amplifier unit SAU via the DBUS bus. Furthermore, each XDL latch circuit is used for DAT data input / output between the read amplifier module 29 and the input / output circuit 21. Each XDL latch circuit can be shared by multiple SAU read amplifier units.

[0045] The bitline interconnect section BLHU, for example, is a protection circuit that prevents a high voltage applied to the NAND string channel NS during the erase process from being applied to the read amplifier section SA. The bitline interconnect section BLHU can be configured to apply a predetermined voltage to the unselected bitlines BL.

[0046] The read amplifier section SA is a circuit used to determine data based on the voltage on the bit line BL and the application of a voltage to the bit line BL. Each read amplifier section SA is coupled to its corresponding bit line BL via the bit line connection section BLHU. When a control signal STB is present during a read operation, the read amplifier section SA determines, based on the voltage on the corresponding bit line BL, whether the data read from the selected memory cell transistor MT is "0" bit data or "1" bit data. The control signal STB is generated, for example, by sequencer 24.

[0047] Each of the latch circuits SDL, ADL, BDL, and CDL can temporarily hold (store) data. The latch circuits SDL, ADL, BDL, and CDL, along with the read amplifier section SA, are configured to send and receive data over the LBUS bus. During data write operation, the read amplifier unit SAU controls the bit line BL according to the data stored in the latch circuit SDL. The other latch circuits are used, for example, to temporarily store the data of each bit when each memory cell transistor MT stores data of two or more bits. Note that the number of latch circuits can be arbitrarily chosen. The number of latch circuits depends on the amount of data (number of bits) that can be stored, for example, in the memory cell transistor MT.

[0048] Transistor T0 controls the transmission of a signal between the associated DBUS and LBUS buses. In other words, transistor T0 acts as a bus switch, connecting the LBUS and DBUS buses. One end of transistor T0 in each read amplifier unit (SAU) is connected to the associated DBUS bus. The other end of transistor T0 in each read amplifier unit (SAU) is connected to the associated LBUS bus. The control signal DSW is input into the gate of transistor T0 in each read amplifier unit. The control signals STB and DSW are generated, for example, by sequencer 24. (1: More detailed circuit configuration of the reading amplifier module 29)

[0049] Fig. Figure 7 is a diagram showing an example of a more detailed circuit configuration of the read amplifier module 29, which is included in the storage device 2 according to the first embodiment. Fig. Figure 7 is an extracted configuration relating to one read amplifier unit (SAU) from the multitude of read amplifier units (SAU) contained in read amplifier module 29. In the following description, either the source or the drain of the transistor is referred to as "one end (of the current path)," and the other end of the source and drain is referred to as "the other end (of the current path)." The configuration assigned to one end and the other end (source or drain) can be different for each transistor.

[0050] As in Fig. As illustrated in Figure 7, the bit line terminal section BLHU, for example, contains transistor T1. The read amplifier section SA includes transistors T2 through T15, capacitors C1 and C2, and nodes SCOM, SSRC, SEN1, and SEN2. Transistor T1 is a high-breakdown-voltage n-channel MOS transistor. Each of transistors T2 through T5 and T7 through T15 is a low-breakdown-voltage n-channel MOS transistor. Transistor T6 is a low-breakdown-voltage p-channel MOS transistor.

[0051] One end of transistor T1 is coupled to the bit line BL. The other end of transistor T1 is coupled to one end of transistor T2. The control signal BLS is applied to the gate of transistor T1. The other end of transistor T2 is coupled to node SCOM. The control signal BLC is applied to the gate of transistor T2. Transistor T2 can clamp the voltage of the indirectly coupled bit line BL to a voltage corresponding to the control signal BLC. One end of transistor T3 is connected to node SCOM. The other end of transistor T3 is coupled to node SRCGND. For example, the ground voltage VSS is applied to node SRCGND. A control signal NLO is applied to the gate of transistor T3. Transistor T2 is used to charge or discharge the indirectly coupled bit line BL.

[0052] One end of transistor T4 is connected to node SCOM. The other end of transistor T4 is connected to node SSRC. The control signal BLX is applied to the gate of transistor T4. One end of each transistor T5 and T6 is connected to node SSRC. A voltage VHSA, for example, is applied to the other end of transistor T5. The voltage VHSA is, for example, a voltage based on the supply voltage VDD. The other end of transistor T6 is connected to node SRCGND. The gates of transistors T5 and T6 are connected to node INV_S. Node INV_S corresponds to a node used by the latch circuit SDL to hold data. Consequently, one of transistors T5 or T6 is turned on and the other is turned off according to the data held by the latch circuit SDL.

[0053] One end of transistor T7 is connected to node SCOM. The other end of transistor T7 is connected to node SEN1. A control signal XXL is applied to the gate of transistor T7. Transistor T7 is used to control a period during which the data of the memory cell transistor MT is acquired. One end of transistor T8 is connected to node SEN1. A voltage VHLB is applied to the other end of transistor T7. The voltage VHLB is, for example, a voltage based on the supply voltage VDD. The control signal SPC is applied to the gate of transistor T7. Transistor T8 can transmit the voltage VHLB applied to its other end and precharge node SEN1 by being switched on by the control signal SPC.

[0054] One end of transistor T9 is connected to node SEN1. The other end of transistor T9 is connected to node SEN2. The control signal S2S is applied to the gate of transistor T9. Transistor T9 can electrically disconnect nodes SEN1 and SEN2 by being switched off by the control signal S2S. Nodes SEN1 and SEN2 act as read nodes for acquiring data from the target memory cell transistor MT at the time of the read. One electrode of capacitive element C1 is connected to node SEN1. The other electrode of capacitive element C1 is connected to the bus LBUS. One electrode of capacitive element C2 is connected to node SEN2. A voltage VLOP is applied to the other electrode of capacitive element C2.

[0055] The gate of transistor T10 is connected to node SEN2. The voltage VLOP is applied to one end of transistor T10. The other end of transistor T10 is connected to one end of transistor T11. The other end of transistor T11 is connected to the bus LBUS. The control signal STB is applied to the gate of transistor T11. The gate of transistor T12 is connected to the bus LBUS. The voltage VLOP is applied to one end of transistor T12. The other end of transistor T12 is connected to one end of transistor T13. The other end of transistor T13 is connected to node SEN2. A control signal LSL is applied to the gate of transistor T13.

[0056] One end of transistor T14 is connected to node SEN2. The other end of transistor T14 is connected to the bus LBUS. The control signal BLQ is applied to the gate of transistor T14. Transistor T14 can transmit the data-based voltage between the bus LBUS and node SEN2 by being switched on by the control signal BLQ. One end of transistor T15 is connected to the bus LBUS. A voltage VDDLT is applied to the other end of transistor T15. The voltage VDDLT is, for example, lower than the voltage VHLB. The control signal LPC is applied to the gate of transistor T15. Transistor T15 can transmit the voltage VDDLT applied at the other end and preload the bus LBUS by being switched on by the control signal LPC.

[0057] During the read process, for example, the charges pre-charged at nodes SEN1 and SEN2 (the capacitance elements C1 and C2) are transferred to the bit line BL, depending on whether transistor MT of the target memory cell is in the on or off state. The data is read by querying the voltages of nodes SEN1 and SEN2 at that time. In the following description, a set of nodes SEN1 and SEN2 is also referred to as a read node SEN.

[0058] Note that each of the control signals BLS, BLC, NLO, BLX, XXL, SPC, S2S, STB, LSL, BLQ, and LPC, for example, is generated by the sequencer 24. The read amplifier module 29 may have a different circuit configuration than the one described above. The read amplifier unit SAU contains at least one read node. The read amplifier unit SAU may contain an operational circuit that is coupled to the bus LBUS and is capable of performing various logical operations (AND operation, OR operation, and the like) using data stored in an internal latch circuit. (2: Arrangement of read amplifier module 29 and data register 28)

[0059] Fig. Figure 8 is a diagram showing an example of the arrangement of the read amplifier module 29 and the data register 28 in the storage device 2 according to the first embodiment. Fig. Figure 8 shows an arrangement of a plurality of read amplifier units SAU contained in the read amplifier module 29 and an arrangement of a plurality of latch circuits XDL contained in the data register 28. In this description, the X direction corresponds to the direction of propagation of the word line WL and the Y direction to the direction of propagation of the bit line BL.

[0060] As in Fig. As illustrated in Figure 8, the read amplifier module 29, for example, provides a DBUS bus for eight read amplifier units SAU. The eight read amplifier units SAU, which are connected to the common DBUS bus, are arranged in the Y direction. Furthermore, several sets of the eight read amplifier units SAU, which are connected to the common DBUS bus, are arranged in the X direction. Note that the number of read amplifier units SAU connected to the common DBUS bus can be different. In the following description, the eight read amplifier units SAU connected to the common DBUS bus are referred to as SAU. <0> to SAU <7> They are designated to distinguish them from one another. Furthermore, a set of eight reading amplifier units (SAU) is used. <0> to SAU <7> , which are coupled to the common bus DBUS, are referred to as the reading amplifier unit SAU<7:0>.

[0061] A latch circuit <7:0>, connected to the read amplifier unit SAU<7:0>, is coupled to each DBUS bus. The eight latch circuits XDL <0> to XDL <7> are each equipped with the reading amplifier units SAU <0> to SAU <7> associated. That is, the number of read amplifier units SAU and the number of latch circuits XDL coupled to the common bus DBUS are designed to be equal. The read amplifier units SAU<7:0> and the latch circuit <7:0> coupled to the common bus DBUS are arranged in the Y direction. It should be noted that each latch circuit XDL is coupled to a multitude of data lines IO, which are connected to the input / output circuit 21. For example, data received by the input / output circuit 21 from the memory controller 1 can first be stored in the latch circuit XDL via the data line IO and then transmitted to the read amplifier unit SAU via the bus DBUS.The same applies to the reverse process.

[0062] In Fig. In section 8, an interval between two adjacent bit lines BL in the X direction is referred to as the "BL division." Furthermore, the width in the X direction of a region where the read amplifier unit SAU<7:0> is located is specified as the "SAU division." In other words, the SAU division corresponds to the width in the X direction of the region where a single read amplifier unit SAU is located. In this example, the width in the X direction of the region where the eight bit lines BL are arranged is essentially equal to the SAU division.

[0063] In the present specification, a group of several reading amplifier units SAU is described. <0> , which are arranged in the X direction, are referred to as "stage 1". A group of several reading amplifier units SAU <1> Those arranged in the X direction are referred to as "stage 2". A group of several reading amplifier units (SAU) <2> Those arranged in the X direction are referred to as "stage 3". A group of several reading amplifier units (SAU) <3> Those arranged in the X direction are referred to as "stage 4". A group of several reading amplifier units (SAU) <4> Those arranged in the X direction are referred to as "stage 5". A group of several reading amplifier units (SAU) <5> Those arranged in the X direction are referred to as "stage 6". A group of several reading amplifier units (SAU) <6> , which are arranged in the X direction, are referred to as "level 7".A group of several reading amplifier units SAU <7> The stages arranged in the X direction are referred to as "stage 8". The number of stages can vary depending on the arrangement of the read amplifier module 29 and the data register 28. <1-1-7> Circuit configuration of driver circuit 26 and detection circuit 30

[0064] Fig. Figure 9 is a diagram showing an example of a circuit configuration of the driver circuit 26 and the detection circuit 30 in the storage device 2 according to the first embodiment. Fig. Figure 9 shows a configuration for applying a voltage to the source line SL in the driver circuit 26. As shown in Fig. As shown in Figure 9, the driver circuit 26 contains, for example, transistors T20 and T21, as well as an error amplifier 261. The detection circuit 30 comprises transistors T30 to T39, a comparator 321, and nodes N1 to N4. Each of transistors T20, T31, T32, T35, and T36 is a p-channel MOS transistor. Each of transistors T21, T30, T33, T34, T37, T38, and T39 is an n-channel MOS transistor.

[0065] The supply voltage VCC is applied to one end of transistor T20. The other end of transistor T20 is connected to the source line SL. A control signal PRECH is applied to the gate of transistor T20. The control signal PRECH is generated, for example, by sequencer 24. Transistor T20 can transmit the supply voltage VCC applied to one end and precharge the source line SL by being switched on by the control signal PRECH. One end of transistor T21 is connected to the source line SL. The other end of transistor T21 is connected to a ground node. A first input of error amplifier 261 is connected to the source line SL. A voltage VREF_SL is applied to a second input of error amplifier 261. The output of error amplifier 261 is connected to the gate of transistor T21.The output voltage of the error amplifier 261 changes based on a voltage difference between the first and second input terminals. The circuit consisting of transistor T21 and the error amplifier 621 acts as a linear regulator and can keep the voltage of the source line SL constant. The output voltage of the error amplifier 261 changes depending on the current flowing through the source line SL.

[0066] One end of transistor T30 is connected to node N1. The other end of transistor T30 is connected to a ground node. The gate of transistor T30 is connected to the output terminal of error amplifier 261. This means that transistor T30 is controlled by error amplifier 261 in a similar way to transistor T21. Therefore, the current flowing through transistor T30 can change based on a change in the current flowing through the source line SL. One end and the gate of transistor T31 are connected to node N1. The supply voltage VCC, for example, is applied to the other end of transistor T31. The gate of transistor T32 is connected to node N1. One end of transistor T32 is connected to node N2. The supply voltage VCC, for example, is applied to the other end of transistor T32.

[0067] One end of transistor T33 is connected to node N2. The other end of transistor T33 is connected to a ground node. The gate of transistor T33 is connected to node N3. One end and the gate of transistor T34 are connected to node N3. The other end of transistor T34 is connected to a ground node. One end of transistor T35 is connected to node N3. The supply voltage VCC, for example, is applied to the other end of transistor T35. The gate of transistor T35 is connected to node N4. One end and the gate of transistor T36 are connected to node N4. The supply voltage VCC, for example, is applied to the other end of transistor T36.

[0068] A set of transistors T37 and T38 is connected in series between node N4 and the ground node. The detection circuit 30 can contain multiple sets of such transistors T37 and T38. Specifically, the detection circuit 30 includes, for example, a reference current generation unit 322 with one set of transistors T37 and T38, a reference current generation unit 323 with two sets of transistors T37 and T38, and a reference current generation unit 324 with four sets of transistors T37 and T38. The gates of transistors T37 are connected to the gate of transistor T39. Transistor T39 is controlled such that a reference current Iref1 flows during a subsequent correction read operation. A control signal CS1 is input to the gate of transistor T38, which is contained in the reference current generation unit 322.A control signal CS2 is input to the gates of transistors T38, which are contained in the reference current generation unit 323. A control signal CS3 is input to the gates of transistors T38 in the reference current generation unit 324. The control signals CS1 to CS3 are generated, for example, by sequencer 24.

[0069] Here, a method for using the reference current generating units 322 to 324 is described, assuming that the sizes of transistors T37 and T39 are the same. The sequencer 24 can set the current flowing through node N4 to the reference current Iref1 by driving only the control signal CS1 to a high level among the control signals CS1 to CS3. The sequencer 24 can set the current flowing through node N4 to twice the value of the reference current Iref1 by driving only the control signal CS2 to a high level among the control signals CS1 to CS3. The sequencer 24 can increase the current flowing through node N4 to four times the reference current Iref1 by driving only the control signal CS1 to a high level among the control signals CS1 to CS3. In this way, the sequencer can change the amount of current flowing through node N4 by selectively using the reference current generating units 322 to 324.

[0070] The current flowing through node N4 is mirrored to node N3 by transistors T35 and T36, which form a current mirror circuit. The current flowing through node N3 is mirrored to node N2 by transistors T33 and T34, which also form a current mirror circuit. The reference current Iref2, flowing through node N1, is mirrored to node N2 by transistors T31 and T32, which also form a current mirror circuit. That is, the reference current Iref3 flowing through node N2 is based on the reference currents Iref1 and Iref2.

[0071] The comparator 321 outputs a comparison result between a voltage VA at node N1 and a voltage VB at node N2 as an output signal OUT1. For example, if the current flowing through the source line SL increases, the gate voltage of transistor T30 rises, and the voltage VA at node N1 increases. Conversely, the voltage VB at node N2 is kept constant based on the reference current Iref1. Consequently, the comparator 321 can detect, for example, that the voltage VA exceeds the voltage VB and reproduce the change in the current of the source line SL in the output signal OUT1. Note that the detection circuit 30 can have a different circuit configuration as long as it can detect a change in the current of the source line SL. <1-1-8> Threshold voltage distribution of the memory cell transistor MT

[0072] The following describes an example of the threshold voltage distribution of the memory cell transistor MT. This specification describes as an example a case where 3-bit data is stored in each memory cell transistor MT, i.e., a case of 3 bits / cell. The system for storing 3-bit data in the memory cell transistor MT is also referred to as a triple-level cell (TLC) system. (1: Threshold voltage distribution of the memory cell transistor MT in 3 bits / cell)

[0073] Fig. Figure 10 is a diagram showing an example of the threshold voltage distribution of the memory cell transistor MT and the data allocation in the memory device 2 according to the first embodiment. The horizontal axis of the diagram is shown in Figure 10. Fig. The threshold voltage distribution shown in Figure 10 corresponds to the threshold voltage (Vth) of the memory cell transistor MT. The horizontal axis of the distribution shown in Figure 10 represents the threshold voltage (Vth) of the memory cell transistor MT. Fig. The threshold voltage distribution illustrated in 10 corresponds to the number of memory cell transistors MT (NMTs). As shown in Fig. As illustrated in Figure 10, the threshold voltage distribution of the memory cell transistor MT comprises a multitude of states. Since randomization is performed on the data written to each cell unit CU, the memory cell transistors MT are essentially evenly distributed across the multitude of states formed. The number of states in the threshold voltage distribution then changes depending on the number of data bits stored in each of the multitude of memory cell transistors MT in the cell unit CU.

[0074] In a case where the memory cell transistor MT stores 3-bit data, the threshold voltage distribution of the memory cell transistor MT has eight states. In this specification, the eight states are designated as states S0 to S7 in order of decreasing threshold voltage. Each of the eight states S0 to S7 is assigned three distinct bit data. The threshold voltage of the memory cell transistor MT in the erase state is distributed to state S0.

[0075] In this specification, the 3-bit data stored in each memory cell transistor MT is also referred to as upper-side data, middle-side data, and lower-side data. One-sided data configured by upper-side, middle-side, and lower-side data stored in each of the multiple memory cell transistors MT contained in each cell unit CU is also referred to as upper-side data, middle-side data, and lower-side data, respectively. An example of data corresponding to the eight states S0 through S7 is described below.

[0076] (Example) State name: "Upper bits / middle bits / lower bits" data State S0: "111" data State S1: "110" data State S2: "100" data State S3: "000" data State S4: "010" data State S5: "011" data State S6: "001" Data Status S7: "101" data.

[0077] A verification voltage and a read voltage are set between two adjacent states. During a write operation, the memory device 2 repeatedly executes a set consisting of a program operation to increase the threshold voltage of the memory cell transistor MT and a read operation using the verification voltage. The memory device 2 can use the verification voltage to determine whether the threshold voltage of the memory cell transistor MT, which the program is targeting, has reached the target state. Furthermore, during the read operation, the memory device 2 performs the read operation using at least one read voltage. The memory device 2 can establish a state corresponding to the threshold voltage of the memory cell transistor MT, based on whether the memory cell transistor MT, to which the read voltage is applied, is switched on or off.

[0078] In the TLC system, the verification voltages V1 to V7 are set in association with states S1 to S7. The read voltage R1 is set between states S0 and S1. Similarly, the read voltages R2 to R7 are set between states S1 and S2, S2 and S3, S3 and S4, S4 and S5, S5 and S6, and S6 and S7, respectively. A read path voltage VREAD is set to a voltage higher than that of the state with the highest threshold voltage (e.g., state S7). The read voltage is also referred to as the read level.

[0079] In a case where the Fig. When the data assignment illustrated in Figure 7 is applied, the lower page data is determined by the read operation using read voltages R1 and R5. The middle page data is determined by the read operation using read voltages R2, R4, and R6. The upper page data is determined by the read operation using read voltages R3 and R7. When reading page data with multiple read voltages, arithmetic processing is performed as needed in the read amplifier unit (SAU). Hereinafter, a series of operations for acquiring data using a single read voltage is also referred to as "read processing." That is, the read operation can comprise multiple read processing processes.

[0080] It should be noted that each memory cell transistor MT can store data of one bit, two bits, four bits, or more. In a case where the memory cell transistor MT stores k-bit data (k being an integer of 1 or greater), the threshold voltage distribution of the memory cell transistor MT comprises at least 2 k States. In other words, if the memory cell transistor MT stores 4-bit data (four bits / cell), the threshold voltage distribution of the memory cell transistor MT has 16 states. With four bits / cell, each of the 16 states is assigned 4-bit data, which are distinct from one another. The system for storing 4-bit data in the memory cell transistor MT is also called a quad-level cell (QLC) system. (2: Combined threshold voltage distribution of NAND strings NS)

[0081] Fig. Figure 11 is a diagram illustrating an example of the combined threshold voltage distribution of NAND strings NS in the storage device 2 according to the first embodiment. In (A) of Fig. 11 is the threshold voltage distribution of the TLC system in Fig. 10 illustrated. In (B) of Fig. Figure 11 illustrates the combined threshold voltage distribution of the NAND strings NS. As described above, each NAND string NS contains, for example, N memory cell transistors MT0 to MT(N-1). In a case where the threshold voltage distribution of the memory cell transistor MT is random, at least one of the memory cell transistors MT0 to MT(N-1) contained in each NAND string NS stochastically enters state S7. Thus, if each NAND string NS is virtually considered as a memory cell transistor, the threshold voltage of the virtual memory cell transistor will be higher than that of state S7. Therefore, in a case where all word lines WL are supplied with the same potential and each NAND string NS is operated as a virtual memory cell transistor, the threshold voltage distribution looks, for example, like the threshold voltage distribution shown in (B) of Figure 11. Fig. Figure 11 illustrates this. In the present description, such a threshold voltage distribution is referred to as a combined threshold voltage distribution. A state contained within the combined threshold voltage distribution is subsequently referred to as a combined state SS. Furthermore, the lower limit of the threshold voltage of the combined state SS is referred to as the combined threshold Vth_TOTAL.

[0082] When the voltages across all word lines WL connected to the NAND strings NS rise and become equal to or greater than the combined threshold Vth_TOTAL, the current flowing through the NAND strings NS increases. Conversely, when the voltages across all word lines WL connected to the NAND strings NS fall and become less than the combined threshold Vth_TOTAL, the current flowing through the NAND strings NS is interrupted and becomes approximately the leakage current. When the voltages across all word lines WL connected to the NAND strings NS are equal to or greater than the combined threshold Vth_TOTAL, the current is significantly larger than the leakage current. The combined threshold voltage distribution appears as a combined state SS in each case where the memory cell transistor MT stores k bits of data (k being an integer of 1 or greater).

[0083] The combined state SS corresponds to state S7 in the case of the TLC system. Fluctuations in the combined state SS are then suppressed by the combination. Consequently, the combined state SS has a narrower distribution than the state with the highest threshold voltage (e.g., state S7) and is shifted upwards. Therefore, the shift state of the threshold voltage distribution can be estimated with high accuracy due to data storage by determining the bottom of the combined state SS. Furthermore, the shift magnitude of the threshold voltage distribution of each state can be estimated based on the shift magnitude at the bottom of the combined threshold voltage distribution.Then the detection circuit 30, which is included in the storage device 2 according to the first embodiment, is configured to be able to detect the bottom of the combined state SS based on a change in the current of the source line SL. <1-2> Operation

[0084] Next, the operation of the MS storage system according to the first embodiment will be described. <1-2-1> Processing procedure of a read operation

[0085] Fig. Figure 12 is a flowchart illustrating an example of a processing operation of the read operation of the MS storage system according to the first embodiment. For example, when a command to read data is received from the host device HD, the MS storage system begins a series of processing operations in Fig. 12 (Start).

[0086] First, the MS storage system performs a normal read operation (step ST10). The normal read operation uses a preset read voltage. During the normal read operation, memory controller 1 first transmits a read instruction and address information to be read to storage device 2 based on an instruction from the host device HD. Then, storage device 2 performs a read operation based on the read instruction and the address information received from memory controller 1 and sends a read result back to memory controller 1. The read voltage used in the normal read operation can be a standard value or a value other than the standard value.

[0087] The storage system MS then determines whether error correction in the read result obtained from the normal read operation was successful (step ST11). If error correction was successful (step ST11: YES), storage controller 1 outputs the read result to the host device HD (step ST12) and terminates the processing sequence. Fig. 12 (End). If, however, error correction fails (step ST11: NO), memory controller 1 executes a correction read result (step ST13). In this example, it is assumed that error correction during the error correction processing of a read result by the correction read operation was successful. When the correction read operation is complete, memory controller 1 outputs the read result to the host device HD (step ST12) and terminates the processing sequence of Fig. 12 (End). <1-2-2> Normal reading operation

[0088] Fig. Figure 13 is a diagram showing an example of a voltage applied to the NAND strings NS at a specific point in time during a normal read operation of the storage device 2 according to the first embodiment. Fig. Figure 13 shows two NAND strings NS coupled with the common bit line BL, representing the selected and unselected string units, respectively. The selected string unit corresponds to the string unit SU, including the cell unit CU to be read. The unselected string unit corresponds to the string unit SU excluding the cell unit CU to be read. In this example, the word line WLi (where i is 0 or greater and (N-1) or less) is selected.

[0089] In the following, the word line WL coupled to the cell unit CU to be read in the selected block BLK is referred to as the "selected word line WLsel". The other word lines WL, other than the selected word line WLsel, in the selected block BLK are referred to as "unselected word lines WLusel". The NAND string NS contained in the selected string unit is referred to as the "selected NAND string NSsel". The NAND string NS contained in the unselected string unit is referred to as the "unselected NAND string NSusel". The selection gate line SGD coupled to the selected string unit is referred to as the "selection gate line SGDsel". The selection gate line SGD contained in the unselected string unit is referred to as the "selection gate line SGDusel". The selection transistor STD coupled to the selected gate line SGDsel is referred to as the "selection transistor STDsel".The selection transistor STD, which is coupled to the selection gate line SGDusel, is referred to as the "selection transistor STDusel". The memory cell transistor MT, which is contained in the cell unit CU to be read, is referred to as the "selected memory cell transistor MTsel".

[0090] As in Fig. As illustrated in Figure 13, a voltage VBLsel, higher than the ground voltage VSS, is applied to the selected bit line BL at a specific time during the normal read operation. A voltage VSRC, higher than the ground voltage VSS, is applied to the source line SL. The read voltage VCG is applied to the selected word line WLsel (e.g., word line WLi). The read voltage VCG corresponds, for example, to one of the values ​​shown in Figure 13. Fig. Ten illustrated read voltages R1 to R7. The read voltage VREAD is applied to the unselected word line WLusel (e.g., word line WL0). A voltage VSGD, higher than the ground voltage VSS, is applied to the selection gate line SGDsel. The ground voltage VSS is, for example, applied to the selection gate line SGDusel. A voltage VSGS, higher than the ground voltage VSS, is applied to the selection gate line SGS.

[0091] As a result, each of the selection transistors STDsel, coupled to the selection gate line SGDsel, and the selection transistor STS, coupled to the selection gate line SGS, can be turned on. Consequently, the read amplifier unit SAU can determine whether the threshold voltage of the selected memory cell transistor MTsel exceeds the read voltage VCG by detecting whether current has flowed between the bit line BL and the source line SL in the selected NAND string NSsel. The memory controller 1 can detect the threshold voltage distribution in the cell unit CU to be read using a variety of read voltage types VCG.

[0092] Fig. Figure 14 is a diagram illustrating an example of an operating waveform of the normal read operation of the storage device 2 according to the first embodiment. Fig. Figure 14 illustrates changes in the voltages of the select-gate line SGDsel, the select-gate line SGDusel, the select-word line WLsel, the non-select-word line WLusel, the select-gate line SGS, the control signal BLC, the bit line BL, the source line SL, and the control signal STB during normal read operation for the bottom side. As shown in Fig. Figure 14 illustrates that, during normal read operation, the sequencer 24 processes the data on the lower page sequentially at times t0 to t6. At the beginning of the normal read operation, the voltage applied to each connection is the ground voltage VSS, and each control signal is at a low level (“L”).

[0093] At time t0, sequencer 24 applies the voltage VSGD to each of the select gate lines SGDsel and SGDusel, applies the voltage VSGS to the select gate line SGS, and applies the read path voltage VREAD to each of the select word line WLsel and the non-select word line WLusel. As described above, the voltage VSGD is applied to the select gate line SGDusel in a rising period of the word line WL, and the non-select select transistor STD is driven into the on state. This suppresses read errors caused by hot charge carriers in the non-select NAND string NSusel.

[0094] At time t1, the sequencer 24 applies the voltage VSRC to the source line SL. In the read operation of a first embodiment, a negative voltage can be applied to the selected memory cell transistor MTsel by applying the voltage VSRC to the source line SL. For example, if the read voltage R1 is lower than the voltage VSRC, a negative voltage is applied to the selected memory cell transistor MTsel. Such read processing is also referred to as negative sampling / reading.

[0095] At time t2, sequencer 24 sets the control signal BLC to the high level ("H"). Then, the read amplifier unit SAU, which is coupled to the selected bit line BLsel, charges the selected bit line BLsel, and the voltage of the selected bit line BLsel rises to the voltage VBLsel. Similarly, the read amplifier unit SAU, which is coupled to the unselected bit line BLusel, charges the unselected bit line BLusel, and the voltage of the unselected bit line BLusel rises to the voltage VBLusel. It should be noted that the unselected bit line BLusel is not necessarily charged at time t2, and the voltage VBLusel can be controlled to maintain the ground voltage VSS. Furthermore, at time t2, sequencer 24 applies the ground voltage VSS to the select gate line SGDusel and applies the read voltage R5 to the selected word line WLsel.At this point, sequencer 24 directly changes the voltage of the read path VREAD to a read voltage R5c, without reducing the voltage to the ground voltage VSS. Then, the selected memory cell transistor MTsel, to which the read voltage R5 is applied, is switched on or off according to the data stored in it.

[0096] Although not illustrated, between time t2 and time t3, sequencer 24 charges the read node SEN of each read amplifier unit SAU by setting the control signal SPC to a high level for a predetermined time. Then, sequencer 24 sets the control signals XXL and S2S to a high level. Finally, the voltage of the read node SEN of each read amplifier unit SAU is either discharged or maintained, depending on the state of the selected memory cell transistor MTsel connected to the read amplifier unit SAU.

[0097] At time t3, sequencer 24 sets the control signal STB to a high level within a predetermined time. That is, at time t3, sequencer 24 activates the control signal STB. Then, transistor T10 of each read amplifier unit SAU is switched on or off depending on the voltage of the read node SEN of the read amplifier unit SAU. Consequently, a read result is reflected on the bus LBUS using the read voltage R5, and this read result is stored in a predetermined latch circuit.

[0098] The processes at times t4 and t5 are similar to the process in which the voltage applied to the selected word line WLsel is changed from the read voltage R5 to the read voltage R1 in the processes described for times t2 and t3, respectively. In short, at time t4, the sequencer 24 applies the read voltage R1 to the word line WLsel. Then, at time t5, the sequencer 24 passes the control signal STB. As a result, a read result using the read voltage R1 is reflected on the bus LBUS, and this read result is stored in a predetermined latch circuit.

[0099] At time t6, sequencer 24 changes the voltage applied to each connection and the voltage of each control signal to the state at the beginning of the normal read operation. Sequencer 24 then determines the lower bit data based on the read result using read voltage R1 and the read result using read voltage R5. Afterward, storage device 2 transmits the determined set of lower bit data as lower page data to memory controller 1 and terminates the normal line read operation for the lower page data.

[0100] Note that the storage device 2 can perform the normal read operation, in which a different side is selected, similarly to the read operation for the data on the lower side, by changing the read voltage and the arithmetic processing for data determination. In the present example, the case was shown where the read result of each read operation is held in different latch circuits, but the present invention is not limited thereto. The read amplifier unit SAU can store the read result of the successive read operation in a latch circuit (e.g., the latch circuit SDL). <1-2-3> Proofreading process

[0101] Details of the proofreading process of the MS storage system according to the first embodiment are described below. (1: Proofreading process)

[0102] Fig. Figure 15 is a flowchart illustrating an example of a processing operation of a proofread operation of the storage device 2 according to the first embodiment. After receiving the command to execute the proofread operation from the storage controller 1, the storage device 2 begins a series of processing operations according to Fig. 15 (Start).

[0103] First, the storage unit 2 applies a search voltage VLUMP to all word lines WL of the selected block BLKsel (step ST20). The search voltage VLUMP is, for example, the same voltage as the read voltage VREAD. The rate at which the search voltage VLUMP is applied to all word lines WL can differ from the rate at which the read path voltage VREAD is applied to the unselected word line WLusel during normal read operation.

[0104] Next, storage device 2 selects a read voltage correction value based on the time at which current flows through the source line SL (step ST21). In a case where the voltage supplied to all word lines WL of the selected block BLKsel increases from the ground voltage VSS towards the search voltage VLUMP, current flows through the source line SL at the time when the voltage supplied to the word line WL reaches the combined threshold Vth_TOTAL of each NAND string NS. Therefore, the time at which current flows through the source line SL is based on the combined threshold voltage distribution. As in Fig. As illustrated in Figure 16, the combined threshold voltage distribution corresponds to the individual threshold voltage distributions, and if one threshold voltage distribution fluctuates, the combined threshold voltage distribution also fluctuates accordingly. Therefore, the combined threshold voltage distribution can be estimated from the time at which the current flows through the source line SL, thus allowing the individual combined threshold voltage distribution to be estimated. A multitude of sets of read voltage correction values ​​are prepared in conjunction with each time at which the current flows through the source line SL. Furthermore, the multiple sets of read voltage correction values ​​are stored in a space that the sequencer 24 can access during the correction read operation. The processing of steps ST20 and ST21 can be referred to as a "search read."

[0105] Next, storage device 2 performs a calibration read using the read voltage to which the selected correction value is applied (step ST22). The calibration read is a read operation using the read voltage to which the selected correction value is applied. The calibration read can be referred to as an "optimal value read." After completing the calibration read, storage device 2 outputs the read result to storage controller 1 and terminates the processing sequence. Fig. 15 (End). Note that the read voltage to which the correction value is applied may be referred to in this specification as the ‘suitable read voltage’. (2: Example of the applied voltage in the proofreading process)

[0106] Fig. Figure 17 is a diagram illustrating an example of a voltage applied to the NAND strings NS at a specific point in time during the correction read operation of the storage device 2 according to the first embodiment. Fig. 17. Selected NAND strings NSsel and unselected NAND strings NSusel, coupled with a common bit line BL, are extracted for illustrative purposes. In this example, the word line WLi is selected.

[0107] As in Fig. Figure 17 illustrates that at a specific time during the proofreading process, a voltage VBLsel is applied to the selected bit line BL. The high voltage VSRC is applied to the source line SL. The search voltage VLUMP is applied to all word lines WL, including the selected word line WLsel. The voltage VSGD is applied to each of the selection gate lines SGDsel and SGDusel. The voltage VSGS is applied to the selection gate line SGS.

[0108] This allows each of the selection transistors STDsel and STDusel, as well as the selection transistor STS, to be turned on. As the voltage of each word line WL rises towards the search voltage VLUMP, a current ISRCsel flows through the selected NAND string NSsel and a current ISRCusel flows through the unselected NAND string NSusel at a time that corresponds to the combined threshold voltage distribution (combined state SS) of all NAND strings NS in block BLK. In particular, a section in which the current of the source line SL has changed corresponds to the lower end of the combined threshold voltage distribution of all NAND strings NS in block BLK. That is, the combined threshold voltage distribution of block BLK, including the cell unit CU to be read, can be determined based on the time at which the current of the source line SL changes.As described above, the detection circuit 30 can detect the combined threshold voltage distribution of block BLK including the cell unit CU to be read based on the change in the total current of ISRCsel and ISRCusel (total Icell). (3: Operating waveform of the proofreading process)

[0109] Fig. Figure 18 is a diagram illustrating an example of an operating waveform of the proofreading process of the storage device 2 according to the first embodiment. Fig. Figure 18 illustrates changes in the voltages of the select-gate line SGDsel, the select-gate line SGDusel, the select-word line WLsel, the unselected word line WLusel, the select-gate line SGS, the control signal BLC, the bit line BL, the source line SL, the output signal OUT1, and the control signal STB, as well as changes in the current ISRC of the source line SL during proofreading for the bottom page. As shown in Fig. As illustrated in Figure 18, during the normal read operation for the data on the lower page, the sequencer 24 performs the processing sequentially at times t0 to t6. At the beginning of the proofreading operation, the voltage applied to each connection is the ground voltage VSS, and each control signal is at a low level.

[0110] At time t0, sequencer 24 applies the voltage VSGD to each of the selection gate lines SGDsel and SGDusel, applies the voltage VSGS to the selection gate line SGS, applies the search voltage VLUMP to all word lines WL, including the selected word line WLsel and the unselected word line WLusel, and applies the voltage VSRC to the source line SL. Additionally, at time t0, sequencer 24 sets the control signal BLC to a high level. Then, the read amplifier unit SAU, which is coupled to the selected bit line BLsel, charges the selected bit line BLsel, and the voltage of the selected bit line BLsel rises to the voltage VBLsel. Similarly, the read amplifier unit SAU, which is coupled to the unselected bit line BLusel, charges the unselected bit line BLusel, and the voltage of the unselected bit line BLusel rises to the voltage VBLusel.It should be noted that the unselected bit line BLusel is not necessarily charged at time t0 and the voltage VBLusel can be controlled so that the ground voltage VSS is maintained.

[0111] When the voltage of each word line WL begins to rise towards the search voltage VLUMP, a leakage current can initially flow through the multiple NAND strings NS connected to the selected bit line BLsel. Then, as the voltage of each word line WL continues to rise and reaches the lower end of the combined threshold voltage distribution of block BLK, a current flows through the NAND string NS coupled to the selected bit line BLsel, and the ISRC current of the source line SL increases. Fig. In section 18, a threshold value, Dth, is defined at which a change in the ISRC current of the source line SL is detected by the detection circuit 30. When the ISRC current exceeds the threshold value Dth, the output signal OUT1 of the detection circuit 30 changes from a low to a high level. Note that the time at which a change in the ISRC current of the source line SL is detected by the detection circuit 30 is defined by time t1. The voltage of each word line WL at time t1 corresponds to Vth_TOTAL. The sequencer 24 then determines the correction value of the read voltage, which is used during the reading process for the bottom page, based on time t1.

[0112] Then, at time t2, sequencer 24 applies the ground voltage VSS to the selection gate line SGDusel and applies the read voltage R5c to the selected word line WLsel. At this time, sequencer 24 directly changes the search voltage VLUMP to the read voltage R5c without reducing the voltage to the ground voltage VSS. The read voltage R5c is the read voltage R5 to which the correction value determined based on time t1 is applied. The other processes at times t2 and t3 are similar to those described with reference to... Fig. 14 were described. In other words, at time t3, the sequencer 24 transmits the control signal STB. As a result, a read result using the read voltage R5c is reflected on the bus LBUS, and the read result using the read voltage R5c is stored in a predetermined latch circuit.

[0113] Then, at time t4, sequencer 24 applies a read voltage R1c to the selected word line WLsel. The read voltage R1c is the read voltage R1 to which the correction value determined based on time t1 is applied. The other operations at times t4 and t5 are similar to the operations at times t4 and t5, respectively, which are described with reference to Fig. 14 were described. In other words, at time t5, the sequencer 24 transmits the control signal STB. As a result, a read result using the read voltage R5c is reflected on the bus LBUS, and the read result using the read voltage R1c is stored in a predetermined latch circuit.

[0114] At time t6, sequencer 24 changes the voltage applied to each connection and the voltage of each control signal to the state at the beginning of the correction read operation. Sequencer 24 then determines the lower bit data based on the read result using read voltage R1c and the read result using read voltage R5c. Afterward, storage device 2 transmits the determined set of lower bit data as lower page data to storage controller 1 and completes the lower page correction read operation. Note that storage device 2 can perform the correction read operation, in which a different page is selected, similarly to the lower page read operation, by changing the read voltage and the arithmetic processing for data determination. (4: Command sequence of the proofreading process)

[0115] Fig. Figure 19 is a diagram illustrating an example of a command sequence for the proofreading operation of the storage device 2 according to the first embodiment. Fig. Figure 19 illustrates the input / output signal I / O and the ready / occupied signal RBn in a case where the proofreading process is being performed. Before the process begins, the ready / occupied signal RBn is "H" (high level: ready state). As shown in Fig. As illustrated in Figure 19, during the execution of the proofreading process, the memory controller 1 first transmits an instruction “xxh”, an instruction “yyh”, an instruction “00h”, an address “ADD” and an instruction “30h” in this order to the memory device 2.

[0116] The instruction "xxh" is used as an option and specifies a proofreading operation. The instruction "yyh" is a command that instructs an operation corresponding to a specific page. The "yyh" instruction is modified depending on the page to be read. The instruction "00h" is a command that instructs a read operation. The address "ADD" can contain information such as the block BLK to be read, the string unit SU, and the word line WL. The address "ADD" can be transmitted in multiple cycles. The instruction "30h" is a command that instructs memory device 2 to start the read operation based on the instruction and the address stored in register circuit 23.

[0117] When the instruction “30h” is held in register circuit 23, the sequencer 24 switches the storage device 2 from the ready state (RBn = “H”) to the busy state (RBn = “L” (low-level: busy state)) and starts the proofreading process. Fig. In section 19, the time period during which the correction read operation is performed is specified by tR. When the correction read operation is complete, the sequencer 24 switches the storage device 2 from the busy state to the ready state. When the end of the read operation is detected based on the change in the ready / busy signal RBn, the storage controller 1 outputs the read result (data DAT) sequentially to the storage device 2, for example by switching the control signal REn. <1-3> Advantageous effects of the first embodiment

[0118] According to the first embodiment, it is possible to provide a storage device and a storage system MS that exhibit high reliability and operate at high speed. Details of the effects of the first embodiment are described below using a comparative example.

[0119] In flash memory where memory cells are stacked three-dimensionally, it is difficult to prevent degradation of the memory cell properties due to the reduced stacking interval and high stacking density. In particular, when 4-bit data or more is stored in a memory cell (MC), error correction cannot be performed during a normal read operation, and the frequency of on-chip tracking increases. On-chip tracking is a read operation in which a search read is performed to locate a more suitable read voltage on the memory device (2), followed by a calibration read using the suitable read voltage determined by the search.

[0120] Fig. Figure 20 is a diagram illustrating an example of an operating waveform of an on-chip tracking process in a comparative example. As shown in Fig. As illustrated in Figure 20, the on-chip tracking process involves performing a search read and a calibration read sequentially. In the search read of the comparison example, for instance, the read processing is performed sequentially using a variety of voltages close to the highest read voltage among a variety of read voltages used in the page being read. In the comparison example, the search read, which targets only one stage, is performed in this way, and the correction values ​​for the read voltages of the other stages are estimated based on the result of one stage's search read. Then, in the calibration read, the read processing is performed using the correction value determined based on the result of the search read. As described above, on-chip tracking requires a large number of read operations.As the number of read operations increases, so does the time spent waiting for the BL bit line to stabilize and the time required for bit counting. Therefore, high-speed on-chip tracking technology is necessary.

[0121] On the other hand, according to the first embodiment, the storage device 2 performs the correction read operation as the operation corresponding to the on-chip tracking operation. Specifically, the correction read operation comprises a first read sequence (search read) and a second read sequence (calibration read). During the search read, the sequencer 24 increases the voltages of the plurality of word lines WL at the same rate and determines the correction value of each of the plurality of read voltages based on the time at which the current across the plurality of NAND strings NS changes with the increase in the voltages of the plurality of word lines WL. During the calibration read, the sequencer 24 performs the read operation using the plurality of read voltages to which the correction values ​​are applied.

[0122] As a result, the sequencer 24 can calculate the displacement of the lower end of the combined threshold voltage distribution based on the voltage of the word line WL in the section where the current of the source line SL has changed, and determine a suitable correction value for the read voltage. Consequently, the storage device 2 according to the first embodiment can perform the correction read operation, which is able to improve the read accuracy similarly to the on-chip tracking operation, but with fewer read operations than the comparison example. <1-4> Further embodiments of the first embodiment

[0123] The MS storage system according to the first embodiment can be modified in various ways. The following describes, in sequence, the first through third further embodiments of the first embodiment. (1: First further embodiment)

[0124] Fig. Figure 21 is a diagram illustrating an example of an operating waveform of the proofreading process according to a first further embodiment of the first embodiment. Fig. 21 illustrates a change in the voltage of the word line WL during proofreading operation of the first further embodiment of the first embodiment. As in Fig. As illustrated in Figure 21, in the first further embodiment of the first embodiment, the rate of rise of the search voltage VLUMP to each word line WL is slower than in the first embodiment.

[0125] Specifically, at time t0, the sequencer 24 begins applying a voltage to each word line WL in the direction of the search voltage VLUMP. The sequencer 24 then controls the rate of rise of the search voltage VLUMP so that it is slower than during the proofreading process of the first embodiment and maintains a constant rate from the midpoint onward. In this example, the voltage of each word line WL reaches the search voltage VLUMP at time t1. Furthermore, between times t0 and t1, the detection circuit 30 detects the time at which current flows through the source line SL. Then, after time t1, the sequencer 24 performs the calibration read using the read voltage, to which the correction value based on the time detected by the detection circuit 30 is applied, similar to the first embodiment.

[0126] The rate of rise of the voltage on the word line WL can vary depending on the distance to the driver circuit 26. In other words, the rise of the voltage on the word line WL can be delayed depending on the distance (perspective difference) to the driver circuit 26. Such a delay can lead to a variation in the threshold voltage distribution. On the other hand, in the first further embodiment of the first embodiment, the rate of rise of the voltage on each word line WL is controlled to be slower than in the first embodiment. As a result, the perspective difference of the voltage on the word line WL is suppressed, and the variation in the threshold voltage distribution caused by the perspective difference can be suppressed.As a result, the detection circuit 30 in the storage system MS according to the first further embodiment of the first embodiment can detect the lower part of the combined threshold voltage distribution with higher accuracy than in the first embodiment. (2: Second further embodiment)

[0127] Fig. Figure 22 is a diagram illustrating an example of an operating waveform of the proofreading process according to a second further embodiment of the first embodiment. Fig. Figure 22 illustrates a change in the voltage of the word line WL during the proofreading process of the second further embodiment of the first embodiment. As in Fig. As illustrated in Figure 22, in the second further embodiment of the first embodiment, the rate of increase of the search voltage VLUMP to each word line WL until reaching a detection period TP is the same as in the first embodiment and is slower in the detection period TP than in the first embodiment.

[0128] Specifically, at time t0, the sequencer 24 begins to apply a voltage to each word line WL, increasing it to the search voltage VLUMP. The sequencer 24 then controls the rate of increase of the search voltage VLUMP, similar to the proofreading process of the first embodiment, until time t1. During the detection period TP, between time t1 and time t2, the sequencer 24 controls the rate of increase of the search voltage VLUMP so that it is slower than during the proofreading operation of the first embodiment and maintains a constant rate. In this example, the voltage of each word line WL reaches the search voltage VLUMP at time t2. During the detection period TP, the detection circuit 30 records the time at which current flows through the source line SL.Then, after time t2, the sequencer 24 performs the calibration read using the read voltage to which the correction value is applied based on the time detected by the detection circuit 30, similar to the first embodiment.

[0129] In the second further embodiment of the first embodiment, the detection period TP is predetermined according to a range in which the combined threshold voltage distribution can be formed. Since the voltage of each word line WL is then quickly raised to the target value (detection period TP), the processing time of the proofreading operation in the second further embodiment of the first embodiment can be reduced compared to the first further embodiment. Therefore, in the storage system MS according to the second further embodiment of the first embodiment, the detection circuit 30 can detect the lower end of the combined threshold voltage distribution with higher accuracy than in the first embodiment, and the proofreading operation can be performed at a higher speed than in the first further embodiment of the first embodiment. (3: Third further embodiment)

[0130] Fig. Figure 23 is a diagram illustrating an example of an operating waveform of the proofreading process according to a third further embodiment of the first embodiment. Fig. 23 illustrates a change in the voltage of the word line WL during proofreading operation of the third further embodiment of the first embodiment. As in Fig. As illustrated in Figure 23, in the third further embodiment of the first embodiment, the rate of increase of the search voltage VLUMP to each word line WL is faster than in the first embodiment, until the detection period TP is reached. Then the sequencer 24 controls the voltage of each word line WL so that it decreases at a constant rate during the detection period TP.

[0131] Specifically, at time t0, the sequencer 24 begins to apply a voltage to each word line WL, increasing it towards the search voltage VLUMP. Furthermore, the sequencer 24 controls the rate of increase of the search voltage VLUMP so that it is faster than during the proofreading process of the first embodiment. In this example, the voltage of each word line WL reaches the search voltage VLUMP at time t1. Then, during the detection period TP, which begins at time t1, the sequencer 24 decreases the voltage of each word line WL from the search voltage VLUMP at a constant rate. In this example, the detection circuit 30 detects the time at which the current to the source line SL is switched off at time t2.Furthermore, based on the detection of the time at which the current of the source line SL is switched off, the sequencer 24 performs the calibration read using the read voltage to which the correction value based on the time detected by the detection circuit 30 is applied, similar to the first embodiment. In the correction read process of the third further embodiment of the first embodiment, the voltage of the selected word line WLsel transitions from the voltage at which the lower part of the combined threshold voltage distribution is detected to the read voltage (e.g., R5c) to which the correction value is applied.

[0132] In the third further embodiment of the first embodiment, the detection circuit 30 detects the lower end of the combined threshold voltage distribution based on the fact that the current of the source line SL falls below the threshold value Dth of the current of the source line SL, which is determined with reference to Fig. 18 in the first embodiment. In the third further embodiment of the first embodiment, the length of the detection period TP changes based on the timing detected by the detection circuit 30. Since the voltage of each word line WL is quickly raised to the target (detection period TP), the processing time of the proofreading operation in the third further embodiment of the first embodiment can be reduced compared to the first further embodiment. Therefore, in the storage system MS according to the third further embodiment of the first embodiment, the detection circuit 30 can detect the base of the combined threshold voltage distribution with higher accuracy than in the first embodiment, and the proofreading operation can be performed at a higher speed than in the first further embodiment of the first embodiment. <2> Second embodiment

[0133] A memory system MS according to a second embodiment performs the correction read operation described in the first embodiment, primarily selecting the plurality of bit lines BL that are arranged on the side of the word line WL coupled to the driver circuit 26. Details of the memory system MS according to the second embodiment are described below, mainly with regard to the differences from the first embodiment. <2-1> Configuration

[0134] The structure of the MS storage system according to the second embodiment is similar to that of the first embodiment. <2-2> Operation

[0135] The following describes the operation of the MS storage system according to the second embodiment. <2-2-1> Arrangement of the bit lines selected in the proofreading process BL

[0136] Fig. Figure 24 is a diagram illustrating an example of the arrangement of bit lines BL selected at the time of acquiring a combined threshold voltage distribution in a proofread operation of a storage device 2 according to the second embodiment. Fig. Figure 24 illustrates a word line WL coupled to a word line driver WLDR and a plurality of bit lines BL arranged in the X direction. Note that the word line driver WLDR is contained in the driver circuit 26. The word line driver WLDR and the word line WL are coupled via a transistor TR. The near end of the word line WL corresponds to a segment located close to a connection point with the transistor TR. The far end of the word line WL corresponds to a segment located far from the connection point with the transistor TR.

[0137] As in Fig. As illustrated in Figure 24, during the correction read operation of the memory system MS according to the second embodiment, the plurality of bit lines BL located on the near end of the word line WL are selected, and the plurality of bit lines BL located on the far end of the word line WL are not selected. In other words, the plurality of NAND strings NS includes a plurality of first strings coupled to some bit lines BL and a plurality of second strings coupled to other bit lines BL. The distance between the driver circuit 26 and the connection section between the plurality of word lines WL is greater for the multiple second strings than for the multiple first strings.In particular, for example, 1 / 4 of the bit lines BL (1 / 4BL) on the near end side are selected from the multitude of bit lines BL, and 3 / 4 of the bit lines BL (3 / 4BL) on the far end side are not selected from the multitude of bit lines BL.

[0138] At the time of detection of the combined threshold voltage distribution during the proofreading process of the second embodiment, at least a smaller number of bit lines BL are selected than the number of bit lines BL selected as targets to be read. Furthermore, it is preferable that the arrangement of the plurality of bit lines BL selected at the time of detection of the combined threshold voltage distribution be unevenly distributed on the near end side of the word line WL. In the second embodiment, it is more advantageous to select 1 / M (M being an integer of 2 or greater) of the plurality of bit lines BL on the near end side of the word line WL at the time of detection of the combined threshold voltage distribution. <2-2-2> Operating waveform of the proofreading process

[0139] Fig. Figure 25 is a diagram illustrating an example of an operating signal waveform for the proofreading operation of the storage device 2 according to the second embodiment. Fig. Figure 25 illustrates changes in the voltages of the select gate line SGDsel, the select gate line SGDusel, the selected word line WLsel, the unselected word line WLusel, the select gate line SGS, the control signal BLC, the bit line BL, the source line SL, the output signal OUT1 and the control signal STB, as well as changes in the current ISRC of the source line SL during proofreading operation for the bottom page.

[0140] As in Fig. Figure 25 illustrates that the proofreading process in the second embodiment differs from that described in Figure 25. Fig. The proofreading process described in Figure 18 in the first embodiment is carried out during operation of the bit line BL. In particular, between times t0 and t2, the voltage VBLsel is applied to the selected bit line BLsel, and the voltage VBLusel is applied to the unselected bit line BLel. At this time, the selected bit line BL is a plurality of bit lines BL arranged at the near end face of the word line WL, as shown in Figure 18. Fig. Figure 24 illustrates this. Then, similarly to the first embodiment, the detection circuit 30 detects the time at which the current ISRC flows through the source line SL at time t1. Then, at time t2, the sequencer 24 begins a calibration read. At this time, the sequencer 24 applies the voltage VBLsel to all bit lines BL connected to the memory cell transistors MT to be read. That is, at time t2, the sequencer 24 changes the bit line BL that was not selected at the time the combined threshold voltage distribution was detected to the selected bit line BLsel and performs the correction read operation. Other operations of the memory system MS according to the second embodiment are similar to those of the first embodiment. <2-3> Advantageous effects of the second embodiment

[0141] As described above, in the storage device 2 according to the second embodiment, in a case where each of the multiple bit lines BL is a target to be read during search read, the sequencer 24 is configured to load only some of the multiple bit lines BL when a voltage is applied to the multiple word lines WL, and to load the multiple bit lines BL when a read voltage is applied to the multiple word lines WL during calibration read.

[0142] In the storage device 2 according to the second embodiment, for example, only the bit line BL, which corresponds, for example, to 1 / 4 (4 KB) on the near end side of the word line WL, is selected, and the base of the combined threshold voltage distribution is captured. As a result, the variation of the combined threshold voltage distribution due to the perspective difference of the word line WL voltage can be suppressed. Consequently, in the storage device 2 according to the second embodiment, it is possible to suppress the variation of the combined threshold voltage distribution even if the slew rate of the search voltage VLUMP is set to a higher value than in the first embodiment.Therefore, the second embodiment can provide the storage device 2 and the storage system MS, which, similar to the first embodiment, exhibit high reliability and can operate at a higher speed than the first embodiment. <3> Third embodiment

[0143] The MS storage system according to a third embodiment modifies part of the operation of the proofreading process described in the first embodiment according to the state of block BLK. Details of the MS storage system according to the third embodiment are described below, focusing particularly on the differences from the first and second embodiments. <3-1> Configuration

[0144] Fig. Figure 26 is a diagram illustrating an example of a state of block BLK in a memory cell array 20 in a storage device 2 according to the third embodiment. Fig. 26 illustrates a case in which the number of word lines WL in block BLK is eight. In (A) of Fig. Figure 26 illustrates a state in which the write operation is performed for all word lines WL in block BLK and data is written to all cell units CU in block BLK. In (B) of Fig. Figure 26 illustrates a state in which the write operation is performed for some of the word lines WL in block BLK and data is written to some of the cell units CU in block BLK.

[0145] In the following, the block BLK in which data is written to all cell units CU is referred to as a "closed block." The block BLK in which data is written to some of the internal cell units CU is referred to as an "open block." The memory controller 1 according to the third embodiment can manage which page (word line WL) is blank (i.e., in the open state). Other configurations of the memory system MS according to the third embodiment are similar to those of the first embodiment. <3-2> Operation

[0146] The following describes the operation of the MS storage system according to the third embodiment. <3-2-1> Proofreading Processing Procedure

[0147] Fig. Figure 27 is a flowchart illustrating an example of a processing procedure for a correction read operation of the MS storage system according to the third embodiment. For example, if error correction fails during the normal read operation, the MS storage system initiates a series of processing operations in Fig. 27 (Start).

[0148] First, storage device 2 receives information about the written word line WL (i.e., the cell unit CU) of the block BLK to be read from memory controller 1 (step ST30). For example, memory controller 1 sends the information of the written word line WL to storage device 2 via a set feature or similar operation. The information of the written word line WL is stored in a predetermined area of ​​storage device 2 (e.g., register circuit 23).

[0149] Next, the storage device 2 receives an instruction set instructing the execution of the proofreading operation from the memory controller 1 (step ST31). The instruction set used in step ST31 is, for example, similar to that in the first embodiment with reference to Fig. The instruction set described in section 19 is then started by storage device 2, which begins the proofreading process based on the received instruction set.

[0150] Next, the memory device 2 in the selected block BLKsel applies the search voltage VLUMP to the written word line WL and, for example, the read voltage R1 to the unwritten word line WL (step ST32). The voltage applied to the unwritten word line WL in step ST32 can be a different voltage, as long as the memory cell transistor MT can be switched on in the erase state.

[0151] Next, as in the first embodiment, the storage device 2 selects a correction value of the read voltage based on the time at which the current flows through the source line SL (step ST21).

[0152] Next, as in the first embodiment, the storage device 2 performs a calibration read using the read voltage to which the selected correction value is applied (step ST22). After completion of the calibration read, the storage device 2 outputs the read result to the storage controller 1 and terminates the processing sequence. Fig. 27 (End). <3-2-2> Operating waveform of the proofreading process

[0153] Fig. Figure 28 is a diagram illustrating an example of an operating waveform of the proofreading process of the storage device according to the third embodiment. Fig. Figure 28 illustrates changes in the voltages of the selection gate line SGDsel, the selection gate line SGDusel, the selected word line WLsel, the unselected word line WLusel, the selection gate line SGS, the control signal BLC, the bit line BL, the source line SL, the output signal OUT1 and the control signal STB, as well as changes in the current ISRC of the source line SL during proofreading operation for the bottom page.

[0154] As in Fig. Figure 28 illustrates that the proofreading process in the third embodiment differs from that described in Figure 28. Fig. The proofreading process described in section 18 in the first embodiment is carried out by operating the unselected word line WLusel. In particular, the proofreading process is similar to that in the first embodiment when the block BLK to be read is a closed block. On the other hand, the proofreading process differs in a case when the block BLK to be read is an open block in that a predetermined reading voltage is applied to the unwritten, unselected word line WLusel.

[0155] More specifically, during the proofreading process, sequencer 24 applies, for example, the search voltage VLUMP to the programmed word line WL and the read voltage R1 to the unwritten, unselected word line WLusel (Erased WL). It should be noted that the read voltage applied to the unwritten, unselected word line WLusel is not limited to the read voltage R1 and can be any voltage as long as the memory cell transistor MT can be switched on in the state corresponding to the erase state (e.g., state S0). <3-3> Advantageous effects of the third embodiment

[0156] In a case where the search voltage VLUMP is applied to the unselected word line WL of the open block at the time of the search read, there is a possibility that the combined threshold voltage distribution cannot be accurately captured. Therefore, in the memory system MS of the third embodiment, the memory controller 1 transmits information about the unwritten word line WL to the memory device 2. The memory device 2 then applies the read voltage R1 to the word line WL, which is in the open state at the time of the search read of the proofread operation. As described above, by applying the read voltage R1, which is lower than the voltage of the read path, to the word line WL in the open state, the possibility of an erroneous capture of the combined threshold voltage distribution can be suppressed.Therefore, the MS storage system according to the third embodiment has a higher reliability than the first embodiment and can operate at a high speed like in the first embodiment. <4> Fourth embodiment

[0157] The MS storage system according to a fourth embodiment logically subdivides and manages the BLK block. In the fourth embodiment, the correction read operation described in the third embodiment is applied according to the state of the logically subdivided BLK block. Details of the MS storage system according to the fourth embodiment are described below, primarily with regard to differences from the first and second embodiments. <4-1> Configuration

[0158] Fig. Figure 29 is a diagram illustrating an example of a block configuration in a memory cell array in a memory device 2 according to the fourth embodiment. Fig. Figure 29 illustrates a case in which the number of word lines WL in block BLK is 16. As in Fig. As illustrated in Figure 29, in a memory cell array 20 contained in the memory device 2 according to the fourth embodiment, the block BLK is subdivided into and managed by a plurality of subblocks SBLK. In particular, each block BLK contains subblocks SBLK1 and SBLK2. For example, subblock SBLK1 is connected to word lines WL0 to WL7, and subblock SBLK2 is connected to word lines WL8 to WL15.

[0159] The number of subblocks SBLK assigned to each block BLK can be three or more. The number of word lines WL assigned to each subblock SBLK can be one or more. The memory controller 1 can be configured to change whether or not it uses the subblock SBLK depending on the operating mode. For example, when used in subblock mode, the memory controller 1 manages each block BLK in the memory device 2 using a plurality of subblocks SBLK. Other configurations of the memory system MS according to the fourth embodiment are similar to those of the first embodiment. <4-2> Operation

[0160] In the proofread operation of the MS storage system according to the fourth embodiment, the voltage applied to the unselected word line WLusel is selected, similarly to the third embodiment, depending on whether the subblock SBLK is a closed or an open block. The first through fifth examples of the state of block BLK, which is the target of the MS storage system's proofread operation according to the fourth embodiment, are described below.

[0161] Fig. Figure 30 is a diagram illustrating the first example of a state of block BLK that is a target of the MS storage system's proofreading operation according to the fourth embodiment. As in Fig. Figure 30 illustrates that in block BLK of the first example, each of the subblocks SBLK1 and SBLK2 is a closed block. Subblock SBLK1 then contains a page to be read. In this case, during the proofreading operation, sequencer 24 applies the search voltage VLUMP to the unselected word line WLusel of each of the subblocks SBLK1 and SBLK2. Other operations of the proofreading process in the first example are similar to those of the proofreading process in the third embodiment.

[0162] Fig. Figure 31 is a diagram illustrating the second example of a block state that is a target of the MS storage system's proofreading operation according to the fourth embodiment. As in Fig. Figure 31 illustrates that in the second example, block BLK contains each of the subblocks SBLK1 and SBLK2 as a closed block. Subblock SBLK2 then contains a page to be read. In this case, during the proofreading operation, sequencer 24 applies the search voltage VLUMP to the unselected word line WLusel of each of the subblocks SBLK1 and SBLK2. Other operations of the proofreading process in the second example are similar to those of the proofreading process described in the third embodiment.

[0163] Fig. Figure 32 is a diagram illustrating the third example of a block state that is a target of the MS storage system's proofreading operation according to the fourth embodiment. As in Fig. As illustrated in Figure 32, in block BLK of the third example, each of the subblocks SBLK1 and SBLK2 is a closed and an open block, respectively. Subblock SBLK1 then contains a page to be read. In this case, during the proofreading process, sequencer 24 applies the search voltage VLUMP to the unselected word line WLusel of subblock SBLK1. Sequencer 24 also applies the search voltage VLUMP to the written, unselected word line WLusel of subblock SBLK2 and, for example, applies the read voltage R1 to the unwritten, unselected word line WLusel of subblock SBLK2. Other operations of the proofreading process in the third example are similar to those of the proofreading process in the third embodiment.

[0164] Fig. Figure 33 is a diagram illustrating the fourth example of a block state that is a target of the MS storage system's proofreading operation according to the fourth embodiment. As in Fig. Figure 33 illustrates that in block BLK of the fourth example, subblocks SBLK1 and SBLK2 are an open and a closed block, respectively. Subblock SBLK1 then contains a page to be read. In this case, during the proofreading process, sequencer 24 applies the search voltage VLUMP to the written, unselected word line WLusel of subblock SBLK1 and, for example, applies the read voltage R1 to the unwritten, unselected word line WLusel of subblock SBLK1. Sequencer 24 also applies the search voltage VLUMP to the unselected word line WLusel of subblock SBLK2. Other operations of the proofreading process in the fourth example are similar to those of the proofreading process in the third embodiment.

[0165] Fig. Figure 34 is a diagram illustrating the fifth example of a block state that is a target of the MS storage system's proofreading operation according to the fourth embodiment. As in Fig. Figure 34 illustrates that in block BLK of the fifth example, each of the subblocks SBLK1 and SBLK2 is an open block. Subblock SBLK1 then contains a page to be read. In this case, during the proofreading operation, sequencer 24 applies the search voltage VLUMP to the written, unselected word line WLusel of subblocks SBLK1 and SBLK2 and, for example, applies the read voltage R1 to the unwritten, unselected word line WLusel of subblocks SBLK1 and SBLK2. Other operations of the proofreading operation in the fifth example are similar to those of the proofreading operation in the third embodiment.

[0166] Other operations of the MS storage system according to the fourth embodiment are similar to those of the first embodiment. <4-3> Advantageous effects of the fourth embodiment

[0167] As described above, the MS storage system according to the fourth embodiment can use sub-block mode and perform the same proofreading operation as in the third embodiment. As a result, in the MS storage system according to the fourth embodiment, when sub-block mode is used, the applied voltage to the unselected word line WLusel can be changed according to the write / erase state of the sub-block SBLK. Consequently, the MS storage system according to the fourth embodiment has high reliability and can operate at a high speed, similar to the third embodiment.

[0168] If the sub-block mode is used, the displacement amount of the combined threshold voltage distribution between the sub-blocks SBLK may differ.

[0169] Therefore, during the correction read operation of the storage system MS according to the fourth embodiment, the sequencer 24 sets the rise rate of the search voltage VLUMP or the read path voltage VREAD in the subblock SBLK to be read to a constant speed, as in the first and second further embodiments of the first embodiment. Then, the sequencer 24 can adjust the rise rate of the search voltage VLUMP or the read path voltage VREAD in the unselected subblock SBLK so that it is faster than that of the subblock SBLK to be read.

[0170] As a result, the MS memory system can suppress the influence of the shift magnitude of the combined threshold voltage distribution of the memory cell transistors MT in the unselected subblock SBLK on the shift magnitude of the combined threshold voltage distribution in the subblock SBLK being read. Consequently, according to the fifth embodiment, the MS memory system can improve the detection accuracy of the lower end of the combined threshold voltage distribution when using the subblock mode. <5> Fifth embodiment

[0171] The MS memory system according to the fifth embodiment performs a simple tracking operation for the read voltage associated with the low state during the correction read operation described in the first embodiment, and improves the read accuracy for the low state. Details of the MS memory system according to the fifth embodiment are described below, primarily with regard to the differences from the first and fourth embodiments. <5-1> Configuration

[0172] The structure of the MS storage system according to the fifth embodiment is similar to that of the first embodiment. <5-2> Operation

[0173] The following describes the operation of the MS storage system according to the fifth embodiment. In the correction read operation of the MS storage system according to the fifth embodiment, a calibration read procedure differs from that of the first embodiment. Furthermore, in the calibration read operation of the MS storage system according to the fifth embodiment, the control procedure of the read amplifier module 29 differs depending on whether the correction read operation is performed or not when the write operation is suspended. <5-2-1> First example of a proofreading process

[0174] Fig. Figure 35 is a diagram illustrating a first example of the operating waveform of the proofreading process and the method for using the read amplifier module 29 of the MS storage system according to the fifth embodiment. Fig. Figure 35 illustrates a case in which the proofreading process is performed if the writing process is not interrupted. As in Fig. As illustrated in Figure 35, the sequencer 24 acquires the combined threshold voltage distribution similarly to the first embodiment. Then, during the proofreading process, the sequencer 24 performs three-point reading with the lowest reading voltage used in the page to be read (e.g., R1c). Three-point reading is a reading process in which the trough positions of two adjacent states are searched for, and a suitable reading voltage between the two adjacent states can be determined.

[0175] Specifically, as in the first embodiment, the search voltage VLUMP is first applied to the selected word line WLsel, and the detection circuit 30 acquires the combined threshold voltage distribution. Then, the sequencer 24 performs the calibration read based on the acquisition result of the combined threshold voltage distribution. Since the bottom side is a target to be read in this example, the read processing is performed first using the read voltage R5c. When the control signal STB is activated while the read voltage R5c is applied to the selected word line WLsel, the read result (voltage of the read node SEN) is transmitted to the bus LBUS of each read amplifier unit SAU. Then, in each read amplifier unit SAU, the read result transmitted to the bus LBUS is passed to the latch circuit SDL (Best X). A three-point read of the read voltage R1c is then performed.

[0176] The three-point read in the first example of the fifth embodiment is performed, for instance, using the read amplifier unit SAU of stage 1 or 2 in the read amplifier module 29, and other read amplifier units SAU (other) are not used. In particular, the sequencer 24 first stores (transfers) the data (Best X) stored in the latch circuit SDL of the read amplifier unit SAU of stage 1 or 2 to a latch circuit (e.g., the latch circuit ADL) that shares the bus LBUS. Subsequently, the sequencer 24 loads the selected bit line BLsel and applies the control signal STB three times at different times.

[0177] In this example, the three read results are illustrated as read results SR1 to SR3. Each of the read results SR1 to SR3 is transferred via the latch circuit SDL to a counter in the storage device 2 and counted by a counter outside the read amplifier module 29. At this point, the counter counts the number of "0" data points or "1" data points contained in the read results SR1 to SR3. When the three-point read is complete, the data (best X) stored in the latch circuit ADL of the read amplifier unit SAU of stage 1 or 2 is returned to the latch circuit SDL.

[0178] The sequencer 24 then determines a suitable read voltage or read timing based on the counter result of each of the read results SR1 to SR3. The sequencer 24 then recharges the selected bit line BLsel and performs a final read using a suitable read voltage or read timing (read time) with all read amplifier units SAU (all-stage final read). Consequently, each read amplifier unit SAU determines the bottom-side (Best) read data based on the read result read on the bus LBUS and the data from the latch circuit SDL.

[0179] Fig. Figure 36 is a diagram illustrating an example of a measurement target by three-point reading of the MS storage system according to the fifth embodiment. Fig. 36 is a relationship between three-point reading for the in Fig. Figure 35 illustrates the read voltage R1c and the threshold voltage distribution of the memory cell transistor MT. As shown in Fig. As illustrated in Figure 36, the level of the threshold voltage associated with the read results SR1 to SR3 changes depending on the activation time of the control signal STB. Specifically, detection based on the threshold voltage level can be performed by modulating the sampling time or the sampling voltage at each acknowledgment. Consequently, the sequencer can detect valley segments of two adjacent states S0 and S1 based on the read results SR1 to SR3 and determine a suitable read voltage or read time. Such a three-point read can be applied to two other adjacent states. <5-2-2> Second example of a proofreading process

[0180] Fig. Figure 37 is a diagram illustrating a second example of the operating waveform of the proofreading process and the method for using the read amplifier module 29 of the MS storage system according to the fifth embodiment. Fig. Figure 37 illustrates a case in which the proofreading process is performed when the writing process is suspended. In this example, the bottom page is a target to be read. As in Fig. As illustrated in Figure 37, the sequencer 24 recognizes the combined threshold voltage distribution similarly to the first embodiment. Then, during the proofreading process, the sequencer 24 performs three-point reading with the lowest reading voltage R1c used in the page to be read.

[0181] The detection of the combined threshold voltage distribution by the detection circuit 30 is similar to that in the first example of the fifth embodiment. During the calibration read, the sequencer 24 first performs the read processing using the read voltage R5c. When the control signal STB is activated while the read voltage R5c is applied to the selected word line WLsel, the read result (voltage of the read node SEN) is transmitted to the bus LBUS of each read amplifier unit SAU. Then, in each read amplifier unit SAU, the read result transmitted to the bus LBUS is passed to the latch circuit SDL (Best X). Subsequently, a three-point read of the read voltage R1c is performed.

[0182] The three-point read in the second example of the fifth embodiment is performed, for example, with the level 1 or 2 read amplifier unit SAU in the read amplifier module 29, and no other read amplifier units SAU (other) are used. Specifically, the sequencer 24 first stores (transmits) the data (Best X) stored in the latch circuit SDL of the level 1 or 2 read amplifier unit SAU to the read node SEN of another read amplifier unit SAU that shares the DBUS bus. Then, the sequencer 24 loads the selected bit line BLsel and applies the control signal STB three times at different times. After completion of the three-point read operation, the data (Best X) stored in the read node SEN of another read amplifier unit SAU is returned to the latch circuit SDL. Other operations in the second example of the fifth embodiment are similar to those in the first example of the fifth embodiment.

[0183] Other operations of the MS storage system according to the fifth embodiment are similar to those of the first embodiment.

[0184] In the proofreading process of the fifth embodiment, the case in which three-point reading is performed on the state side of the read processing, where the threshold voltage is low, was illustrated by way of example, but the present invention is not limited thereto. The three-point reading in the fifth embodiment can be a read operation in which a plurality of read results are acquired by changing the sampling time without changing the voltage of the selected word line WLsel, and a suitable read voltage is determined based on the acquired plurality of read results. <5-3> Advantageous effects of the fifth embodiment

[0185] In the correction reading process described in the first to fourth embodiments, the displacement of the threshold voltage distribution due to data retention at a different level is estimated based on the displacement information of the threshold voltage distribution on the state side where the threshold voltage is high. Conversely, the influence of the displacement component of the threshold voltage distribution due to the read error with respect to the threshold voltage distribution on the state side where the threshold voltage is low is also significant.

[0186] Therefore, according to the fifth embodiment, the storage device 2 performs a three-point read with respect to the read processing on the state side with a low threshold voltage. As a result, according to the fifth embodiment, the storage device 2 can improve the read accuracy on the state side where the threshold voltage is low. Therefore, according to the fifth embodiment, the storage device 2 can achieve both high speed and high accuracy.

[0187] Furthermore, there is a case where only the read node SEN and the latch circuit SDL can be used for data in the read amplifier unit SAU at the time of suspension of a write operation or similar event. In this case, the normal read operation is performed at the time of suspension by rewriting the data of the latch circuit SDL through a No Lockout (NLK) operation. During the correction read operation at the time of suspension, the NLK operation, in which the latch circuit SDL is not used for charge control of the bit line BL, is executed, and then the read operation limited to level 1 or 2 is performed at the time of the three-point read. Then, at the time of the three-point read, the read result stored in the latch circuit SDL of the read amplifier unit SAU (level 1 or 2) is stored in the read node SEN of the read amplifier unit SAU, which shares the DBUS bus.As described above, the storage system MS according to the fifth embodiment can avoid a deficiency of the latch circuit in the read amplifier unit SAU by using the read node SEN of the read amplifier unit SAU, which shares the DBUS bus.

[0188] In the fifth embodiment, the number of stages of the reading amplifier unit SAU used at the time of three-point reading can be less than the total number of stages. Preferably, the number of stages of the reading amplifier unit SAU used at the time of three-point reading is close to one. <5-4> Further embodiment of the Fifth embodiment

[0189] Fig. Figure 38 is a diagram illustrating an example of an operating waveform of the proofreading process according to a further embodiment of the fifth embodiment. As in Fig. 38 illustrates that in the further embodiment of the fifth embodiment, the search reading is performed in the manner referred to in Fig. The comparative example described in section 20 and the calibration read described in the fifth embodiment are combined. Thus, the calibration read described in the fifth embodiment can be combined with various types of search reads. Consequently, according to a further embodiment of the fifth embodiment, the MS storage system can adjust the read voltage on the low-state side to a preferred voltage and improve the read accuracy. <6> Sixth embodiment

[0190] The memory system MS according to the sixth embodiment detects the combined threshold voltage of the plurality of series-connected memory cell transistors MT in the NAND string NS based on the voltage change of the predetermined node on the bit line side BL during the correction read operation described in the first embodiment. Details of the memory system MS according to the sixth embodiment are described below, primarily with regard to the differences from the first and fifth embodiments. <6-1> Configuration

[0191] First, a configuration of the MS storage system according to the sixth embodiment is described. <6-1-1> Configuration of storage device 2A

[0192] Fig. Figure 39 is a block diagram illustrating an example of a hardware configuration of a storage device 2A included in the MS storage system according to the sixth embodiment. As shown in Fig. As illustrated in Figure 39, the storage device 2A comprises, for example, a memory cell array 20, an input / output circuit 21, a logic controller 22, a register circuit 23, a sequencer 24, a ready / occupied controller 25, a driver circuit 26, a line decoder module 27, a data register 28, a read amplifier module 29 and a detection circuit 40.

[0193] Each configuration of the memory cell array 20, the input / output circuit 21, the logic controller 22, the register circuit 23, the sequencer 24, the ready / occupied controller 25, the driver circuit 26, the line decoder module 27, the data register 28, and the read amplifier module 29 in the sixth embodiment is similar to that in the first embodiment. During the proofreading process, the detection circuit 40 detects the state of the page to be read based on a voltage change at a specific node of the read amplifier module 29. The detection circuit 40 then outputs the detection result to the sequencer 24. As in the first embodiment, the sequencer 24 can determine a shift value of the read voltage used in the proofreading process based on the detection result. <6-1-2> Circuit configuration of the reading amplifier module 29 and the detection circuit 40

[0194] Fig. Figure 40 is a diagram illustrating an example of a circuit configuration of the read amplifier module 29 and the detection circuit 40 in the storage device 2A according to the sixth embodiment. Fig. Figure 40 illustrates part of the configuration of the read amplifier module 29, including transistor T3, of each read amplifier unit SAU. As shown in Fig. As illustrated in Figure 40, the detection circuit 40 includes transistors T40 and 41, a constant current source 41, a comparator 42, and nodes N5 and N6. Each of transistors T40 and T41 is a p-channel MOS transistor.

[0195] One end and one gate of transistor T40 are connected to node N5. The supply voltage VCC, for example, is applied to the other end of transistor T40. One end of transistor T41 is connected to node N6. The supply voltage VCC, for example, is applied to the other end of transistor T41. The gate of transistor T41 is connected to node N5. One end of a current path of constant current source 41 is connected to node N5. The other end of the current path of constant current source 41 is connected to a ground node. The current flowing through node N5 is mirrored to node N6 by transistors T40 and T41, which form a current mirror circuit. The voltage at node N6 is subsequently referred to as voltage VN6.

[0196] Comparator 42 outputs a comparison result between the voltage of the first input side and the voltage of the second input side as an output signal OUT2. For example, the reference voltage VREF is applied to the first input side of comparator 42. The second input side of comparator 42 is connected to node N6. This means that comparator 42 outputs a comparison result between the reference voltage VREF and the voltage VN6 as an output signal OUT2. For example, when each memory cell transistor MT of the NAND string NS is turned on, and the current flowing through transistors T3 and T2 in each read amplifier unit SAU increases, the voltage VN6 drops. Consequently, comparator 42 can detect, for example, that the voltage VN6 is lower than the reference voltage VREF and reflect in the output signal OUT2 that the NAND string NS is turned on.

[0197] As described above, the detection circuit 40 can indirectly detect changes in the current of the source line SL and reproduce the change in the output signal OUT2. Note that the detection circuit 40 can have a different circuit configuration as long as it can detect changes in the current of the NAND array NS. Other configurations of the memory system MS according to the sixth embodiment are similar to those of the first embodiment. <6-2> Operation

[0198] Next, the operation of the MS storage system according to the sixth embodiment will be described. <6-2-1> Proofreading process

[0199] Fig. Figure 41 is a flowchart illustrating an example of a processing operation of a proofreading operation of storage device 2A according to the sixth embodiment. After receiving the instruction to execute the proofreading operation from the memory controller 1, storage device 2A begins a series of processing operations. Fig. 41 (Start).

[0200] First, as in the first embodiment, the storage device 2A applies a search voltage VLUMP to all word lines WL of the selected block BLKsel (step ST20).

[0201] Next, the storage device 2A selects a read voltage correction value based on the time at which the voltage drops at node N6 (step ST40). A multitude of read voltage correction values ​​is prepared in association with each time at which the voltage drops at node N6. Furthermore, the multitude of read voltage correction value sets is stored in a space that sequencer 24 can reference during the correction read operation.

[0202] Next, as in the first embodiment, the storage device 2A performs a calibration read using the read voltage to which the selected correction value is applied (step ST22). After completion of the calibration read, the storage device 2A outputs the read result to the storage controller 1 and terminates the processing sequence. Fig. 41 (End). <6-2-1> Operating waveform of the proofreading process

[0203] Fig. Figure 42 is a diagram showing an example of an operating waveform of the proofreading process of the storage device 2 according to the sixth embodiment. Fig. Figure 42 illustrates a change in the voltage of each of the selected word lines WLsel, node N6, and output signal OUT1, as well as a change in the control signal RRC during proofreading. The control signal RRC is generated, for example, by sequencer 24. In this example, the control signal RRC is used to control the voltage applied to word line WL. As shown in Fig. Figure 42 illustrates that, during the proofreading process of the sixth embodiment, the sequencer 24 performs the processing at times t0 and t1. At the beginning of the proofreading process, the voltage VN6 of node N6 is the ground voltage VSS, and the output signal OUT2 is at a low level.

[0204] At time t0, the sequencer 24, as in the first embodiment, applies the search voltage VLUMP to the selected word line WLsel. The sequencer 24 also increases the voltage VN6 at node N6 from the ground voltage VSS to VDDSA via the detection circuit 40. The voltage VN6 of node N6 is then transferred via the read amplifier unit SAU to the selected bit line BLsel. Subsequently, when the voltage of each word line WL rises and reaches the voltage corresponding to the lower end of the combined threshold voltage distribution, each memory cell transistor MT of the NAND string NS is switched on, and current flows through the NAND string NS between almost all bit lines BL and the source line SL. The voltage VN6 of node N6 then drops due to the overcurrent. The comparator 42 of the detection circuit 40 changes the output signal from a low level to a high level when the dropped voltage VN6 falls below the reference voltage VREF.

[0205] As a result, the sequencer 24 can detect the lower part of the combined threshold voltage distribution and determine the correction value of the read voltage based on the time of detection of the lower part of the combined threshold voltage distribution, as in the first embodiment. Subsequently, the sequencer 24 performs the calibration read similarly to the first embodiment, using the determined correction value of the read voltage.

[0206] In proofread mode, the sequencer 24 continuously sends the control signal RRC as a function of the rise in the word line WL. The control signal RRC indicates the voltage present on the word line WL at the corresponding time. The sequencer 24 can determine the correction value of the read voltage based on the information from the control signal RRC, which is transmitted when the output signal OUT2 reaches the high level. Other operations of the memory system MS according to the sixth embodiment are similar to those of the first embodiment. <6-3> Advantageous effects of the sixth embodiment

[0207] The storage system MS according to the sixth embodiment performs a search read operation to determine the degree of data retention and a calibration read operation during the proofreading process. Then, during the search read operation of the sixth embodiment, the voltages of all word lines WL are increased similarly to the first embodiment, and the detection circuit 40 detects the lower end of the combined threshold voltage distribution based on the change in the voltage VN6 of node N6 of the read amplifier unit SAU.

[0208] Consequently, in the sixth embodiment of the storage device 2, the sequencer 24 can determine the degree of data retention as in the first embodiment and determine a suitable displacement amount of the read voltage. As a result, in the sixth embodiment, it is possible to provide a storage device and a storage system MS that exhibit high reliability and operate at high speed.

[0209] Note that in the sixth embodiment, the detection circuit 40 can be implemented by extending the existing circuitry of a peripheral circuit. Therefore, it is easy to switch from the existing circuit, and in some cases, it is also possible to refine it. The impact on the circuit area can be minimized. In the storage device 2 according to the sixth embodiment, the voltage of the source line SL during read operation can be set to the ground voltage VSS instead of the voltage VSRC. That is, the correction read operation described in the sixth embodiment is not limited to the case of negative sampling. <7> Miscellaneous

[0210] In the memory controller 1 of the above embodiments, a microprocessing unit (MPU) can be used instead of the CPU 12. Furthermore, each of the processing operations described above can be performed by a dedicated hardware circuit, a processor executing a program (firmware), or a combination thereof. The CPU 12 can also be referred to as the processor. The sequencer 24 can be referred to as the controller. The activation of the control signal STB by the sequencer 24 corresponds to an operation in which the control signal STB is temporarily changed from a low level to a high level, or an operation in which the control signal STB is temporarily changed from a high level to a low level.

[0211] The above embodiments described the case in which the read processing is performed using the higher read voltage in the order of the read operation, but the present invention is not limited to this. During the read operation, the read processing can also be performed using the lower read voltage in the order of the read operation. In the first to fifth embodiments, the information from the control signal RRC described in the sixth embodiment can be used to determine the time at which the lower edge of the combined threshold voltage distribution is detected.

[0212] The command sequences presented above are merely an example. The page to be read can be specified by the address ADD. Any number can be applied to "xxh" and "yyh". The flowcharts used in the description above are merely examples. Further processing can be added to the flowcharts shown. In this description, the term "couple" refers to electrical coupling and does not preclude the insertion of another element in between. "Electrical coupling" can be achieved via an insulator, as long as it can function in the same way as an electrical coupling. The word line WL, the select-gate lines SGD and SGS, and the like can simply be referred to as "connections".

[0213] The high-level voltage is a voltage at which the n-channel MOS transistor, to which the voltage with the gate level is applied, is switched on, and the p-channel MOS transistor, to which the voltage with the gate level is applied, is switched off. The low-level voltage is a voltage at which the n-channel MOS transistor, to which the voltage with the gate level is applied, is switched off, and the p-channel MOS transistor, to which the voltage with the gate level is applied, is switched on. In this specification, applying a voltage to the word line WL corresponds to applying a voltage to the word line WL by the driver circuit 26 via the line decoder module 27. Similarly, applying the voltage to the other connections corresponds to applying the voltage by the driver circuit 26 via the line decoder module 27.The voltage of each connection can be estimated based on the voltage of the signal line connecting the driver circuit 26 and the line decoder module 27.

[0214] Some or all of the embodiments described above may be described as in the following supplementary notes, but are not limited to them: [Supplementary Note 1]

[0215] A storage device comprising: a plurality of strings (NS), each of which contains a plurality of serially connected memory cells (MT); a plurality of bit lines (BL), wherein one end of each of the strings is connected to a different bit line among the bit lines; a multitude of word lines (WL), each of which is connected to the memory cells in each of the strings; a source line (SL), with the other end of each string connected to the source line; and a controller (24) configured to perform a first read operation with a first read sequence and a second read sequence, wherein the controller is also configured: in the first reading sequence, to increase the voltages of the word lines at the same rate and to determine a correction value for each of a multitude of reading voltages based on a timing in which a current through the strings changes with an increase in the voltages of the word lines; and In the second reading sequence, a reading process is to be carried out with the reading tensions to which the correction value is applied. [Supplementary Note 2]

[0216] The storage device of supplementary note 1, wherein In a case where each of the bit lines is a destination to be read in the first read operation, the control unit is further configured to: to load only some of the bit lines when a voltage is applied to the word lines in the first read sequence; and to charge the bit lines when a read voltage is applied to the word lines in the second read sequence. [Supplementary Note 3]

[0217] The storage device of supplementary note 2, which also includes: a driver circuit configured to apply a voltage to the word lines, whereby the strings contain several first strings connected to some bit lines, and several second strings connected to other bit lines, and The interval between the driver circuit and a connecting part between the word lines is larger in the second strings than in the first strings. [Supplementary Note 4]

[0218] The storage device of supplementary note 1, furthermore comprising: an error amplifier (261) configured to maintain a constant voltage on the source line; and a first detection circuit (30) configured to determine the timing based on a comparison result between a first reference current, which changes based on an output signal of the error amplifier, and a second reference current, which is controlled to be constant, and to inform the control about a determination result. [Supplementary Note 5]

[0219] The storage device of supplementary note 1, furthermore comprising: a plurality of read amplifiers (SAUs), each connected to the bit lines, each of the read amplifiers being configured to transmit a voltage applied to a first node (N6) to an associated bit line; and a second detection circuit (40) configured to determine the timing based on a comparison result between a voltage of the first node, which changes based on a current flowing through the bit lines, and a reference voltage, which is controlled to be constant, and to inform the control about a determination result. [Supplementary Note 6]

[0220] The storage device of Supplementary Note 1, wherein the controller is also configured as follows: to perform a second reading process with a preset reading voltage; to apply a first voltage (VPASS) to an unselected word line, while a reading voltage is applied to a selected word line in the second reading operation; and a rate of increase of the voltages of the word lines in a first period (TP) that is included in the first reading sequence is lower than a rate of increase when the first voltage is applied to the unselected word line. [Supplementary Note 7]

[0221] The storage device of supplementary note 6, wherein the controller is also configured In the first reading sequence, up to the beginning of the first period, the rate of increase of the voltages of the word lines is to be adjusted so that it is similar to the rate of increase when the first voltage is applied to the unselected word line in the second reading process. [Supplementary Note 8]

[0222] The storage device of supplementary note 1, wherein the controller is also configured to increase the tensions of the word lines to a second tension (VLUMP) and then decrease the tensions of the word lines in the first reading sequence, and to detect the timing based on a decrease in the current through the strings when the voltages of the word lines decrease. [Supplementary Note 9]

[0223] The storage device of supplementary note 1, wherein The controller is also configured in the first read sequence: to apply a third voltage (R1) to an unselected word line before it is written under unselected word lines; and to apply a fourth voltage (VLUMP), which is higher than the third voltage, to a written, unselected word line. [Supplementary Note 10]

[0224] A storage system, comprehensive: the storage device in accordance with Supplementary Note 9; and a memory controller (1) configured to transmit information indicating whether an unselected word line associated with a block to be read has been written to the storage device prior to the first read operation. [Supplementary Note 11]

[0225] The storage device of supplementary note 1, wherein the strings are divided into a multitude of subblocks (SBLK), and In the first reading sequence, the rate of increase of the voltage of an unselected word line connected to an unselected subblock among the subblocks is faster than the rate of increase of the voltage of an unselected word line connected to a selected subblock among the subblocks. [Supplementary Note 12]

[0226] The storage device of supplementary note 1, wherein The highest reading voltage among the reading voltages used in the reading process is lower than the voltage present at the word lines at the time of timing. [Supplementary Note 13]

[0227] A storage system with: the storage device in accordance with Additional Note 1; and a memory controller (1) configured to instruct the storage device to perform a second read operation using a preset read voltage based on a command from an external host device, and in a case where error correction of data read from the storage device by the second read operation fails, instructs the storage device to perform the first read operation selecting the same word line. [Supplementary Note 14]

[0228] A storage device comprising: a plurality of strings (NS), each of which contains a plurality of serially connected memory cells (MT); a plurality of bit lines (BL), wherein one end of each of the strings is connected to a different bit line among the bit lines; a multitude of word lines (WL), each of which is connected to the memory cells in each of the strings; a source line (SL), with the other end of each string connected to the source line; and a controller (24) configured to perform a first read operation with a first read sequence and a second read sequence, wherein the controller is also configured: to look for a suitable level of reading tension in the first reading sequence; in the second reading sequence; to perform a reading operation using the desired suitable reading voltage; and While the lowest read voltage is applied, a large number of read operations are performed, and furthermore, the final read operation is performed based on a result of the bit counting during each of the read operations. [Supplementary Note 15]

[0229] The storage device of supplementary note 14, furthermore comprising: a multitude of read amplifiers (SAU), each connected to the bit lines, wherein The controller is further configured to perform the read times using some of the read amplifiers. [Supplementary Note 16]

[0230] The storage device of supplementary note 15, wherein Each of the reading amplifiers contains a first latch circuit and a second latch circuit, and the controller is also configured: to cause the first intermediate storage circuit to hold a read result using the preferred read voltage used in the second read sequence; To transfer data held in the first latch circuit of some read amplifiers to the second latch circuit before the read times; and Before the final reading, the data stored in the second latch circuit of the read amplifiers is transferred to the first latch circuit. [Supplementary Note 17]

[0231] The storage device of supplementary note 16, wherein Each of the read amplifiers contains a first latch circuit and a read node (SEN), and the controller is also configured: to cause the first intermediate storage circuit to hold a read result using the preferred read voltage used in the second read sequence; To transfer data held in the first latch circuit of some read amplifiers to the read node of another read amplifier before the read times; and Before the final read, data stored in the read node of the other read amplifier is transferred to the first latch circuit of the two read amplifiers. [Supplementary Note 18]

[0232] The storage device of supplementary note 14, wherein the controller is also configured In the first reading sequence, the voltages of the word lines are increased at the same rate, and a suitable reading voltage is determined based on a timing in which the amount of current through the strings changes with the increase in the voltages of the word lines. [Supplementary Note 19]

[0233] The storage device of supplementary note 1, wherein the controller is also configured In the first read sequence, a read processing operation is performed using a variety of voltages close to a highest read voltage, and a suitable read voltage is determined, which is used in the second read sequence based on a result of each bit count of the read processing operation using the voltages. [Supplementary Note 20]

[0234] A storage system, comprehensive: the storage device in accordance with Supplementary Note 14; and a storage controller (1) configured to instruct the storage device to perform a second read operation using a preset read voltage based on a command from an external host device, and in a case where error correction of data read from the storage device by the second read operation fails, instructs the storage device to perform the first read operation selecting the same word line.

[0235] Although certain embodiments have been described, these embodiments are presented only as examples and are not intended to limit the scope of the inventions. The novel devices and methods described herein can be embodied in a multitude of other forms; moreover, various omissions, substitutions, and modifications to the form of the embodiments described herein can be made without departing from the spirit of the inventions. The appended claims and their equivalents are intended to cover such forms or further embodiments that fall within the scope and spirit of the inventions.

Claims

[1] Storage device comprising: a plurality of strings (NS), each of which contains a plurality of serially connected memory cells (MT); a plurality of bit lines (BL), wherein one end of each of the strings is connected to another bit line among the bit lines; a multitude of word lines (WL), each of which is connected to the memory cells in each of the strings; a source line (SL), with the other end of each string connected to the source line; and a controller (24) configured to perform a first read operation with a first read sequence and a second read sequence, wherein the controller is also configured: in the first read sequence, to increase the voltages of the word lines at the same rate and to determine a correction value for each of a multitude of read voltages based on a timing in which a current through the strings changes with an increase in the voltages of the word lines; and In the second reading sequence, a reading process is to be carried out with the reading tensions to which the correction value is applied. [2] Storage device according to claim 1, wherein in a case where each of the bit lines is a destination that The control unit is further configured to: in the first read operation, the control unit is to be read. to load only some of the bit lines when a voltage is applied to the word lines in the first read sequence; and to charge the bit lines when a read voltage is applied to the word lines in the second read sequence. [3] Storage device according to claim 2, further comprising: a driver circuit configured to apply a voltage to the word lines, whereby the strings comprise several first strings connected to some bit lines, and several second strings connected to other bit lines, and The interval between the driver circuit and a connecting part between the word lines is larger in the second strings than in the first strings. [4] Storage device according to claim 1, further comprising: an error amplifier (261) configured to maintain a constant voltage on the source line; and a first detection circuit (30) configured to determine the timing based on a comparison result between a first reference current, which changes based on an output signal of the error amplifier, and a second reference current, which is controlled to be constant, and to inform the controller of a determination result. [5] Storage device according to claim 1, further comprising: a plurality of read amplifiers (SAUs), each connected to the bit lines, each of the read amplifiers being configured to transmit a voltage applied to a first node (N6) to an associated bit line; and a second detection circuit (40) configured to determine the timing based on a comparison result between a voltage of the first node, which changes based on a current flowing through the bit lines, and a reference voltage, which is controlled to be constant, and to inform the control about a determination result. [6] Storage device according to claim 1, wherein the controller is further configured as follows: to perform a second reading process with a preset reading voltage; to apply a first voltage (VPASS) to an unselected word line, while a reading voltage is applied to a selected word line in the second reading operation; and a rate of increase of the voltages of the word lines in a first period (TP) that is included in the first reading sequence is lower than a rate of increase when the first voltage is applied to the unselected word line. [7] Storage device according to claim 6, wherein the controller is also configured In the first reading sequence, up to the beginning of the first period, adjust the rate of increase of the voltages of the word lines so that they are similar to the rate of increase when the first voltage is applied to the unselected word line in the second reading process. [8] Storage device according to claim 1, wherein the controller is also configured to increase the tensions of the word lines to a second tension (VLUMP) and then decrease the tensions of the word lines in the first reading sequence, and to detect the timing based on a decrease in the current through the strings when the voltages of the word lines decrease. [9] Storage device according to claim 1, wherein in the first read sequence the controller is further configured: to apply a third voltage (R1) to an unselected word line before it is written between unselected word lines; and to apply a fourth voltage (VLUMP), which is higher than the third voltage, to a written, unselected word line. [10] Storage system, comprising: the storage device according to claim 9; and a memory controller (1) configured to transmit information indicating whether an unselected word line associated with a block to be read has been written to the storage device prior to the first read operation. [11] Storage device according to claim 1, wherein the strings are divided into a multitude of subblocks (SBLK), and In the first reading sequence, the rate of increase of the voltage of an unselected word line connected to an unselected subblock among the subblocks is faster than the rate of increase of the voltage of an unselected word line connected to a selected subblock among the subblocks. [12] Storage device according to claim 1, wherein the highest read voltage among the read voltages used during the read operation is lower than the voltage applied to the word lines at the time of timing. [13] Storage system, comprising: the storage device according to claim 1; and a storage controller (1) configured to instruct the storage device to perform a second read operation using a preset read voltage based on a command from an external host device, and in a case where error correction of data read from the storage device by the second read operation fails, instructs the storage device to perform the first read operation selecting the same word line. [14] Storage device comprising: a plurality of strings (NS), each of which contains a plurality of serially connected memory cells (MT); a plurality of bit lines (BL), wherein one end of each of the strings is connected to a different bit line among the bit lines; a multitude of word lines (WL), each of which is connected to the memory cells in each of the strings; a source line (SL), with the other end of each string connected to the source line; and a controller (24) configured to perform a first read operation with a first read sequence and a second read sequence, wherein the controller is also configured: to look for a suitable reading tension in the first reading sequence; in the second reading sequence; to perform a reading operation using the desired suitable reading voltage; and While the lowest read voltage is applied, a large number of read operations are performed, and furthermore, the final read operation is performed based on a result of the bit counting during each of the read operations. [15] Storage device according to claim 14, further comprising: a multitude of read amplifiers (SAU), each connected to the bit lines, wherein The controller is further configured to perform the read times using some of the read amplifiers. [16] Storage device according to claim 15, wherein Each of the reading amplifiers contains a first latch circuit and a second latch circuit, and the controller is also configured: to cause the first latch circuit to hold a read result using the preferred read voltage used in the second read sequence; To transfer data held in the first latch circuit of some read amplifiers to the second latch circuit before the read times; and Before the final reading, the data stored in the second latch circuit of the read amplifiers is transferred to the first latch circuit. [17] Storage device according to claim 16, wherein Each of the read amplifiers contains a first latch circuit and a read node (SEN), and the controller is also configured: to cause the first intermediate storage circuit to hold a read result using the preferred read voltage used in the second read sequence; To transfer data held in the first latch circuit by some of the read amplifiers to the read node of another read amplifier before the read times; and Before the final read, data stored in the read node of the other read amplifier is transferred to the first latch circuit of the two read amplifiers. [18] Storage device according to claim 14, wherein the controller is also configured In the first reading sequence, the voltages of the word lines are increased at the same rate, and a suitable reading voltage is determined based on a timing in which the amount of current through the strings changes with the increase in the voltages of the word lines. [19] Storage device according to claim 1, wherein the controller is also configured In the first read sequence, a read processing operation is performed using a variety of voltages close to a highest read voltage, and a suitable read voltage is determined, which is used in the second read sequence based on a result of each bit count of the read processing operation using the voltages. [20] Storage system, comprising: the storage device according to claim 14; and a storage controller (1) configured to instruct the storage device to perform a second read operation using a preset read voltage based on a command from an external host device, and in a case where error correction of data read from the storage device by the second read operation fails, instructs the storage device to perform the first read operation selecting the same word line.

Images