SYSTEM ON INTEGRATED CHIPS AND METHOD FOR FORMING

Abstract

A semiconductor device (for example, a system-on-integrated chip (SoIC) device) is formed by vertically integrating (for example, bonding) semiconductor dies, each of which has a front-side interconnect structure and a back-side interconnect structure. A front-to-front bonding process is used to bond the integrated semiconductor dies, reducing the length of the communication paths between them. The reduced length of these communication paths lowers their electrical resistance and signal transmission delay, thereby improving the processing speed of the semiconductor device and reducing its power consumption.Furthermore, the bonding film stack around the bonding structure of the semiconductor dies can be formed thinner, which reduces the risk of metal cracking and thus improves the reliability and production yield of the devices.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US patent application No. 63 / 694,249, filed on September 13, 2024, entitled “SPR on SoIC Signal to Signal Bonding W / BPV Landing on Metal Structure”, which is hereby incorporated in full by reference into the present text. BACKGROUND

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material onto a semiconductor substrate. These material layers are then patterned using lithography to create circuit components and elements. Typically, dozens or hundreds of integrated circuits are fabricated on a single semiconductor wafer. The individual dies are separated by sawing the integrated circuits along a score line. These individual dies are then encapsulated separately, for example, in multi-chip modules or other encapsulation methods.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest possible feature size, thus enabling the integration of more components in a given area. As feature sizes become increasingly smaller in advanced semiconductor manufacturing nodes, new challenges arise that must be addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figures 1-4 illustrate cross-sectional views of a semiconductor die at different manufacturing stages according to one embodiment. Fig. Figure 5 illustrates a cross-sectional view of a wafer according to one embodiment. Fig. Figures 6-8 illustrate cross-sectional views of a semiconductor device at various manufacturing stages according to one embodiment. Fig. 9A and Fig. Figure 9B illustrates exemplary cross-sectional views of a bonding structure according to some embodiments. Fig. 10 and Fig. Figure 11 illustrates cross-sectional views of a semiconductor device at various manufacturing stages according to another embodiment. Fig. Figures 12-16 illustrate cross-sectional views of a semiconductor device at various manufacturing stages according to a further embodiment. Fig. Figure 17 illustrates a flowchart of a process for forming a semiconductor device in some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the invention. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.Throughout this description, unless otherwise stated, identical or similar reference numerals in different figures refer to the same or a similar component formed by the same or a similar process using one or more identical or similar materials.

[0006] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0007] According to some embodiments, a semiconductor device (for example, a system-on-integrated chip (SoIC) device) is formed by vertically integrating (for example, bonding) semiconductor dies, each semiconductor die having a backside power distribution network (PDN) formed by a backside interconnect structure. A front-to-front bonding process is used to bond the integrated semiconductor dies, reducing the length of the communication paths between them. The reduced communication path lengths decrease the electrical resistance and signal transmission delay of the communication paths, thereby improving the processing speed of the semiconductor device and reducing power consumption.Furthermore, the bonding film stack around the bonding structure of the semiconductor dies can be formed thinner, which reduces the risk of metal cracking and thus improves the reliability and production yield of the devices.

[0008] Fig. Figures 1-4 illustrate cross-sectional views of a semiconductor die 150 at various fabrication stages according to one embodiment. As will be discussed in more detail below, several semiconductor dies 150 are formed on a wafer 100, and the wafer 100 is then singulated by a separation process to form several individual (for example, separate) semiconductor dies 150.

[0009] Fig. Figure 1 illustrates a cross-sectional view of a wafer 100 at an early stage of fabrication. For clarity, only one section of the wafer 100 is shown, and not all structural elements of the wafer 100 are illustrated. The illustrated section of the wafer 100 may represent one of the semiconductor dies (see Figure 150 in Figure 1). Fig. 4) correspond to those formed on wafer 100.

[0010] As in Fig. As illustrated in Figure 1, the wafer 100 comprises a substrate 101, electrical components 103 formed on the substrate 101, one or more dielectric layers 107 over the substrate 101 and around the electrical components 103, and interconnect structures 112 over the one or more dielectric layers 107.

[0011] Substrate 101 can be a semiconductor substrate (for example, a silicon substrate), doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon-germanium, SOI, silicon-germanium on insulator (SGOI), or combinations thereof. Other substrates that can be used are multilayer substrates, gradient substrates, or hybrid orientation substrates. In one embodiment, substrate 101 is a silicon substrate (for example, a bulk silicon substrate).

[0012] The electrical components 103 comprise a wide variety of active devices (for example, transistors) and passive devices (for example, capacitors, resistors, inductors), and the like. The electrical components 103 can be formed either within or on the substrate 101 using any suitable method. For example, the electrical components 103 can include fin field-effect transistors (FinFETs) that have fins extending beyond the substrate 101, gate structures over the fins, and source / drain regions over the fins on opposite sides of the gate structures.As another example, the electrical components 103 can include nanostructured field-effect transistors (NSFETs) (for example, gate all-around transistors (GAA transistors)) which have fins extending beyond the substrate 101, nanostructures (for example, nanolayers or nanowires) over the fins, gate structures around the nanostructures, and source / drain regions over the fins on opposite sides of the gate structures.

[0013] One or more dielectric layers 107, such as one or more inter-layer dielectric (ILD) layers (for example, a first ILD layer and a second ILD layer), are formed over the substrate 101 and around the electrical components 103.In some embodiments, each of the ILD layers is formed from a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and can be deposited by any suitable process, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), flowable CVD (FCVD) (for example, CVD-based material deposition in a non-contact plasma system and post-curing to convert it into another material, such as an oxide), or the like.

[0014] Fig. Figure 1 further illustrates contact plugs 109 (for example, vias) formed in one or more dielectric layers 107, such as source / drain contact plugs and gate contact plugs, which are electrically coupled to the source / drain regions and gate structures of the transistors, respectively. The contact plugs 109 can be formed, for example, by creating contact openings in one or more dielectric layers 107 and filling the contact openings with an electrically conductive material (for example, tungsten, cobalt, copper, or the like). A lining material, such as titanium, titanium nitride, tantalum, or tantalum nitride, can be formed to line the sidewalls of the contact openings before the electrically conductive material fills the contact openings.After the contact openings are filled, a planarization process, such as a chemical-mechanical planarization (CMP) process, can be performed to achieve a coplanar surface between the contact plugs 109 and the one or more dielectric layers 107. For the sake of simplicity in this text, the electrical components 103, the contact plugs 109, and the one or more dielectric layers 107 can be collectively referred to as a device layer 108.

[0015] Next, interconnect structures 112 (also called front-side interconnect structures) are formed on one or more dielectric layers 107. The interconnect structure 112 of each semiconductor die connects the respective electrical components 103 of the semiconductor die to form a functional circuit of the semiconductor die. The interconnect structure 112 comprises one or more dielectric layers 111 and conductive structural elements (for example, conductive traces 115 and vias 113) formed in the one or more dielectric layers 111.The one or more dielectric layers 111 can be formed from a suitable dielectric material such as silicon oxide, silicon nitride, dielectrics with low k-values ​​such as carbon-doped oxides, dielectrics with extremely low k-values ​​such as porous carbon-doped silicon dioxide, combinations thereof, or the like. The one or more dielectric layers 111 can be formed by a process such as CVD, although any suitable process may be used. The conductive traces 115 and the vias 113 can be formed from a conductive material, such as copper, using any suitable formation process, such as deposition, damascening, dual damascening, or the like.It should be noted that in this discussion, unless otherwise stated, the term ‘conductive’ means ‘electrically conductive’ (for example, as opposed to ‘thermally conductive’).

[0016] Fig. Figure 1 further illustrates conductive structural elements 117 formed on a surface of the interconnect structure 112 located distal to the substrate 101. The conductive structural elements 117 can be, for example, conductive pads such as copper pads. Figure 1 also illustrates... Fig. 1 Silicon through-silicon vias (TSVs) 105. In the illustrated embodiment, the TSVs 105 extend from the conductive structural elements 117 through the interconnect structure 112, through the device layer 108, and into the substrate 101. It should be noted that at this stage of processing, the TSVs 105 are located in Fig. 1 into substrate 101, but not through substrate 101.

[0017] Next, in Fig. 2. A support substrate 123 (which can also be referred to as a support) is attached to the interconnect structure 112. The support substrate 123 (or another support substrate, which will be discussed further below) is a silicon substrate (for example, a bulk silicon substrate, such as a silicon wafer) in which, in some embodiments, no electrical components are formed. In addition to a silicon substrate, any other suitable support substrate can also be used. The support substrate 123 can be attached to the interconnect structure 112 using an adhesive layer 121.

[0018] Next, a thinning process is performed to reduce the thickness of the substrate 101 such that the end faces of the TSVs 105 are exposed on a surface of the substrate 101 facing away from the support substrate 123. The thinning process may include a planarization process (for example, mechanical grinding, CMP, or the like), a back-etching process, a combination thereof, or the like. In some embodiments, the thickness of the substrate 101 after the thinning process is less than approximately 100 nm.

[0019] Next, interconnect structures 132 (also referred to as backside interconnect structures) are formed on the back side of the substrate 101. The interconnect structures 132 comprise one or more dielectric layers 131 and conductive structural elements (for example, conductive lines 135 and vias 133) formed within the one or more dielectric layers 131. The one or more dielectric layers 131 and conductive structural elements (for example, conductive lines 135 and vias 133) of the interconnect structure 132 can be formed from one or more identical or similar materials using the same or similar formation process as the one or more dielectric layers 111 and the conductive structural elements (for example, conductive lines 115 and vias 113) of the interconnect structure 112, therefore no details are repeated here.

[0020] As in Fig. As illustrated in Figure 2, the conductive structural elements of the interconnect structure 132 are electrically coupled to the electrical components 103 and the TSVs 105. For example, vias 139 can be formed such that they extend through the substrate 101 and electrically couple the conductive structural elements of the interconnect structure 132 to the electrical components 103. In some embodiments, the vias 139 extend from the back of the substrate 101 to the front of the substrate 101 and are, for example, electrically coupled to source / drain regions and / or gate structures of the transistors of the electrical components 103. In this discussion, the front of the substrate 101 refers to the side of the substrate 101 facing the electrical components 103, and the back of the substrate 101 refers to the side of the substrate 101 facing away from the electrical components 103.

[0021] As in Fig. As illustrated in Figure 2, the TSVs 105, which extend through the thinned substrate 101, are electrically coupled to conductive structural elements of the interconnect structure 132. Conductive structural elements 137 (for example, copper pads) of the interconnect structure 132 are formed on a surface of the interconnect structure 132 that faces away from the substrate 101.

[0022] In some embodiments, the conductive lines 135 of the rear interconnect structures 132 are busbars, that is, conductive lines that electrically connect the electrical components 103 to a reference voltage (for example, electrical ground), a supply voltage (for example, +1.5 V, +3 V, +5 V, or the like), or the like. In other words, unlike the front interconnect structure 112, which routes data and control signals, in some embodiments the rear interconnect structures 132 are used to route power signals (for example, supply voltage, reference voltage). By placing busbars on the rear side of the resulting semiconductor die instead of on the front side, advantages can be realized. For example, the gate density of the FinFETs (or NSFETs) and / or the interconnect density of the front interconnect structure 112 can be increased.Furthermore, the back side of the semiconductor die can accommodate wider busbars, thereby reducing resistance and increasing the efficiency of power supply to the electrical components 103. For example, the width T2 of the conductive traces 135 of the back-side interconnect structure 132 can be at least twice the width T1 of the conductive traces 115 of the front-side interconnect structure 112.

[0023] In the example of Fig. 2 The rear interconnect structure 132 further comprises capacitors 142 formed between laterally adjacent conductive lines 135. In one embodiment, each capacitor 142 comprises a first depletion layer 141A along a first side wall of a first conductive line 135, a second depletion layer 141B along a second side wall of a second conductive line 135 located laterally adjacent to the first conductive line 135, and a high k-value dielectric material 143 between the first depletion layer 141A and the second depletion layer 141B. The high k-value dielectric material 143 completely fills the space between the first depletion layer 141A and the second depletion layer 141B (for example, it extends continuously from the first depletion layer 141A to the second depletion layer 141B).

[0024] The first junction 141A and the second junction 141B can be formed from a conductive material such as tantalum nitride, titanium nitride, tantalum, titanium, or the like, and function as the electrodes of the capacitor 142. The high k-value dielectric material 143 can have a k-value greater than approximately 7.0 (for example, between approximately 7.0 and approximately 40) and can contain metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The high k-value dielectric material 143 acts as the dielectric medium between the electrodes of the capacitor 142. The capacitor 142 can be described as a metal-insulator-metal (MIM) capacitor or a MIM capacitor embedded in the rear interconnect structure 132.In some embodiments, the rear interconnect structure 132 is used to distribute power for the formed semiconductor device and can be referred to as a rear power distribution network (PDN). The embedded MIM capacitors 142 can be used to form circuits and / or to stabilize voltages (for example, reference voltages, supply voltages) in the PDN, thereby achieving improved performance for the formed device.

[0025] Next, in Fig. 3. A carrier substrate 145 is attached to the rear interconnect structure 132. In some embodiments, an adhesive layer (not shown separately) is used to attach the carrier substrate 145 to the rear interconnect structure 132. Next, the carrier substrate 123 (see Fig. 2) for example, by mechanically peeling off the carrier substrate 123, by a grinding process, an etching process, combinations thereof, or the like. The adhesive layer 121 can be removed together with the carrier substrate 123. In some embodiments, after removal of the carrier substrate 123, residues of the adhesive layer 121 are removed by a cleaning process (for example, an etching process) such that the conductive structural elements 117 on the surface of the front interconnect structure 112, which is located distal to the substrate 101, are exposed.

[0026] Next, a bonding film stack 151 is formed on the front interconnect structure 112, and bonding structures 154 are formed (e.g., embedded) within the bonding film stack 151. In some embodiments, the bonding film stack 151 comprises multiple dielectric layers, and each of the bonding structures 154 includes a bonding pad 153 and a bonding pad via 155. The bonding pad 153 (e.g., a copper pad) may have a coplanar surface with the bonding film stack 151, with the coplanar surface facing away from the substrate 101. The BPV 155 (e.g., a copper via) is positioned between the bonding pad 153 and a respective conductive structure 117 of the front interconnect structure 112, electrically coupling these two. It should be noted that some of the bonding structures 154 are electrically coupled to the TSVs 105.Examples of the bonding structure 154 and the bonding film stack 151 are in the . Fig. 9A and Fig. 9B shown.

[0027] We are temporarily turning Fig. 9A, which illustrates an example of the bonding structure 154 and the bonding film stack 151. To illustrate the electrical connection of the bonding structure 154, in Fig. 9A also illustrates the conductive structure 117 and one of the dielectric layers 111 of the front interconnect structure 112, with the understanding that the conductive structure 117 and the dielectric layers 111 are not part of the bonding structure 154 or the bonding film stack 151.

[0028] In the example of Fig. In 9A, the bonding film stack 151 comprises a bonding film 151A, a dielectric layer 151B, a dielectric layer 151C, a dielectric layer 151D, a dielectric layer 151E, and an etch stop layer (ESL) 151F. The bonding pad 153 of the bonding structure 154 is formed (e.g., embedded) in the bonding film 151A, the dielectric layer 151B, and the dielectric layer 151C. The bonding pad 155 is formed (e.g., embedded) in the dielectric layer 151D, the dielectric layer 151E, and the ESL 151F. In other words, the top surface of the bonding pad 153 is flush with the top surface of the bonding film 151A, and the bottom surface of the bonding pad 153 is flush with the bottom surface of the dielectric layer 151C. Similarly, the top of the BPV 155 is flush with the top of the dielectric layer 151D, and the bottom of the BPV 155 is flush with the bottom of the ESL 151F.

[0029] In some embodiments, the bonding pad 153 and the BPV 155 are formed by performing several etching processes to create a pad opening and a via opening in the respective layers of the bonding film stack 151, and by filling the pad opening and the via opening with a conductive material (for example, copper). Next, a planarization process, such as CMP, can be performed to remove excess portions of the conductive material located outside the pad opening and the via opening. The remaining portions of the conductive material in the pad opening and the via opening form the bonding pad 153 and the BPV 155, respectively.

[0030] In some embodiments, both the bonding film 151A and the dielectric layers 151B - 151E are produced using a suitable dielectric material such as SiO2, SiN, SiON, SiC, SiCN, SiCO, AlN, GaN, ZnO, BN, Al2O xThe ESL 151F can be formed, for example, using hydrogen and nitrogen doped carbide (HNDC) or SiN. In some embodiments, adjacent layers of the bonding film stack 151 are formed from different dielectric materials to provide etch selectivity between the adjacent layers, enabling simple control (e.g., control of the etch stop point) of the etching processes used to form the pad opening and the via opening.Furthermore, the materials of the uppermost dielectric layers in the bonding film stack 151, such as the bonding film 151A and the dielectric layers 151B and 151C, can be selected to control the warping of the top surface 151U of the bonding film stack 151 and to achieve a desired profile (for example, a flat surface or a concave or convex surface with a desired curvature). In subsequent processing, the wafer 100 is separated into individual semiconductor dies 150, and the semiconductor dies 150 are attached (for example, bonded) to a wafer 200 in a bonding process (see, for example, Figure 1). Fig. 6) In some embodiments, due to the process conditions and / or the manufacturing tooling used in the bonding process, a specific profile of the semiconductor die 150 can contribute to achieving reliable bonding between the semiconductor die 150 and the wafer 200. The materials of the top dielectric layers (for example, 151A, 151B, and 151C) of the bonding film stack 151 can advantageously be selected such that the desired profile for the bonding process is achieved according to the profile of the bonding surface of the wafer 200. Furthermore, the materials of the dielectric layers of the bonding film stack 151 are selected to have good thermal conductivity in order to avoid or reduce problems such as warping, delamination, or cracking caused by stresses due to temperature changes.

[0031] In some embodiments, the thickness (for example, along the vertical direction of Fig. The thickness (measured at 9A) of each dielectric layer of the bonding film stack 151 is between approximately 10 nm and approximately 1000 nm. The thickness of the conductive structure 117 can be between approximately 70 nm and approximately 250 nm. The ratio between a width W1 of the bonding film stack 151, measured at an interface between the bonding film stack 151 and the conductive structure 117, and a width W2 of the conductive structure 117 is between approximately 0.025 and approximately 1 (for example, 0.025 ≤ W1 / W2 ≤ 1).

[0032] Fig. Figure 9B illustrates another example of the bonding structure 154 and the bonding film stack 151. In Fig. In 9B, the bonding film stack 151 has a smaller number of dielectric layers than the bonding film stack 151 in Fig. 9A, and the bonding pad 153 in Fig. 9B is formed (for example, embedded) in the bonding film 151A. In particular, the bonding film stack 151 comprises Fig. 9B the bonding film 151A, the dielectric layers 151D and 151E, and the ESL 151F. The BPV 155 is formed (for example, embedded) in the dielectric layer 151D, the dielectric layer 151E, and the ESL 151F. In some embodiments, the materials of adjacent dielectric layers in the bonding film stack 151 are in Fig. 9B is different to provide etch selectivity, and the materials of the bonding film 151A and the dielectric layer 151D are chosen to achieve a desired profile for the subsequently formed semiconductor dies 150 in order to achieve reliable bonding of the semiconductor dies 150 as discussed above.

[0033] We now turn Fig. 4 to. After the in Fig. In the illustrated processing step 3, a separation process is carried out to isolate the wafer 100 into several individual (for example, separate) semiconductor dies 150 (which can also be referred to as dies). The separation process can be carried out, for example, using a plasma separation process along separation regions (indicated by the dashed lines 165) around the semiconductor dies 150. The separation process can start from the side of the wafer 100 where the bonding film stack 151 is located, in the direction of the support substrate 145. Fig. Figure 4 illustrates trenches formed by the separation process in the wafer 100. The separation process continues until the trenches extend through the support substrate 145, thereby dividing the wafer 100 into several separate semiconductor dies 150. In other words, after the separation process is complete, the section of wafer 100 illustrated between the dashed lines 165 corresponds to one semiconductor die 150.

[0034] Fig. Figure 5 illustrates a cross-sectional view of a wafer 200 according to one embodiment. The wafer 200 is similar to the wafer 100 in Figure 5. Fig. 3 and can be formed using the same or a similar formation process as wafer 100, therefore no details are repeated. In Fig. 5 corresponds to a component with a reference number beginning with the digit "2" (for example, 2XY), the same or a similar component in Fig. 3 with a reference number that begins with the digit "1" (for example, 1XY). For example, substrate 201 of wafer 200 corresponds to substrate 101 of wafer 100. As another example, the front-side interconnect structure 212 of wafer 200 corresponds to the front-side interconnect structure 112 of wafer 100. As yet another example, the bonding structure 254 of wafer 200 corresponds to the bonding structure 154 of wafer 100. It should be noted that wafer 200 in Fig. Figure 5 shows that the support substrate 245 is located at the bottom, while the wafer 100 is in Fig. Figure 3 shows that the carrier substrate 245 is located at the top.

[0035] Fig. Figures 6-8 illustrate cross-sectional views of a semiconductor device 350 at various manufacturing stages according to one embodiment. The semiconductor device 350 (see Fig. 8) can, for example, be a "System on Integrated Chip" device (SoIC device). The semiconductor device 350 can also be referred to as a semiconductor package with vertically integrated semiconductor dies or a semiconductor package. As will be described in detail below, the semiconductor dies 150 are Fig. 4 are attached to the wafer 200 to form a semiconductor structure 300. After desired processing of the semiconductor structure 300, a separation process is carried out to separate the semiconductor structure 300 into individual semiconductor devices 350.

[0036] We now turn Fig. 6 to where the semiconductor dies 150 are attached (for example, bonded) to the wafer 200 to form a semiconductor structure 300, which at this stage of processing is referred to as a "chip-on-wafer" (CoW) structure. It should be noted that, for the sake of clarity, only a section of the semiconductor structure 300 is shown in Fig. Figure 6 illustrates this. The illustrated section shows a single semiconductor die 150 attached to the wafer 200, with the understanding that multiple semiconductor dies 150 will be attached to the wafer 200.

[0037] In the illustrated embodiment of Fig. 6. The bonding pads 153 of each semiconductor die 150 are aligned with the respective bonding pads 253 of the wafer 200 and bonded together. The bond between the semiconductor die 150 and the wafer 200 can be a direct bond, without the use of a bonding material such as solder. For example, direct metal-to-metal bonding (between the bonding pads 153 and 253) and direct dielectric-to-dielectric bonding (between the bonding film stacks 151 and 251) can be used to bond the semiconductor die 150 to the wafer 200. In other embodiments, the semiconductor dies 150 are bonded to the wafer 200 via solder regions.

[0038] After bonding the semiconductor die 150 to the wafer 200, a thinning process is performed to reduce the thickness of the support substrate 145 of each semiconductor die 150. The thinning process may include a planarization process (for example, mechanical grinding, CMP, or the like), a back-etching process, a combination thereof, or the like. Next, a gap-filling material 301 is formed over the wafer 200 and around the semiconductor dies 150. In some embodiments, the gap-filling material 301 is an oxide (for example, silicon oxide) and may be formed by a suitable formation process such as CVD. In addition to oxide, other suitable dielectric materials, such as a potting compound, may also be used as the gap-filling material 301 to fill the gaps between the semiconductor dies 150.Next, a planarization process, such as CMP, can be performed to remove excess sections of the gap-filling material 301 from the top surfaces of the support substrates 145, such that the gap-filling material 301 and the support substrates 145 have a coplanar top surface. The gap-filling material 301 makes contact (for example, physically) with—and extends along—the side walls of the semiconductor dies 150 and along a top surface of the bonding film stack 251 distal to the substrate 201.

[0039] Next, in Fig. 7 a support substrate 305 on the semiconductor structure 300 of Fig. 6. The support substrate 305 can be the same as or similar to the support substrate 145 (or 245) and can be a different wafer (for example, a silicon wafer). The support substrate 305 is attached to the support substrates 145 of the semiconductor dies 150 using an adhesive layer 303. Therefore, the attachment process of the support substrate 305 can also be described as a wafer-to-wafer bonding process. In some embodiments, the thickness of the support substrate 305 is greater than that of the (thinned) support substrate 145, and furthermore, the thickness of the (thinned) support substrate 145 is greater than that of the (thinned) substrate 101 (or 201).

[0040] Next, in Fig. 8. The support substrate 245 of the wafer 200 is removed. The process for removing the support substrate 245 may be the same as, or similar to, the process for removing the support substrate 123, so no details are repeated. After removal of the support substrate 245, the conductive structures 237 of the backside interconnect structure 231 are exposed on a surface distal to the substrate 201.

[0041] Next, external connectors 307 (which may also be referred to as conductive bumps) are formed on the conductive structures 237 to provide an electrical connection to one or more other devices. The external connectors 307 can be any suitable type of external contact, such as controlled collapse chip connect (C4) bumps, micro bumps, copper pillars, a copper layer, a nickel layer, a lead-free (LF) layer, an electroless nickel / electroless palladium immersion gold (ENEPIG) layer, a Cu / LF layer, a Sn / Ag layer, a Sn / Pb layer, combinations thereof, or the like.

[0042] Next, a separation process is performed to separate the semiconductor structure 300 into individual (for example, separate) semiconductor devices 350 (for example, SoIC devices). The separation process can be performed along the separation regions indicated by the dashed lines 310 in Fig. 8 are indicated. The separation process can begin from the backside interconnect structure 231 of the wafer 200 towards the support substrate 305. It should be noted that after the separation process is complete, the wafer 200 is separated into several semiconductor dies 250. Therefore, the section of the semiconductor structure 300 that is shown in Fig. Figure 8 between the dashed lines 310 illustrates a semiconductor device 350. In the example of Fig. 8 The semiconductor device 350 comprises a section of the support substrate 305, a semiconductor die 150 and a semiconductor die 250. The number of dies in the Fig. The semiconductor device 350 illustrated in Figure 8 (or other disclosed semiconductor devices, such as 350A and 450) is merely a non-limiting example, and other numbers of dies may be integrated into the semiconductor device, and more than two layers of vertically stacked dies may also be present in the semiconductor device, and these and other variations are intended to fall fully within the scope of protection of the present disclosure.

[0043] As in Fig. As illustrated in Figure 8, the bond between semiconductor die 150 and semiconductor die 250 is a front-to-front bond. Therefore, communication (for example, the exchange of data / control signals) between semiconductor die 150 and semiconductor die 250 in the semiconductor device 350 is accomplished via conductive paths (also referred to as communication paths) that extend through the front-side interconnect structures 112 and 212 and the bonding film stacks 151 and 251. This shortens the communication paths between semiconductor die 150 and semiconductor die 250, thereby reducing the electrical resistance and signal transmission delay of the communication paths and increasing the processing speed of the formed device.

[0044] To appreciate the advantages, we consider a reference design in which the bonding structures 154 and 254 of the semiconductor dies 150 and 250 are formed on the backside interconnect structures 132 and 232, respectively. In such a reference design, the semiconductor dies 150 and 250 are bonded by a back-to-back bond, and the frontside interconnect structures 112 and 212 face away from each other. Communication between the semiconductor dies 150 and 250 is achieved through TSVs, which extend, for example, through the front interconnect structure 112, the fixture layer 108, the substrate 101, the back interconnect structure 132, the bonding film stack 151, the bonding film stack 251, the back interconnect structure 232, the substrate 201, the fixture layer 208 and the front interconnect structure 212.The communication paths of the reference design are significantly longer than in the disclosed embodiments, resulting in a longer signal transmission delay and higher electrical resistance. The disclosed embodiments considerably shorten the communication path and consequently reduce the electrical resistance and signal transmission delay.

[0045] A further advantage of the disclosed embodiments is the reduced risk of metal cracking due to stress. Compared to the reference design discussed above, the bonding film stacks 151 and 251 are thinner in the embodiments disclosed herein (for example, they have a reduced thickness). The reduced thickness of the bonding film stack can lead to fewer stresses (for example, thermal and / or mechanical stresses) between the bonding structures and the bonding film stack. These stresses can be caused, for example, by mismatched coefficients of thermal expansion (CTE) during thermal cycles and / or by an uneven stress distribution in a thick bonding film stack. Thanks to the thinner bonding film stacks, the disclosed embodiments reduce the risk of metal cracking and thus improve the reliability of the devices and the production yield.

[0046] Fig. 10 and Fig. Figure 11 illustrates cross-sectional views of a semiconductor device 350A at various manufacturing stages according to another embodiment. Fig. 10 will be - using the same or a similar bonding process as for forming the semiconductor structure 300 in Fig. 6 - The semiconductor dies 150 are attached (for example, bonded) to the wafer 200 to form a semiconductor structure 300A (for example, a CoW structure). Next, the support substrate 145 is removed using the same or a similar support substrate ablation process as discussed above. Next, the gap-filling material 301 is formed around the semiconductor dies 150 on the wafer 200. Next, a planarization process, such as CMP, can be performed to remove excess sections of the gap-filling material 301 and achieve a coplanar surface between the gap-filling material 301 and the semiconductor dies 150. After the planarization process, the conductive structures 137 of the backside interconnect structure 132 are exposed on a face distal to the substrate 101 of the backside interconnect structure 232.

[0047] Next, in Fig. Eleven external interconnects 307 are formed on the conductive structures 137. Next, a separation process is carried out to separate the semiconductor structure 300A into individual (for example, separate) semiconductor devices 350A (for example, SoIC devices). The separation can begin from the rear interconnect structure 132 of the semiconductor die 150 towards the support substrate 245. The dashed lines 310 in Fig. Figure 11 illustrates the discontinuity regions. The section of wafer 200 in Fig. 11 between the dashed lines 310 forms a semiconductor die 250 after completion of the separation process. Therefore, the section of semiconductor structure 300A between the dashed lines 310 corresponds to the section shown in Figure 310. Fig. Figure 11 illustrates the separation process of a semiconductor device 350A. Each semiconductor device 350A comprises a section of the support substrate 245, a semiconductor die 250, and a semiconductor die 150.

[0048] Fig. Figures 12-16 illustrate cross-sectional views of a semiconductor device 450 at various manufacturing stages according to a further embodiment. Fig. 12 is a wafer 100, which is the wafer 100 of Fig. 1 resembles, but is formed with the bonding film stack 151 and the bonding structures 154, and is aligned on a wafer 200' such that bonding pads 153 of wafer 100 are aligned with respective bonding pads 253 of wafer 200'. It should be noted that at this stage of processing, the backside interconnect structures 132 of wafer 100 have not yet been formed. The wafer 200' in Fig. Wafer 12 has the same or a similar structure to wafer 100. Fig. 12 and corresponds to wafer 200 in Fig. 5, but without the rear interconnect structure 232 and the support substrate 245. In addition, the substrate 201 of the wafer 200' is in Fig. 12 not yet thinned out.

[0049] Next, in Fig. 13 of the wafer 100, for example, are bonded to the wafer 200' by direct metal-to-metal bonding and direct dielectric-to-dielectric bonding to form a semiconductor structure 400, although another suitable bonding process may also be used. The semiconductor structure 400 at this stage of processing can be referred to as a wafer-on-wafer (WoW) structure. Next, a thinning process is performed to thin the substrate 101 such that end faces of the TSVs 105 are exposed on the surface of the substrate 101 distal to the wafer 200'.

[0050] Next, in Fig. 14 The rear interconnect structures 132 are formed on the substrate 101. The rear interconnect structures 132 comprise conductive lines 135 and vias 133 and may include integrated MIM capacitors 142. In some embodiments, the conductive lines 135 are thicker than the conductive lines 115 of the front interconnect structures 112. The details of the rear interconnect structures 132 are the same as or similar to those discussed above and are therefore not repeated.

[0051] Next, in Fig. 15. A support substrate 401 is attached to the backside interconnect structures 132 of wafer 100. The support substrate 401 can be the same as, for example, support substrate 145 or similar, so no details are repeated. Next, a thinning process is carried out to thin the substrate 201 of wafer 200' such that end faces of the TSVs 205 are exposed on the surface of substrate 201 distal to wafer 100.

[0052] Next, in Fig. 16 The backside interconnect structures 232 of the wafer 200' are formed on the substrate 201. The backside interconnect structures 232 comprise conductive lines 235 and vias 233 and may include integrated MIM capacitors 242. In some embodiments, the conductive lines 235 are thicker than the conductive lines 215 of the frontside interconnect structures 212. The details of the backside interconnect structures 232 are the same as or similar to those discussed above and are therefore not repeated.

[0053] Next, external connectors 403 are formed on the conductive structures 237, which are exposed on the surface of the backside interconnect structures 232 located distal to the substrate 201. A separation process is then performed to separate the semiconductor structure 400 into individual (e.g., separate) semiconductor devices 450 (e.g., SoIC devices). The separation can begin from the backside interconnect structure 232 of the wafer 200' towards the support substrate 401. The dashed lines 410 in Fig. Figure 16 illustrates the discontinuity regions. The section of wafer 100 in Fig. 16 between the dashed lines 410 forms a semiconductor die 150 after completion of the separation process. Similarly, the section of wafer 200' in Fig. 16. Between the dashed lines 410, after completion of the separation process, a semiconductor die 250 is formed. Therefore, the section of the semiconductor structure 400 between the dashed lines 410 corresponds to the semiconductor structure 400, as shown in Fig. Figure 16 illustrates the separation process of a semiconductor device 450. Each semiconductor device 450 comprises a section of the support substrate 401, a semiconductor die 150, and a semiconductor die 250.

[0054] Fig. Figure 17 illustrates a flowchart of a method 1000 for forming a semiconductor device in some embodiments. It is understood that the in Fig. The method illustrated in Figure 17 is only one example of many possible embodiments. The average person skilled in the art can think of many variations, alternatives, and modifications. For example, different steps, as in Fig. 17 can be illustrated, added, omitted, replaced, rearranged and repeated.

[0055] With reference to Fig.In block 1010, a first bonding pad of a die is aligned with a second bonding pad of a wafer, wherein the die comprises: a first substrate, a first transistor on a first side of the first substrate, a first interconnect structure over the first side of the first substrate and electrically coupled to the first transistor, the first bonding pad over the first interconnect structure, a second interconnect structure on a second, opposite side of the first substrate and electrically coupled to the first transistor, a second substrate attached to the second interconnect structure, and a first through-silicon via (TSV) electrically coupling the second interconnect structure and the first bonding pad, wherein the wafer comprises: a third substrate, a second transistor on a first side of the third substrate,A third interconnect structure is located over the first side of the third substrate and electrically coupled to the second transistor. The second bonding pad is located over the third interconnect structure. A fourth interconnect structure is located on a second, opposite side of the third substrate and electrically coupled to the second transistor. A fourth substrate is attached to the fourth interconnect structure, and a second TSV electrically couples the fourth interconnect structure and the second bonding pad. In block 1020, the first bonding pad of the die is bonded to the second bonding pad of the wafer. In block 1030, after bonding, a gap filler material is formed on the wafer around the die. In block 1040, the first of the second and fourth substrates is removed.to expose a first surface of the first, second, and fourth interconnect structures. In block 1050, an external connector is formed on the exposed first surface of the first, second, and fourth interconnect structures.

[0056] The disclosed embodiments realize several advantages. For example, the disclosed semiconductor devices 350, 350A, and 450 are formed by front-to-front bonding of the semiconductor dies integrated in the semiconductor device. Compared to a reference design in which the semiconductor dies are bonded by back-to-back bonding, the disclosed embodiments reduce the length of the communication paths between the semiconductor dies integrated in the semiconductor assembly. The shortened communication paths reduce electrical resistance and signal transmission delay, resulting in faster signal processing. Furthermore, the bonding film stack of the semiconductor dies integrated in the semiconductor device has a reduced thickness compared to the reference design.The thinner bonding film stack advantageously reduces the risk of metal cracking, thus improving the reliability of the devices and the production yield.

[0057] According to one embodiment, a semiconductor device comprises: a first die comprising: a first substrate; a first transistor on a first side of the first substrate; a first interconnect structure over the first side of the first substrate and electrically coupled to the first transistor; a first bonding pad over the first interconnect structure; a second interconnect structure on a second side of the first substrate and electrically coupled to the first transistor, the second side of the first substrate facing the first side of the first substrate; a second substrate attached to a first face of the second interconnect structure facing away from the first substrate; and a first through-silicon via (TSV) electrically coupling the second interconnect structure and the first bonding pad.The semiconductor device further comprises a second die bonded to the first die, the second die comprising: a third substrate; a second transistor on a first side of the third substrate; a third interconnect structure over the first side of the third substrate and electrically coupled to the second transistor; a second bonding pad over the third interconnect structure, the first bonding pad being bonded to the second bonding pad; a fourth interconnect structure on a second side of the third substrate and electrically coupled to the second transistor, the second side of the third substrate facing the first side of the third substrate; and a second TSV electrically coupling the fourth interconnect structure and the second bonding pad.The semiconductor device further comprises an external connector attached to a conductive structural element of the fourth interconnect structure, the conductive structural element being located on a first surface of the fourth interconnect structure that faces away from the third substrate. In one embodiment, the semiconductor device further comprises a gap-filling material surrounding, and in contact with, the first die, wherein side walls of the first die are covered by the gap-filling material and side walls of the second die are exposed by the gap-filling material. In one embodiment, an outer side wall of the gap-filling material, facing away from the first die, is aligned with a corresponding side wall of the second die along the same line.In one embodiment, the semiconductor device further comprises a fourth substrate attached to the second substrate and the gap-filling material, wherein the first die is arranged between the fourth substrate and the second die. In another embodiment, the semiconductor device further comprises a gap-filling material surrounding, and in contact with, the second die, wherein side walls of the second die are covered by the gap-filling material and side walls of the first die are exposed by the gap-filling material. In another embodiment, an outer side wall of the gap-filling material, facing away from the second die, is aligned with a corresponding side wall of the first die along the same line. In another embodiment, a first width of the first die, measured between opposite side walls of the first die, is the same as a second width of the second die, measured between opposite side walls of the second die.In one embodiment, the first, second, and third substrates are silicon substrates. In another embodiment, the second substrate is thicker than the first and third substrates. In yet another embodiment, the conductive traces of the second interconnect structure are thicker than the conductive traces of the first interconnect structure.In one embodiment, the second interconnect structure comprises a first capacitor, wherein the first capacitor comprises: a first depletion layer extending along a first side wall of a first conductive line of the second interconnect structure; a second depletion layer extending laterally alongside the first conductive line along a second side wall of a second conductive line of the second interconnect structure, the second side wall facing the first side wall; and a high k-value dielectric material extending from the first depletion layer to the second depletion layer.

[0058] According to one embodiment, a semiconductor device comprises a first die comprising: a first substrate; first electrical components on a first side of the first substrate; a first interconnect structure on the first side of the first substrate and electrically coupled to the first electrical components; a second interconnect structure on a second side of the first substrate and electrically coupled to the first electrical components, the second side of the first substrate facing the first side of the first substrate; a second substrate attached to the second interconnect structure, the second interconnect structure being arranged between the second substrate and the first substrate; a first bonding film stack on the first interconnect structure, the first interconnect structure being located between the first bonding film stack and the first substrate; first bonding structures,which are embedded in the first bonding film stack; and a first through-silicon via (TSV) extending from the second interconnect structure to the first bonding structures. The semiconductor device further comprises a second die bonded to the first die, the second die comprising: a third substrate; second electrical components on a first side of the third substrate; a third interconnect structure on the first side of the third substrate and electrically coupled to the second electrical components; a fourth interconnect structure on a second side of the third substrate and electrically coupled to the second electrical components, the second side of the third substrate facing the first side of the third substrate; a second bonding film stack on the third interconnect structure,wherein the third interconnect structure is located between the second bonding film stack and the third substrate; second bonding structures embedded in the second bonding film stack, the second bonding structures being bonded to respective first bonding structures; and a second TSV extending from the fourth interconnect structure to the second bonding structures. The semiconductor device further comprises external connectors bonded to conductive structural elements on a face of the fourth interconnect structure facing away from the third substrate. In one embodiment, a first width of the first bonding film stack, measured between opposite side walls of the first bonding film stack, is smaller than a second width of the second bonding film stack.measured between opposite sidewalls of the second bonding film stack. In one embodiment, the semiconductor device further comprises a gap-filling material around the first die, wherein the gap-filling material contacts and extends along sidewalls of the first bonding film stack and a surface of the second bonding film stack facing the first bonding film stack. In one embodiment, the semiconductor device further comprises a fourth substrate attached to the second substrate and the gap-filling material, wherein a third width of the fourth substrate, measured between opposite sidewalls of the fourth substrate, is the same as the second width of the second bonding film stack. In one embodiment, each of the first bonding structures comprises a first bonding pad and a first bonding pad via (BPV).wherein the first BPV electrically couples the first bonding pad to the first interconnect structure, wherein each of the second bonding structures comprises a second bonding pad and a second BPV, wherein the second BPV electrically couples the second bonding pad to the third interconnect structure, wherein the first bonding pad of each of the first bonding structures is bonded to a second bonding pad of a respective second bonding structure.

[0059] According to one embodiment, a method for forming a semiconductor device comprises aligning a first bonding pad of a die with a second bonding pad of a wafer, wherein the die comprises: a first substrate, a first transistor on a first side of the first substrate, a first interconnect structure over the first side of the first substrate and electrically coupled to the first transistor, the first bonding pad over the first interconnect structure, a second interconnect structure on a second, opposite side of the first substrate and electrically coupled to the first transistor, a second substrate attached to the second interconnect structure, and a first through-silicon via (TSV) electrically coupling the second interconnect structure and the first bonding pad, wherein the wafer comprises: a third substrate, a second transistor on a first side of the third substrate,A third interconnect structure is located over the first side of the third substrate and electrically coupled to the second transistor. The second bonding pad is located over the third interconnect structure. A fourth interconnect structure is located on a second, opposite side of the third substrate and electrically coupled to the second transistor. A fourth substrate is attached to the fourth interconnect structure. A second TSV electrically couples the fourth interconnect structure and the second bonding pad. The process further comprises: bonding the first bonding pad of the die to the second bonding pad of the wafer; after bonding, forming a gap-filling material on the wafer around the die; and removing the first of the second and fourth substrates.to expose a first face of the first, second, and fourth interconnect structures; and forming an external connector at the exposed first face of the first, second, and fourth interconnect structures. In one embodiment, the method further comprises, after forming the external connector, performing a separation process along separation regions around the die. In one embodiment, the method further comprises, after forming the gap filler material and prior to removal, attaching a fifth substrate to the second substrate and the gap filler material. In one embodiment, removal comprises removing the fourth substrate to expose the first face of the fourth interconnect structure.

[0060] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 694,249

[0001]

Claims

[1] Semiconductor device comprising: a first one, which includes: a first substrate; a first transistor on a first side of the first substrate; a first interconnect structure over the first side of the first substrate and electrically coupled to the first transistor; a first bonding pad over the first interconnect structure; a second interconnect structure on a second side of the first substrate and electrically coupled to the first transistor, with the second side of the first substrate opposite the first side of the first substrate; a second substrate attached to a first surface of the second interconnect structure, which points away from the first substrate; and a first silicon through-silicon via (TSV) that electrically couples the second interconnect structure and the first bonding pad; a second die bonded to the first die, the second die comprising: a third substrate; a second transistor on a first side of the third substrate; a third interconnect structure over the first side of the third substrate and electrically coupled to the second transistor; a second bonding pad above the third interconnect structure, wherein the first bonding pad is bonded to the second bonding pad; a fourth interconnect structure on a second side of the third substrate and electrically coupled to the second transistor, with the second side of the third substrate facing the first side of the third substrate; and a second TSV that electrically couples the fourth interconnect structure and the second bonding pad; and an external connector attached to a conductive structural element of the fourth interconnect structure, wherein the conductive structural element is located on a first surface of the fourth interconnect structure that points away from the third substrate. [2] Semiconductor device according to claim 1, further comprising a gap-filling material around, and in contact with, the first die, wherein side walls of the first die are covered by the gap-filling material and side walls of the second die are exposed by the gap-filling material. [3] Semiconductor device according to claim 2, wherein an outer side wall of the gap-filling material, pointing away from the first die, is aligned with a respective side wall of the second die along the same line. [4] Semiconductor device according to claim 2 or 3, further comprising a fourth substrate attached to the second substrate and the gap-filling material, wherein the first die is arranged between the fourth substrate and the second die. [5] Semiconductor device according to any one of claims 1 to 4, which further comprises a gap-filling material around the, and in contact with the, second die, wherein side walls of the second die are covered by the gap-filling material and side walls of the first die are exposed by the gap-filling material. [6] Semiconductor device according to claim 5, wherein an outer side wall of the gap-filling material, which points away from the second die, is aligned with a respective side wall of the first die along the same line. [7] Semiconductor device according to any one of claims 1 to 6, wherein a first width of the first die, measured between opposite side walls of the first die, is the same as a second width of the second die, measured between opposite side walls of the second die. [8] Semiconductor device according to any one of claims 1 to 7, wherein the first substrate, the second substrate and the third substrate are silicon substrates. [9] Semiconductor device according to claim 8, wherein the second substrate is thicker than the first substrate and the third substrate. [10] Semiconductor device according to any one of claims 1 to 9, wherein conductive lines of the second interconnect structure are thicker than conductive lines of the first interconnect structure. [11] Semiconductor device according to claim 10, wherein the second interconnect structure comprises a first capacitor, the first capacitor comprising: a first barrier layer extending along a first side wall of a first conductive conductor of the second interconnect structure; a second barrier layer extending laterally alongside the first conductive line along a second side wall of a second conductive line of the second interconnect structure, with the second side wall facing the first side wall; and a dielectric material with a high k-value, extending from the first barrier layer to the second barrier layer. [12] Semiconductor device comprising: a first one, which includes: a first substrate; first electrical components on a first side of the first substrate; a first interconnect structure on the first side of the first substrate and electrically coupled to the first electrical components; a second interconnect structure on a second side of the first substrate and electrically coupled to the first electrical components, with the second side of the first substrate facing the first side of the first substrate; a second substrate attached to the second interconnect structure, wherein the second interconnect structure is arranged between the second substrate and the first substrate; a first bonding film stack on the first interconnect structure, wherein the first interconnect structure is located between the first bonding film stack and the first substrate; first bonding structures embedded in the first bonding film stack; and a first silicon through-silicon via (TSV) extending from the second interconnect structure to the first bonding structures; a second die bonded to the first die, the second die comprising: a third substrate; second electrical components on a first side of the third substrate; a third interconnect structure on the first side of the third substrate and electrically coupled to the second electrical components; a fourth interconnect structure on a second side of the third substrate and electrically coupled to the second electrical components, with the second side of the third substrate facing the first side of the third substrate; a second bonding film stack on the third interconnect structure, wherein the third interconnect structure is located between the second bonding film stack and the third substrate; second bonding structures embedded in the second bonding film stack, wherein the second bonding structures are bonded to each of the first bonding structures; and a second TSV extending from the fourth interconnect structure to the second bonding structures; and external connectors bonded to conductive structural elements on a surface of the fourth interconnect structure, pointing away from the third substrate. [13] Semiconductor device according to claim 12, wherein a first width of the first bonding film stack, measured between opposite side walls of the first bonding film stack, is smaller than a second width of the second bonding film stack, measured between opposite side walls of the second bonding film stack. [14] Semiconductor device according to claim 13, which further comprises a gap-filling material around the first die, wherein the gap-filling material contacts and extends along side walls of the first bonding film stack and a surface of the second bonding film stack facing the first bonding film stack. [15] Semiconductor device according to claim 14, further comprising a fourth substrate attached to the second substrate and the gap-filling material, wherein a third width of the fourth substrate, measured between opposite side walls of the fourth substrate, is the same as the second width of the second bonding film stack. [16] Semiconductor device according to any one of claims 12 to 15, wherein each of the first bonding structures comprises a first bonding pad and a first bonding pad via (BPV), wherein the first BPV electrically couples the first bonding pad to the first interconnect structure, wherein each of the second bonding structures comprises a second bonding pad and a second BPV, wherein the second BPV electrically couples the second bonding pad to the third interconnect structure, wherein the first bonding pad of each of the first bonding structures is bonded to a second bonding pad of a respective second bonding structure. [17] Method for forming a semiconductor device, the method comprising: Aligning a first bonding pad of a die with a second bonding pad of a wafer, wherein the die comprises: a first substrate, a first transistor on a first side of the first substrate, a first interconnect structure over the first side of the first substrate and electrically coupled to the first transistor, the first bonding pad over the first interconnect structure, a second interconnect structure on a second, opposite side of the first substrate and electrically coupled to the first transistor, a second substrate attached to the second interconnect structure, and a first through-silicon via (TSV) electrically coupling the second interconnect structure and the first bonding pad, wherein the wafer comprises: a third substrate, a second transistor on a first side of the third substrate,a third interconnect structure over the first side of the third substrate and electrically coupled to the second transistor, the second bonding pad over the third interconnect structure, a fourth interconnect structure on a second, opposite side of the third substrate and electrically coupled to the second transistor, a fourth substrate attached to the fourth interconnect structure, and a second TSV electrically coupling the fourth interconnect structure and the second bonding pad; Bonding the first bonding pad of the die to the second bonding pad of the wafer; After bonding, a gap-filling material is formed on the wafer around the die; Removing a first of the second substrate and the fourth substrate to expose a first surface of a first of the second interconnect structure and the fourth interconnect structure; and Forming an external connector on the exposed first surface of the first, second, and fourth interconnect structures. [18] The method of claim 17, which further comprises, after forming the external connector, performing a separation process along separation regions around the die. [19] Method according to claim 17 or 18, further comprising, after forming the gap-filling material and before removal, attaching a fifth substrate to the second substrate and the gap-filling material. [20] Method according to claim 19, wherein the removal comprises removing the fourth substrate to expose the first surface of the fourth interconnect structure.

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