PIXEL CIRCUIT AND LUMINESCENT DISPLAY DEVICE HAVING THE SAME

Abstract

The present application relates to a pixel circuit and an electroluminescent display device. A pixel circuit comprises: a drive transistor (DR) having a gate electrode connected to a gate node (DTG) and a source electrode connected to a source node (DTS), and correspondingly generating a drive current; a first light-emitting device (OLED1) having a first anode electrode and emitting light with the drive current; a second light-emitting device (OLED2) having a second anode electrode and emitting light with the drive current; a first emission transistor (ET1) connecting the source node (DTS) to the first anode electrode in an odd-numbered frame and disconnecting the source node (DTS) from the first anode electrode during an even-numbered frame in response to a first emission signal (EM1); and a second emission transistor (ET2).which connects the source node (DTS) to the second anode electrode in the even-numbered frame and disconnects the source node (DTS) from the second anode electrode during the odd-numbered frame in response to a second emission signal (EM2).

Description

REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0025778, filed on February 22, 2024. FIELD OF THE INVENTION

[0002] The present disclosure relates to a pixel circuit and an electroluminescent display device having the same. background

[0003] Electroluminescent display devices have pixels arranged in a matrix and supply image data to the pixels in synchronization with a scanning signal, thus implementing a luminance corresponding to the image data in the pixels.

[0004] Each pixel includes a driving element that generates a driving current corresponding to image data, and a light-emitting device that emits light with a brightness corresponding to the driving current. The driving current level is proportional to the gray level of the image data, and as the driving current increases, the amount of light emitted by the light-emitting device increases, contributing to the luminance.

[0005] However, if a gray level of image data applied to a pixel is changed from black to white and then maintains a white gray level for several frames, a luminance deviation occurs between a first frame immediately after the change to a white gray level and the other frames that maintain a white gray level. A gray level of the image data is maintained in the other frames, and in the first frame, a gray level of the image data is changed from black to white. Due to this, a charge delay of a light-emitting device of a corresponding pixel occurs in the first frame, resulting in a luminance lower than a target luminance. OVERVIEW

[0006] To overcome the above-mentioned problem of the related art, the present disclosure can provide a pixel circuit and an electroluminescent display device having the same, which can reduce a luminance deviation occurring in a pixel at the moment a gray level of image data is changed from black to white.

[0007] To achieve these objects and other advantages, and in accordance with the purpose of the disclosure as embodied and broadly described herein, a pixel circuit and an electroluminescent display device are provided according to the independent claims. Further embodiments are described in the subclaims. According to one aspect of the present disclosure, a pixel circuit comprises: a drive transistor configured to have a gate electrode connected to a gate node and a source electrode connected to a source node and to generate a drive current; a first light-emitting device configured to have a first anode electrode and to emit light in response to the drive current; a second light-emitting device configured to have a second anode electrode and to emit light in response to the drive current;a first emission transistor connecting the source node to the first anode electrode in an odd-numbered frame and disconnecting the source node from the first anode electrode during an even-numbered frame in response to a first emission signal; and a second emission transistor connecting the source node to the second anode electrode in the even-numbered frame and disconnecting the source node from the second anode electrode during the odd-numbered frame in response to a second emission signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate one embodiment(s) of the disclosure and, together with the description, serve to explain the principle of the disclosure. In the drawings: Fig. 1 is a diagram showing an electroluminescent display device according to the present disclosure; Fig. 2 is a diagram schematically showing a configuration of a pixel circuit used in a display panel of Fig. 1 is provided; Fig. 3 is a diagram for describing a luminance deviation that occurs at the moment a gray level of image data is changed from black to white; Fig. 4A is a schematic diagram of a drive waveform of a pixel circuit of Fig. 2 in an odd-numbered frame; Fig. 4B is a schematic diagram of a drive waveform of the pixel circuit of Fig. 2 in an even-numbered frame; Fig. 5 is a diagram showing an example in which a luminance deviation occurring at the moment a gray level of image data is changed from black to white is reduced by application of the present disclosure; Fig. 6 is a diagram showing a configuration of a pixel circuit according to the present disclosure; Fig. 7 is a diagram showing a driving waveform of a pixel circuit of Fig. 6 in an odd-numbered frame; Fig. 8A is a diagram showing an operation of a pixel circuit in a first initialization period of an odd-numbered frame; Fig. 8B is a diagram showing an operation of a pixel circuit in a threshold voltage sampling period of an odd-numbered frame; Fig. 8C is a diagram showing an operation of a pixel circuit in a data write period of an odd frame; Fig. 8D is a diagram showing an operation of a pixel circuit in a second initialization period of an odd-numbered frame; Fig. 8E is a diagram showing an operation of a pixel circuit in an emission period of an odd-numbered frame; Fig. 9 is a diagram showing a driving waveform of a pixel circuit from Fig. 6 in an even-numbered frame; Fig. 10A is a diagram showing an operation of a pixel circuit in a first initialization period of an even-numbered frame; Fig. 10B is a diagram showing an operation of a pixel circuit in a threshold voltage sampling period of an even frame; Fig. 10C is a diagram showing an operation of a pixel circuit in a data write period of an even frame; Fig. 10D is a diagram showing an operation of a pixel circuit in a second initialization period of an even-numbered frame; and Fig. 10E is a diagram showing an operation of a pixel circuit in an emission period of an even frame. DETAILED DESCRIPTION OF REVELATION

[0009] Below, the present disclosure will be described in more detail with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. However, the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the disclosure to those skilled in the art.

[0010] Advantages and features of the present disclosure and their implementation methods are illustrated by the following embodiments, which are described with reference to the accompanying drawings. However, the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is defined only by the scope of the claims.

[0011] The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings to describe various embodiments of the present disclosure are merely exemplary, and the present disclosure is not limited thereto. Like reference numerals refer to like elements throughout. Throughout this description, like elements are identified by like reference numerals. As used herein, the terms "comprise," "having," "include," and the like indicate that other parts may be added unless the term "only" is used. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0012] Elements in various embodiments of the present disclosure should be interpreted as having margins of error even without explicit indication.

[0013] When describing a positional relationship, e.g. when describing a positional relationship between two parts as "on~", "over~", "under~" and "next to~", one or more other parts may be located between the two parts unless "direct" or "immediate" is used.

[0014] It should be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the present disclosure.

[0015] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, an organic light-emitting display device including an organic light-emitting material will be mainly described as an example of an electroluminescent display device. However, the inventive concept is not limited to the organic light-emitting display device and can be applied to an inorganic light-emitting display device including an inorganic light-emitting material.

[0016] Fig. 1 is a diagram showing an electroluminescent display device according to the present disclosure.

[0017] With reference to Fig. 1, the electroluminescent display device may include a display panel 10, a timing controller 11, a data driver 12, a gate driver 13, and a power circuit.

[0018] A plurality of pixels PXL included in the display panel 10 may be arranged in a matrix-type manner to form a pixel array. In the pixel array, each of the plurality of pixels PXL may be connected to a data line 14, a gate line 15, a reset voltage current line, a reference voltage current line, a high-level current line, and a low-level current line. Here, the gate line 15 connected to a pixel PXL may include a plurality of scan lines and a plurality of emission lines.Each pixel PXL can be supplied with a data voltage via the data line 14, a plurality of scan signals having different phases via a plurality of scan lines, a plurality of emission signals having different phases via a plurality of emission lines, a reset voltage Var via the reset voltage current line, a reference voltage Vref via the reference voltage current line, a high-level pixel source voltage EVDD via the high-level current line, and a low-level pixel source voltage EVSS via the low-level current line.

[0019] The reset voltage line, the reference voltage line, the high-level current line, and the low-level current line can be connected to the power circuit. The power circuit can output the reset voltage Var, the reference voltage Vref, the high-level pixel source voltage EVDD, and the low-level pixel source voltage EVSS.

[0020] A pixel circuit included in each pixel PXL may include a drive transistor and two light-emitting devices. The drive transistor may generate a drive current to be supplied to the light-emitting devices based on image data DATA. The two light-emitting devices may be alternately connected to the drive transistor at a specific time period, and thus alternately emit light at a specific time period. While one of the two light-emitting devices is emitting light, the other light-emitting device may not emit light. The drive transistor included in each pixel PXL may be implemented as an oxide transistor having good leakage current characteristics, but the present disclosure is not limited thereto.

[0021] The timing controller 11 can receive image data DATA and timing control information Vsync, Hsync, DCLK, and DE from a host system. The timing control information Vsync, Hsync, DCLK, and DE can include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock DCLK, and a data enable signal DE.

[0022] The timing controller 11 may generate a source control signal DDC for controlling an operating timing of the data driver 12 and a gate control signal GDC for controlling an operating timing of the gate driver 13 based on the timing control information Vsync, Hsync, DCLK, and DE.

[0023] The timing controller 11 can supply the data driver 12 with the source control signal DDC along with the image data DATA. The timing controller 11 can supply the gate driver 13 with the gate control signal GDC.

[0024] The data driver 12 can convert the image data DATA from a digital format to an analog format to generate a data voltage corresponding to the image data DATA based on the source control signal DDC. The data voltage can be generated to have a level that varies based on a gray level of the image data DATA within a predetermined voltage range. A lower voltage limit of the voltage range can correspond to a data voltage representing a black gray level. An upper voltage limit of the voltage range can correspond to a data voltage representing a white gray level.

[0025] The data driver 12 can output a data voltage to data lines 14 of the display panel 10.

[0026] The gate driver 13 can generate the plurality of scan signals and the plurality of emission signals having different phases based on the gate control signal GDC. The gate driver 13 can output the plurality of scan signals to the plurality of scan lines and output the plurality of emission signals to the plurality of emission lines, thus selecting a pixel row to be written to. Here, the pixel row can refer to a group of pixels PXL that are adjacent to each other in the horizontal direction. Pixels PXL that form a pixel row can be connected to the data driver 12 via a plurality of data lines and connected to the gate driver 13 via a plurality of scan lines and a plurality of emission lines.

[0027] The gate driver 13 can be formed directly in an aperture area of ​​the display panel 10, based on a gate driver-in-panel (GIP) type. Here, the aperture area can correspond to a non-display area outside a screen area configured with the pixel array. The aperture area may not display an image.

[0028] Fig. 2 is a diagram showing a configuration of a pixel circuit used in a display panel of Fig. 1 is provided, schematically shows. Fig. Figure 3 is a diagram for describing a luminance deviation that occurs when a gray level of image data is changed from black to white. Fig. Figure 4A is a schematic diagram of a driving waveform of a pixel of Fig. 2 in an odd frame. Fig. Figure 4B is a schematic diagram of a driving waveform of the pixel circuit of Fig. 2 in an even-numbered frame. Fig. 5 is a diagram showing an example in which a luminance deviation occurring at the moment a gray level of image data is changed from black to white is reduced by the application of the present disclosure.

[0029] With reference to Fig. 2 shows a pixel PXL arranged in a pixel row.

[0030] A pixel PXL according to the present disclosure may be configured to reduce a luminance deviation occurring in a first frame in which a gray level of a data voltage Vdata is changed from black to white, as shown in Fig. 3.

[0031] The luminance deviation may occur because a luminance of a first frame (hereinafter referred to as the nth frame) immediately after changing from a black gray level to a white gray level is lower than that of a next frame (hereinafter referred to as the (n+1)th frame) maintaining a white gray level. That is, the luminance deviation may occur because a level of a drive current IEL of the nth frame for implementing the same white gray level is lower than that of the drive current IEL of the (n+1)th frame.

[0032] The degree of charge delay of an internal capacitor of a light-emitting device may be changed based on a gray level of a previous frame, and due to this, a deviation may occur in the drive current IEL and an anode voltage of the light-emitting device. The data voltage representing a white gray level may be larger than the data voltage representing a black gray level. Therefore, as in one embodiment, when a gray level of an (n-1)th frame is black and a gray level of both the nth frame and the (n+1)th frame is white, a charge delay may be relatively large in the nth frame that changes from a black gray level to a white gray level, and a charge delay may be relatively small in the (n+1)th frame that maintains a white gray level.

[0033] Such a luminance deviation can be referred to as the shooting amount ratio (SAR). The SAR may be highest in the nth frame, which contains a moment where a gray level changes from black to white, may progressively decrease in the nth frame, which contains subsequent frames that maintain a white gray level, and may be almost zero starting at a specific subsequent frame. For example, the SAR of the nth frame may be 54% lower than that of the specific subsequent frame.

[0034] A SAR can be a concept that has both a black grayscale detection error and a white grayscale detection error. However, a black grayscale detection error can be ignored because a black grayscale detection error is far smaller than a white grayscale detection error.

[0035] In other words, a SAR can be easily detected when a gray level of a previous frame is black and a gray level of a current frame is white. However, in the opposite case, namely, when a gray level of a previous frame is white and a gray level of a current frame is black, a SAR may not be easily detected. Therefore, in the following description, only a detection deviation of a white gray level is described as an example of a SAR.

[0036] The pixel PXL of the present disclosure, which is Fig. 2 may be used to reduce a SAR and may have a feature in which an anode voltage of a light emitting device is initialized the same in all frames regardless of a gray level of a previous frame.

[0037] Such a feature can be implemented based on an on-off alternating drive using two light-emitting devices and a discharge drive performed in one light-emitting device that is off. This will be described in detail below.

[0038] The pixel PXL according to the present disclosure may include a first light emitting device OLED1, a second light emitting device OLED2, a driving transistor DR, a first emitting transistor ET1, and a second emitting transistor ET2 for alternating on-off driving and discharge driving.

[0039] The drive transistor DR can generate a drive current to be supplied to the first light-emitting device OLED1 or the second light-emitting device OLED2. A gate electrode of the drive transistor DR can be connected to a gate node DTG, and a source electrode of the drive transistor DR can be connected to a source node DTS. The drive current can be proportional to the square of a voltage difference between the gate node DTG and the source node DTS.

[0040] The first light-emitting device OLED1 may include a first anode electrode, a first cathode electrode, and a first emission layer disposed therebetween. A low-level pixel source voltage EVSS may be supplied to the first cathode electrode, and the first anode electrode may be coupled to the first cathode electrode via an internal capacitor and an internal resistor.

[0041] The second light-emitting device OLED2 may include a second anode electrode, a second cathode electrode, and a second emission layer disposed therebetween. The low-level pixel source voltage EVSS may be supplied to the second cathode electrode, and the second anode electrode may be coupled to the second cathode electrode via an internal capacitor and an internal resistor. The second light-emitting device OLED2 may emit light with a drive current supplied by the drive transistor DR.

[0042] The first light-emitting device OLED1 can be driven on (i.e., emit light) during an odd-numbered frame with the drive current supplied by the drive transistor DR, and driven off (i.e., not emit light) during an even-numbered frame. An anode voltage of the first light-emitting device OLED1 can be driven by the low-level pixel source voltage EVSS through the internal resistor during an even-numbered frame.

[0043] The second light-emitting device OLED2 can be driven on (i.e., emit light) during an even-numbered frame with the drive current supplied by the drive transistor DR, and driven off (i.e., not emit light) during an odd-numbered frame. An anode voltage of the second light-emitting device OLED2 can be driven by the low-level pixel source voltage EVSS through the internal resistor during an odd-numbered frame.

[0044] The first emission transistor ET1 and the second emission transistor ET2 can be configured for alternating on-off control of the first light emission device OLED1 and the second light emission device OLED2.

[0045] In response to a first emission signal EM1, the first emission transistor ET1 may connect a first anode electrode of the first light-emitting device OLED1 to the source node DTS in an odd-numbered frame and disconnect the first anode electrode of the first light-emitting device OLED1 from the source node DTS during an even-numbered frame. The first emission transistor ET1 may have a gate electrode connected to a first emission line EL1, a drain electrode connected to the source node DTS, and a source electrode connected to the first anode electrode of the first light-emitting device OLED1.

[0046] In response to a second emission signal EM2, the second emission transistor ET2 may connect a second anode electrode of the second light-emitting device OLED2 to the source node DTS in an even-numbered frame and disconnect the second anode electrode of the second light-emitting device OLED2 from the source node DTS during an odd-numbered frame. The second emission transistor ET2 may have a gate electrode connected to a second emission line EL2, a drain electrode connected to the source node DTS, and a source electrode connected to the second anode electrode of the second light-emitting device OLED2.

[0047] With reference to the Fig. 4A and Fig. 4B, a frame may include a first initialization period X1 and Y1, a threshold voltage sampling period X2 and Y2, a data write period X3 and Y3, a second initialization period X4 and Y4, and an emission period X5 and Y5.

[0048] The first emission signal EM1 can be input at an on-level Lon during the first initialization period X1 and the emission period X5 of an odd-numbered frame, and can be input at an off-level Loff during the threshold voltage sampling period X2, the data write period X3, and the second initialization period X4 of the odd-numbered frame. The first emission signal EM1 can be input at the off-level Loff during all periods Y1 to Y5, including the emission period Y5 of an even-numbered frame.

[0049] In response to the first emission signal EM1, the first emission transistor ET1 may be turned on during the first initialization period X1 and the emission period X5 of the odd-numbered frame and turned off during all periods Y1 to Y5 of the even-numbered frame.

[0050] Therefore, the first light-emitting device OLED1 may be turned on during the emission period X5 of the odd-numbered frame and turned off during all periods Y1 to Y5 of the even-numbered frame.

[0051] The second emission signal EM2 can be input at the on-level Lon during the first initialization period Y1 and the emission period Y5 of the even-numbered frame, and can be input at the off-level Loff during the threshold voltage sampling period Y2, the data write period Y3, and the second initialization period Y4 of the even-numbered frame. The second emission signal EM2 can be input at the off-level Loff during all periods X1 to X5, including the emission period X5 of the odd-numbered frame.

[0052] In response to the second emission signal EM2, the second emission transistor ET2 may be turned on during the first initialization period Y1 and the emission period Y5 of the even-numbered frame and turned off during all periods X1 to X5 of the odd-numbered frame.

[0053] Therefore, the second light-emitting device OLED2 may be turned on during the emission period Y5 of the even-numbered frame and turned off during all periods X1 to X5 of the odd-numbered frame.

[0054] With further reference to Fig. 2, the pixel PXL according to the present disclosure may further supply an external reset voltage Var to an anode electrode of a corresponding light-emitting device being driven off to more effectively initialize the light-emitting device before being driven on. For this purpose, the pixel PXL according to the present disclosure may further include a first scan transistor ST1 and a second scan transistor ST2.

[0055] The first scan transistor ST1 may further supply a reset voltage Var to the first anode electrode of the first light-emitting device OLED1 based on a first scan signal SCAN1. The first scan transistor ST1 may have a gate electrode connected to a first scan line SL1, a drain electrode connected to an input terminal of the reset voltage Var, and a source electrode connected to the first anode electrode of the first light-emitting device OLED1.

[0056] The second scan transistor ST2 may further supply the reset voltage Var to the second anode electrode of the second light-emitting device OLED2 based on a second scan signal SCAN2. The second scan transistor ST2 may have a gate electrode connected to a second scan line SL2, a drain electrode connected to the input terminal of the reset voltage Var, and a source electrode connected to the second anode electrode of the second light-emitting device OLED2.

[0057] With further reference to the Fig. 4A and Fig. 4B, the first scan signal SCAN1 can be input at the on-level Lon in the other periods X1 to X4, except for the emission period X5 of the odd-numbered frame, and in all periods Y1 to Y5, including the emission period Y5 of the even-numbered frame. In contrast, the second scan signal SCAN2 can be input at the on-level Lon in the other periods Y1 to Y4, except for the emission period Y5 of the even-numbered frame, and in all periods X1 to X5, including the emission period X5 of the odd-numbered frame.

[0058] In response to the first scan signal SCAN1, the first scan transistor ST1 can be turned on during all periods Y1 to Y5 of the even-numbered frame and initialize the first anode electrode of the first light-emitting device OLED1 to the reset voltage Var. In response to the second scan signal SCAN2, the second scan transistor ST2 can be turned on during all periods X1 to X5 of the odd-numbered frame and initialize the second anode electrode of the second light-emitting device OLED2 to the reset voltage Var.

[0059] Here, the reset voltage Var can be lower than the data voltage representing a black / grayscale for stable off-state control. For example, if the data voltage representing a black grayscale is 0.5 V, the reset voltage Var can be set to -3 V.

[0060] As described above, according to the present disclosure, an anode voltage of a light-emitting device can be initialized the same in all frames regardless of a gray level of a previous frame. As a result, as shown in Fig. 5, the luminance of a first frame immediately after changing from a black grayscale to a white grayscale may be essentially the same as that of a subsequent frame maintaining a white grayscale. This may mean that the SAR drops to 0%.

[0061] With further reference to Fig. 2, the pixel PXL according to the present disclosure may further include a node control circuit CPG for programming a voltage difference (hereinafter referred to as Vgs) between the gate node DTG and the source node DTS in front of the first or second light-emitting device OLED1 or OLED2 in each of an odd-numbered frame and an even-numbered frame. A configuration of the node control circuit CPG may be modified in various ways.

[0062] For example, the node control circuit CPG may be connected to the data line 14 to receive a data voltage Vdata, may be further connected to third and fourth scan lines SL3 and SL4 to further receive third and fourth scan signals SCAN3 and SCAN4, may be further connected to a third emission line EL3 to further receive a third emission signal EM3, may be connected to the reference voltage current line to receive the reference voltage Vref, and may be connected to the high-level current line to receive the high-level pixel source voltage EVDD.

[0063] A configuration of a pixel circuit having a configuration of a node control circuit CPG according to an embodiment is shown in Fig. 6 shown. In Fig. 6, the other elements except the node control circuit CPG may be the same as in Fig. 2.

[0064] With reference to Fig. 6, the node control circuit CPG may include a third scan transistor ST3 for supplying a data voltage Vdata to a gate node DTG, a fourth scan transistor ST4 for supplying a reference voltage Vref to the gate node DTG, a third emission transistor ET3 for supplying a high-level pixel source voltage EVDD to a drive transistor DR, a first capacitor Cst, and a second capacitor CA.

[0065] The third scan transistor ST3 may have a gate electrode connected to a third scan line SL3, a drain electrode connected to a data line 14, and a source electrode connected to the gate node DTG.

[0066] The fourth scan transistor ST4 may have a gate electrode connected to a fourth scan line SL4, a drain electrode connected to a reference voltage current line, and a source electrode connected to the gate node DTG.

[0067] The third emission transistor ET3 may have a gate electrode connected to a third emission line EL3, a drain electrode connected to an input terminal of the high-level pixel source voltage EVDD, and a source electrode connected to a drain electrode of a drive transistor DR.

[0068] One electrode of the first capacitor Cst may be connected to the gate node DTG, and the other electrode of the first capacitor Cst may be connected to a source node DTS.

[0069] One electrode of the second capacitor CA may be connected to the input terminal of the high-level pixel source voltage EVDD, and the other electrode of the second capacitor CA may be connected to the source node DTS.

[0070] Fig. Fig. 7 is a diagram of a driving waveform of the pixel circuit of Fig. 6 in an odd frame. Fig. 8A is a diagram showing an operation of a pixel circuit in a first initialization period of an odd-numbered frame. Fig. 8B is a diagram showing an operation of a pixel circuit in a threshold voltage sampling period of an odd frame. Fig. 8C is a diagram showing an operation of a pixel circuit in a data write period of an odd frame. Fig. 8D is a diagram showing an operation of a pixel circuit in a second initialization period of an odd-numbered frame. Fig. 8E is a diagram showing an operation of a pixel circuit in an emission period of an odd-numbered frame.

[0071] With reference to the Fig. 7 and Fig. 8A, in a first initialization period X1 of an odd-numbered frame, a first scan transistor ST1 may be turned on based on a first scan signal SCAN1 at an on-level Lon, a second scan transistor ST2 may be turned on based on a second scan signal SCAN2 at the on-level Lon, a fourth scan transistor ST4 may be turned on based on a fourth scan signal SCAN4 of the on-level Lon, and a first emission transistor ET1 may be turned on based on a first emission signal EM1 of the on-level Lon. In addition, the other transistors DR, ST3, ET2, and ET3 may be turned off.

[0072] As a result, in the first initialization period X1 of the odd-numbered frame, a gate node DTG may be initialized to a reference voltage Vref, and a source node DTS may be initialized to a reset voltage Var. For stability of operation, the reference voltage Vref may be set to be greater than a data voltage representing a black gray level, and the reset voltage Var may be set to be less than the data voltage representing a black gray level. For example, if the data voltage representing a black gray level is 0.5 V, the reset voltage Var may be set to -3 V, and the reference voltage Vref may be set to 1.5 V.

[0073] With reference to the Fig. 7 and Fig. 8B, in a threshold voltage sampling period X2 of the odd-numbered frame, the first scanning transistor ST1 may be turned on based on the first scanning signal SCAN1 of the on-level Lon, the second scanning transistor ST2 may be turned on based on the second scanning signal SCAN2 of the on-level Lon, the fourth scanning transistor ST4 may be turned on based on the fourth scanning signal SCAN4 of the on-level Lon, a third emission transistor ET3 may be turned on based on a third emission signal EM3 of the on-level Lon, and a driving transistor DR may be turned on. In addition, the other transistors ST3, ET1, and ET2 may be turned off.

[0074] As a result, in the threshold voltage sampling period X2 of the odd-numbered frame, a threshold voltage of the drive transistor DR can be sampled and stored in the first capacitor Cst. In the threshold voltage sampling period X2 of the odd-numbered frame, an electric potential of the gate node DTG can be the reference voltage Vref, and an electric potential of the source node DTS can be "Vref-Vth." Here, Vth can denote a threshold voltage of the drive transistor DR.

[0075] With reference to the Fig. 7 and Fig. 8C, in a data write period X3 of the odd-numbered frame, the first scan transistor ST1 may be turned on based on the first scan signal SCAN1 of the on-level Lon, the second scan transistor ST2 may be turned on based on the second scan signal SCAN2 of the on-level Lon, and a third scan transistor ST3 may be turned on based on a third scan signal SCAN3 of the on-level Lon. In addition, the other transistors DR, ST4, ET1, ET2, and ET3 may be turned off.

[0076] As a result, in the data write period X3 of the odd-numbered frame, a data voltage Vdata representing a white gray level may be supplied to the gate node DTG. In the data write period X3 of the odd-numbered frame, an electric potential of the gate node DTG may be the data voltage Vdata, and an electric potential of the source node DTS may be "Vref - Vth + C(Vdata-Vref)". Here, C may denote a value obtained by dividing a capacitance of the first capacitor Cst by a sum of the capacitance of the first capacitor Cst and a capacitance of the second capacitor CA.

[0077] In addition, the third scan signal SCAN3 can be delayed for a certain time Td from a start time T0 of the data write period X3 and then shifted to the on-level Lon, thereby preventing an abnormal short circuit between the data line DL and the input terminal of the reference voltage Vref, which occurs because the third scan transistor ST3 and the fourth scan transistor ST4 are turned on simultaneously at a time (ie, T0) when the threshold voltage sampling period X2 is changed to the data write period X3.

[0078] With reference to the Fig. 7 and Fig. 8D, in a second initialization period X4 of the odd-numbered frame, the first scan transistor ST1 may be turned on based on the first scan signal SCAN1 of the on-level Lon, and the second scan transistor ST2 may be turned on based on the second scan signal SCAN2 of the on-level Lon. In addition, the other transistors DR, ST3, ST4, ET1, ET2, and ET3 may be turned off.

[0079] As a result, the reset voltage Var can be applied to a first anode electrode of a first light-emitting device OLED1 and a second anode electrode of a second light-emitting device OLED2. An electric potential of the first anode electrode and an electric potential of the second anode electrode can continuously maintain the reset voltage Var until the second initialization period X4 from the first initialization period X1.

[0080] Based on the reset voltage Var maintained by the first and second anode electrodes until the second initialization period X4 from the first initialization period X1, the first anode electrode of the first light-emitting device OLED1 and the second anode electrode of the second light-emitting device OLED2 can be equally initialized (or discharged) regardless of a gray level of a previous frame.

[0081] The first light-emitting device OLED1 and the second light-emitting device OLED2 may be turned off (or emit no light) until the second initialization period X4 from the first initialization period X1, and thus an image with a black gray level can be implemented.

[0082] With reference to the Fig. 7 and Fig. 8E, in an emission period X5 of the odd-numbered frame, the second scanning transistor ST2 may be turned on based on the second scanning signal SCAN2 of the on-level Lon, a first emission transistor ET1 may be turned on based on a first emission signal EM1 of the on-level Lon, a third emission transistor ET3 may be turned on based on the third emission signal EM3 of the on-level Lon, and the driving transistor DR may be turned on. In addition, the other transistors ST1, ST3, ST4, and ET2 may be turned off.

[0083] In an emission period X5 of the odd-numbered frame, an electric potential of the gate node DTG may be "Vdata+Voled," and an electric potential of the source node DTS may be "Vref - Vth + C(Vdata-Vref) + Voled." Here, Voled may be a turn-on voltage (or an operating point voltage) of the first light-emitting device OLED1.

[0084] A potential difference between the gate node DTG and the source node DTS, which determines a drive current level, can be "Vdata - Vref - C(Vdata-Vref) + Vth." Accordingly, the drive current loled can be expressed as in the following Equation 1. loled=k / 2{(1−C)*(Vdata−Vref)}2

[0085] As in Equation 1, the driving current loled can be compensated independently of a shift of the threshold voltage Vth of the driving transistor DR, and the first light-emitting device OLED1 can be turned on (or emit light) by the driving current loled during the emission period X5 of the odd-numbered frame, thereby implementing a white gray-level image.

[0086] On the other hand, the second light-emitting device OLED2 may be kept in an off state during an entire period of the odd-numbered frame and may thus be initialization-driven (or discharged).

[0087] Fig. Fig. 9 is a diagram of a driving waveform of a pixel circuit of Fig. 6 in an even-numbered frame. Fig. 10A is a diagram showing an operation of a pixel circuit in a first initialization period of an even-numbered frame. Fig. 10B is a diagram showing an operation of a pixel circuit in a threshold voltage sampling period of an even frame. Fig. 10C is a diagram showing an operation of a pixel circuit in a data write period of an even frame. Fig. 10D is a diagram showing an operation of a pixel circuit in a second initialization period of an even-numbered frame. Fig. 10E is a diagram showing an operation of a pixel circuit in an emission period of an even frame.

[0088] With reference to the Fig. 9 and Fig. 10A, in a first initialization period Y1 of an even-numbered frame, a first scan transistor ST1 may be turned on based on a first scan signal SCAN1 having an on-level Lon, a second scan transistor ST2 may be turned on based on a second scan signal SCAN2 having the on-level Lon, a fourth scan transistor ST4 may be turned on based on a fourth scan signal SCAN4 having the on-level Lon, and a second emission transistor ET2 may be turned on based on a second emission signal EM2 having the on-level Lon. In addition, the other transistors DR, ST3, ET1, and ET3 may be turned off.

[0089] As a result, in the first initialization period Y1 of the even-numbered frame, a gate node DTG can be initialized to a reference voltage Vref and a source node DTS can be initialized to a reset voltage Var.

[0090] With reference to the Fig. 9 and Fig. 10B, in a threshold voltage sampling period Y2 of the even-numbered frame, the first scanning transistor ST1 may be turned on based on the first scanning signal SCAN1 of the on-level Lon, the second scanning transistor ST2 may be turned on based on the second scanning signal SCAN2 of the on-level Lon, the fourth scanning transistor ST4 may be turned on based on the fourth scanning signal SCAN4 of the on-level Lon, a third emission transistor ET3 may be turned on based on a third emission signal EM3 of the on-level Lon, and a driving transistor DR may be turned on. In addition, the other transistors ST3, ET1, and ET2 may be turned off.

[0091] As a result, in the threshold voltage sampling period Y2 of the even-numbered frame, a threshold voltage of the drive transistor DR can be sampled and stored in the first capacitor Cst. In the threshold voltage sampling period Y2 of the even-numbered frame, an electric potential of the gate node DTG can be the reference voltage Vref, and an electric potential of the source node DTS can be "Vref-Vth." Here, Vth can denote a threshold voltage of the drive transistor DR.

[0092] With reference to the Fig. 9 and Fig. 10C, in a data write period Y3 of the even-numbered frame, the first scan transistor ST1 may be turned on based on the first scan signal SCAN1 of the on-level Lon, the second scan transistor ST2 may be turned on based on the second scan signal SCAN2 of the on-level Lon, and a third scan transistor ST3 may be turned on based on a third scan signal SCAN3 of the on-level Lon. In addition, the other transistors DR, ST4, ET1, ET2, and ET3 may be turned off.

[0093] As a result, in the data write period Y3 of the even-numbered frame, a data voltage Vdata representing a white gray level may be supplied to the gate node DTG. In the data write period Y3 of the even-numbered frame, an electric potential of the gate node DTG may be the data voltage Vdata, and an electric potential of the source node DTS may be "Vref - Vth + C(Vdata-Vref)". Here, C may denote a value obtained by dividing a capacitance of the first capacitor Cst by a sum of the capacitance of the first capacitor Cst and a capacitance of the second capacitor CA.

[0094] In addition, the third scan signal SCAN3 may be delayed for a certain time Td from a start time T0 of the data write period Y3 and then shifted to the on-level Lon, thereby preventing an abnormal short circuit between the data line DL and the input terminal of the reference voltage Vref, which occurs because the third scan transistor ST3 and the fourth scan transistor ST4 are turned on simultaneously at a time (ie, T0) when the threshold voltage sampling period Y2 is changed to the data write period Y3.

[0095] With reference to the Fig. 9 and Fig. 10D, in a second initialization period Y4 of the even-numbered frame, the first scan transistor ST1 may be turned on based on the first scan signal SCAN1 of the on-level Lon, and the second scan transistor ST2 may be turned on based on the second scan signal SCAN2 of the on-level Lon. In addition, the other transistors DR, ST3, ST4, ET1, ET2, and ET3 may be turned off.

[0096] As a result, the reset voltage Var can be applied to a first anode electrode of a first light-emitting device OLED1 and a second anode electrode of a second light-emitting device OLED2. An electric potential of the first anode electrode and an electric potential of the second anode electrode can continuously maintain the reset voltage Var until the second initialization period Y4 from the first initialization period Y1.

[0097] Based on the reset voltage Var maintained by the first and second anode electrodes until the second initialization period Y4 from the first initialization period Y1, the first anode electrode of the first light-emitting device OLED1 and the second anode electrode of the second light-emitting device OLED2 can be equally initialized (or discharged) regardless of a gray level of a previous frame.

[0098] The first light-emitting device OLED1 and the second light-emitting device OLED2 may be turned off (or emit no light) until the second initialization period Y4 from the first initialization period Y1, and thus an image with a black gray level can be implemented.

[0099] With reference to the Fig. 9 and Fig.10E, in an emission period Y5 of the even-numbered frame, the first scanning transistor ST1 may be turned on based on the first scanning signal SCAN1 of the on-level Lon, a second emission transistor ET2 may be turned on based on a second emission signal EM2 of the on-level Lon, a third emission transistor ET3 may be turned on based on the third emission signal EM3 of the on-level Lon, and the driving transistor DR may be turned on. In addition, the other transistors ST2, ST3, ST4, and ET1 may be turned off.

[0100] In an emission period Y5 of the even-numbered frame, an electric potential of the gate node DTG may be "Vdata+Voled," and an electric potential of the source node DTS may be "Vref - Vth + C(Vdata-Vref) + Voled." Here, Voled may be a turn-on voltage (or an operating point voltage) of the second light-emitting device OLED2.

[0101] A potential difference Vgs between the gate node DTG and the source node DTS, which determines a drive current level, can be "Vdata - Vref - C(Vdata-Vref) + Vth." Accordingly, the drive current loled can be expressed as in Equation 1.

[0102] As in Equation 1, the driving current loled can be compensated independently of a shift in the threshold voltage Vth of the driving transistor DR, and the second light-emitting device OLED2 can be turned on (or emit light) by the driving current loled during the emission period Y5 of the even-numbered frame, thereby implementing a white gray-level image.

[0103] In contrast, the second light-emitting device OLED2 may be kept in an off state during an entire period of the even-numbered frame and thus be initialization-driven (or discharged).

[0104] As described above, in a case where a gray level of image data applied to a pixel is changed from black to white and then maintains a white gray level during a plurality of frames, the present disclosure can reduce a luminance deviation between a first frame immediately after the change to a white gray level and the other frames maintaining a white gray level, thereby improving display quality.

[0105] The effects according to the present disclosure are not limited to the above examples, and the description may include various other effects.

[0106] Although the present disclosure has been particularly shown and described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present disclosure as defined by the following claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2024-0025778

[0001]

Claims

[1] Pixel circuit that has: a drive transistor (DR) comprising: a gate electrode connected to a gate node (DTG) and a source electrode connected to a source node (DTS), and configured to generate a drive current; a first light-emitting device (OLED1) having a first anode electrode and configured to emit light in response to the driving current; a second light-emitting device (OLED2) having a second anode electrode and configured to emit light in response to the driving current; a first emission transistor (ET1) configured to connect the source node (DTS) to the first anode electrode in an odd-numbered frame and to disconnect the source node (DTS) from the first anode electrode during an even-numbered frame in response to a first emission signal (EM1); and a second emission transistor (ET2) configured to connect the source node (DTS) to the second anode electrode in the even-numbered frame and to disconnect the source node (DTS) from the second anode electrode during the odd-numbered frame in response to a second emission signal (EM2). [2] The pixel circuit of claim 1, further configured such that the first emission transistor (ET1) is turned on during an emission period (X5) of the odd-numbered frame and is turned off during all periods (Y1, ..., Y5) of the even-numbered frame, and the second emission transistor (ET2) is turned on during an emission period (Y5) of the even-numbered frame and is turned off during all periods (X1, ..., X5) of the odd-numbered frame. [3] The pixel circuit according to claim 1 or 2, further configured such that the first light-emitting device (OLED1) is turned on during an emission period (X5) of the odd-numbered frame and remains in an off state during the even-numbered frame, and the second light-emitting device (OLED2) is switched on during an emission period (Y5) of the even-numbered frame and remains in an off state during the odd-numbered frame. [4] A pixel circuit according to claim 3, further comprising: a first scan transistor (ST1) configured to apply a reset voltage (Var) to the first anode electrode based on a first scan signal (SCAN1); and a second scan transistor (ST2) configured to apply the reset voltage (Var) to the second anode electrode based on a second scan signal (SCAN2). [5] The pixel circuit according to claim 4, further configured such that the first scanning transistor (ST1) is turned on in the other periods (X1, ..., X4) except the emission period (X5) of the odd-numbered frame and in all periods (Y1, ..., Y5) of the even-numbered frame, and the second scanning transistor (ST2) is switched on in the other periods (Y1, ..., Y4) of the even-numbered frame, except for the emission period (Y5), and is switched on in all periods (X1, ..., X5) of the odd-numbered frame. [6] The pixel circuit according to claim 4 or 5, further configured so that in a data write period (X3) preceding the emission period (X5) of the odd-numbered frame or a data write period (Y3) preceding the emission period (Y5) of the even-numbered frame, a data voltage (Vdata) contained in a predetermined voltage range is applied to the gate node (DTG) to implement a gray level, and the reset voltage (Var) is less than a lower limit voltage value of the predetermined voltage range. [7] An electroluminescent display device comprising: a display panel (10) having a plurality of pixels (PXL); a gate driver (13) configured to drive scan lines and emission lines connected to the plurality of pixels (PXL); and a data driver (12) configured to drive data lines (14) connected to the plurality of pixels (PXL), wherein a pixel circuit comprises each of the plurality of pixels (PXL): a drive transistor (DR) comprising: a gate electrode connected to a gate node (DTG) and a source electrode connected to a source node (DTS), and configured to generate a drive current; a first light-emitting device (OLED1) having a first anode electrode and configured to emit light in response to the driving current; a second light-emitting device (OLED2) having a second anode electrode and configured to emit light in response to the driving current; a first emission transistor (ET1) configured to connect the source node (DTS) to the first anode electrode in an odd-numbered frame and to disconnect the source node (DTS) from the first anode electrode during an even-numbered frame in response to a first emission signal (EM1) supplied via a first emission line (EL1); and a second emission transistor (ET2) configured to connect the source node (DTS) to the second anode electrode in the even-numbered frame and to disconnect the source node (DTS) from the second anode electrode during the odd-numbered frame in response to a second emission signal (EM2) supplied via a second emission line (EL2). [8] The electroluminescent display device according to claim 7, further configured such that the first emission transistor (ET1) is turned on during an emission period (X5) of the odd-numbered frame and is turned off during all periods (Y1, ..., Y5) of the even-numbered frame, and the second emission transistor (ET2) is turned on during an emission period (Y5) of the even-numbered frame and is turned off during all periods (X1, ..., X5) of the odd-numbered frame. [9] The electroluminescent display device according to claim 7 or 8, further configured such that the first light-emitting device (OLED1) is turned on during an emission period (X5) of the odd-numbered frame and remains in an off state during the even-numbered frame, and the second light-emitting device (OLED2) is turned on during an emission period (Y5) of the even-numbered frame and remains in an off state during the odd-numbered frame. [10] An electroluminescent display device according to claim 9, further comprising: a first scan transistor (ST1) configured to supply a reset voltage (Var) to the first anode electrode based on a first scan signal (SCAN1) supplied via a first scan line (SL1); and a second scan transistor (ST2) configured to supply the reset voltage (Var) to the second anode electrode based on a second scan signal (SCAN2) supplied via a second scan line (SL2). [11] The electroluminescent display device according to claim 10, further configured such that the first scanning transistor (ST1) is turned on in the other periods (X1, ..., X4) except the emission period (X5) of the odd-numbered frame and in all periods (Y1, ..., Y5) of the even-numbered frame, and the second scanning transistor (ST2) is turned on in the other periods (Y1, ..., Y4) of the even-numbered frame except the emission period (Y5) and is turned on in all periods (X1, ..., X5) of the odd-numbered frame. [12] An electroluminescent display device according to claim 10 or 11, further configured such that in a data writing period (X3) preceding the emission period (X5) of the odd-numbered frame or a data writing period (Y3) preceding the emission period (Y5) of the even-numbered frame, a data voltage (Vdata) contained in a predetermined voltage range is applied to the gate node (DTG) to implement a gray level, and the reset voltage (Var) is less than a lower limit voltage value of the specified voltage range. [13] An electroluminescent display device according to any one of claims 7 to 12, wherein the pixel circuit is configured to in a period before an emission period (X5) of the odd-numbered frame, during the odd-numbered frame, supplies a reset voltage (Var) to the first and second anode electrodes and in a period before an emission period (Y5) of the even-numbered frame, during the even-numbered frame, supplies the reset voltage (Var) to the first and second anode electrodes.

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