Stacked multi-gate devices with optimized performance

Abstract

Semiconductor devices and methods for forming them are provided. An example method includes: forming a fin over a substrate, wherein a first section of the fin has a plurality of first channel layers interleaved with a plurality of first sacrificial layers, and a second section of the fin has a plurality of second channel layers interleaved with a plurality of second sacrificial layers; forming a trench extending through the fin; laterally sparing the plurality of first sacrificial layers and the plurality of second sacrificial layers with different etch rates; and replacing a remaining section of the plurality of first sacrificial layers with a first gate structure and replacing a remaining section of the plurality of second sacrificial layers with a second gate structure.

Description

PRIORITY DATA

[0001] This application claims priority over the preliminary US patent application serial no. 63 / 710,914, which was filed on October 23, 2024, and the entire disclosure of which is hereby incorporated by reference. BACKGROUND

[0002] The integrated semiconductor (IC) circuit industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. Function density (i.e., the number of interconnected components per unit area of ​​the chip) has generally increased throughout IC development, while geometric size (i.e., the smallest component (or trace) that can be produced using a manufacturing process) has decreased. This miniaturization (scaling) process offers fundamental advantages by increasing production efficiency and reducing associated costs.

[0003] Such miniaturization also increased the complexity of IC processing and manufacturing. As integrated circuit (IC) technologies have advanced to smaller technology nodes, multi-gate devices, for example, are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). A multi-gate device generally refers to a device that has a gate structure, or a portion thereof, that extends over more than one side of a channel region. Fin-type field-effect transistors (FinFETs) and gate-all-around transistors (GAA transistors) are examples of multi-gate devices that have become popular and promising candidates for high-performance, low-leakage-current applications.A FinFET features a raised channel enclosed by a gate on more than one side (for example, the gate encloses the top and side walls of a "fin" made of a semiconductor material extending from a substrate). A GAA transistor features a gate structure that can partially or completely surround a channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can be formed from nanowires, nanofilms, other nanostructures, and / or other suitable structures. The shapes of the channel region have also given rise to alternative names for a GAA transistor, such as nanofilm transistor or nanowire transistor.

[0004] As the semiconductor industry reached sub-10-nanometer technology nodes (sub-10 nm technology nodes) in pursuit of higher device density, improved performance, and lower costs, challenges related to both fabrication and design led to stacked device structures, such as complementary field-effect transistors (C-FETs), where a multi-gate n-transistor and a multi-gate p-transistor are stacked vertically. While existing C-FETs are generally functional, they are not satisfactory in all aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is best understood from the detailed description below, when read together with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a perspective view of a semiconductor device comprising a vertical C-FET, according to one or more aspects of the present disclosure. Fig. Figure 2 shows a flowchart of a first method for forming a semiconductor device comprising a vertical C-FET according to one or more aspects of the present disclosure. Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. Figure 32 shows cross-sectional views of the semiconductor device during various manufacturing stages in the first process of Fig. 2, according to various aspects of the present revelation. Fig. Figure 15 shows a flowchart of a second method for forming a semiconductor device having a vertical C-FET according to one or more aspects of the present disclosure. Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. Figure 20 shows cross-sectional views of the semiconductor device during various manufacturing stages in the second process of Fig. 15, according to various aspects of the present revelation. Fig. Figure 21 shows a flowchart of a third method for forming a semiconductor device comprising a vertical C-FET according to one or more aspects of the present disclosure. Fig. 22, Fig. 23, Fig. Figure 24 shows cross-sectional views of the semiconductor device during various manufacturing stages in the third process of Fig. 21, according to various aspects of the present revelation. Fig. Figure 25 shows a flowchart of a fourth method for forming a semiconductor device comprising a vertical C-FET according to one or more aspects of the present disclosure. Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. Figure 31 shows cross-sectional views of the semiconductor device during various manufacturing stages in the fourth process of Fig. 25, according to various aspects of the present revelation. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements may not be in direct contact.

[0007] Terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms used herein relating to spatial relativity may likewise be interpreted accordingly.

[0008] When a number or range of numbers is described with "approximately," "about," and the like, it is further intended that the term encompasses numbers that are within a reasonable range when variations inherent in manufacturing are taken into account, as understood by a person skilled in the art. For example, the number or range of numbers encompasses a reasonable range including the described number, such as within + / -10% of the described number, based on the manufacturing tolerances known per se that are associated with the production of an item that has a characteristic associated with the number.For example, a material layer that has a thickness of "approximately 5 nm" may have a dimensional range of 4.25 nm to 5.75 nm if it is known to a person skilled in the art that the manufacturing tolerances associated with the deposition of the material layer are + / -15%.

[0009] Integrated circuits incorporate a variety of circuit device components, such as transistors. Transistors with different configurations can be suitable for various circuit functions due to their differing performance characteristics. A stacked multi-gate device refers to a semiconductor device that includes a lower multi-gate device and an upper multi-gate device stacked above the lower multi-gate device. If the lower and upper multi-gate devices have different conductivity types, the stacked multi-gate device can be a complementary field-effect transistor (C-FET). The multi-gate devices in a C-FET can be FinFETs or GAA transistors. An n-type transistor (e.g., NFET) has a pair of n-doped source / drain elements, and its majority carriers are electrons. A p-type transistor (e.g.,A PFET has a p-doped source / drain pair, and its majority carriers are holes. If the NFET and PFET in a C-FET are manufactured with identical configurations (e.g., same channel sheet thickness, same gate length), either the PFET or the NFET may not exhibit its corresponding optimal performance. Furthermore, C-FETs can be configured to perform different functions (e.g., as part of a logic cell or as part of a memory cell) and / or can be used in different applications (e.g., high-performance computing (HPC) or low-current driving). These different functions or applications may require the C-FETs to exhibit different performance characteristics (e.g., high current handling capability or low power consumption).In some cases, a shorter gate length can lead to a lower channel resistance Rch, which can be advantageous for one aspect of the transistor's performance. However, if the gate length is too short, the gate drive capability may be unsatisfactory. A thinner channel can lead to better gate drive capability. However, if the channel thickness is too thin, the channel resistance Rch may be too high. The present disclosure shows several ways to design C-FETs with different performance capabilities by individually adapting the configurations of the upper multi-gate device and the lower multi-gate device.

[0010] The various aspects of this revelation will now be described in more detail with reference to the figures. In this respect, it shows Fig. 1 a perspective view of a semiconductor device comprising a vertical C-FET, according to one or more aspects of the present disclosure. Fig. 2, Fig. 15, Fig. 21, Fig. Figures 25 each show a flowchart of a method for forming a semiconductor device comprising a vertical C-FET, according to one or more aspects of the present disclosure. Methods that are Fig. 2, Fig. 15, Fig. 21, Fig. Figures 25 are merely examples and are not intended to limit the present disclosure to what is explicitly illustrated therein. Additional steps may be provided for additional embodiments of the method before, during, and after each process, and some described steps may be replaced, eliminated, or postponed. For the sake of simplicity, not all steps are described in detail here. Furthermore, throughout this application and in the various embodiments, identical reference numerals refer to identical elements with similar structures and compositions, unless otherwise indicated. To avoid confusion, the directions X, Y, and Z in the figures are perpendicular to each other and are used consistently throughout.

[0011] Fig. Figure 1 shows an example semiconductor device (e.g., a C-FET) 10. The semiconductor device 10 has a lower device 10L (e.g., a p-transistor) and an upper device 10U (e.g., an n-transistor) above the lower device 10L. The lower device 10L has a channel layer 26'L enclosed by a lower gate structure. The lower gate structure 72 has a gate dielectric layer 78 and a gate electrode 80L. The lower device 10L also has source / drain elements (e.g., epitaxial p-source / drain elements) 62L coupled to the channel layers 26'L and adjacent to the lower gate structure 72.

[0012] The upper device 10U has a channel layer 26'U enclosed by an upper gate structure 74. The upper gate structure 74 includes the gate dielectric layer 78 and a gate electrode 80U. The upper device 10U also has source / drain elements (e.g., epitaxial n-source / drain elements) 62U coupled to the channel layers 26'U and adjacent to the upper gate structure 74. An insulating layer 90 is arranged between the upper device 10U and the lower device 10L to electrically isolate the upper gate structure 74 of the upper device 10U from the lower gate structure 72 of the lower device 10L. The configurations of the elements in the semiconductor device 10 described above are shown for illustrative purposes and may be modified depending on the actual implementations. It is understood that some elements have been omitted from this figure for the sake of simplicity.

[0013] With reference to Fig. 2 and Fig. 3. Method 100 comprises a block 102 in which a superlattice structure 204 is formed over a substrate 202. In one embodiment, the substrate 202 can be a silicon substrate (Si substrate). In some other embodiments, the substrate 202 can comprise other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Examples of III-V semiconductor materials include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 can also have an insulating layer, such as a silicon oxide layer, to have an SOI (silicon on an insulator) structure.Although not explicitly shown in the figures, substrate 202 can have an n-well region and a p-well region for fabricating transistors of different conductivity types. If present, each is formed by the n-well and the p-well in substrate 202 and exhibits a doping profile. An n-well can have a doping profile of an n-type dopant, such as phosphorus (P) or arsenic (As). A p-well can have a doping profile of a p-type dopant, such as boron (B). The doping in the n-well and the p-well can be formed using ion implantation or thermal diffusion and can be considered sections of the substrate.

[0014] The superlattice structure 204 is formed over the substrate 202. The superlattice structure 204 can be deposited over the substrate 202 using an epitaxial process. Suitable epitaxial processes include vapor deposition (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. For ease of reference, the superlattice structure 204 can be vertically divided into a lower section 204B, a middle sacrificial layer 206M on the lower section 204B, and an upper section 204T on the middle sacrificial layer 206M.

[0015] The lower section 204B has a number of first channel layers (e.g., first channel layers 208L1, 208L2, 208L3) nested with a number of first sacrificial layers (e.g., first sacrificial layers 206L1, 206L2, 206L3). The first channel layers 208L1, 208L2, 208L3 can be referred to individually or collectively as the first channel layer(s) 208L. The first sacrificial layers 206L1, 206L2, 206L3 can be referred to individually or collectively as the first sacrificial layer(s) 206L. The first sacrificial layers 206L and the first channel layers 208L are deposited alternately, one after the other, to form the lower section 204B of the superlattice structure 204. The first sacrificial layers 206L and the first channel layers 208L can have different semiconductor compositions.In some implementations, the first channel layers 208L are formed from silicon (Si), and the first sacrificial layers 206L are formed from silicon germanium (SiGe). In these implementations, the additional germanium content in the first sacrificial layers 206L allows for selective removal or omission of the first sacrificial layers 206L without causing significant damage to the first channel layers 208L.

[0016] The upper section 204T features a number of second channel layers (e.g., second channel layers 208U1, 208U2, 208U3) nested with a number of second sacrificial layers (e.g., second sacrificial layers 206U1, 206U2). The second channel layers 208U1, 208U2, and 208U3 can be referred to individually or collectively as the second channel layer(s) 208U. The second sacrificial layers 206U1 and 206U2 can be referred to individually or collectively as the second sacrificial layer(s) 206U. The second sacrificial layers 206U and the second channel layers 208U are deposited alternately, one after the other, to form the upper section of the superlattice structure 204. The second sacrificial layers 206U and the second channel layers 208U can have different semiconductor compositions.In some implementations, the second channel layers 208U are formed from silicon (Si), and the second sacrificial layers 206U are formed from silicon germanium (SiGe). In these implementations, the additional germanium content in the second sacrificial layers 206U allows for the selective removal or omission of the second sacrificial layers 206U without causing significant damage to the second channel layers 208U. The channel layers 208L1, 208L2, 208L3, 208U1, 208U2, and 208U3 provide nanostructures for the C-FET. In some embodiments, channel layers 208U1-208U2 provide channel elements for an upper GAA transistor of the C-FET, and channel layers 208L2-208L3 provide channel elements for a lower GAA transistor in the C-FET.The term “channel element(s)” is used herein to denote any section of material for a channel (channels) in a transistor with nanoscale dimensions, having an elongated shape, regardless of the cross-sectional shape of that section.

[0017] In some existing technologies for forming C-FETs, the sacrificial layers 206 have exactly the same characteristics (e.g., thickness, composition). In this embodiment, to optimize the performance of C-FETs, the second sacrificial layers 206U and the first sacrificial layers 206L are configured to have different germanium concentrations. The germanium concentrations lead to different etch rates during a subsequent etching process and therefore to different gate lengths. In this illustrated embodiment, the first sacrificial layers 206L have a first germanium content. In one embodiment, the first germanium content of the first sacrificial layers 206L is between approximately 5% and approximately 45%.If the initial germanium content is less than 5%, a longer etching time may be required to remove the first sacrificial layers 206L in a subsequent channel release process, which can damage other elements adjacent to the sacrificial layers. Furthermore, a low germanium content can lead to poor etch selectivity between the first sacrificial layers 206L and the first channel layers 208L. This means that the first sacrificial layers 206L may not be selectively removed without significantly etching the first channel layers 208L, resulting in a reduced overlap area at the interface and increased parasitic resistance. If the initial germanium content is greater than 45%, more germanium diffuses into the first channel layers 208L, increasing the impurity concentration in these layers and impairing device performance.To achieve the etch rate difference described above, the second sacrificial layers 206U have a second germanium content that is higher than the first germanium content. In one embodiment, the second germanium content of the second sacrificial layers 206U is between approximately 10% and approximately 50%.

[0018] In one embodiment, etch selectivity is also present between the middle sacrificial layer 206M and the first sacrificial layers 206L, and between the middle sacrificial layer 206M and the second sacrificial layers 206U. In one embodiment, the middle sacrificial layer 206M is formed from silicon germanium, and the germanium content of the middle sacrificial layer 206M can differ from the first and second germanium contents of the first and second sacrificial layers 206U and 206L, respectively. In one embodiment, the middle sacrificial layer 206M has a third germanium content that is greater than the first and second germanium contents. The third germanium content is between approximately 30% and approximately 100%.If the third germanium content is less than 30%, the etch selectivity between the middle sacrificial layer 206M and other layers of the superlattice structure 204 may be too low to ensure the complete and selective removal of the middle sacrificial layer 206M without substantially etching the channel layers 208U and 208L.

[0019] In some embodiments, the bottommost channel layer 208L3 of the first channel layers 208L has a thickness T1, and the topmost channel layer 208U1 of the second channel layers 208U has a thickness T2. Each thickness T1 and T2 is in a range between approximately 3 nm and approximately 30 nm. If the thickness T1 or T2 is greater than 30 nm, the aspect ratio of the superlattice structure 204 may be increased, leading to a greater processing challenge. Furthermore, parasitic capacitance associated with the semiconductor device 200 may also increase, negatively impacting the performance of the semiconductor device 200. Conversely, if the thickness T1 or T2 is less than 3 nm, a reduced thickness of the channel layers 208 (e.g., the first channel layers 208L and / or the second channel layers 208U) may increase the difficulty of epitaxy for forming satisfactory layers in the superlattice structure 204.The first sacrificial layers 206L each have a thickness T3, and the second sacrificial layers 206U each have a thickness T4. Each thickness T3 and T4 is in a range between approximately 2 nm and approximately 30 nm. If the thickness T3 or T4 is greater than 30 nm, the aspect ratio of the superlattice structure 204 may be increased, leading to a greater process challenge. Furthermore, parasitic capacitance associated with the semiconductor device 200 may also increase, negatively impacting the performance of the semiconductor device 200. If the thickness T3 or T4 is less than 2 nm, a reduced thickness of the sacrificial layers 206 (e.g., the first sacrificial layers 206L and / or the second sacrificial layers 206U) may narrow the process window for forming satisfactory gate structures enclosing nanostructures. The middle sacrificial layer 206M has a thickness T5.The thickness T5 lies in a range between approximately 2 nm and approximately 30 nm. If the thickness T5 is greater than 30 nm, the aspect ratio of the superlattice structure 204 may be increased, leading to a greater process challenge; if the thickness T5 is less than 2 nm, a reduced thickness of the middle sacrificial layer 206M may reduce the process window for forming an insulating layer located between the gate structure of the upper device and the gate structure of the lower device. In this illustrated embodiment, the topmost channel layer 208L1 of the first channel layers 208L and the bottommost channel layer 208U3 of the second channel layers 208U are in direct contact with the middle sacrificial layer 206M and are released during subsequent fabrication processes to form nanostructures 2080N1 and 2080N2. The topmost channel layer 208L1 has a thickness T6. The bottommost channel layer 208U3 has a thickness T7.Thickness T6 and thickness T7 can be smaller than thickness T1. In one embodiment, thickness T6 and thickness T7 are each less than approximately 10 nm (e.g., 0 ≤ T6 ≤ 1 nm; 0 ≤ T7 ≤ 10 nm). If thickness T6 or T7 is greater than 10 nm, the aspect ratio of the superlattice structure 204 may be increased, leading to a greater process challenge. Furthermore, parasitic capacitance associated with the semiconductor device 200 may also increase, negatively impacting the performance of the semiconductor device 200.

[0020] It should be noted that the superlattice structure 204 in Fig. 3 comprising six (6) layers of channel layers 208 nested with six (6) layers of sacrificial layers 206, which is for illustrative purposes only and is not intended to limit beyond what is expressly stated in the claims. It is understood that any number of channel layers 208 may be incorporated in the superlattice structure 204 and distributed within the lower section 204B and the upper section 204T. The number of layers depends on the desired number of channel elements for the upper GAA transistor and the lower GAA transistor. In some embodiments, the number of channel layers 208 in the superlattice structure 204 may be between 2 and 10.

[0021] With reference to Fig. 4 and Fig. 5 the process 100 comprises a block 104 in which the superlattice structure 204 and an upper section 202t of the substrate 202 are structured to form fin-shaped structures 210. Fig. Figure 4 illustrates a cross-sectional view of the intermediate structure 200, and Fig. Figure 5 illustrates a cross-sectional view of the intermediate structure 200, which runs along the in Fig. The superlattice structure 204 is shown in line AA. After the superlattice structure 204 is formed, the superlattice structure 204 and the upper section 202t are then structured to form the fin-shaped structures 210. The structured section of the substrate 202 can be referred to as a projection 202t, a mesa 202t, or a base fin 202t. For structuring purposes, a hard mask layer can be deposited over the superlattice structure 204. The hard mask layer can be a single layer or a multilayer. In one example, the hard mask layer has a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. As shown in Fig. As shown in Figures 4-5, each fin-shaped structure 210 extends vertically along the Z-direction from the substrate 202 and longitudinally along the X-direction. The fin-shaped structures 210 can be structured using suitable processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, smaller pitches than can otherwise be achieved using a single direct photolithographic process. For example, in one embodiment, a layer of material is formed over a substrate and structured using a photolithographic process. Spacers are formed along the structured layer of material using a self-aligning process.The material layer is then removed and the remaining spacers, or spikes, can then be used as an etching mask for etching the superlattice structure 204 and the substrate 202 to form the fin-shaped structures 210.

[0022] The intermediate structure 200 also includes an insulating element 212 (shown in Fig. 4) formed around the fin-shaped structures 210 to separate two adjacent fin-shaped structures 210. The insulating element 212 can be referred to as its STI (shallow trench insulation) element 212. In an example process, a dielectric material for the insulating element 212 is deposited over the intermediate structure 200, which has the fin-shaped structure 210, using a CVD, a subatmospheric CVD (SACVD), a flowable CVD, a rotational coating, and / or another suitable process. The deposited dielectric material is then planarized and recessed to form the insulating element 212. As in Fig. As shown in Figure 4, the fin-shaped structure 210 projects beyond the insulating element 212. The dielectric material for the insulating element 212 can include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials.

[0023] With reference to Fig. 2 and Fig. In section 6, the process 100 comprises a block 106 in which dummy gate stacks 214 are formed over channel regions 210C of the fin-shaped structure 210. In some embodiments, a gate-exchange process (or gate-last process) is used, wherein the dummy gate stack 214 is to be replaced as a placeholder for a functional gate structure. Other processes and embodiments are possible. To form the dummy gate stack 214, a dummy dielectric layer 216, a dummy gate electrode layer 218, and a gate-top hard mask layer 220 are deposited over the intermediate structure 200.The deposition of these layers can involve the use of chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electron beam evaporation, other suitable deposition techniques, and / or combinations thereof. The dummy dielectric layer 216 can contain silicon oxide, the dummy gate electrode layer 218 can contain polysilicon, and the gate-top hard mask layer 220 can be a multilayer structure containing silicon oxide and silicon nitride. The gate-top hard mask layer 220 is patterned using photolithographic and etching processes. The photolithographic process can include photoresist deposition (e.g., rotary coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g.,The etching process may include rotary drying and / or hard baking), other suitable lithographic techniques, and / or combinations thereof. The etching process may include dry etching, wet etching, and / or other etching methods. Similar to the fin-shaped structures 210, the dummy gate stack 214 may also be patterned using double-patterning or multiple-patterning techniques. Subsequently, using the patterned gate-top hard mask 220 as an etching mask, the dummy dielectric layer 216 and dummy gate electrode layer 218 are etched to form the dummy gate stack 214. The dummy gate stack 214 extends longitudinally along the Y-direction to enclose the fin-shaped structure 210 and terminates on the insulating element 212. The portion of the fin-shaped structure 210 that lies beneath the dummy gate stack 214 defines a channel region 210C.Channel region 210C and dummy gate stack 214 also define source / drain regions 210SD that are not vertically overlapped by dummy gate stack 214. Channel region 210C is located between two source / drain regions 210SD along the Y-direction. A source / drain region (or regions) can, individually or collectively, refer to a source region to form a source and / or a drain region to form a drain, depending on the context.

[0024] With further reference to Fig. 2 and Fig. In section 6, the process 100 comprises a block 108 in which source-drain regions 210SD of the fin-shaped structure 210 are recessed to form trenches 224. Operations at block 108 may include forming at least one gatespacer 222 over the sidewalls of the dummy gate stack 214 before the source-drain regions 210SD are recessed. In some embodiments, forming the at least one gatespacer 222 includes depositing one or more dielectric layers over the intermediate structure 200. In an example process, the one or more dielectric layers are conformally deposited using CVD, SACVD, or ALD. The one or more dielectric layers may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxicacarbide, silicon oxicacarbonitride, and / or combinations thereof.In some embodiments, fin sidewall spacers 222' (shown in . Fig. 10) together with the gatespacer 222. The fin sidewall spacers 222' and the gatespacer 222 have the same composition. After the gatespacer 222 has formed, an anisotropic etching process is carried out on the intermediate structure 200 to form the trenches 224. The etching process at block 108 can be a dry etching process or another suitable etching process. An example of a dry etching process can implement an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF4, SF6, NF3, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. As in Fig. As shown in Figure 6, the side walls of the sacrificial layers 206 and the channel layers 208 in the channel areas 210C are exposed in the trenches 224. In one embodiment, the trenches 224 have substantially straight side walls. That is, after the trenches 224 have been formed, the channel layers 208 and the sacrificial layers 206 can have a substantially uniform width.

[0025] With reference to Fig. 2 and 7-8, the process 100 comprises a block 110 in which internal spacer elements 226 are formed. With reference to Fig. In section 7, an etching process is performed on block 110 to selectively and partially recess the sacrificial layers 206 exposed in the trenches 224, so that internal space recesses 225 are formed without substantially etching the exposed channel layers 208. In this embodiment, the second sacrificial layers 206U have a second germanium content that is greater than the first germanium content of the first sacrificial layers 206L, and an etchant in the etching process etches the second sacrificial layers 206U at a higher rate than it etches the first sacrificial layers 206L. In some embodiments, the etching process can be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the first sacrificial layers 206L and the second sacrificial layers 206U are recessed is controlled by the duration of the etching process.The selective dry etching process can involve the use of one or more fluorine-based etchants, such as fluorine gas or fluorocarbons. The selective wet etching process can involve the use of hydrogen fluoride (HF) or ammonium hydroxide (NH4OH). In this illustrated embodiment, the inner spacer recesses 225 have an inner spacer recess 225a, which is arranged between the channel layers 208U1 and 208U2, an inner spacer recess 225b, which is arranged between the channel layers 208U2 and 208U3, an inner spacer recess 225c, which is arranged between the channel layers 208L1 and 208L2, an inner spacer recess 225d, which is arranged between the channel layers 208L2 and 208L3, and an inner spacer recess 225e, which is arranged between the channel layer 208L3 and the substrate 202.The inner spacer recesses 225a and 225b are formed above the middle sacrificial layer 206M, and the inner spacer recesses 225c, 225d, and 225e are formed below the middle sacrificial layer 206M. After completion of the etching process, the inner spacer recess 225c / 225d / 225e extends over a first width W1, and the inner spacer recess 225a / 225b extends over a second width W2, which is greater than the width W1. Likewise, the recessed first sacrificial layer 206L has a width greater than the width of the recessed second sacrificial layer 206U.

[0026] With reference to Fig. 8 After forming the inner spacer recesses 225, an inner spacer material layer is deposited over the intermediate structure 200, which has the inner spacer recesses 225. The inner spacer material layer can contain silicon oxide, silicon nitride, silicon oxica carbide, silicon oxica carbonitride, silicon carbonitride, metal nitride, or another suitable dielectric material. The deposited inner spacer material layer is then back-etched to remove excess sections of the inner spacer material layer over the dummy gate stack 214, the gate spacer 222, and sidewalls of the channel layers 208, thereby removing the Fig. The inner spacer elements 226 shown in Figure 8 are formed. The inner spacer elements 225 correspond to the shape of the inner spacer recesses 225. In the present embodiments, the inner spacer elements 226 comprise an inner spacer element 226a formed in the inner spacer recess 225a, an inner spacer element 226b formed in the inner spacer recess 225b, an inner spacer element 226c formed in the inner spacer recess 225c, an inner spacer element 226d formed in the inner spacer recess 225d, and an inner spacer element 226e formed in the inner spacer recess 225e. The inner spacer element 226a / 226b has a width of W2, and the inner spacer element 226c / 226d / 226e has a width of W1, which is smaller than the width W2.

[0027] As through Fig. 7 and Fig. In the embodiment shown in Figure 8, the middle sacrificial layer 206M is replaced by a middle dielectric layer 226M. In this embodiment, the middle sacrificial layer 206M remains unetched during the formation of the inner spacer recesses 225. This can be achieved by selectively forming an inhibitor layer that covers the exposed sidewalls of the middle sacrificial layer 206M. The inhibitor layer can be removed after the formation of the inner spacer elements 226. A further etching process can then be carried out to selectively remove the middle sacrificial layer 206M. A dielectric material can then be deposited in the space left behind by the selective removal of the middle sacrificial layer 206M, thereby forming the middle dielectric layer 226M.The middle dielectric layer 226M and the inner spacer elements 226 can have the same composition or they can be formed from different compositions. In some alternative embodiments, no inhibitor layer is formed during the formation of the inner spacer recesses 225 to cover the exposed sidewalls of the middle sacrificial layer 206M. Due to its higher germanium content, the middle sacrificial layer 206M can be substantially removed during the formation of the inner spacer recesses 225. The inner spacer material layer can also be deposited in the space left behind by selective removal of the middle sacrificial layer 206M, thereby forming the middle dielectric layer 226M.

[0028] With further reference to Fig. 2 and Fig. In Figure 8, the method 100 comprises a block 112 in which lower source / drain elements 230 are formed in the grooves 224. In some embodiments, a blocking layer (not shown) can be deposited over the intermediate structure 200 prior to the deposition of the lower source / drain elements 230 to cover sidewalls of the upper section 204T of the superlattice structure 204. The blocking layer can also cover sidewalls of the middle dielectric layer 226M and the channel layer 208L1. The blocking layer can contain dielectric materials. After the formation of the blocking layer, the lower source / drain elements 230 can be formed using an epitaxial process, such as VPE, UHV-CVD, MPE, and / or other suitable processes.The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the composition of the substrate 202 and the channel layers 208 that are not covered by the blocking layer. In the present embodiments, the epitaxial growth of the lower source / drain elements 230 can occur both from the upper surface of the substrate 202 and from the exposed sidewalls of the channel layers 208L2 and 208L3. Due to its dielectric composition, the blocking layer prevents the formation of the lower source / drain elements 230 on the sidewalls of the channel layers 208U1-208U3 and 208L1. As shown in... Fig. As shown in Figure 8, the lower source / drain elements 230 are in physical contact with (or adjacent to) the channel layers 208L2 and 208L3. Depending on the design, the lower source / drain elements 230 can be n-type or p-type. In the illustrated embodiments, the lower source / drain elements 230 are p-type and can contain germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or another suitable material, and can be doped in situ during the epitaxial process by introducing a p-type dopant, such as boron or gallium, or ex situ using a transition implantation process. In some cases, an undoped semiconductor layer 228 (e.g. undoped silicon or undoped silicon germanium) can be formed in the trenches 224 before the lower source / drain elements 230 are formed, in order to fill a lower section of the trenches 224.

[0029] With further reference to Fig. 2 and Fig. In Figure 8, the process 100 comprises a block 114 in which a lower contact etch stop layer (CESL) 332 and a lower dielectric intermediate layer (ILD) 234 are formed over the lower source / drain elements 230. The lower CESL 232 may contain silicon nitride, silicon oxicarbonate, and / or other materials and may be formed by means of a CVD, an ALD, a plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. In one embodiment, the lower CESL 232 contains silicon nitride. In some embodiments, the lower CESL 232 is first conformally deposited on the intermediate structure 200, and the lower ILD 234 is deposited over the lower CESL 232 by a spin coating, a flowable CVD (FCVD), a CVD, or another suitable deposition technique. The lower ILD layer 234 can contain materials such as e.g.Tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass or doped silicon dioxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. The lower CESL 232 and the lower ILD layer 234 can be etched back to exposed sidewalls of the channel layers 208U1 and 208U2. In embodiments described by... Fig. As illustrated in Figure 8, after back-etching the lower CESL 232 is in direct contact with the inner spacer elements 226b-226c, the channel layers 208U3 and 208L1, and the middle dielectric layer 226M. The blocking layer can be removed during back-etching of the lower CESL 232 and the lower ILD layer 234.

[0030] With further reference to Fig. 2 and Fig. In section 8, process 100 comprises a block 116 in which upper source / drain elements 248 are formed above the lower CESL 232 and the lower ILD layer 234. The upper source / drain elements 248 can be formed using an epitaxial process, such as VPE, UHV-CVD, MPE, and / or other suitable processes. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with a composition of the channel layers (e.g., channel layers 208U1 and 208U2) of the upper section 204T of the superlattice structure 204. The epitaxial growth of upper source / drain elements 248 can occur from the exposed sidewalls of channel layers 208U1 and 208U2. The isolated upper source / drain elements 248 are in physical contact with (or adjacent to) the channel layers of the upper section 204T of the superlattice structure 204.Depending on the design, the upper source / drain elements 248 can be of n-type or p-type. In the illustrated embodiments, the upper source / drain elements 248 are n-type and can contain silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or another suitable material. They can be doped in situ during the epitaxial process by introducing an n-type dopant, such as phosphorus, arsenic, or antimony, or ex situ using a transition implantation process. In some embodiments, an additional dielectric layer (e.g., silicon nitride) can be formed over the lower CESL 232 and the lower ILD 234 prior to the formation of the upper source / drain elements 248. This additional dielectric layer can be positioned between the upper source / drain elements 248 and the lower CESL 232 and the lower ILD 234.

[0031] With further reference to Fig. 2 and Fig. In Figure 8, the process 100 comprises a block 118 in which an upper CESL 250 and an upper ILD layer 252 are deposited over the upper source / drain elements 248. The upper CESL 250 can contain silicon nitride, silicon oxicarbonate, and / or other materials known in the art and can be formed by means of a CVD, an ALD, a plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. In some embodiments, the upper CESL 250 is first conformally deposited on the intermediate structure 200, and the upper ILD layer 252 is then deposited over the upper CESL 250 by a spin coating, FCVD, CVD, or another suitable deposition technique. The upper ILD layer 252 can comprise materials such as tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass, or doped silicon oxide, such as...Boron phosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. In some embodiments, after the formation of the upper ILD layer 252, the intermediate structure 200 can be tempered to improve the integrity of the ILD layer 252. To remove excess material and expose the upper surfaces of the dummy gate electrode layers 218, a planarization process, such as a chemical-mechanical polishing (CMP) process, can be performed.

[0032] With reference to Fig. In sections 2 and 9-10, procedure 100 includes a block 120 in which the dummy gate stack 214 and the sacrificial layers 206 are replaced by gate structures. Fig. Figure 10 shows a partial cross-sectional view of the intermediate structure 200, which runs along the in Fig. The process is shown in line BB in Figure 9. Operations at block 120 can include the removal of the dummy gate stacks 214, the exposure of the channel layers 208 as channel elements (comprising upper channel elements 2080U1, 2080U2, and lower channel elements 2080L1, and 2080L2), and nanostructures (comprising nanostructures 2080N1 and 2080N2). The removal of the dummy gate stacks 214 can involve one or more etching processes that are selective with respect to the material in the dummy gate stacks 214. For example, the removal of the dummy gate stacks 214 can be performed using selective wet etching, selective dry etching, or a combination thereof. The selective removal of the dummy gate stacks 214 forms gate trenches (now filled by an outer section 254O of the upper gate structures 254T).

[0033] After removal of the dummy gate stacks 214, the sidewalls of the channel layers 208 and sacrificial layers 206 in the channel regions 210C are exposed. The sacrificial layers 206 in the channel regions 210C are then selectively removed to expose the channel layers 208 as the channel elements (comprising the upper channel elements 2080U1, 2080U2, the lower channel elements 2080L1, and 2080L2) and nanostructures (comprising the nanostructures 2080N1 and 2080N2). In embodiments described by Fig. 9 are represented, the upper channel elements 2080U1 and 2080U2 are in direct contact with the upper source / drain elements 248; the lower channel elements 2080L1 and 2080L2 are in direct contact with the lower source / drain elements 230; and the nanostructures 2080N1, 2080N2 and the middle dielectric layer 226M are in direct contact with the lower CESL 232.

[0034] The selective removal of the first sacrificial layers 206L forms first gate openings (now filled by the lower gate structures 254B), and the selective removal of the second sacrificial layers 206U forms second gate openings (now filled by an inner section 2541 of the upper gate structures 254T). The first gate openings extend over a width greater than the width of the second gate openings. The selective removal of the sacrificial layers 206 can be implemented by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etching includes APM etching (e.g., an ammonia-water-hydrogen peroxide-water mixture). In some other embodiments, the selective removal includes SiGe oxidation followed by silicon germanium oxide removal.For example, oxidation can be achieved by ozone purification followed by the removal of silicon germanium oxide by an etchant, such as NH4OH.

[0035] The lower gate structure 254B is then formed in the first gate opening and adjacent to the lower source / drain elements 230, and the upper gate structure 254T is formed in the second gate opening and adjacent to the upper source / drain elements 248 and in the gate groove. The lower gate structure 254B and the upper gate structure 254T can be referred to individually or collectively as a gate structure 254. The lower gate structure 254B is configured to enclose each of the lower channel elements 2080L1 and 2080L2, forming a lower multi-gate transistor 260B (e.g., similar to device 10L in [reference]). Fig. 1) is formed, and the upper gate structure 254T is formed such that it encloses each of the upper channel elements 2080U1 and 2080U2, thereby forming an upper multi-gate transistor 260T (e.g. similar to the device 10U in Fig. 1), which is located above the lower multi-gate transistor 260B.

[0036] Forming the lower gate structure 254B and the upper gate structure 254T comprises forming a lower gate dielectric layer 254a surrounding the channel elements 2080L1 and 2080L2, and an upper gate dielectric layer 254b surrounding the channel elements 2080U1 and 2080U2. In one embodiment, the lower gate dielectric layer 254a and the upper gate dielectric layer 254b are formed simultaneously and have the same composition. For example, each of the lower gate dielectric layer 254a and the upper gate dielectric layer 254b has an interface layer (not separately characterized) and a high-k dielectric layer (not separately characterized) above the interface layer. The interface layer can be formed over the channel elements 2080U1-2080U2, 2080L1-2080L2 and the nanostructures 2080N1-2080N2 and covers the upper and side wall surfaces of projections 202t.The interface layer can be formed by thermal oxidation, chemical oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), another suitable process, or a combination thereof. In embodiments where the interface layer is formed by thermal oxidation, the interface layer forms on semiconductor surfaces (e.g., channel elements 208011-2080U2, 2080L1-2080L2, and the nanostructures 2080N1-2080N2), but not on dielectric surfaces (e.g., insulating elements 212). In some other embodiments, the interface layer can be conformally deposited over the substrate 202, including the insulating elements 212. The interface layer contains a dielectric material, such as SiO2 or SiGeO. x, HfSiO, SiON, another dielectric material, or a combination thereof. In some embodiments, the interface layer comprises group IV-based oxide layers, which generally refer to oxides of a group IV-based material (i.e., a material containing at least one group IV element, such as Si, Ge, C, etc.). In some embodiments, the interface layer comprises group III-V-based oxide layers, which generally refer to oxides of a group III-V-based material (i.e., a material containing at least one group III element, such as Al, Ga, In, B, etc., and one group V element, such as N, P, As, Sb, etc.). The high-K dielectric layer may contain dielectric materials exhibiting a high dielectric constant, for example, greater than that of silicon dioxide.Examples of high-k dielectric materials include hafnium, zirconium, tantalum, titanium, oxygen, nitrogen, another suitable component, or combinations thereof. In some implementations, the high-k dielectric layer may contain a high-k dielectric material, such as HfO₂, HfSiO₂, HfSiON₂, HfTaO, HfTiO₂, HfZrO₂, ZrO₂, TiO₂, Ta₂O₅, another suitable high-k dielectric material, or combinations thereof. Forming the lower gate structure 254B and the upper gate structure 254T also includes forming a lower gate electrode 254c for the lower gate structure 254B and an upper gate electrode 254d for the upper gate structure 254T.Each of the lower and upper gate electrodes 254c-254d can have one or more output work layers with suitable output work, so that the corresponding transistor is improved in terms of its device performance (for example, has a reduced threshold voltage).

[0037] In embodiments where the lower multi-gate transistor 260B is a p-type transistor and the upper multi-gate transistor 260T is an n-type transistor, the lower gate electrode 254c has a p-type exit layer, and the upper gate electrode 254d has an n-type exit layer. The n-type exit layer can contain a titanium-aluminum-based metal, such as titanium-aluminum-carbon (TiAlC) or titanium-aluminum (TiAl). The p-type exit layer can contain titanium nitride (TiN), tungsten carbonitride (WCN), tantalum nitride (TaN), or molybdenum nitride (MoN). The gate electrode 254c / 254d may also have a metal fill layer comprising aluminium (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or a combination thereof.

[0038] The lower gate structure 254B has a first gate length Lg1 along the X-direction, and the inner section 2541 of the upper gate structure 254T has a second gate length Lg2 that is shorter than the first gate length Lg1. In one embodiment, the ratio of the second gate length Lg2 to the first gate length Lg1 is greater than 0.3 and less than 1. If the ratio is less than 0.3, then the inner section 254I of the upper gate structure 254T may be too short, resulting in weak gate control and increased leakage current. By forming gate structures with different gate lengths (Lg1, Lg2), the performance of the upper multi-gate transistor 260T and the lower multi-gate transistor 260B can be adjusted. In general, the performance of the transistor with a longer gate length may be lower than that of the transistor with a shorter gate length.In one embodiment, the lower multi-gate transistor 260B is a p-transistor and the upper multi-gate transistor 260T is an n-transistor, and the performance of the lower multi-gate transistor 260B is weaker than the performance of the upper multi-gate transistor 260T.

[0039] With further reference to Fig. 2 and Fig. In section 9, the method 100 comprises a block 122 in which further processes are carried out to complete the fabrication of the semiconductor device 200. Such further processes may include forming a dielectric cover layer 255 over the upper gate structure 254T. These further processes may also include forming a silicide layer over the upper source / drain elements and forming a multilayer interconnect (MLI) structure over the intermediate structure 200. The MLI may include various interconnect elements, such as vias and conductive traces, arranged in dielectric layers, such as etch stop layers and ILD layers. In some embodiments, the vias are vertical interconnect elements configured to connect device-level contacts, such as source / drain contacts, formed over the upper source / drain elements 248.Furthermore, other processes can be carried out.

[0040] Method 100 can be applied to form an IC structure 300 with improved performance (e.g., improved speed, reduced power consumption, or reduced performance difference between NFETs and PFETs). For example, the semiconductor device 200 is part of the IC structure 300. With reference to Fig. Figures 11, 12A-12B, and 13 show that the IC structure 300 comprises at least one array of memory cells. The array may include static random-access memory cells (SRAM cells), dynamic random-access memory cells (DRAM cells), non-volatile random-access memory cells (NVRAM cells), flash memory cells, other suitable memory cells, or combinations thereof. In one embodiment, the array comprises a number of SRAM cells that generally provide a memory or storage device capable of retaining data when supplied. In the present embodiments, each SRAM cell comprises one or more C-FETs 200 as described above.

[0041] Fig. Figure 11 shows an example circuit diagram for a single-port SRAM cell (e.g., a 1-bit SRAM cell). The single-port SRAM cell has pull-up transistors PU-1 and PU-2; pull-down transistors PD-1 and PD-2; and pass-gate transistors PG-1 and PG-2. As shown in the circuit diagram, transistors PU-1 and PU-2 are P-type transistors, and transistors PG-1, PG-2, PD-1, and PD-2 are N-type transistors. The drains of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled together, and the drains of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled together. Transistors PU-1 and PD-1 are cross-coupled with transistors PU-2 and PD-2 to form an initial data latch.The gates of transistors PU-2 and PD-2 are coupled to each other and to the drains of transistors PU-1 and PD-1 to form a first memory node SN1, and the gates of transistors PU-1 and PD-1 are coupled to each other and to the drains of transistors PU-2 and PD-2 to form a complementary memory node SNB1. The sources of the pull-up transistors PU-1 and PU-2 are coupled to a power voltage Vdd, and the sources of the pull-down transistors PD-1 and PD-2 are coupled to a voltage Vss, which in some embodiments may be an electrical ground. The first memory node SN1 of the first data latch is coupled to a bit line BL via the pass-gate transistor PG-1, and the complementary first memory node SNB1 is coupled to a complementary bit line BLB via the pass-gate transistor PG-2.The first memory node SN1 and the complementary first memory node SNB1 are complementary nodes that are often at opposite logic levels (logic high or logic low). The gates of pass-gate transistors PG-1 and PG-2 are coupled by a word line WL. In this embodiment, p-transistors (e.g., PU-1, PU-2) have a gate length that is greater than the gate length of n-transistors (e.g., PD-1, PD-2, PG-1, PG-2).

[0042] In this embodiment, the SRAM cell is a C-FET-based SRAM cell. Fig. Figure 12A shows a fragmentary front-side layout of the SRAM cell of the IC structure 300. Fig. Figure 12B shows a fragmentary back-side layout of the SRAM cell of IC structure 300. The SRAM cell has active regions 305a, each located in a p-doped region, and active regions 305b, each located in an n-doped region. The active regions 305a and 305b may be similar to the active regions 210 after the channel release process. The SRAM cell of IC structure 300 has gate structures 310a, 310b, 310c, and 310d that enclose the channel regions of the active regions 305a and 305b of various transistors, such as pull-down transistors PD-1 and PD-2, pull-up transistors PU-1 and PU-2, and pass-gate transistors PG-1 and PG-2.Gate structure 310a and active region 305a form part of pull-down transistor PD-1, gate structure 310b and active region 305a form part of pass-gate transistor PG-1, gate structure 310a and active region 305b form part of pass-gate transistor PG-2, and gate structure 310b and active region 305b form part of pull-down transistor PD-2. Gate structure 310c and active region 305a form part of pull-up transistor PU-1, and gate structure 310d and active region 305b form part of pull-up transistor PU-2. Each of the gate structures 310a and 310b can be similar to the upper gate structure 254T, and each of the gate structures 310c and 310d can be similar to the lower gate structure 254B. The SRAM cell has a cell 380.The IC structure 300 also includes a number of gate isolation elements 390 which are configured to cut at least one of the gate structures 310a-310d into physically and electrically isolated pieces.

[0043] Fig. Figure 13 shows a partial cross-sectional view of the SRAM cell of the IC structure 300, which is located along the Fig. Line CC is shown in 12A-12B. As shown by Fig. As represented by 13, the pull-down transistor PD-1 is formed across the pull-up transistor PU-1. The pull-down transistor PD-1 and the pass-gate transistor PG-1 are similar to the upper multi-gate transistor 260T, and the pull-up transistor PU-1 is similar to the lower multi-gate transistor 260B. That is, the gate length of the pass-gate transistor PG-1 and the pull-down transistor PD-1 is smaller than the gate length of the pull-up transistor PU-1.

[0044] By reducing the gate lengths of the pass-gate transistors PG-1, PG-2 and the pull-down transistors PD-1, PD-2, the saturation current Isat of the pass-gate transistors PG-1, PG-2 can be reduced. Therefore, the "alpha ratio" of the saturation currents, which represents the ratio of the saturation current Isat of the pull-up transistors to the saturation current Isat of the pass-gate transistors, can be increased to achieve a larger write window and thus better write headroom.

[0045] In the above with reference to Fig. In embodiments 3 to 13 described, the first sacrificial layers 206L of the superlattice structure 204 have a germanium content that is lower than that of the second sacrificial layers 206U, and the resulting semiconductor device 200 and the IC structure 300 comprise a C-FET having an upper multi-gate device and a lower multi-gate device, wherein a gate length Lg1 of the gate structure of the lower multi-gate device is greater than a gate length Lg2 of the gate structure of the upper multi-gate device. The upper multi-gate device can be an n-device or a p-device, and the lower multi-gate device can be a p-device or an n-device. In a Fig. In the alternative embodiment represented in Figure 14, the first sacrificial layers 206L of the superlattice structure 204 have a germanium content greater than that of the second sacrificial layers 206U, and the resulting semiconductor device 400 comprises a C-FET having an upper multi-gate device 260T' and a lower multi-gate device 260B', wherein a gate length Lg1' of a gate structure 254B' of the lower multi-gate device 260B' is shorter than a gate length Lg2' of an inner section 254I' of a gate structure 254T' of the upper multi-gate device 260T'. The ratio of gate length Lg2' to gate length Lg1' is greater than 1 and less than 3. If the ratio is greater than 0.3, the lower gate structure may be too short, leading to weak gate control and increased leakage current.The upper multi-gate device 260T' can be an n-type or a p-type device, and the lower multi-gate device 260B' can be a p-type or an n-type device. In one embodiment, the semiconductor device 400 comprises an upper multi-gate n-type device 260T' and a lower multi-gate p-type device 260B'. Compared with existing C-FETs that have the same gate length for the lower multi-gate device and the upper multi-gate device, the upper multi-gate n-type device 260T', with its increased gate length Lg2', can dissipate less power than the upper multi-gate n-type device of the existing C-FETs.The semiconductor device 400 also includes internal spacer elements 226', and the internal spacer elements 226a'-226b' formed above the central dielectric layer 226M have a width W2 that is smaller than the width W1 of the internal spacer elements 226c', 226d', 226e' formed below the central dielectric layer 226M. Other elements of the semiconductor device 400 that are similar to those of the semiconductor device 200 are represented by the same reference numerals, and a repeated description of these similar elements is omitted for the sake of simplicity.

[0046] In one embodiment, the semiconductor device 400 can be a section of a logic cell (e.g., a NOR gate) comprising one or more C-FETs. A path is defined as a route for signal distribution in a circuit. A critical path is the region that significantly determines the circuit speed (or signal distribution speed), which depends on various circuit applications. If the circuit speed varies strongly with the performance of transistors, then the path is called a critical path; if the circuit speed is not significantly associated with the performance of transistors, the path is called a non-critical path.It is advantageous if the critical path and the non-critical path are designed to have different configurations during operation in order to reduce power consumption while maintaining a satisfactory circuit speed. In one embodiment, to achieve lower power consumption, n-transistors in a non-critical path can be configured similarly to the upper multi-gate device 260T' of semiconductor device 400, and p-transistors in a critical path can be configured similarly to the lower multi-gate device 260B' of semiconductor device 400. Other suitable applications are also possible.

[0047] In the foregoing embodiments, the performance of the C-FETs is optimized by individually optimizing the gate lengths of the upper and lower multi-gate devices. In another embodiment, the performance of the C-FETs can be optimized by individually optimizing the channel thicknesses of the upper and lower multi-gate devices. Fig. Figure 15 shows a flowchart of a method 500 for forming a semiconductor device 600 having a vertical C-FET, according to one or more aspects of the present disclosure. The method 500 is used in conjunction with Fig. Figures 16 to 20 describe the cross-sectional views of the semiconductor device 600 at various manufacturing stages according to embodiments of the method 500.

[0048] With reference to Fig. 15 and Fig. In section 16, process 500 comprises a block 502 in which a superlattice structure 604 is formed over the substrate 202. The fabrication processes for forming the superlattice structure 604 are the same as those for the superlattice structure 204. Differences between the superlattice structure 604 and the superlattice structure 204 include the dimensional relationships between different layers within the superlattice structure 604. In particular, the superlattice structure 604 has a lower section 604B, a middle sacrificial layer 606M on the lower section 604B, and an upper section 604T on the middle sacrificial layer 606M. The lower section 604B has a number of first channel layers (e.g., first channel layers 608L1, 608L2, 608L3) nested with a number of first sacrificial layers (e.g., first sacrificial layers 606L1, 606L2, 606L3).The first channel layers 608L1, 608L2, 608L3 can be referred to individually or collectively as the first channel layer(s) 608L. The first sacrificial layers 606L1, 606L2, 606L3 can be referred to individually or collectively as the first sacrificial layer(s) 606L. In some implementations, the first channel layers 608L are formed from silicon (Si), and the first sacrificial layers 606L are formed from silicon germanium (SiGe).

[0049] The upper section 604T features a number of second channel layers (e.g., second channel layers 608U1, 608U2, 608U3) nested with a number of second sacrificial layers (e.g., second sacrificial layers 606U1, 606U2). The second channel layers 608U1, 608U2, and 608U3 can be referred to individually or collectively as the second channel layer(s) 608U. The second sacrificial layers 606U1 and 606U2 can be referred to individually or collectively as the second sacrificial layer(s) 606U. In some implementations, the second channel layers 608U are formed from silicon (Si), and the second sacrificial layers 606U are formed from silicon germanium (SiGe). In this embodiment, the first and second sacrificial layers 606L and 606U have the same germanium content, which is smaller than the third germanium content of the middle sacrificial layer 606M.Channel layers 608L1, 608L2, 608L3, 608U1, 608U2, and 608U3 provide nanostructures for the C-FET. In some embodiments, the second channel layers 608U1-608U2 provide channel elements for an upper GAA transistor of the C-FET, and channel layers 608L2-608L3 provide channel elements for a lower GAA transistor in the C-FET. The term "channel element(s)" is used herein to denote any portion of material for a channel (channels) in a transistor with nanoscale dimensions that has an elongated shape, regardless of the cross-sectional shape of that portion. In some existing technologies for forming C-FETs, the first and second channel layers 608L1 and 608U1 have the same thickness. In this embodiment, in order to optimize the performance of C-FETs, the first and second channel layers 608L1 and 608U1 are arranged to have different thicknesses.The middle sacrificial layer 606M can be the same as the middle section 202M.

[0050] In this illustrated embodiment, each of the first channel layers 608L1-608L2 has a thickness T1', and each of the second channel layers 608U1-608U2 has a thickness T2'. T1' has a region equal to the thickness T1, and the thickness T2' is greater than the thickness T1' but less than approximately 30 nm. In various embodiments, the thickness of the lowest second channel layer 608U3, which is in direct contact with the middle sacrificial layer 606M, can be equal to or less than the thickness T2'; and the thickness of the upper first channel layer 608L3, which is in direct contact with the middle sacrificial layer 606M, can be equal to or less than the thickness T1'. In one embodiment, the thickness of the lowest second channel layer 608U3 is equal to the thickness of the upper first channel layer 608L3.By forming the first channel layers 608L1-6008L2 and the second channel layers 608U1-608U2 with different thicknesses, the channel resistance Rch and the short channel effect of the lower and upper multi-gate devices can be adjusted. Therefore, the performance of the lower and upper multi-gate devices can be individually optimized.

[0051] After forming the superlattice structure 604, operations in blocks 104 to 122, as described above, are carried out to complete the fabrication of the semiconductor device 600. Fig. Figure 17 shows a partial cross-sectional view of semiconductor device 600 after completion of the operations in blocks 104 to 122. Semiconductor device 600 is similar to semiconductor device 200. For the sake of simplicity, similar and / or identical elements between two semiconductor devices 200 and 600 are represented by the same reference numerals, and repeated descriptions are omitted. The main differences between the two semiconductor devices 200 and 600 are described in detail.One of the differences between the two semiconductor devices 200 and 600 is that a lower transistor 600B of semiconductor device 600 has channel layers 6080L1 and 6080L2, each with a sheet height of H1, while an upper transistor 600T of semiconductor device 600 has channel layers 6080U1 and 6080U2, each with a sheet height of H2, where sheet height H1 is less than sheet height H2. In one embodiment, the ratio between sheet height H2 and sheet height H1 is in a range between approximately 1 and approximately 3. If the ratio is greater than 3, then the gate control capability of the upper multi-gate transistor may be too poor, resulting in less precise control of a drain current, or the channel layers of the lower multi-gate transistor may be too thin, resulting in a high channel resistance for the lower multi-gate transistor.In one embodiment, the upper multi-gate transistor comprises a multi-gate n-transistor, and the lower multi-gate transistor comprises a multi-gate p-transistor, and the semiconductor device 600 can be part of another SRAM cell of the IC structure 300 described above. That is, n-transistors in the other SRAM cell can have thicker channel layers than p-transistors in the other SRAM cell. In another embodiment, the upper multi-gate transistor comprises a multi-gate p-transistor, and the lower multi-gate transistor comprises a multi-gate n-transistor.

[0052] A second difference between the two semiconductor devices 200 and 600 is that semiconductor device 600 also incorporates nanostructures 6080N1 and 6080N2. These nanostructures can have different layer thicknesses. A third difference between semiconductor devices 200 and 600 is that semiconductor device 600 also incorporates internal spacer elements, such as internal spacer elements 626a, 626b, 626c, 626d, and 626e. The widths of the internal spacer elements 626a-626e in semiconductor device 600 can be essentially the same.

[0053] In the reference to Fig. In the embodiment described above in section 17, the layer height H2 of the upper multi-gate transistor 600T is greater than the layer height H1 of the lower multi-gate transistor 600B. In a further embodiment, described by Fig. Figure 18 represents an alternative semiconductor device 600'. The semiconductor device 600' is similar to the semiconductor device 600, and one of the differences between the semiconductor device 600 and the semiconductor device 600' is that the upper multi-gate transistor 600T' and the lower multi-gate transistor 600B' have a different layer height relationship. In particular, the lower multi-gate transistor 600B' has channel layers 6080L1' and 6080L2', each having a layer height of H1', ​​while the upper multi-gate transistor 600T' has channel layers 6080U1' and 6080U2', each having a layer height of H2', and the layer height H1' is greater than the layer height H2'. In one embodiment, the ratio of layer height H2' to layer height H1' is greater than approximately 0.3 and less than 1.If the ratio is less than 0.3, then the gate control capability of the lower multi-gate transistor 600B' may be too poor, resulting in less precise control of a drain current, or the channel layers of the upper multi-gate transistor 600T' may be too thin, resulting in high channel resistance for the upper multi-gate transistor. In one embodiment, the upper multi-gate transistor 600T' is a multi-gate n-transistor, and the lower multi-gate transistor 600B' is a multi-gate p-transistor, and the semiconductor device 600' may be located in a non-critical path of another logic cell similar to the logic cell described above. In another embodiment, the upper multi-gate transistor is a multi-gate p-transistor, and the lower multi-gate transistor is a multi-gate n-transistor.

[0054] Four embodiments have been described above with reference to Fig. 9, Fig. 14, Fig. 17 and Fig. 18 described. Key concepts (e.g. different gate lengths, different layer heights) of these four embodiments can be combined to form four different alternative embodiments.

[0055] Fig. Figure 19 shows a first of the four alternative embodiments. With reference to Fig. Figure 19 shows a semiconductor device 700. In this embodiment, the semiconductor device 700 has the inner spacer elements 226, the lower gate structure 254B and the inner section 2541 of the upper gate structure, and the channel layers 6080U1-6080U2 and 6080L1-6080L2. The gate length relationship and the channel layer height relationship were described above with reference to Fig. 9 and Fig. The semiconductor device 700 is described in Figure 17, and a repeated description is omitted for simplicity. In one embodiment, the semiconductor device 700 can be part of another SRAM cell of the IC structure to increase the alpha ratio of that other SRAM cell.

[0056] Fig. Figure 20 shows a second of the four alternative embodiments. With reference to Fig. Figure 20 shows a semiconductor device 700'. In this embodiment, the semiconductor device 700' has the inner spacer elements 226', the lower gate structure 254B' and the inner section 254I' of the upper gate structure, and the channel layers 6080U1'-6080U2' and 6080L1'-6080L2'. The gate length relationship and the channel layer height relationship were described above with reference to Fig. 14 and Fig. 18 described, and a repeated description is omitted for the sake of simplicity. In one embodiment, the semiconductor device 700' may be located in a non-critical path of another logic cell.

[0057] Two further embodiments of the four alternative embodiments are not explicitly illustrated by figures. However, it should be noted that a third embodiment of the four alternative embodiments may include a C-FET comprising the inner section 2541 and the lower gate structure 254B, the inner spacer elements 226, and also the channel layers 6080U1'-6080U2' and 6080L1'-6080L2'. A fourth embodiment of the four alternative embodiments may include a C-FET comprising the inner section 254I' and the lower gate structure 254B', the inner spacer elements 226', and also the channel layers 6080U1-6080U2 and 6080L1-6080L2.

[0058] The performance of the C-FETs can also be optimized by individually optimizing the gate heights of the upper and lower multi-gate device. Fig. Figure 21 shows a flowchart of a method 800 for forming a semiconductor device 900 having a vertical C-FET, according to one or more aspects of the present disclosure. The method 800 is described in conjunction with Fig. 22-23 describe the cross-sectional views of the semiconductor device 900 at various manufacturing stages according to embodiments of the method 800.

[0059] With reference to Fig. 21 and Fig. In section 22, process 800 comprises a block 802 in which a superlattice structure 904 is formed over the substrate 202. The fabrication processes for forming the superlattice structure 904 are the same as those for the superlattice structure 204. Differences between the superlattice structure 904 and the superlattice structure 204 include the dimensional relationships between different layers within the superlattice structure 904. In particular, the superlattice structure 904 has a lower section 904B, the middle sacrificial layer 206M on the lower section 904B, and an upper section 904T on the middle sacrificial layer 206M. The lower section 904B has a number of first channel layers (e.g., first channel layers 208L1, 208L2, 208L3) nested with a number of first sacrificial layers (e.g., first sacrificial layers 906L1, 906L2, 906L3).The first sacrificial layers 906L1, 906L2, 906L3 can be referred to individually or collectively as the first sacrificial layer(s) 906L. In some implementations, the first channel layers 208L are formed from silicon (Si), and the first sacrificial layers 906L are formed from silicon germanium (SiGe). The upper section 904T has a number of second channel layers (e.g., second channel layers 208U1, 208U2, 208U3) nested with a number of second sacrificial layers (e.g., second sacrificial layers 906U1, 906U2). The second sacrificial layers 906U1 and 906U2 can be referred to individually or collectively as the second sacrificial layer(s) 906U. In some implementations, the second channel layers 208U are formed from silicon (Si), and the second sacrificial layers 906U are formed from silicon germanium (SiGe). The first channel layers 208L and the second channel layers 208U can have the same thickness.In this embodiment, the first and second sacrificial layers 906L and 906U have the same germanium content, which is smaller than the third germanium content of the middle sacrificial layer 206M.

[0060] In some existing technologies for forming C-FETs, the first and second sacrificial layers 906L and 906U have the same thickness, and consequently, the heights of the lower gate structure and the inner section of the upper gate structure can be the same. In this embodiment, to optimize the performance of C-FETs, the first and second sacrificial layers 906L and 906U are configured to have different thicknesses. In this embodiment, each of the first sacrificial layers 906L has a thickness T3', and each of the second sacrificial layers 906U has a thickness T4'. T3' has a region equal to the thickness T3, and the thickness T4' is greater than the thickness T4' but less than approximately 30 nm. By forming the first sacrificial layers 906L and the second sacrificial layers 906U with different thicknesses, a spacing for forming gate structures within them can be established.Therefore, the thicknesses and / or number of different layers of the gate structures of the lower multi-gate device and the upper multi-gate device can be individually optimized.

[0061] After forming the superlattice structure 904, operations in blocks 104 to 122, as described above, are carried out to complete the fabrication of the semiconductor device 900. Fig. Figure 23 shows a partial cross-sectional view of semiconductor device 900 after completion of the operations in blocks 104 to 122. Semiconductor device 900 is similar to semiconductor device 200. For the sake of simplicity, similar and / or identical elements between two semiconductor devices 200 and 900 are represented by the same reference numerals, and repeated descriptions are omitted. The main differences between the two semiconductor devices 200 and 900 are described in detail. One of the differences between the two semiconductor devices 200 and 900 is that a lower multi-gate transistor 900B of semiconductor device 900 has a gate structure 954B having a first gate height Hg1, and an inner section 954I of an upper gate structure 954T of an upper multi-gate transistor 900T has a second gate height Hg2. The second gate height Hg2 is greater than the first gate height Hg1.In one embodiment, the upper multi-gate transistor 900T comprises a multi-gate n-transistor, and the lower multi-gate transistor 900B comprises a multi-gate p-transistor. In another embodiment, the upper multi-gate transistor 900T comprises a multi-gate p-transistor, and the lower multi-gate transistor 900B comprises a multi-gate n-transistor. A second difference between the two semiconductor devices 200 and 900 is that the semiconductor device 900 also comprises internal spacer elements, such as internal spacer elements 926a, 926b, 926c, 926d, and 926e. The widths of the internal spacer elements 926a-926e of the semiconductor device 900 can be substantially the same. However, the internal spacer elements 926a-926e can have different heights.In this embodiment, the height of the internal spacer elements 926a-926b formed above the middle dielectric layer 226; is greater than the height of the internal spacer elements 926c-926e formed below the middle dielectric layer 226M.

[0062] In the reference to Fig. In the embodiment described above in section 23, the gate height Hg2 of the upper multi-gate transistor 900T is greater than the gate height Hg1 of the lower multi-gate transistor 900B. In a further embodiment, described by Fig. Figure 24 represents an alternative semiconductor device 900'. The semiconductor device 900' is similar to the semiconductor device 900, and one of the differences between the semiconductor device 900 and the semiconductor device 900' is that the upper multi-gate transistor 900T' and the lower multi-gate transistor 900B' have different gate height relationships. In particular, the lower multi-gate transistor 900B' has a lower gate structure having a gate height Hg1', the upper multi-gate transistor 900T' has an upper gate structure 954T' having an inner section 954I' having a gate height Hg2', and the height Hg1' is greater than the height Hg2'. In this embodiment, the semiconductor device 900' also includes internal spacer elements 926a', 926b', 926c', 926d', and 926e'. The widths of the internal spacer elements 926a'-926e' of the semiconductor device 900' can be substantially the same.However, the internal spacer elements 926a'-926e' can have different heights. In this embodiment, the height of the internal spacer elements 926a'-926b' formed above the middle dielectric layer 226M is less than the height of the internal spacer elements 926c'-926e' formed below the middle dielectric layer 226M.

[0063] Six main forms of execution were described above with reference to Fig. 9, Fig. 14, Fig. 17, Fig. 18, Fig. 23, and Fig. 24 described. Two or three of the key concepts (e.g. different gate lengths, different layer heights, different gate heights) of these six embodiments can be combined to form different alternative embodiments in order to flexibly adjust the performance of the C-FETs.

[0064] The performance of C-FETs can also be optimized by individually optimizing the compositions of the channel layers of the upper and lower multi-gate device. Fig. Figure 25 shows a flowchart of a method 1000 for forming a semiconductor device 1100 having a vertical C-FET, according to one or more aspects of the present disclosure. The method 1000 is used in conjunction with Fig. 26-27 describe the cross-sectional views of the semiconductor device 1100 at various manufacturing stages according to embodiments of the method 1000.

[0065] With reference to Fig. 25 and Fig. In section 26, process 1000 comprises a block 1002 in which a superlattice structure 1104 is formed over the substrate 202. The manufacturing processes for forming superlattice structure 1104 are the same as those for superlattice structure 204. The differences between superlattice structure 1104 and superlattice structure 204 lie in their different compositions. In particular, superlattice structure 1104 has a lower section 1104B, a middle sacrificial layer 206M on the lower section 1104B, and an upper section 1104T on the middle sacrificial layer 206M. The lower section 1104B has a number of first channel layers (e.g., first channel layers 1108L1, 1108L2, 1108L3) nested with a number of first sacrificial layers (e.g., first sacrificial layers 1106L1, 1106L2, 1106L3).The first sacrificial layers 1106L1, 1106L2, 1106L3 can be referred to individually or collectively as the first sacrificial layer(s) 1106L. The upper section 1104T has a number of second channel layers (e.g., second channel layers 1108U1, 1108U2, 1108U3) nested with a number of second sacrificial layers (e.g., second sacrificial layers 1106U1, 1106U2). The second sacrificial layers 1106U1, 1106U2 can be referred to individually or collectively as the second sacrificial layer(s) 1106U.

[0066] In some existing technologies for forming C-FETs, both the first and second channel layers in the lower and upper sections are formed from silicon. In this embodiment, to optimize the performance of C-FETs, the first channel layers 1108L and / or the second channel layers 1108U are formed from silicon germanium. In this illustrated embodiment, both the first channel layers 1108L and the second channel layers 1108U contain silicon germanium with the same first germanium content, and both the first sacrificial layers 1106L and the second sacrificial layers 1106U contain silicon germanium with the same second germanium content, which is higher than the first germanium content of the first channel layers 1108L and / or the second channel layers 1108U and lower than the germanium content of the middle sacrificial layer 206M.In one embodiment, the first germanium content is less than 30%, the second germanium content is between approximately 40% and approximately 50%, and the germanium content of the middle sacrificial layer 206M is between approximately 60% and approximately 100%. The higher second germanium content and the highest germanium content of the middle sacrificial layer 206M provide etch selectivity between the three SiGe-based channel layers and sacrificial layers of the superlattice structure 1104.

[0067] After forming the superlattice structure 1104, operations in blocks 104 to 122, as described above, are carried out to complete the fabrication of the semiconductor device 1100. Fig. Figure 27 shows a partial cross-sectional view of semiconductor device 1100 after completion of the operations in blocks 104 to 122. Semiconductor device 1100 is similar to semiconductor device 200 and semiconductor device 600. For the sake of simplicity, similar and / or identical elements between semiconductor devices 200, 600, and 1100 are represented by the same reference numerals, and repeated descriptions are omitted. The main differences between semiconductor devices 200, 600, and 1100 are described in detail.One of the differences between the two semiconductor devices 200 and 1100 is that a lower multi-gate transistor 1100B of the semiconductor device 1100 has channel elements 11080L1 and 11080L2 formed from the channel layers 1108L2 and 1108L3, and an upper multi-gate transistor 1100T of the semiconductor device 1100 has channel elements 11080U1 and 11080U2 formed from the channel layers 1108U1 and 1108U3, wherein the channel elements 11080U1-11080U2 and 11080L1-11080L2 are formed from silicon germanium having a germanium content of less than 30%. The semiconductor device 1100 also features nanostructures 11080N1 and 11080N2 formed from channel layers 1108U3 and 1108L1, and features silicon germanium having a germanium content of less than 30%.Another difference between the two semiconductor devices 200 and 1100 is that the lower multi-gate transistor 1100B has inner spacer elements 626c-626e, and the upper multi-gate transistor 1100T has inner spacer elements 626a-626b. The inner spacer elements 626a-626e have the same width. In one embodiment, the upper multi-gate transistor 1100T is a multi-gate n-transistor, and the lower multi-gate transistor 1100B is a multi-gate p-transistor. In another embodiment, the upper multi-gate transistor 1100T is a multi-gate p-transistor, and the lower multi-gate transistor 1100B is a multi-gate n-transistor.

[0068] In the reference to Fig. In the embodiment described above in section 27, both the first channel layers 1108L and the second channel layers 1108U contain silicon germanium having the same initial germanium content. In a Fig. Figure 28 represents a further embodiment and shows an alternative semiconductor device 1100'. The semiconductor device 1100' is similar to the semiconductor device 1100, and one of the differences between the semiconductor device 1100 and the semiconductor device 1100' is that the first channel layers of the lower multi-gate transistor 1100B' and the second channel layers of the upper multi-gate transistor 1100T' have different compositions. In particular, in this embodiment, the lower multi-gate transistor 1100B' has channel elements 11080L1-11080L2 formed from silicon germanium, and the upper multi-gate transistor 1100T' has channel elements 2080U1 and 2080U2 formed from silicon. The semiconductor device 1100' also has nanostructures 2080N1 and 11080N2.In one embodiment, the upper multi-gate transistor 1100T' comprises a multi-gate n-transistor, and the lower multi-gate transistor 1100B' comprises a multi-gate p-transistor. In another embodiment, the upper multi-gate transistor 1100T' comprises a multi-gate p-transistor, and the lower multi-gate transistor 1100B' comprises a multi-gate n-transistor. Although not shown, Method 1000 can also be used to fabricate a semiconductor device comprising an upper multi-gate transistor having channel elements formed from silicon germanium and a lower multi-gate transistor having channel elements formed from silicon.

[0069] The concept of procedure 1000 can also be combined with others mentioned above with reference to Fig. 9, Fig. 14, Fig. 17, Fig. 18, Fig. 23, and Fig. The 24 described embodiments can be combined. For example, they show Fig. 29-30 Cross-sectional views of a semiconductor device 1200 during various manufacturing processes. The semiconductor device 1200 is similar to the semiconductor device 200 and the semiconductor device 1100. For the sake of simplicity, similar and / or identical elements between the semiconductor devices 200, 1100, and 1200 are represented by the same reference numerals, and repeated descriptions are omitted. Key differences between the semiconductor devices 200, 1100, and 1200 are described in detail. In particular, [reference to relevant section] shows Fig. 29 a superlattice structure 1204 formed over the substrate 202. The superlattice structure 1204 has channel layers 1108 nested with sacrificial layers 206. That is, first channel layers 1108L and second channel layers 1108U contain silicon germanium with the same initial germanium content. The superlattice structure 1204 also has the sacrificial layers 206 described above with reference to Fig. 3. That is, the first sacrificial layers 206L and the second sacrificial layers 206U have different germanium contents. It should be noted that the germanium content of both the first sacrificial layers 206L and the second sacrificial layers 206U is higher than the germanium content of the channel layers 1108.

[0070] After the formation of the superlattice structure 1204, processes in blocks 104 to 122, as described above, are carried out to manufacture the components. Fig. to conclude the semiconductor device 1200 represented by 30. Differences between semiconductor devices 200, 1100, and 1200 are that semiconductor device 1200 represents the semiconductor device 1200 with reference to Fig. 27 described channel elements 11080U1-11080U2 and 11080L1 and 11080L2, and also the gate structures 254B and 2541 and inner spacer elements 226, which with reference to Fig. 9 described, exhibits. That is, channel elements of the semiconductor device 1200 can contain silicon germanium, and gate lengths of a gate structure of a lower multi-gate transistor 1200B of the semiconductor device 1200 and an inner section of a gate structure of an upper multi-gate transistor 1200T of the semiconductor device 1200 are different.

[0071] In the foregoing, with reference to Fig. The embodiment described in section 30 includes both channel elements of the lower multi-gate transistor 1200B and channel elements of the upper multi-gate transistor 1200T silicon germanium.

[0072] In another, through Fig. Figure 31 shows an alternative semiconductor device 1200'. The semiconductor device 1200' is similar to the semiconductor device 1200, and one of the differences between the semiconductor device 1200 and the semiconductor device 1200' is that the channel elements of a lower multi-gate transistor 1200B' of the semiconductor device 1200' and the channel elements of an upper multi-gate transistor 1200T' of the semiconductor device 1200' are different. In this illustrated embodiment, the lower multi-gate transistor 1200B' has channel elements 2080U1 and 2080U2 formed from silicon, and the upper multi-gate transistor 1200T' has channel elements 11080L1 and 11080L2 formed from silicon germanium.

[0073] The present disclosure comprises an optimization of various aspects (e.g., gate lengths, channel layer thicknesses, gate heights, channel element compositions) of the lower and upper multi-gate transistors of C-FETs to achieve various performance improvements. These various aspects can be applied individually or combined in a variety of ways to create different C-FETs. Although only some of these combinations are explicitly shown or described, it is understood that the present disclosure covers all such combinations.

[0074] In the above with reference to Fig. In the embodiments described in sections 2 to 31, all semiconductor devices feature the nanostructures (e.g., 2080N1 and 2080N2, shown in Fig. 9) in direct contact with the middle dielectric layer 226M. In some alternative embodiments, as described by Fig. 32 represents, such nanostructures are omitted. Fig. Figure 32 shows a partial cross-sectional view of an alternative semiconductor device 200'. The semiconductor device 200' is similar to the semiconductor device 200, and one of the differences between the semiconductor devices 200 and 200' is that the semiconductor device 200' does not have the 2080N1 and 2080N2. That is, the middle dielectric layer 226M is in direct contact with the upper gate structure 254T and the lower gate structure 254B. This alternative embodiment can be applied to any of the above with reference to Fig. The embodiments described in sections 13 to 31 may also be used.

[0075] Although not intended to be limiting, one or more embodiments of the present disclosure offer many advantages for a semiconductor device and its design. For example, the present disclosure provides a C-FET device comprising an upper multi-gate device and a lower multi-gate device. One or more features of the upper multi-gate device and the lower multi-gate device can be optimized to enhance the performance of the C-FET device. Such a feature may include gate lengths, gate heights, channel layer thicknesses, and / or channel element compositions.

[0076] The present disclosure provides many different embodiments. Semiconductor structures and methods for fabricating them are disclosed here. In one exemplary aspect, the present disclosure relates to a method. The method comprises: forming a fin-shaped structure projecting from a substrate, wherein a first section of the fin-shaped structure has a plurality of first channel layers nested with a plurality of first sacrificial layers, and a second section of the fin-shaped structure has a plurality of second channel layers nested with a plurality of second sacrificial layers; forming a trench extending through the fin-shaped structure; and, after forming the trench, performing an etching process to laterally recess the plurality of first sacrificial layers and the plurality of second sacrificial layers.wherein an etchant of the etching process etches the majority of first sacrificial layers and the majority of second sacrificial layers at different rates, and after carrying out the etching process, replacing a remaining section of the majority of first sacrificial layers with a first gate structure and replacing a remaining section of the majority of second sacrificial layers with a second gate structure.

[0077] In some embodiments, the majority of first sacrificial layers may contain silicon germanium having a first germanium concentration, and the majority of second sacrificial layers may contain silicon germanium having a second germanium concentration greater than the first germanium concentration. In some embodiments, the length of the first gate structure is greater than the length of the second gate structure. In some embodiments, the method may further comprise: prior to replacement, forming a first source / drain element coupled to the majority of first channel layers, and forming a second source / drain element coupled to the majority of second channel layers, wherein the first source / drain element and the second source / drain element have different conductivity types.In some embodiments, the method may further comprise: after performing the etching process, forming first inner spacer elements adjacent to the remaining portion of the plurality of first sacrificial layers, and forming second inner spacer elements adjacent to the remaining portion of the plurality of second sacrificial layers. In some embodiments, the first inner spacer elements and the second inner spacer elements have different widths. In some embodiments, the fin-shaped structure may further comprise a central section arranged vertically between the first section and the second section, and the method may further comprise: selectively removing the central section to form an opening, and forming a dielectric layer in the opening.In some embodiments, the middle section may contain silicon germanium, and the germanium concentration of the middle section is greater than the germanium concentration of the plurality of first sacrificial layers and the germanium concentration of the plurality of second sacrificial layers. In some embodiments, each of the plurality of first channel layers has a first thickness, and each of the plurality of second channel layers has a second thickness that differs from the first thickness.

[0078] In a further exemplary aspect, the present disclosure relates to a method. The method comprises: forming a first semiconductor layer stack over a substrate and a second semiconductor layer stack over the first semiconductor layer stack, wherein the first semiconductor layer stack has a first upper semiconductor layer over a first lower semiconductor layer, and the second semiconductor layer stack has a second upper semiconductor layer over a second lower semiconductor layer; forming a first source / drain element coupled to the first upper semiconductor layer and the first lower semiconductor layer; forming a second source / drain element coupled to the second upper semiconductor layer and the second lower semiconductor layer.Forming a first gate structure located adjacent to the first source / drain element and between the first upper semiconductor layer and the first lower semiconductor layer, and forming a second gate structure located adjacent to the second source / drain element and between the second upper semiconductor layer and the second lower semiconductor layer, wherein the first gate structure and the second gate structure have different gate lengths.

[0079] In some embodiments, the first semiconductor layer stack and the second semiconductor layer stack have the same width. In some embodiments, the first source / drain element may contain p-type dopants, the second source / drain element may contain n-type dopants, and the gate length of the first gate structure is greater than the gate length of the second gate structure. In some embodiments, the thickness of the first lower semiconductor layer is less than the thickness of the second upper semiconductor layer. In some embodiments, the method may further include: forming a first inner spacer located between the first gate structure and the first source / drain element, and forming a second inner spacer located between the second gate structure and the second source / drain element. In some embodiments, the first inner spacer and the second inner spacer have different widths.In some embodiments, the method may further include: forming a dielectric layer between the first semiconductor layer stack and the second semiconductor layer stack, wherein the dielectric layer, the first inner spacer, and the second inner spacer have the same composition.

[0080] In a further example, the present disclosure relates to a semiconductor device. The semiconductor device comprises: a substrate, a lower source / drain element arranged above the substrate, a first plurality of nanostructures coupled to the lower source / drain element, a first gate structure enclosing each of the first plurality of nanostructures, an upper source / drain element above the lower source / drain element, a second plurality of nanostructures coupled to the upper source / drain element, and a second gate structure enclosing each of the second plurality of nanostructures, wherein the first gate structure and the second gate structure have different gate lengths.

[0081] In some embodiments, the lower source / drain element may contain p-type dopants, the upper source / drain element may contain n-type dopants, and the gate length of the first gate structure is greater than the gate length of the second gate structure. In some embodiments, the semiconductor device may further comprise: a first inner spacer positioned between the first gate structure and the lower source / drain element, and a second inner spacer positioned between the second gate structure and the upper source / drain element, wherein the first and second inner spacers have different widths. In some embodiments, the thickness of each of the first plurality of nanostructures differs from the thickness of each of the second plurality of nanostructures.

[0082] The foregoing outlines features of several embodiments so that a person skilled in the art may better understand the aspects of the present disclosure. A person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing and modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments presented herein. A person skilled in the art should also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 710,914

[0001]

Claims

[1] Procedure, encompassing: Forming a fin-shaped structure projecting from a substrate, wherein a first section of the fin-shaped structure has a plurality of first channel layers nested with a plurality of first sacrificial layers, and a second section of the fin-shaped structure has a plurality of second channel layers nested with a plurality of second sacrificial layers. Forming a trench that extends through the fin-shaped structure, After forming the trench, carrying out an etching process to laterally spare the majority of first sacrificial layers and the majority of second sacrificial layers, wherein an etchant of the etching process etches the majority of first sacrificial layers and the majority of second sacrificial layers at different rates, and After performing the etching process, replacing a remaining section of the majority of first sacrificial layers with a first gate structure and replacing a remaining section of the majority of second sacrificial layers with a second gate structure. [2] Method according to claim 1, wherein the plurality of first sacrificial layers contains silicon germanium having a first germanium concentration, and the plurality of second sacrificial layers contains silicon germanium having a second germanium concentration greater than the first germanium concentration. [3] Method according to claim 1 or 2, wherein the length of the first gate structure is greater than the length of the second gate structure. [4] Method according to any one of the preceding claims, further comprising: prior to replacement, forming a first source / drain element coupled with the majority of first channel layers, and Forming a second source / drain element coupled to the plurality of second channel layers, wherein the first source / drain element and the second source / drain element have different conductivity types. [5] Method according to any one of the preceding claims, further comprising: after carrying out the etching process, forming the first internal spacer elements that border the remaining section of the majority of the first sacrificial layers, and Forming second interior spacer elements adjacent to the remaining section of the majority of second sacrificial layers. [6] Method according to claim 5, wherein the first inner spacer elements and the second inner spacer elements have different widths. [7] A method according to any of the preceding claims, wherein the fin-shaped structure further comprises a central section arranged vertically between the first section and the second section, and the method further comprises: selective removal of the middle section to create an opening, and Formation of a dielectric layer in the opening. [8] Method according to claim 7, wherein the middle section contains silicon germanium, and a germanium concentration of the middle section is greater than a germanium concentration of the majority of first sacrificial layers and a germanium concentration of the majority of second sacrificial layers. [9] Method according to any of the preceding claims, wherein each of the plurality of first channel layers has a first thickness, and each of the plurality of second channel layers has a second thickness which is different from the first thickness. [10] Procedures, including: Forming a first semiconductor layer stack over a substrate and a second semiconductor layer stack over the first semiconductor layer stack, wherein the first semiconductor layer stack has a first upper semiconductor layer over a first lower semiconductor layer, and the second semiconductor layer stack has a second upper semiconductor layer over a second lower semiconductor layer. Forming a first source / drain element coupled to the first upper semiconductor layer and the first lower semiconductor layer, Forming a second source / drain element coupled to the second upper semiconductor layer and the second lower semiconductor layer, Forming a first gate structure that is adjacent to the first source / drain element and located between the first upper semiconductor layer and the first lower semiconductor layer, and Forming a second gate structure that is adjacent to the second source / drain element and located between the second upper semiconductor layer and the second lower semiconductor layer, where the first gate structure and the second gate structure have different gate lengths. [11] Method according to claim 10, wherein the first semiconductor layer stack and the second semiconductor layer stack have the same width. [12] Method according to claim 10 or 11, wherein the first source / drain element comprises p-doping materials, the second source / drain element comprises n-doping materials, and a gate length of the first gate structure is greater than a gate length of the second gate structure. [13] Method according to any one of claims 10 to 12, wherein the thickness of the first lower semiconductor layer is less than the thickness of the second upper semiconductor layer. [14] Method according to any one of claims 10 to 13, further comprising: Forming a first inner spacer that is positioned between the first gate structure and the first source / drain element, and Forming a second inner spacer that is positioned between the second gate structure and the second source / drain element. [15] Method according to claim 14, wherein the first inner spacer and the second inner spacer have different widths. [16] Method according to any one of claims 10 to 15, further comprising: Formation of a dielectric layer between the first semiconductor layer stack and the second semiconductor layer stack, wherein the dielectric layer, the first inner spacer, and the second inner spacer have the same composition. [17] Semiconductor device comprising: a substrate, a lower source / drain element positioned above the substrate, a first plurality of nanostructures coupled to the lower source / drain element, a first gate structure that encloses each of the first plurality of nanostructures, an upper source / drain element above the lower source / drain element, a second plurality of nanostructures coupled to the upper source / drain element, and a second gate structure that encloses each of the second plurality of nanostructures, where the first gate structure and the second gate structure have different gate lengths. [18] Semiconductor device according to claim 17, wherein the lower source / drain element comprises p dopants, the upper source / drain element comprises n dopants, and a gate length of the first gate structure is greater than a gate length of the second gate structure. [19] Semiconductor device according to claim 17 or 18, further comprising: a first inner spacer positioned between the first gate structure and the lower source / drain element, and a second inner spacer positioned between the second gate structure and the upper source / drain element, where the first inner spacer and the second inner spacer have different widths. [20] Semiconductor device according to one of claims 17 to 19, wherein a thickness of each from the first plurality of nanostructures differs from a thickness of each from the second plurality of nanostructures.

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