Method for producing a monolithic layer stack structure

Abstract

According to one embodiment, a method (100) for producing a monolithic layer stack structure (200) comprises the following steps: providing (110) a semiconductor substrate provided with a structured insulation layer, carrying out (120, 130) a first or second manufacturing module, wherein the carrying out (120) of the first manufacturing module comprises the following steps: structured application (120-1) of a semiconductor thick-film structure, wherein trenches and / or through-openings are arranged in the semiconductor thick-film structure, and structured application (120-2) of an insulation layer structure onto the semiconductor thick-film structure for filling the trenches and / or through-openings in the semiconductor thick-film structure and for providing an insulating surface layer on the semiconductor thick-film structure, wherein the semiconductor thick-film structure is further structured in such a way,that the applied insulation layer structure divides the semiconductor thick-film structure into a functional material region and a sacrificial material region, wherein the execution (130) of a second manufacturing module comprises the following steps: structured application (130-1) of a highly doped semiconductor thin-film structure, wherein trenches and / or through-openings are arranged in the highly doped semiconductor thin-film structure, and structured application (130-2) of a further insulation layer structure onto the highly doped semiconductor thin-film structure for filling the trenches and / or through-openings in the highly doped semiconductor thin-film structure and for providing an insulating surface layer on the highly doped semiconductor thin-film structure, wherein the highly doped semiconductor thin-film structure is further structured so,that the applied further insulation layer structure divides the semiconductor thin-film structure into a functional material region and a sacrificial material region, repeating (135) the execution of the first and / or second manufacturing module (120, 130) to obtain a layer stack arrangement (201), structured application (140) of an etching mask structure to the exposed, rear-side main surface region of the semiconductor substrate, rear-side etching (145) through the semiconductor substrate, etching (150) into the layer stack arrangement to remove the sacrificial material regions, wherein the applied insulation layer structures form an etch stop layer structure, and region-wise removal (155) of the etch stop layer structure to expose surface regions of the functional material regions adjacent to the etch stop layer structure to obtain the monolithic layer stack structure (200).

Description

Technical area

[0001] The present invention relates to a method for fabricating a monolithic layer stack structure, such as a monolithic multi-aperture plate for a multi-beam electron beam system or an inertial sensor. Embodiments particularly relate to a process for depositing and patterning semiconductor / insulating layer multilayers, such as poly-Si / oxide multilayers. Technical background

[0002] In the field of electron-optical and / or ion-optical applications for imaging surface analysis or for modifying thin coatings (paint cross-linking, ablation, etc.), electrostatic single-lens or field-lens arrays with very high geometric specifications of the electrode arrangement are required. In particular, the production of 3D-stacked electrode arrays (e.g., for a multi-beam electron beam system) for the targeted deflection of charged particles in transit is of great interest.

[0003] The production of electrically and mechanically functionalized, stacked multilayer assemblies is difficult to achieve with sufficient placement accuracy and at a reasonable cost by vertically joining individual functional layers from discrete substrates (wafers). Furthermore, the routing of conductor tracks through the various stacked levels to a contact side of the stacked assembly is difficult due to the various requirements for mechanical layer guidance while simultaneously establishing electrical contact, without errors due to layer misalignment, particle contamination, or the formation of surface oxides. Vertically stacked multilayer assemblies from discretely stacked individual substrates are therefore typically only feasible for a small number of functional layers.

[0004] The object underlying the present invention is therefore to provide an improved method for producing a monolithic layer stack structure with (at least) one through-opening.

[0005] This problem is solved by the subject matter of independent patent claim 1.

[0006] Specific embodiments, implementations and further developments of the present invention are defined in the dependent claims. Overview of the inventive concept

[0007] According to one embodiment, a method for manufacturing a monolithic layer stack structure (e.g., a monolithic multi-aperture plate or a monolithic inertial sensor) comprises the following steps: Providing a (monocrystalline) semiconductor substrate (e.g. Si substrate) provided with a structured insulation layer (oxide - nitride), Executing a first or second manufacturing module, (on the exposed process surface = the exposed main surface area), wherein the execution of the first manufacturing module (process module) comprises the following steps (substeps): structured application of a HL thick-film structure (HL = semiconductor) (on the respective process surface of the currently present layer stack arrangement), wherein trenches and / or through-openings are arranged in the HL thick-film structure, and structured application of an insulation layer structure to the HL thick-film structure for filling the trenches and / or through-openings in the HL thick-film structure and for providing an insulating surface layer on the HL thick-film structure, wherein the HL thick-film structure is further structured such that the applied insulation layer structure divides (separates) the HL thick-film structure into a functional material region and a sacrificial material region, wherein the execution of a second manufacturing module (process module) comprises the following steps (substeps): structured application of a highly doped HL thin-film structure (on the respective process surface of the currently present layer stack arrangement), wherein trenches and / or through-openings are arranged in the highly doped HL thin-film structure, and structured application of a further insulation layer structure to the highly doped HL thin-film structure for filling the trenches and / or through-openings in the highly doped HL thin-film structure and for providing an insulating surface layer on the highly doped HL thin-film structure, wherein the highly doped HL thin-film structure is further structured such that the applied further insulation layer structure divides the HL thin-film structure into a functional material region and a sacrificial material region, Repeating the execution of the first and / or second manufacturing module (several times) to obtain a layer stack arrangement (with an exposed process surface = with an exposed main surface area), wherein the sacrificial material areas define a through-opening through the layer stack arrangement, structured application of an etching mask structure (resist material layer structure) to the exposed, rear main surface area of the HL substrate, backside (e.g. anisotropic) etching through the HL substrate, (e.g. isotropic) etching into the layer stack arrangement to remove the sacrificial material regions and to create the through-opening through the layer stack arrangement, wherein the applied insulation layer structures (= trenches and / or through-openings filled with the insulation material) form a lateral (vertically extending) etch stop layer structure, and Region-wise removal of the etch stop layer structure (oxide etching back) in order to expose surface areas of the functional material regions adjacent to the etch stop layer structure in order to obtain the monolithic layer stack structure.

[0008] According to one embodiment, the following steps (substeps) may be performed before executing the first or second manufacturing module (on the exposed process surface = the exposed main surface area): structured application, e.g., by means of a deposition, lithography, and etching process, of a semiconductor thick-film structure, e.g., a poly-Si thick-film structure, onto the semiconductor substrate, e.g., Si substrate, provided with the structured insulation layer, e.g., oxide or nitride layer, wherein trenches and / or feedthrough openings are arranged or provided in the semiconductor thick-film structure, (structured) application of an insulation layer structure, e.g. an oxide or nitride layer structure, to the semiconductor thick-film structure for filling the trenches and / or the through-openings in the semiconductor thick-film structure and for providing an insulating surface layer, e.g. an oxide or nitride surface layer, on the semiconductor thick-film structure, wherein the semiconductor thick-film structure is further structured (based on the trenches and / or through-openings) such that the applied insulation layer structure divides or separates the semiconductor thick-film structure into a functional material region and a sacrificial material region.

[0009] In the following description, the material of the structured insulation layers is referred to, for example, as silicon dioxide (SiO2), silicon oxynitride (SiO X N Y) or silicon nitride (SiN) and, in the case of the applied semiconductor layer structures, reference is made to polycrystalline silicon layers (poly-Si) or poly-Si layer structures, whereby other suitable insulation materials for the insulation layer and other semiconductor materials for the semiconductor layers can also be used.

[0010] In this case, single-layer polycrystalline silicon layers (semiconductor thick-film structures), e.g., with a thickness in the range of 2 - 90 µm, can be deposited and structured on a pre-oxidized (e.g., provided with a thermal oxide) silicon substrate with openings in the oxide coating or on an applied insulating layer structure (silicon oxide layer structure) with openings in the insulating layer structure. In addition, highly doped thin (e.g., 100 nm - 1000 nm), single-layer, in-situ doped polysilicon conductor tracks and via contacts can be deposited and structured, and these can be embedded on all sides in the silicon oxide. In order to now create a structured multilayer arrangement orIn order to be able to form a monolithic layer stack structure, a multilayer process is used according to the present invention, wherein the final semiconductor etching (silicon etching) and the final oxide etching are carried out from the back of the substrate.

[0011] To ensure compliance with the required geometric structural dimensions, silicon oxide etch stop layers are introduced (previously) into the polysilicon layers in the lateral and vertical directions during the process. The interlayer spacing between thick polysilicon layers can be mechanically thickened and thus adjusted by incorporating individual or multiple stacked thin polysilicon conductor layers as spacers in oxide layers. The structuring of the thin polysilicon layers can be designed in such a way that, in addition to the purely electrical conductor functionality, a mechanical spacer function (mechanical connection function) and chemically inert, lateral, and vertically elevated silicon etch stop layers can be created.

[0012] Embodiments of the present invention are thus based on the finding that an alternating, additive deposition and structuring process, e.g. of silicon dioxide (SiO2 by means of a TEOS deposition), of silicon oxynitride (SiO X N Y ) or silicon nitride (SiN) and polycrystalline silicon layers on a silicon substrate, whereby this can be done without interrupting the cleanroom processing and thus high-precision cleanroom process technologies can be used. Short description of the drawing and figures

[0013] Preferred embodiments of the present invention are explained in more detail below with reference to the accompanying drawings and figures. They show: Fig. 1a-b are schematic representations of a flow chart of the manufacturing method according to the invention according to an embodiment; Fig.2 shows an exemplary basic flow diagram of the manufacturing method according to the invention according to a further embodiment; Fig. 3 an exemplary basic flow diagram with further details of the Fig. 2 shows steps 1 - 3 of the manufacturing method according to the invention according to a further embodiment; Fig. 4 shows an exemplary embodiment of the (manufactured) monolithic layer stack structure according to another embodiment; and Fig. 5a-d show exemplary embodiments of further structures (substructures) of the manufactured monolithic layer stack structure according to further embodiments.

[0014] Before exemplary embodiments of the present invention are explained in more detail below with reference to the drawings, it is pointed out that identical, functionally equivalent or equivalent elements, objects, functional blocks and / or method steps in the different figures are provided with the same designations or reference symbols, so that the description of these elements, objects, functional blocks and / or method steps (with the same designations or reference symbols) shown in different exemplary embodiments is interchangeable or can be applied to one another. Detailed description of the figures and embodiments

[0015] In the following description, the description of a semiconductor layer means that the semiconductor layer comprises a semiconductor material, ie, is formed at least partially or entirely from the semiconductor material. In the following description, the description of an insulating substrate means that the substrate comprises an electrically insulating material, ie, is formed at least partially or entirely from the electrically insulating material.

[0016] It is understood that when an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is described as being "directly connected" or "coupled" to another element, no intervening elements are present. Other terms used to describe the relationship between elements should be interpreted similarly (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0017] To simplify the description of the different exemplary embodiments, at least some of the figures have a Cartesian coordinate system x, y, z, wherein the directions x, y, z are arranged orthogonal to one another. In the exemplary embodiments, the xy plane corresponds to the (upper) main surface area of a carrier or substrate (= reference plane = xy plane), wherein the vertical direction upwards with respect to the reference plane (xy plane) corresponds to the "+z" direction, and wherein the direction vertically downwards with respect to the reference plane (xy plane) corresponds to the "-z" direction. In the following description, the term "lateral" means a direction parallel to the x and / or y direction, i.e. parallel to the xy plane, wherein the term "vertical" indicates a direction parallel to the + / -z direction.

[0018] In the following description, a thickness or height of an element typically indicates a vertical dimension of that element, while a width or length of an element typically indicates a lateral dimension of that element. In the figures, the various elements are not necessarily drawn to scale. Therefore, the lateral and vertical dimensions of the described elements, e.g., the thicknesses and widths of the individual semiconductor layers, insulation layers, the semiconductor substrate, etc., may not be drawn to scale.

[0019] In the context of this description, terms and / or text passages placed in brackets are to be understood as further alternative designations or exemplary explanations, embodiments, additions or alternatives (to the corresponding term or text passage).

[0020] Fig.1a-b show schematic representations of a flow chart of the inventive manufacturing method 100 according to an embodiment.

[0021] In the following, we will use Fig. 1a, a basic flow diagram of the method 100 according to the invention for producing a monolithic layer stack structure 200 according to an embodiment is described, while Fig. 1b a schematic representation of the process flow of the manufacturing method 100 of Fig. 1a shows the different manufacturing modules (process modules).

[0022] The monolithic layer stack structure obtained in the manufacturing method 100 can be designed, for example, as a monolithic multi-aperture plate (e.g., a monolithic multi-beam micro-optics for a particle-optical system) or an inertial sensor or as a structural section or sub-region of such an arrangement.

[0023] Referring to the method 100 of Fig. 1a-b, a semiconductor substrate provided with a structured insulation layer is now provided in step 110. For example, a (monocrystalline) Si substrate (Si = silicon) provided with a structured oxide layer (thermal oxide or SiO2) or with a nitride layer (SiN) can be provided.

[0024] The semiconductor substrate, e.g., a monocrystalline Si substrate, can be provided with an insulating layer, e.g., a thermal oxide layer (SiO2), by thermally oxidizing the main surface area of the semiconductor substrate intended for the subsequent process. This creates a thin layer of amorphous silicon dioxide on the surface of the silicon substrate (e.g., a silicon wafer). The oxidation process is based on the diffusion of oxygen and its chemical reaction with silicon, e.g., at temperatures above 1100°C. Examples of processes for oxidizing a silicon substrate include dry oxidation, in which oxidation is caused solely by oxygen at typical temperatures between 800°C and 1200°C. The resulting layer thickness of the oxide layer depends on the temperature and the oxidation time.Another oxidation process is a so-called “wet oxidation”, in which water vapor is used as an oxidizing agent (also called “moist oxidation”).

[0025] In addition to thermal oxidation with pure oxygen (dry oxidation) or water vapor (wet oxidation), as described above, there are other processes in which the actual reactants for the oxidation of silicon are only formed by a reaction in the process chamber.

[0026] In a further (subsequent) step 120, 130, a first or second manufacturing module or process module (on the exposed process surface = on the exposed main surface area) is now carried out.

[0027] Thus, in step 120, the first manufacturing module or process module can now be executed. Executing the first manufacturing module (process module) comprises the following steps (substeps). - In a first substep 120-1 of the first manufacturing module, a semiconductor thick-film structure is applied in a structured manner (to the respective process surface of the currently present layer stack arrangement), wherein trenches and / or through-openings are or will be arranged in the further semiconductor thick-film structure. The structured application of the semiconductor thick-film structure comprises, for example, a deposition, lithography, and etching process or process steps.

[0028] For example, the first sub-step 120-1 of the first manufacturing module can be a structured application of a poly-Si thick-film structure (on the respective process surface of the currently present layer stack arrangement), wherein trenches and / or through openings are or will be arranged in the poly-Si thick-film structure.

[0029] In a further sub-step 120-2 of the first manufacturing module, an insulating layer structure is applied in a structured manner to the semiconductor thick-film structure to fill the trenches and / or through-openings in the semiconductor thick-film structure and to provide an insulating surface layer on the semiconductor thick-film structure. The semiconductor thick-film structure is further structured such that the applied insulating layer structure divides or separates the semiconductor thick-film structure into a functional material region and a sacrificial material region.In the second sub-step 120-2 of the first manufacturing module, for example, an oxide layer structure can be applied in a structured manner to the respective poly-Si thick-film structure in order to fill the trenches and / or through-openings in the further poly-Si thick-film structure and to provide an oxide surface layer on the poly-Si thick-film structure, wherein the poly-Si thick-film structure is further structured such that the applied oxide layer structure divides or separates the poly-Si thick-film structure into the functional material region and the sacrificial material region.

[0030] In step 130, a second manufacturing module or process module is executed. Executing the second manufacturing module (process module) comprises the following steps (substeps): - In a first substep 130-1 of the second manufacturing module, a highly doped semiconductor thin-film structure is patterned (on the respective process surface of the currently present layer stack arrangement), wherein trenches and / or through-openings are or will be arranged in the highly doped semiconductor thin-film structure.

[0031] For example, in sub-step 130-1, a highly doped poly-Si thin-film structure can be applied in a structured manner to the respective process surface of the currently present layer stack arrangement, wherein trenches and / or through openings are arranged in the highly doped poly-Si thick-film structure.

[0032] According to a further sub-step 130-2 of the second manufacturing module, a further insulation layer structure is applied in a structured manner to the highly doped semiconductor thin-film structure in order to fill the trenches and / or through-openings in the highly doped semiconductor thin-film structure and to provide an insulating surface layer on the highly doped semiconductor thin-film structure, wherein the highly doped semiconductor thin-film structure is further structured such that the applied further insulation layer structure divides the semiconductor thin-film structure into a functional material region and a sacrificial material region.

[0033] For example, in the second sub-step 130-2 of the second manufacturing module, a further oxide layer structure can be applied in a structured manner to the highly doped poly-Si thin-film structure in order to fill the trenches and / or through-openings in the highly doped poly-Si thin-film structure and to provide an oxide surface layer on the highly doped poly-Si thin-film structure, wherein the highly doped poly-Si thin-film structure is further structured such that the applied further oxide layer structure divides the poly-Si thin-film structure into a functional material region and a sacrificial material region.

[0034] In the two process modules, additive deposition and structuring processes are carried out alternately, whereby semiconductor layers (thin or thick layers, e.g. made of poly-Si) are applied in a structured manner to the topmost applied insulation layer structure (= current process surface for the semiconductor deposition), while in turn insulation layer structures (e.g. SiO2 or SiN layers) are applied in a structured manner to the (topmost) applied semiconductor layer (= current process surface for the insulation material deposition).

[0035] According to step 135, the execution 120, 130 of the first manufacturing module and / or the second manufacturing module can be repeated. Thus, the first manufacturing module and the second manufacturing module can each be repeated individually, multiple times, or in (any) combination or sequence individually or multiple times consecutively. As a result of step 135, a resulting layer stack arrangement (intermediate structure) with an exposed process surface (= with an exposed main surface area) is again obtained.

[0036] In a (subsequent) step 140, an etch mask structure, e.g., in the form of a resist material layer structure, is applied to the exposed, rear-side main surface area of the semiconductor substrate, e.g., the monocrystalline silicon substrate. Optionally, the etch mask structure (resist material layer structure) can also be applied to the exposed, current process surface of the layer stack structure.

[0037] In a next step 145, the semiconductor substrate, e.g., the monocrystalline silicon substrate, is etched, i.e., etched from the back side. This can, for example, be an anisotropic etching process.

[0038] This (anisotropic) etching process 145 can be stopped or terminated, for example, after etching through the semiconductor substrate, e.g., after complete vertical etching through the semiconductor substrate and upon reaching the (first) semiconductor thick or thin film structure (e.g., from step 115, 120, or 130).

[0039] In a subsequent step 150, etching is now carried out through the semiconductor substrate opened at the rear in step 145 (e.g. isotropic) into the layer stack arrangement in order to remove the sacrificial material regions of the different semiconductor thick-film structures or semiconductor thin-film structures, wherein the applied insulation layer structures (ie the trenches and / or through openings filled with the insulation material) form a lateral (vertically running) etch stop layer structure.

[0040] In step 150, for example, the monocrystalline silicon substrate opened at the back in step 145 can be etched isotropically into the layer stack arrangement (DRIE processes) in order to remove the sacrificial material regions of the poly-Si thick-film structures and the poly-Si thin-film structures, wherein the applied oxide layer structures form a lateral (side) etch stop layer structure.

[0041] In a (subsequent) step 155, the etch stop layer structure is now removed in regions, that is to say, for example, an insulating material etching back is carried out in order to expose surface regions of the functional material regions adjacent to the etch stop layer structure in order to obtain the monolithic layer stack structure.

[0042] In step 155 of removing the etch stop layer structure in regions, an oxide etching back can be carried out, for example, in order to expose the surface regions of the functional material regions of the poly-Si thick-film structures and poly-Si thin-film structures adjacent to the etch stop layer structure in order to obtain the monolithic layer stack structure.

[0043] With regard to the above description, it should be noted that a structured application of a semiconductor layer structure (semiconductor thin-film or thick-film structure) can be regarded, for example, as a process with several sub-steps in which the semiconductor layer structure is first deposited onto the process surface (= currently exposed uppermost surface region of the layer stack) (e.g. by means of CVD processes), whereupon a lithography process is carried out on the surface of the deposited semiconductor thick-film structure in order to define the trenches and / or through openings which are to be formed with the subsequent etching step by a targeted removal of material regions of the semiconductor thick-film structure.

[0044] Furthermore, during the structured application of a semiconductor layer structure (semiconductor thin- or thick-film structure), annealing can also be performed at temperatures between 900°C and 1100°C, for example. Annealing is the term used to describe a temperature treatment (heat treatment) of the semiconductor layer structure (semiconductor thin- or thick-film structure) or the layer stack arrangement to anneal the applied and doped semiconductor material. During this temperature process, for example, the lattice defects created during doping (e.g., ion implantation) are annealed, and the dopants are electrically activated by incorporation into the crystal lattice of the semiconductor material.

[0045] According to one embodiment, further steps (sub-steps) 115, 118 may be performed prior to the execution 120, 130 of the first or second manufacturing module (on the exposed process surface = the exposed main surface area).

[0046] Thus, in a step 115, a semiconductor thick-film structure, e.g., a poly-Si thick-film structure, can be applied in a structured manner to the semiconductor substrate, e.g., Si substrate, provided with the structured insulation layer, e.g., oxide or nitride layer, e.g., by means of a deposition, lithography, and etching process, wherein trenches and / or feedthrough openings are arranged or provided in the semiconductor thick-film structure.

[0047] Furthermore, in a step 118, an insulation layer structure, e.g., an oxide (SiO2) or nitride layer structure, may be applied in a structured manner to the semiconductor thick-film structure for filling the trenches and / or the vias in the semiconductor thick-film structure and for providing an insulating surface layer, e.g., an oxide or nitride surface layer, on the semiconductor thick-film structure, e.g., by means of a deposition, lithography, and etching process, wherein the semiconductor thick-film structure is further structured (based on the trenches and / or vias) such that the applied insulation layer structure divides or separates the semiconductor thick-film structure into a functional material region and a sacrificial material region.

[0048] According to one embodiment, in a further manufacturing step 160, for example, a metallic, structured cover layer can be applied in contact with the (topmost) semiconductor thin-film structure. This structured metallic cover layer can, for example, be configured as contact areas (bond pads) for contacting the semiconductor thin-film structures (e.g., semiconductor conductor tracks) as well as a protective structure to prevent excessive undercutting.

[0049] Since the applied structured metallic cover layer (e.g. a gold layer) has a higher coefficient of expansion than the remaining layer materials, this can also result in a tensile stress in the layer stack arrangement, i.e. the layer arrangement (membrane) can be kept taut.

[0050] According to one embodiment, in step 160 of applying the metallic, structured cover layer, the metallic, structured cover layer can be applied as a layer sequence comprising a base layer and a metal layer arranged thereon. The base layer is arranged, for example, as an adhesion promoter layer for the metal layer beneath the metal layer.

[0051] According to one embodiment, an optional step 161 of structuring the base layer and an optional step 162 of structuring the metal layer may be performed to form contact regions for contacting the semiconductor thin-film structures. According to one embodiment, in step 161 of structuring the base layer, circumferential trench structures may be formed around the contact regions by the capping layer.

[0052] According to one embodiment, in step 160 of applying the layer sequence with the base layer and metal layer, a WTi material (WTi = tungsten titanium) can be applied for the base layer and a gold material can be applied for the metal layer.

[0053] According to a further embodiment, a titanium, tantalum, or chromium material, for example, can also be applied for the base layer in step 160. The base layer can also be applied as a layer sequence or layer stack with multiple layers of the aforementioned materials, e.g., as a titanium-WTi layer sequence.

[0054] According to a further embodiment, a tungsten, rhenium, osmium, iridium, platinum, silver, tantalum, or lead material can also be applied for the metal layer in step 160. The metal layer can also be applied as a layer sequence or layer stack with multiple layers of the aforementioned materials.

[0055] According to one embodiment, an optional step 163 of applying a dielectric covering layer at least in regions to the layer stack arrangement and a step of structuring the applied dielectric covering layer can be carried out, wherein during the structuring 164 of the dielectric covering layer, the contact regions are exposed, for example, such that circumferential edge surface regions of the contact regions remain covered with a width of at least 1 µm.

[0056] According to one embodiment, during the application and structuring of the dielectric covering layer, regions on the main surface region of the layer stack arrangement adjacent to the contact regions can also be covered at least in regions with the dielectric covering layer.

[0057] According to a further embodiment, main surface areas of the monolithic layer stack structure can be exposed (circumferentially) around an aperture opening (in the metallic, structured cover layer) in order to obtain an efficient shielding effect of the metallic, structured cover layer.

[0058] According to one embodiment, the dielectric capping layer can be conformally deposited on the layer stack arrangement using an ALD (atomic layer deposition) process.

[0059] According to an optional step 165, for example, prior to step 150 of etching into the layer stack arrangement, a conformal, polymer-based protective coating, e.g., a parylene layer, may be applied to the exposed process surface of the layer stack arrangement.

[0060] According to one embodiment, the region-wise removal of the etch stop layer structure involves, for example, etching of the insulation material arranged on the side walls and further undercutting into the insulation material layers.

[0061] According to one embodiment, the conformal polymer-based protective coating may further be removed from the layer stack arrangement. This may be performed during (together with) the region-wise removal 155 of the etch stop layer structure or also in a separate process step (separate from the region-wise removal 155 of the etch stop layer structure). According to a further embodiment, the (remaining) etch mask structure may further be removed from the semiconductor substrate. This may be performed during (together with) the region-wise removal 155 of the etch stop layer structure or also in a separate process step (separate from the region-wise removal 155 of the etch stop layer structure).

[0062] According to one embodiment, structured deposition is understood to mean a material deposition process, e.g., a CVD process, a lithography process for defining regions to be etched on the respective process surface area, and a subsequent etching process. According to one embodiment, a thermal treatment (annealing) of the deposited semiconductor layer structure (semiconductor thin- or thick-film structure) can also be performed (alternatively or additionally).

[0063] According to one embodiment, trenches and / or through-openings are provided in the step of structured application of the insulation layer structure in order to obtain vertical electrical connections or vias between adjacent semiconductor levels in the subsequent step of structured application of a semiconductor thick-film structure or structured application of a semiconductor thin-film structure.

[0064] According to one embodiment, the first manufacturing module can be performed multiple times or multiple times consecutively, and the second manufacturing module can be performed multiple times or multiple times consecutively. Furthermore, according to one embodiment, a consecutive execution of the first and second manufacturing modules can be performed multiple times.

[0065] According to one embodiment, a CMP treatment of the deposited semiconductor thick films and / or semiconductor thin films can be carried out (CMP = chemically mechanically polishing).

[0066] According to one embodiment, the monolithic layer stack structure may be formed as a monolithic multi-aperture plate (stigmator), wherein the sacrificial material region defines the (optical) through-opening (aperture) through the layer stack structure.

[0067] According to one embodiment, an aperture, which is also referred to as an (optical) passage opening, is a free passage opening through the layer stack structure through which rays or radiation, such as optical rays (light rays), particle beams, such as electrically charged particles such as electrons or ions, X-rays, etc., can pass through the layer stack structure. Thus, the aperture or apertures are not laterally offset through the layer stack structure, but after etching into the layer stack arrangement have a (vertical) layering (layer sequence) of openings through the layer stack structure with centers lying one above the other or aligned with one another. According to one embodiment, the centers of the openings through the layer stack structure can, for example, lie on or almost on a common line.

[0068] According to one embodiment, the monolithic layer stack structure may be formed as an inertial sensor with a movable element, wherein the sacrificial material region defines the cavity with the movable element in the layer stack structure.

[0069] According to one embodiment, the monolithic layer arrangement can be separated into individual functional elements or chips.

[0070] According to one embodiment, in step 155, the surface regions of the functional material regions adjacent to the etch stop layer structure are exposed to obtain the monolithic layer stack structure. Thus, lateral, exposed semiconductor material regions can be doped to form lateral electrodes (deflection electrodes) in the apertures of the monolithic multi-aperture plate (stigmator).

[0071] Materials: The description refers, for example, to silicon (polysilicon) for the epitaxially applied layers and monocrystalline silicon for the semiconductor substrate. Other semiconductor materials, including associated oxides (e.g., SiO2) or insulating materials, can also be used in principle.

[0072] For example, silicon germanium (SiGe) could also be grown in a similar way. Aluminum oxide and aluminum nitride layers could, in principle, also be used as insulators and etch-stop layers.

[0073] Side electrodes: The doping of the side electrodes (deflection electrodes) can be done during the deposition of the corresponding silicon layers. When depositing thick polysilicon layers, intrinsic phosphorus doping is present. For SiGe, boron can be added as a dopant during deposition.

[0074] Sequence of modules (see e.g. Fig.1b): For example, a predetermined sequence of modules can be provided for the “thick” poly-Si layers and the highly doped poly-Si conductor tracks. Module C (see Fig. 1b) can (always) be used as the upper terminating layer, for example, or could even be omitted. The order of the thick poly-Si layers and conductor tracks is arbitrary. There is even a way to structure thick poly-Si layers in such a way that thin poly-Si conductor tracks are not necessary, but then the number of contacts is limited because it is difficult to create crossovers.

[0075] According to one embodiment, the etched substrate (silicon substrate) can serve as a support frame for the (monolithic) layer stack structure. The individual layers of the layer stack structure can, for example, be applied to create a slight / limited tensile stress in the layers or individual layers of the layer stack structure in order to increase the structural strength of the layer stack structure, particularly during the process steps.

[0076] According to one embodiment, all individual layers, poly-Si layers and intermediate insulation layers (oxide or SiO2 layers), are applied one upon the other, with vertically extending insulation layers, for example, acting as (lateral) etch stop layers to prevent (excessive) back-etching by means of these introduced oxide layers. Furthermore, vertical connections can be provided between the laterally extending conductor track levels, i.e., the individual conductor track levels can be specifically connected to one another, enabling targeted control of the individual conductor tracks.

[0077] According to one embodiment, thin sidewall metallizations may also be applied to the exposed electrodes (e.g., by sputtering) to increase the insensitivity of the finished responses to charging effects.

[0078] According to embodiments, a modular approach can be used in the present manufacturing method, i.e., manufacturing modules for thick intermediate layers, insulation layers and thin highly doped conductor tracks can be carried out in any order to obtain the desired monolithic layer stack structure.

[0079] In the process sequence shown, intermediate etching and polishing processes (CMP = chemical mechanical polishing or MP = mechanical polishing) can also be performed. For example, after the application (post-deposition) of a thick film, the relatively "rough" surface of the thick semiconductor layer can be planarized in order to apply highly doped poly-Si conductor tracks with a thickness in the range of 500 nm (300-700 nm) to a surface as flat as possible, for example, after the application of a thin insulation layer.

[0080] As indicated in step 165, a conformal polymer-based protective coating or sealing layer 240 (e.g., made of parylene, BCB, or polyimide) can (optionally) be conformally applied to the metallic, structured cover layer 230 (current process surface) of the layer stack applied in step 160. The conformally deposited protective coating is chemically very stable, water-repellent, and self-supporting. After performing the process steps of the manufacturing method 100, the protective coating can be removed, for example, by ashing in an oxygen plasma. The sealing layer (protective coating) is provided to enable cooling of the layer stack during high-rate etching. This means that the layer stack rests with the protective coating on a chuck, via which surface cooling of the layer stack is achieved using helium. Without the protective coating, the helium provided for cooling (surface cooling) could escape.

[0081] Furthermore, the protective coating also serves as an etch stop layer for the (isotropic) etching process in the layer stack arrangement, whereby the through-hole or cavity in the layer stack arrangement is created during the etching process. The protective coating, which acts as an etch stop layer, withstands overetching so that all openings can be safely etched through.

[0082] Due to the inhomogeneous etching rate, it should be noted that the internal geometry of the layer stack arrangement does not change or does not change significantly during over-etching, so that, for example, vertically running and laterally running etch stop layers (e.g. oxide layers SiO2) were applied in a correspondingly structured manner during the previous process steps.

[0083] The individual layers (or individual layers) can be applied with a tensile stress or a pressure distribution to provide a slight tensile stress in the layer stack structure, so that no cracking occurs in the layer stack arrangement during various process steps when working at temperatures such as 150 °C. This allows a layer stack arrangement stretched over the carrier wafer frame to be achieved.

[0084] In the following, various aspects of the method 100 for producing a monolithic layer stack structure of Fig. 1a-b shown or summarized.

[0085] The electrical insulation layers made of thermal oxide and / or TEOS oxide (LPCVD / LP-CVD TEOS oxide) serve not only to mechanically (electrically insulate) the individual semiconductor layers but also to adjust the vertical spacing between the stacked semiconductor layers. Furthermore, the applied thermal oxide and TEOS oxide layers also serve as (lateral and / or vertical) etch stop layers during the etching of the semiconductor material of the semiconductor layers. In the manufacturing process, for example, electrical contact layers are formed from an in-situ doped LPCVD poly-Si material (poly-Si thin films). Functional layers (poly-Si thick films) are formed, for example, from a doped, epitaxially deposited, polycrystalline silicon material. Furthermore, an electrically conductive absorber layer made of electroplated gold or tantalum (or another suitable material) can be applied.

[0086] The monolithic layer stack structure (also called membrane) has a structure with a monolithic (i.e. gap-free) stack of conductive layers (doped semiconductor layers or doped poly-Si layers) alternating with insulating layers (oxide layers or SiO2 layers), whereby the top layer (the galvanically thickened gold layer) has an absorbing effect for (charged) particles and X-rays.

[0087] The thick functional layers (semiconductor thick films) can be produced from an epitaxially deposited poly-Si material (epi-poly), whereby the (resulting) layer stress of the membrane (the monolithic layer stack structure) can be or is adjusted during the deposition of the functional layers.

[0088] In the method 100, insulating structures, e.g., lines, trenches, areas, can be produced by trench etching and / or by etching through-holes with subsequent filling with TEOS oxide (LPCVD TEOS oxide) and subsequent surface smoothing, e.g., by CMP (chemical mechanical polishing).

[0089] In the manufacturing method 100 according to the invention, an alternating layer deposition and structuring for producing conductor track levels and contacts and through-contacts (vias) can thus be carried out by the deposition of LPCVD TEOS oxide and LPCVD poly-Si material.

[0090] Furthermore, a metallic starting layer can be applied (on the exposed process surface of the obtained monolithic layer stack structure), followed by local thickening by galvanic deposition of gold and final structuring of the metallic starting layer.

[0091] The production of through holes and blind holes in the membrane (the resulting monolithic layer stack structure) can be achieved, for example, by high-rate silicon etching from the back side of the wafer (substrate back side) using the trenches filled with LPCVD TEOS oxide for sidewall stabilization (to avoid expansion effects).

[0092] The following Table 1 provides an overview of the different processes for producing / applying the different layers, typical thickness ranges of the applied layers, typical temperature ranges during the application process, set mechanical stress and doping materials / types for the applied semiconductor layers. Table 1: Proceedings Thickness temperature stress Endowment Epi-poly silicon 3-100 µm 900-1100 °C + / - 20 MPa Any typical phosphorus (n+) LP Poly-Si <= 5000nm, typically 500nm 500-700 °C deposition + 900-1100 °C annealing Will not be discontinued phosphorus LPCVD TEOS oxide <= 5000 nm 500-800 °C Deposition Typical 670 °C Will not be discontinued No funding Au Electroplating <= 50µm Will not be discontinued No funding Plating Base: Tungsten Titanium, Titanium, Gold, Platinum, Titanium Nitride, Tantalum <= 200 nm, manufactured by sputtering or evaporation processes Will not be discontinued Will not be discontinued

[0093] Semiconductor thick-film structures (epi-poly silicon), for example, are deposited (epitaxially) onto the process surface at a temperature of 900-1100°C with a layer thickness of 3-100 µm and exhibit, for example, a mechanical stress (a tensile stress or pressure distribution) of + / - 20 MPa. Such an epi-poly silicon layer is therefore polycrystalline in nature and grows in its crystal orientation (possibly with the exception of a few direct anchoring points or anchoring areas with the monocrystalline silicon substrate) due to the respective oxide interlayer, independent of the orientation of the silicon substrate.

[0094] Semiconductor thin-film structures (LP polysilicon), for example, are applied to the process surface at a temperature of 500-700°C with a layer thickness of approximately 500 nm (≤ 5000 nm) using an LP CVD process (LP CVD = low pressure CVD) and are subjected to a temperature treatment (annealing), for example, at a temperature of 900-1100°C.

[0095] The insulation layer structure is applied, for example, using an LPCVD TEOS oxide process at a temperature of 500-800°C (and typically 670°C) with a layer thickness of about 500 nm (≤ 5000 nm).

[0096] The metallic, structured cover layer (e.g. Au) can, for example, be applied galvanically in contact with the (respectively) uppermost semiconductor layer structure with a layer thickness of ≤ 50 µm.

[0097] Furthermore, thin sidewall metallizations (plating base) can be applied to the exposed electrodes (e.g. by sputtering or vapor deposition) with a layer thickness of approximately ≤ 200 nm.

[0098] The following Table 2 gives an example of the resulting flatness of the polished layers for the CMP process. Table 2: CMP for Flatness Epi-Poly Ra <= 50 nm typical: 2 nm LPCVD TEOS oxide Leveling the steps depending on the layout

[0099] The following Table 3 shows examples of the etching processes used (RIE = reactive ion etching; DRIE = deep reactive ion etching) with the resulting etching depths. Table 3: Proceedings Etching depths RIE Oxide DRIE Trench <= 100µm THREE back <= 1mm HF gas phase etching Removal of the sidewall stabilization. No directed process

[0100] According to Table 3 above, the following etching methods can be used for the following processes: oxide etching with RIE, trench etching with DRIE, backside etching (145) with DRIE, and oxide back etching with HF vapor phase etching.

[0101] Fig.2 shows an exemplary basic flow diagram of the manufacturing method according to the invention according to a further embodiment. The following will now be explained with reference to Fig. 2 in the Fig. an exemplary, possible sequence of the process steps of the basic flow diagram of the inventive manufacturing method 100 according to an embodiment is described. Fig. from Fig. The coordinate system shown in Figure 2 applies to all images of Fig. 2.

[0102] In the following description, for example, we refer to monocrystalline silicon for the semiconductor substrate and silicon (polycrystalline silicon = poly-Si) for the epitaxially deposited layers. Therefore, the insulation layers comprise, for example, an oxide material (e.g., SiO2 from thermal oxide or LPCVD TEOS oxide). In principle, however, other suitable semiconductor materials and, associated with them, other oxides or insulation materials can also be used.

[0103] As the following statements regarding the Fig. 2, an integrated manufacturing process is carried out in which layer structures are stacked and this stacking process is repeated, wherein lithography processes, etching processes, doping processes and deposition techniques are used in these processes.

[0104] As now in Fig. from Fig. 2, in step 110 of the method 100, a semiconductor substrate 204 provided with a structured insulation layer 202 is provided. For example, a (monocrystalline) Si substrate 204 provided with a structured oxide layer 202 (e.g., thermal oxide or SiO2) can be provided, i.e., it is arranged at or on a first main surface region 204-A of the semiconductor substrate 204. Thus, for example, a Si wafer 204 with an SiO2 layer 202 on its main surface region 204-A serves as the starting point of the method 100.

[0105] In the following description of the manufacturing process 100 based on the Fig. 2 process steps shown as examples in Figures 1 - 9, it is pointed out that the Si substrate can be designed, for example, as a Si wafer, whereby a large number of the Fig.2 shown structures (apertures or optical through-openings) can be manufactured laterally next to each other in the monolithic layer stack structure as a corresponding array.

[0106] The oxide layer 202 can now be structured, for example, to provide through openings or through regions 206 to the Si substrate 204 (ie, to the first main surface region 204-A of the Si substrate 204). Such through openings (vias) are shown by way of example in the following Fig. shown.

[0107] As now in Fig. from Fig. 2 is shown as an example, the first manufacturing module (process module) 120 is now carried out.

[0108] The thick functional layers (semiconductor thick films or poly-Si thick films) 210-1 can be produced, for example, from an epitaxially deposited poly-Si material (epi-poly). The structured application of the (first) semiconductor thick-film structure 210-1 can be carried out, for example, using a deposition (epitaxy), lithography, and etching process. This means that structured application is understood to mean, for example, a material deposition process, e.g., a CVD process (epitaxy process), a lithography process for defining areas to be etched on the respective process surface area, and a subsequent etching process.

[0109] As in Fig. from Fig.2, in steps 120-1 and 120-2 of the first manufacturing module 120, insulating structures 208, 208-1, 208-2, e.g., lines, trenches, areas, etc., can be produced by trench etching and / or by etching through-openings with subsequent filling by an insulating material, e.g., TEOS oxide or LPCVD TEOS oxide, and subsequent surface smoothing, e.g., by CMP (chemical mechanical polishing). For example, the first sub-step 120-1 of the first manufacturing module can be a structured application of the poly-Si thick-film structure 210-1 onto the insulation layer 202 (process surface of the currently present layer stack arrangement 201), wherein trenches and / or through openings 212 are or will be arranged in the poly-Si thick-film structure 210-1.

[0110] In the further sub-step 120-2 of the first manufacturing module, an insulation layer structure 208 is applied in a structured manner to the semiconductor thick-film structure 210-1 to provide an insulating surface layer 208-1 on the semiconductor thick-film structure 210-1 and as (vertical) filling regions 208-2 for filling the trenches and / or through-openings 212 in the semiconductor thick-film structure 210-1. The semiconductor thick-film structure 210-1 is further structured such that the applied insulation layer structure 208 (208-1 + 208-2) divides or separates the semiconductor thick-film structure 210-1 into a functional material region 210-A and a sacrificial material region 210-B.

[0111] In the second sub-step 120-2 of the first manufacturing module, for example, an oxide layer structure 208 can be applied in a structured manner to the poly-Si thick-film structure 210-1 in order to fill the trenches and / or through-openings 212 in the further poly-Si thick-film structure 210-1 as (insulating) filling regions 208-2 and to provide an oxide surface layer 208-1 on the poly-Si thick-film structure 210-1. The poly-Si thick-film structure 210-1 is further structured such that the applied oxide layer structure 208 divides the poly-Si thick-film structure 210-1 into the functional material region 210-A and the sacrificial material region 210-B.

[0112] The Fig. 2 shown Fig.thus shows a first epi-poly-Si process cycle for the method 100 for producing a monolithic layer stack structure 200, e.g. for a monolithic multi-aperture plate, which can be used, for example, as a multiple lens arrangement for a multi-beam electron beam system.

[0113] As in Fig. 2 based on Fig. As shown by way of example, the first process module or manufacturing module 120 can be executed again (step 135) in order to apply a further semiconductor thick-film structure (poly-Si thick-film structure) 210-2 in a structured manner on the current process surface, that is to say on that of the insulating surface layer 208 covering the first semiconductor thick-film structure 210-1 (poly-Si thick-film structure).

[0114] Thus, in the first sub-step 120-1 of the first manufacturing module, the further poly-Si thick-film structure 210-2 is applied in a structured manner to the insulation layer structure 208 (process surface of the currently present layer stack arrangement), wherein trenches and / or through openings 212 are or will be arranged in the poly-Si thick-film structure 210-2.

[0115] In the second sub-step 120-2 of the first manufacturing module, for example, the oxide layer structure 208 is applied in a structured manner to the further poly-Si thick-film structure 210-2 in order to fill the trenches and / or through-openings 212 in the further poly-Si thick-film structure 210-2 as (insulating) filling regions 208-2 and to provide an oxide surface layer 208-1 on the further poly-Si thick-film structure 210-2, wherein the further poly-Si thick-film structure 210-2 is further structured such that the applied oxide layer structure 208 subdivides or separates the poly-Si thick-film structure 210-2 into the functional material region 210-A and the sacrificial material region 210-B.

[0116] As in Fig. from Fig.As shown by way of example in Figure 2, a through opening or a through region (via) 206 can be arranged or provided between the first and second semiconductor thick-film structures 210-1, 210-2 (in their functional material regions). However, a plurality of through openings or through regions (vias) 206 can also be arranged or provided between the first and second semiconductor thick-film structures 210-1, 210-2 (in their functional material regions).

[0117] Fig. from Fig. 2 thus shows a repeated execution (repeat 135 of the execution) of the first manufacturing module 120. Fig. from Fig. 2 thus shows, for example, a second epi-poly process cycle in which, for example, stigmator electrodes 215 of the monolithic layer stack structure 201 (e.g., multi-aperture plate) are formed as part of the functional material region of the further deposited semiconductor thick-film structure 210-2.

[0118] Fig. from Fig. 2 now shows, by way of example, a step 130 of executing a second manufacturing module / process module. Executing the second manufacturing module (process module) comprises the following steps (substeps). In the first substep 130-1 of the second manufacturing module, a (first) highly doped semiconductor thin-film structure 220-1 is applied in a structured manner to the respective process surface of the currently present layer stack arrangement, i.e., to the uppermost insulation layer structure 208, wherein trenches and / or through openings 222 are or will be arranged in the highly doped semiconductor thin-film structure 220-1.

[0119] For example, in sub-step 130-1, a (first) highly doped poly-Si thin-film structure 220-1 can be applied in a structured manner to the respective process surface of the currently present layer stack arrangement 201, wherein trenches and / or through openings 222 are or will be arranged in the highly doped poly-Si thin-film structure 220-1.

[0120] According to a further sub-step 130-2 of the second manufacturing module, a further insulation layer structure 208 is applied in a structured manner to the highly doped semiconductor thin-film structure 220-1 in order to fill the trenches and / or through-openings 222 in the highly doped semiconductor thin-film structure 220-1 as (vertical) filling regions 208-2 and to provide an insulating surface layer 208-1 on the highly doped semiconductor thin-film structure 220-1, wherein the highly doped semiconductor thin-film structure 220-1 is further structured such that the applied further insulation layer structure 208 divides the semiconductor thin-film structure 220-1 into a functional material region 220-A and a sacrificial material region 220-B.

[0121] For example, in the second sub-step 130-2 of the second manufacturing module, a further oxide layer structure 208 (208-1, 208-2) can be applied in a structured manner to the highly doped poly-Si thin-film structure 220-1 in order to fill the trenches and / or through-openings 222 in the highly doped poly-Si thin-film structure 220-1 as (vertical) filling regions 208-2 and to provide an oxide surface layer 208-1 on the highly doped poly-Si thin-film structure 220-1, wherein the highly doped poly-Si thin-film structure 220-1 is further structured such that the applied further oxide layer structure 208 divides the poly-Si thin-film structure 220-1 into the functional material region 220-A and a sacrificial material region 220-B.

[0122] The respectively applied insulation layer structure 208 can fill a trench 212, 222 and / or a through-opening 212, 222 provided there in the respective semiconductor thick-film structure 210-# and / or the respective semiconductor thin-film structure 220-# in order to form a vertically extending section (filling region) 208-2 of the respective insulation layer structure 208. This makes it possible to obtain, for example, lateral (vertically extending) etch stop layer structures or structures for electrically isolating (laterally) adjacent regions, e.g., in a plane of a respective semiconductor layer structure 210-#, 220-#, wherein the laterally extending regions 208 of the insulation layer structure, for example, mechanically interconnect horizontally adjacent semiconductor layers 210-#, 220-# and electrically separate them from one another, provided that no electrically conductive through-openings 206 are provided there.If electrical through openings 206 are present in the laterally extending regions of the insulation layer structure 208, these can act as electrically conductive through openings (vias).

[0123] The thin functional layers (semiconductor thin-film structures) 220-1, ..., 220-# can be produced from an epitaxially applied poly-Si material (epi-poly), wherein the respective semiconductor thin-film structure 220-# can be applied in a structured manner by means of lithography and etching processes, wherein trenches and / or through openings can in turn be arranged / provided in the semiconductor thin-film structure 220-#.

[0124] Fig. from Fig.2 thus shows, for example, the implementation of a third poly-Si process cycle for depositing / applying a (first) thin poly-Si layer structure 220-1, which is formed, for example, as the first wiring level in the monolithic layer stack structure.

[0125] In the following Fig. from Fig. 2 shows (for reasons of clarity) the reference symbols of the “newly received” elements as well as the reference symbols of some (essential) previously received elements. The reference symbols of the remaining elements from the Fig. from Fig. 2 apply equally to the corresponding elements in the Fig. from Fig. 2.

[0126] Fig. from Fig.2 now shows, by way of example, the repetition 135 of the execution of the second manufacturing module 130 in order to apply or deposit, in a fourth poly-Si process cycle, a (second) thin poly-Si layer structure 220-2 onto the insulation layer structure 208 (process surface) covering the (first) thin poly-Si layer structure 220-1, wherein the (second) thin poly-Si layer structure 220-2 is provided, for example, as a further (second) wiring level of the monolithic layer stack structure 200.

[0127] As the above explanations clearly show, the execution of the first and / or second manufacturing module can be repeated or repeated several times (step 135), wherein the execution of the respective manufacturing module 120, 130 is carried out on the exposed process surface (the currently exposed main surface area of the current layer stack intermediate arrangement 201).

[0128] Fig. from Fig.2 now shows, by way of example, the (re-)execution of the first manufacturing module with the application of a further (third) semiconductor thick-film structure (poly-Si thick-film structure) 220-3 on the currently exposed process surface of the layer stack intermediate arrangement, ie on the insulation layer structure 208 covering the (second) thin poly-Si layer structure 220-2.

[0129] Thus, in the first sub-step 120-1 of the first manufacturing module, the further (third) poly-Si thick-film structure 210-3 is applied in a structured manner to the insulation layer structure 208 (process surface) covering the second poly-Si thin-film structure 220-2, wherein trenches and / or through openings 212 are or will be arranged in the poly-Si thick-film structure 210-2.

[0130] In the second sub-step 120-2 of the first manufacturing module, for example, the oxide layer structure 208 is applied in a structured manner to the further poly-Si thick-film structure 210-3 in order to fill the trenches and / or through-openings 212 in the further poly-Si thick-film structure 210-3 as (insulating) filling regions 208-2 and to provide an oxide surface layer 208-1 on the further poly-Si thick-film structure 210-3, wherein the further poly-Si thick-film structure 210-3 is further structured such that the applied oxide layer structure 208 subdivides or separates the poly-Si thick-film structure 210-3 into the functional material region 210-A and the sacrificial material region 210-B. Fig. from Fig. 2 thus shows, for example, a fifth process cycle in which a final poly-Si layer level (here the third poly-Si thick-layer structure 210-3) is applied.

[0131] At Fig. from Fig.2, by way of example (e.g., prior to applying a conformal polymer-based protective coating), in the (optional) step 160, a metallic, structured cover layer 230 is applied in contact with the (respectively) uppermost semiconductor thin-film structure or semiconductor thick-film structure 210-#, 220-#. Fig. from Fig. 2, this is the third poly-Si thick-film structure 210-3. This structured metallic cover layer 230 can, for example, be formed as contact areas (bond pads) 230-1 for contacting the semiconductor thin-film structures (e.g., semiconductor interconnects) 220-1, ..., 220-#, as well as a protective structure 230-2 to prevent excessive undercutting.

[0132] This structured metallic cover layer 230 can further be configured as an (electron-dense or electron-opaque) layer for forming separate single electron beams (in a multi-aperture plate) with a high electron-stopping efficiency. The structured metallic cover layer 230 can, for example, be several micrometers thick and comprise, for example, tungsten, rhenium, osmium, iridium, platinum, gold, tantalum, or lead.

[0133] As now with Fig. from Fig. 2 is further illustrated by way of example, according to a further exemplary embodiment, in step 160 of applying the metallic, structured cover layer 230, the metallic, structured cover layer 230 can be applied as a (structured) layer sequence (layer stack or layer structure) with a base layer 231 and a metal layer 232 arranged thereon. The base layer 231 can be arranged, for example, as an adhesion promoter layer for the metal layer 232 below the metal layer 232, i.e., between the metal layer 232 and the uppermost layer of the layer stack arrangement 201.

[0134] According to one embodiment, a step 161 of structuring the base layer 231 and a step 162 of structuring the metal layer 232 may be performed to form contact regions 230-1 for contacting the semiconductor thin-film structures 220-# (semiconductor interconnects). According to one embodiment, in step 161 of structuring the base layer 161, (laterally) circumferential trench structures 230-3 may be formed around the contact regions 230-1 through the cap layer 230.

[0135] According to one embodiment, in step 160 of applying the layer sequence with the base layer 231 and metal layer 232, a WTi material (WTi = tungsten titanium) can be applied for the base layer 231 and a gold material can be applied for the metal layer 232.

[0136] According to a further embodiment, in step 160, a titanium, tantalum, or chromium material can also be applied for the base layer 231 (as an alternative to tungsten titanium). The base layer 231 can also be applied as a layer sequence or layer stack with multiple layers of the aforementioned materials, e.g., as a titanium-WTi layer sequence.

[0137] According to a further embodiment, in step 160, a tungsten, rhenium, osmium, iridium, platinum, silver, tantalum, or lead material can also be applied for the metal layer 232 (as an alternative to gold). The metal layer 232 can also be applied as a layer sequence or layer stack with multiple layers of the aforementioned materials. For example, metals with a high atomic number are used for the metallic, structured cover layer 230 in order to achieve an efficient shielding effect, e.g., also against X-rays, with the metallic, structured cover layer 230.

[0138] According to one embodiment, a step 163 of applying a dielectric cover layer (surface passivation layer) 234 at least partially (or completely) to the layer stack arrangement 201 and a step 164 of structuring the applied dielectric cover layer 234 can be carried out, wherein during the structuring 164 of the dielectric cover layer 234 the contact regions (bond pads) 230-1 are exposed such that circumferential edge surface regions (on the top side) of the contact regions 230-1 remain covered with a width of at least 1 µm (and e.g. up to 5 µm).

[0139] According to one embodiment, during the application 163 and the structuring 164 of the dielectric cover layer 234, regions 230-2, 230-3 adjacent to the contact regions 230-1 on the (upper) first main surface region 201-A of the layer stack arrangement 201 may further be covered at least partially or completely with the dielectric cover layer 234.

[0140] According to one embodiment, the dielectric cap layer 234 may be conformally deposited on (the exposed surface areas of) the layer stack arrangement 201 using an ALD (atomic layer deposition) process.

[0141] Fig. from Fig. 2 now shows an optional step 165 of applying a conformal polymer-based protective coating 240, e.g., a parylene layer, to the exposed process surface of the layer stack arrangement (e.g., prior to the step of etching 150 into the layer stack arrangement). As in Fig. from Fig. As further illustrated in Figure 2, in step 140, an etch mask structure 250, e.g., in the form of a resist material layer structure, may now be applied to the exposed, rear-side main surface region of the semiconductor substrate 204, e.g., the monocrystalline silicon substrate. Optionally, the etching compound structure (resist material layer structure) 250 may also be applied to the exposed, current process surface of the layer stack arrangement 201.

[0142] In a next step 145, the semiconductor substrate 204, e.g., the monocrystalline silicon substrate, is etched, i.e., etched from the back side 204-B. This can be, for example, an anisotropic etching process. This (anisotropic) etching process 145 can, for example, be stopped or terminated after etching through the semiconductor substrate 204, e.g., after the complete vertical etching through of the semiconductor substrate 204 and upon reaching the (first) semiconductor thick- or thin-film structure 210-1 or 220-1 (e.g., from step 115, 120, or 130).

[0143] In a subsequent step 150, etching is now carried out through the semiconductor substrate 204 opened at the rear in step 145 (e.g., isotropic) into the layer stack arrangement 201 in order to remove the sacrificial material regions 210-A, 220-A of the different semiconductor thick-film structures 210-1, ..., 210-# or semiconductor thin-film structures 220-1, ..., 220-#, wherein the applied insulation layer structures 208, ie the trenches and / or through openings 212 filled with the insulation material 208-2, form a lateral (vertically extending) etch stop layer structure.

[0144] In step 150, for example, isotropically etching can be carried out into the layer stack arrangement through the monocrystalline silicon substrate 204 opened at the rear in step 145 in order to remove the sacrificial material regions 210-B, 220-B of the poly-Si thick-film structures 210-1, ..., 210-# and the poly-Si thin-film structures 220-1, ..., 220-#, wherein the applied oxide layer structures 208 or the regions of the applied oxide layer structures 208 acting as (vertical) filling regions 208-2 form a lateral (side) etch stop layer structure.

[0145] The Fig. from Fig. 2, a conformal polymer-based protective coating (e.g., made of parylene, BCB (benzocyclobutene), or polyimide) can be applied to the process surface (= currently exposed upper surface area) of the layer stack. The conformally deposited protective coating is chemically very stable, water-repellent, and self-supporting. After completing the process steps (in Figure 8 of Fig. 2) The protective coating can be removed, for example, by ashing in oxygen plasma. The sealing layer (protective coating) is provided to enable cooling of the layer stack during high-rate etching. This means that the layer stack rests with the protective coating on a chuck, through which the surface of the layer stack is cooled using helium. Without the protective coating, the helium used for cooling (surface cooling) could escape.

[0146] Furthermore, the protective coating also serves as an etch stop layer for the (isotropic) etching process in the layer stack arrangement, whereby the through-hole or cavity in the layer stack arrangement is created during the etching process. The protective coating, which acts as an etch stop layer, withstands overetching so that all openings can be safely etched through.

[0147] Due to the inhomogeneous etching rate, the internal geometry must not change during overetching, so that, for example, vertically and laterally extending etch stop layers (e.g., oxide layers SiO2) were applied in a correspondingly structured manner during the previous process steps. From process step 8 ( Fig. from Fig. 2) The etching processes can be performed, for example, using dry etching. Chip contour etching creates a circumferential support frame, with the etching process ending on the parylene membrane (protective coating). This protective coating holds individual adjacent elements (chips) of the layer stack structure together, e.g., for transfer to further processing steps.

[0148] The oxide layers applied during the manufacturing process can, for example, be applied as so-called TEOS layers, which ultimately hold the layer stack structure together. Only the oxide layer present on the semiconductor substrate (silicon substrate) can be formed as a thermal oxide.

[0149] The individual layers (or individual layers) can be applied with a tensile stress or a pressure distribution to provide a slight tensile stress in the layer stack structure, so that no cracking occurs in the layer stack arrangement during various process steps when working at temperatures such as 150 °C. This allows a layer stack arrangement stretched over the carrier wafer frame to be achieved.

[0150] Since the applied structured metallic cover layer (e.g. a gold layer) generally has a higher coefficient of expansion than the remaining layer materials, this can also result in a tensile stress in the layer stack arrangement, i.e. the layer arrangement (membrane) can be kept taut.

[0151] As shown by example Fig. the Fig. 2, in step 155 the etch stop layer structure is now removed in regions, that is to say, for example, an etching back of the insulation material 208, 208-1, 208-2 is carried out in order to expose surface regions of the functional material regions 210-A, 220-A adjacent to the etch stop layer structure in order to obtain the monolithic layer stack structure 200 using the manufacturing method 100.

[0152] In step 155 of removing the etch stop layer structure in regions, an oxide etch-back may be performed, for example, to expose the surface regions of the functional material regions 210-A, 220-B of the poly-Si thick-film structures 210-1, ..., 210-# and poly-Si thin-film structures 220-1, ..., 220-# adjacent to the etch stop layer structure in order to obtain the monolithic layer stack structure 200.

[0153] Finally, in step 155-1, for example, the conformal polymer-based protective coating 240, e.g., the parylene layer, can be removed from the exposed process surface of the layer stack arrangement, and in step 155-2, the etch mask structure 250, e.g., the resist material layer structure, can be removed from the exposed, rear-side main surface region 204-B of the semiconductor substrate 204.

[0154] According to one embodiment, step 163 of applying the dielectric cap layer 234 may be performed, for example, before the step 165 of applying the conformal polymer-based protective coating 240 to the layer stack arrangement 201. According to one embodiment, step 164 of patterning the applied dielectric cap layer 234 may be performed, for example, after the step 155-1 of removing the conformal polymer-based protective coating 240 from the layer stack arrangement 201.

[0155] According to a further embodiment, main surface regions of the monolithic layer stack structure 200 (directly) adjacent to an aperture opening 230-4 in the metallic, structured cover layer 230 can be exposed by removing the dielectric cover layer 234 at these regions in order to obtain an efficient shielding effect of the metallic, structured cover layer 230. The metallic cover layer 230 exposed around the aperture opening(s) 230-4 can, for example, efficiently dissipate charges and prevent static charging of the upper main surface of the layer stack structure 200. Such charges can, for example, originate from scattered or unfocused charged particles of the incident particle beam 270. The metallic cover layer 230 is, for example, (multiply) grounded (connected to ground potential) for charge dissipation.

[0156] Finally, the monolithic layer arrangement 200 can, for example, be separated into individual functional elements (chips) (step 170) if the layer arrangement 200 has a plurality or an array of apertures (through openings) 260 or aperture plates or inertial sensors.

[0157] With regard to further details of the obtained monolithic layer arrangement 200 and the associated manufacturing method 100, Fig. from Fig. 2 for example, the portion designated 200' of the monolithic layer stack structure 200 of Fig. the Fig. 2 in an enlarged cross-sectional view.

[0158] As exemplified by Fig. the Fig. 2, the contact regions (bond pads) 230-1 in the cover layer 230 can be formed, for example, by forming circumferential trenches 230-3 in the cover layer 230 at the positions where the contact regions are to be provided on the layer stack arrangement. The trenches 230-3 extend (at least) to the (insulating) layer of the layer stack arrangement 201 arranged below the cover layer 230. As shown in Fig. from Fig. As shown by way of example in Figure 2, the layer arranged beneath the applied covering layer 230 can be or comprise an insulating layer, e.g., an SiO2 layer. The trenches 230-3 of the covering layer 230, which define the contact regions 230-1, have, for example, a depth that corresponds at least to the thickness of the covering layer 230. The covering layer 230 has, for example, a thickness of several µm, e.g., between 1 and 50 µm or between 2 and 20 µm.

[0159] The lateral dimensions of the contact pads 230-2 as shown in Fig. from Fig. 2 (and also in Fig. 4) are illustrated by way of example in a cross-sectional view, are predetermined and defined, for example, by circumferential trench structures 230-3 in the cover layer 230. The trench structures 230-3 are formed, for example, without overhangs (undercuts) and solely by the cover layer 230. Furthermore, the dielectric cover layer (surface passivation) 234 is provided as a dielectric coating on the circumferential edge regions of the contact pads 230-1 and the adjacent surface regions of the layer stack arrangement 201.This configuration of the contact pads 230-1 with the trench structure 230-3 and the dielectric capping layer 234 can effectively prevent high-voltage short circuits that could otherwise occur, for example, due to particles 300 depositing on the main surface region of the layer stack arrangement 201 between adjacent structures that are at a different electrical potential. As shown in FIG. Fig. from Fig. 2, the (possibly depositing) particle 300, which could be arranged on the trench structure 230-3 between the contact connection region 230-1 and an adjacent region 230-2 of the capping layer 230, cannot cause an electrical short circuit between these two adjacent regions due to the dielectric capping layer 234.

[0160] The dielectric cover layer 234 can, for example, be conformally deposited as a dielectric thin film, for example using an ALD (atomic layer deposition) process. The dielectric cover layer 234 can, for example, comprise an Al2O3 material or an ALD-based aluminum nitride material, titanium oxide material, or tantalum oxide material. The dielectric cover layer 234 applied as a thin film can, for example, be patterned with a patterned resist cover by means of plasma etching, e.g., in a chlorine-containing atmosphere, in order to expose the exposed contact surfaces of the contact connection regions 230-1, e.g., for a wire bonding process. As an alternative to plasma etching in a chlorine-containing atmosphere, the dielectric cover layer 234 can also be patterned by means of wet etching or ion milling, etc.The resist material for the patterned resist covering of the dielectric covering layer 234 is then removed (after patterning 164 of the dielectric covering layer 234).

[0161] The dielectric cover layer 234 applied as a thin film can fulfill a variety of functions. By applying the dielectric cover layer 234 to the main surface region of the layer stack arrangement 201, the sidewalls and bottom regions of the trenches 230-3 in the cover layer 230 are also covered, so that undercutting of the planar SiO2 insulation layers and the base layer (e.g., adhesion promoter layer) 231 beneath the contact pad 232 is prevented during the etching step 150 into the layer stack arrangement 201. The dielectric passivation layer 234 also prevents circumferential insulation trenches 222 filled with an insulation material, e.g., SiO2, from being eroded into the depth during the etching step 150, which is carried out, for example, as an HF gas-phase etching (HF = hydrofluoric acid), and thus could again become difficult to inspect (visible) particle traps.If particles 300 then deposit on the trenches 230-3 or bridge them, a short circuit is prevented by the insulating effect of the deposited dielectric covering layer (thin film passivation) 234 to directly adjacent potential surfaces 230-2 (which are at a different electrical potential to the contact areas 230-1).

[0162] In the following, some aspects of the Fig. 2 is shown again in other words for clarification, wherein the integrated manufacturing process 100 is carried out by stacking and repeating individual processes (lithography processes, etching processes, doping and deposition techniques) or process modules.

[0163] As in Fig. from Fig. As shown in Figure 2, the manufacturing method begins, for example, with a Si substrate 204 having a SiO2 layer 202 on its top side 204-A (first main surface area). Subsequently, several (epitaxial) polysilicon deposition cycles (first and / or second manufacturing module 120, 130) are performed to apply poly-Si thick films (epi-poly-Si) 210-1, ..., 210-# for providing electrodes and poly-Si thin films 220-1, ..., 220-# for providing wiring levels. This predefines the following structures or arrangements of the monolithic layer stack structure 200: a) Functional material areas 210-A, 220-A (= volume of functional poly-Si material), e.g. as substrate, electrodes, signal connectors including planar lines and (vertical) vias (feedthroughs), b) sacrificial material regions 210-B, 220-B (volumes of sacrificial poly-Si material), such as initial fillings of openings, and a separation of poly-silicon material between the multi-electrodes, c) structured horizontal layers 208-1 and vertical walls 208-2 of silicon dioxide 208 (SiO2) for electrical isolation and for providing a mechanical support function, d) Isolation structures 208 with structured horizontal layers 208-1 and vertical walls 208-2 made of an insulating material, e.g. SiO2, which surround the functional regions (functional Si volumes) 210-A, 220-A from all sides and separate them from the sacrificial material regions (sacrificial Si volumes) 210-B, 220-B, wherein these structures further have an etch stop function to protect the functional material regions (functional Si material regions) during the Si etching steps.

[0164] As exemplified in Fig. from Fig. 2, a conductive material layer (metallic, patterned cap layer) may be applied (as one of the last process steps before the etching processes of the through-hole or aperture 260), such as a several µm thick gold material, in contact with the uppermost semiconductor layer structure 210-# or 220-#, to form a layer of the conductive (metallic) material that forms separate single electron beam regions, the conductive layer having a high electron stopping efficiency (effectiveness).

[0165] As shown by example Fig. from Fig. As shown in Figure 2, the sacrificial material regions (sacrificial Si volumes) 210-B, 220-B can be removed or etched by a chemical reaction or by a Si etching process. A sequence of steps can be performed, starting with an SF6-based anisotropic silicon etching step followed by a Si etching step.

[0166] As further exemplified in Fig. from Fig. 2, for example, the SiO2 layers that covered the Si electrodes and protected their functional material areas (functional Si material) during the sacrificial Si etching processes can finally be removed or etched.

[0167] Fig. from Fig. Figure 2 shows the result of the etched aperture(s) 260 after removal of the exposed SiO2 layers. The exposed SiO2 layers can be etched using wet-chemical or dry-chemical etching. In a dry-chemical etching process, e.g., with HF vapor-phase etching, the oxide material is etched dry with HF gas. The HF gas can, for example, contain a small alcohol content for surface conditioning. Thin metal layers can be deposited on the inner surfaces (electrodes 215) of the apertures (optical through-openings) 260 by deposition. Finally, the protective etching layer is removed.

[0168] Fig. from Fig. Finally, Figure 2 shows the uppermost layers of the monolithic multi-aperture plate 200 facing the incident electrode beam 270. The connecting contacts of the metal layer 230 provided on the upper side, which are provided for the electrical connection of the electrodes 215, can also be connected to a control unit so that the respectively transmitted electron beams can be individually influenced during operation, e.g., by means of focusing, beam shaping, astigmatic transformation, or beam deflection.

[0169] As shown by the Fig. 1a-b and Fig. 2, a monolithic layer stack structure 200, e.g., a monolithic multi-aperture plate or an initial sensor, can be obtained with the inventive manufacturing method 100. The Fig. 1a-b and Fig. The manufacturing method 100 for the monolithic layer stack structure 200 shown in Figure 2 can now be summarized, for example, as follows.

[0170] First (in a first step), a bottom plate 204 made of doped silicon with an insulating SiO2 layer 202 is provided. The SiO2 layer 202 is photolithographically patterned, and a further doped silicon layer 210-# or 220-# is epitaxially grown and patterned. A further insulating SiO2 layer structure 208 (208-1 and 208-2) is created above this. These steps are repeated, and further poly-Si layer structures 210-#, 220-# are formed. In each of these layers, conductive structures are photolithographically separated by insulating structures 208, which conductive structures then (finally) form the embedded electrodes 215 and the conductive connections. Thus, various functional layers of the monolithic layer stack structure 200, e.g.a monolithic multi-aperture plate, wherein the applied poly-Si layer structures are designed as functional layers with a supporting function, as passive electrodes or spacers, and / or as active electrodes. Finally, the conductive absorber layer 230 made of dense material (e.g., with a high atomic number) is applied and patterned. For the chemical etching of the future apertures 260, an etch protection layer is applied and photolithographically patterned according to the future apertures. The apertures are then etched into the doped silicon, with the etch protection layer and the silicon dioxide structures acting as the etch protection layer.

[0171] The monolithic layer stack structure 200 can thus be used, for example, as a monolithic multi-beam micro-optics system for a particle-optical system. Due to the functionality of the micro-optics 200 as a monolithic multi-aperture plate, several individual beams can be generated from a wide incident particle beam, for example, whereby beam shaping (stigmization, focusing, lateral deflection) can also be achieved for the individual beams (using the lateral electrodes 215).

[0172] In the manufacturing method 100, a microchip with the membrane 200 (= the monolithic layer stack structure) or a thin microchip can be obtained over the entire surface. The basic structure of the membrane 200 now has a monolithic (= gap-free) stack of conductive layers 210-1, ..., 210-#, and 220-1, ..., 220-# alternating with insulating layers 208, 208-1, 208-2. Furthermore, a structured metallic cover or aperture layer 230 is formed as the uppermost layer, which has an absorbing effect on particles (electrically charged particles) and / or X-rays.

[0173] Particle beams 270, for example, can pass through the through aperture(s) 260 in the microchip 200. In the layer stack structure 200, the insulating structures 208, 208-1, 208-2, which are formed, for example, as lines, trenches, surface areas, etc., are embedded in the conductive layers 210-1, ..., 210-#, 220-1, ..., 220-#, wherein the conductive layers 210-1, ..., 210-#, 220-1, ..., 220-# are in turn provided for forming electrodes, e.g., ring or octopole electrodes, and conductor tracks. Furthermore, local electrical connections 206 are provided between the conductive layers 210-1, ..., 210-# and / or 220-1, ..., 220-#, which are provided as so-called vias (conductive feedthroughs) through the insulating layers 208.

[0174] Since the opening (aperture) 230-4 in the metallic cover layer 230 (aperture layer) has a smaller diameter D1, e.g., a diameter D2, D3 that is at least half smaller than the following structures in the (optical) through-opening 260, direct lines of sight between insulating surfaces and individual beams (of the incident particle beams) 270 as well as between voltage-carrying conductor tracks 210-1, ..., 210-#, 220-1, ..., 220-# and individual beams (of the incident particle radiation) can be avoided.

[0175] Example dimensions for the elements of the monolithic layer stack structure 200 are given below.

[0176] The membrane thickness, i.e., the (vertical) thickness of the monolithic layer stack structure 200, can typically range from 50 to 250 µm. The total chip thickness, i.e., the membrane (layer stack structure) 200 with the carrier frame or support frame 204-A (made of the through-etched semiconductor substrate 204), can typically range from 400 to 1000 µm. The number of apertures 260 can, for example, range from 50 to 1000. The diameter D2, D3 of the apertures 260 (optical through openings without taking into account the opening in the cover layer 230) can be in a range of 40 - 80 µm and typically 50 µm, while the metallic cover layer 230 has an opening (diaphragm) with a diameter D1 which is in a range of 30 - 60% of the diameter of the underlying through opening (aperture) 260, e.g. 20 - 40 µm and typically 30 µm.

[0177] In a multi-aperture arrangement, the spacing between adjacent apertures 260 can be 80 - 150 µm or typically 100 µm. The uppermost layer 230 (absorption layer) typically comprises a metal with a high atomic number, e.g., gold, with a thickness between 0.5 and 5 µm. Conductive layers 210-1, ..., 210-# (semiconductor thick films), which, for example, perform beam-shaping functions (as electrodes 215), typically comprise doped silicon (e.g., poly-Si) with a thickness of typically 5 - 50 µm. Conductive layers 220-1, ..., 220-# (semiconductor thin films) for forming conductor tracks typically comprise doped silicon (e.g., poly-Si) with a thickness of typically 0.25 - 5 µm. The insulating layers or structures 208, 208-1, 208-2 typically comprise silicon dioxide (SiO2) as material with a (lateral and / or vertical) thickness of typically 0.5 - 5 µm.

[0178] The Fig. the Fig. The monolithic layer stack structure 200 shown in Figure 2 has, for example, only one through-opening 260. However, the monolithic layer stack structure 200 can also be designed, for example, as a monolithic multi-aperture plate (monolithic multi-beam micro-optics for a particle-optical system) with a plurality of through-openings. In this case, the monolithic layer stack structure 200 has the uppermost layer 230 as an absorption layer (metallic cover layer), which acts as a diaphragm to form the individual beams from a broad beam incident from above. Voltages can be applied between electrodes 215 in the same layer, e.g., the second semiconductor thick-film structure 210-2, in order to achieve beam deflection or stigmation of individual beams 270 within the aperture 260. Furthermore, (arbitrarily) further semiconductor layers, e.g.,Further semiconductor thick-film structures 210-# may be provided, wherein voltages may again be applied between the electrodes 215 in the same layer, i.e., the respective semiconductor thick-film structure 210-#, in order to achieve (further) beam deflection or stigmation of individual beams 270 within the aperture 260. Furthermore, voltages may be applied to or between conductive semiconductor layer structures 210-#, 220-# in order to achieve focusing of the individual beams 270. Furthermore, a voltage may be applied between the bottommost plate and "infinity" in order to achieve focusing of the individual beams. The application of a voltage towards "infinity" is provided by applying a bias voltage to this bottommost plate 210-1.

[0179] The described manufacturing method 100 for producing the monolithic layer stack structure 200 enables gap-free production between the individual layers or layer structures 208, 208-1, 208-2, 210-1, ..., 210-#, 220-1, ..., 220-# of the layer stack arrangement 200. The manufacturing method 100 according to the invention makes it possible to expand the monolithic layer stack structure 200 to essentially any desired number of functional layers. Furthermore, the manufacturing method 100 makes it possible to maintain no further gaps within layers other than the apertures 260, wherein the electrodes 215 can be individually contacted via the conductor track levels 210-1, ..., 210-#, 220-1, ..., 220-#. Furthermore, an essentially desired number of electrodes (ring electrodes) 215 arranged vertically one above the other can be realized.Furthermore, the structure of the monolithic layer stack structure 200 obtained by the manufacturing method 100 can avoid direct lines of sight between insulating surfaces 208, 208-1, 208-2 and individual beams (particle beams) 270 as well as between voltage-carrying conductor tracks 210-1, ..., 210-#, 220-1, ..., 220-# and individual beams (particle beams) 270.

[0180] The monolithic structure can be achieved by the insulation structures or insulation layers 208, 208-1, 208-2, since these layers establish the mechanical connection between the applied conductive semiconductor layers 210-1, ..., 210-#, 220-1, ..., 220-#. Furthermore, by removing (etching back) the insulation layer structures 208, 208-1, 208-2 in certain regions, these insulation layer structures 208, 208-1, 208-2 can be electrically shielded from the particle beams 270, thus preventing the insulation regions (insulation surfaces) 208, 208-1, 208-2 from becoming electrically charged, thereby preventing a deterioration in the beam quality of the particle beams 270. Furthermore, the structure of the monolithic layer stack structure 200 obtained by the manufacturing method 100 can ensure that the voltage-carrying conductor tracks 220-1, ..., 220-# are also shielded from the particle beams 270.This electrical shielding of the insulation material structures 208, 208-1, 208-2 and the voltage-carrying conductor tracks 220-1, ..., 220-# can be achieved, for example, by a "labyrinthine arrangement" (of etched-back insulation regions) in a vertical step plane and / or by labyrinthine zigzag trenches between the electrodes 215 in a horizontal section plane. These configurations will be explained in more detail below.

[0181] In the following, Fig. 3 further details of the Fig. 2 shown Fig. of the inventive manufacturing method 100. Thus, Fig. 3 an exemplary basic flow diagram with further manufacturing details of the Fig. 2 shown Fig. of the inventive manufacturing method 100 according to a further embodiment. The part shown in Figure 1-1 of Fig. The coordinate system shown in Figure 3 applies to all partial images of Fig. 3.

[0182] In the successive partial images of Fig. 3 shows (for reasons of clarity) the reference symbols of the “newly obtained” elements as well as the reference symbols of some (essential) previously obtained elements. The reference symbols of the remaining elements from the respective preceding partial figures of Fig. 3 apply equally to the corresponding elements in all sub-figures of Fig. 3.

[0183] As shown in sub-figure 1-1 of Fig. As shown in Figure 3, in step 110 of the method 100, a (e.g., monocrystalline) Si substrate 204 provided with a structured oxide layer 202, e.g., a thermal oxide or SiO2-coated layer, is provided. For example, a silicon wafer 204 with the SiO2 layer (e.g., thermal oxide) 202 on its first main surface region 204-A serves as the starting point for the manufacturing method 100.

[0184] As shown in Figure 1-2 of Fig. 3, the Si wafer 204 provided with the SiO2 layer 202 can be provided with a photoresist structure 302 (on the SiO2 layer 202) by means of a lithography process in order to define trenches and / or through openings 306 in the SiO2 layer 202, which are formed in a subsequent etching step by a targeted removal of the areas in the SiO2 layer 202 not covered by the photoresist material.

[0185] As shown in Figure 1-3 of Fig. 3, the photoresist material was removed (stripped), wherein then, according to the manufacturing module 120 or 130, a Si layer structure 210-#, 220-# (e.g., a first Si layer structure 210-1 or 220-1) is epitaxially applied to the process surface, i.e., a poly-Si material (epi-poly) is applied. This epi-poly-Si material can be formed as a Si thick-film structure 210-# or a poly-Si thin-film structure 220-#. Such a grown epi-poly-Si layer is therefore polycrystalline and, due to the respective oxide intermediate layer, has an orientation (crystal orientation) that is independent of the orientation of the silicon substrate 204. Only in the case of any direct anchoring points orIn the anchoring areas of the first grown epi-poly-Si layer to the monocrystalline silicon substrate, the crystal orientation of the first grown epi-poly-Si layer there may depend on that of the monocrystalline silicon substrate. The deposited poly-Si layer can then be subjected to a polishing process, e.g., MP (mechanical polishing) or CMP (chemical mechanical polishing) to achieve the desired surface finish (roughness) and / or layer thickness of the deposited poly-Si layer 210-#, 220-#.

[0186] As shown in sub-figure 1-3 of Fig. 3, in the regions 206 exposed by the SiO2 layer 202, the epitaxially deposited poly-Si layer is connected to the silicon material of the substrate 204. This ensures that in the central region 203 of the present layer arrangement, the sacrificial material regions of the substrate 204 and the deposited poly-Si layer 210-# or 220-# abut one another or are connected to one another, while in the feedthrough 206, an electrical connection is maintained between the deposited poly-Si layer 210-#, 220-# and the semiconductor substrate 204 (i.e., functional material regions).

[0187] As shown in Figure 1-4 of Fig. As shown in Figure 3, a photoresist material 304 is deposited and patterned on the surface of the deposited poly-Si layer structure 210-#, 220-# during a lithography process to define trenches and / or vias 212 in the poly-Si layer structure. During a subsequent etching process, the trenches and / or vias 212 are formed in the poly-Si layer structure 210-#, 220-#, after which the photoresist material 304 is removed.

[0188] As shown in sub-figure 2-1 of Fig. As shown in Figure 3, an insulating material 208, e.g., SiO2, is now applied (grown) to the process surface and thus also introduced into the trenches 212, so that the SiO2 material 208-2 extends into the trenches 212 or fills these trenches 212. Thus, the vertical filling regions 208-2 of the insulating layer structure 208 are formed.

[0189] As shown in sub-figure 2-2 of Fig. 3, the SiO2 material 208 located on the upper main surface region of the poly-Si layer structure is planarized by a CMP process to further obtain the insulating surface layer 208-1 on the poly-Si layer structure.

[0190] As shown in sub-figures 2-2 and 2-3 of Fig. 3 is further optionally shown, the insulating material located on the main surface region of the poly-Si layer structure can also be removed by means of the CMP method, wherein in a subsequent further application step the insulating SiO2 surface layer 208-1 of the SiO2 structure 208 can be applied and then subjected to a surface treatment (e.g. CMP).

[0191] The applied SiO2 layer structure 208, ie in particular the vertical filling regions 208-2 thereof, now divides the poly-Si layer structure 210-#, 220-# into a functional material region 210-A, 220-A and a sacrificial material region 210-B, 220-B. The SiO structure 208 thus forms an electrical separation between adjacent Si material regions.

[0192] Thus, in Figure 2-3 of Fig. 3 a first process cycle (e.g. process module 120 or 130) of the manufacturing method 100 for epitaxially depositing a polysilicon 210-# or 220-# is completed.

[0193] Such an (epi-)poly-Si cycle can thus be summarized as follows: The silicon wafer 204 is provided with the SiO2 layer 202. In a lithography step, a photoresist layer is applied and patterned to provide a photoresist mask. The SiO2 layer 202 is then etched using the photoresist mask, i.e., removed in the areas exposed by the photoresist mask (see partial figures in 1-1 and 1-2).

[0194] A poly-Si layer structure 210-#, 220-# is then deposited, such as an epitaxial deposition for a poly-Si thick film 210-# and a plasma deposition for a poly-Si thin film 220-#.

[0195] The applied poly-Si layer 210-#, 220-# is now polished using a CMP process to obtain a sufficiently smooth surface finish and / or a desired layer thickness (see Figure 1-3).

[0196] Then, trenches and / or through-holes 212 are formed in the poly-Si layer structure by forming defined regions of the poly-Si layer structure through a further photoresist mask using a DRIE process (e.g., cyclic etching and passivation) (see sub-figure 1-4).

[0197] The resist material is then removed, and an SiO2 material is applied to fill the trenches and / or vias 212 in the poly-Si layer structure 210-#, 220-#, i.e., to form the insulating filling regions 208-2 of the SiO2 structure 208. Furthermore, or additionally, a thin SiO2 layer 208-1 is applied to the main surface regions of the poly-Si layer structure 210-#, 220-# by means of plasma deposition. Finally, a CMP process can be performed for surface treatment (see Figures 2-1, 2-2, and 2-3).

[0198] Alternatively, the insulating SiO2 layer 208-1 and the filling regions 208-2 of the SiO2 structure 208 can also be obtained by means of separate SiO2 material deposition processes and a CMP process performed in between. This completes a first poly-Si deposition cycle for a poly-Si layer structure 210-# or 220-#.

[0199] In the following sub-figures 2-4, 2-5, 2-6, 2-7 and 3, another poly-Si deposition cycle (120 or 130) is shown for depositing another poly-Si layer structure 210-# or 220-#.

[0200] As shown in Figure 2-4 of Fig. 3, the poly-Si layer structure 210-1, 220-1 provided with the SiO2 layer 208-1 can be provided with a photoresist structure 304 (on the SiO2 layer 208-1) by means of a lithography process in order to define trenches and / or through openings 306 in the SiO2 layer 208-1, which are formed in a subsequent etching step by a targeted removal of the areas in the SiO2 layer 208-1 not covered by the photoresist material.

[0201] As shown in Figure 2-5 of Fig. 3, the photoresist material 304 is removed (stripped), wherein then, according to the manufacturing module 120 or 130, a further Si layer structure 210-#, 220-# (e.g., a second Si layer structure 210-1 or 220-1) is epitaxially deposited on the process surface, i.e., a poly-Si material (epi-poly) is deposited. This epi-poly-Si material can be formed as a Si thick-film structure 210-# or a poly-Si thin-film structure 220-#. The deposited poly-Si layer can now be subjected to a polishing process, e.g., polishing. B. MP process (MP = mechanical polishing) or a CMP process (CMP = chemical mechanical polishing) in order to obtain the desired surface finish (roughness) and / or the desired layer thickness of the applied poly-Si layer 210-#, 220-#.

[0202] As shown in sub-figure 2-5 of Fig. 3, in the regions exposed by the SiO2 layer 208-1, the epitaxially deposited poly-Si layer is connected to the silicon material of the underlying poly-Si layer 210-#, 220-#. This ensures that, in the central region of the present layer arrangement, the sacrificial material regions of the deposited poly-Si layers 210-# and 220-# abut one another or are connected to one another, while in the feedthrough 206, an electrical connection is maintained between the deposited poly-Si layers 210-# and 220-# (i.e., functional material regions).

[0203] As shown in Figure 2-6 of Fig. As shown in Figure 3, a photoresist material 304 is deposited and patterned on the surface of the (topmost) deposited poly-Si layer structure 210-#, 220-# during a lithography process to define trenches and / or vias 212 or 222 in this poly-Si layer structure. During a subsequent etching process, the trenches and / or vias 212 or 222 are formed in this poly-Si layer structure 210-#, 220-#, after which the photoresist material is removed again.

[0204] As shown in Figure 2-7 of Fig. 3, an insulating material, e.g., SiO2, is now applied (grown) to the (current) process surface, ie, to the uppermost deposited poly-Si layer structure 210-#, 220-#, and thus also introduced into the trenches 212, so that the SiO2 material extends into the trenches 212 or fills these trenches 212. Thus, the vertical filling regions 208-2 of the insulating layer structure 208 (in the uppermost deposited poly-Si layer structure 210-#, 220-#) are formed.

[0205] As shown in Figure 3 of Fig. 3, the SiO2 material 208 located on the upper main surface region of the (topmost) poly-Si layer structure 210-#, 220-# is planarized by means of a CMP process in order to further obtain the insulating surface layer 208-1 on this poly-Si layer structure.

[0206] Furthermore, the insulating material located on the main surface region of the (topmost) poly-Si layer structure can also be removed by means of the CMP method, wherein the insulating SiO2 surface layer 208-1 of the SiO2 structure 208 can be applied in a subsequent further application step and then subjected to a surface treatment (e.g., CMP).

[0207] The applied SiO2 layer structure 208, ie in particular the vertical filling regions 208-2 thereof, now divide the poly-Si layer structure 210-#, 220-# into a functional material region 210-A, 220-A, e.g., with the electrodes 215, and a sacrificial material region 210-B, 220-B. The SiO2 structure 208 thus forms an electrical separation between adjacent Si material regions.

[0208] Thus, in Figure 3 of Fig. 3 a further process cycle (e.g. process module 120 or 130) of the manufacturing method 100 for the epitaxial deposition of a polysilicon 210-# or 220-# is completed.

[0209] Fig. 4 now shows an exemplary embodiment of the manufactured monolithic layer stack structure 200 according to a further embodiment.

[0210] Alternatively to the above Fig. the Fig. 2, in which the illustrated monolithic layer stack structure 200 has, for example, only one through-opening 260, the monolithic layer stack structure 200 can, however, also be designed, for example, as a monolithic multi-aperture plate (monolithic multi-beam micro-optics for a particle-optical system) with a plurality of through-openings 260, as is shown, for example, in Fig. 4 with three through openings 260.

[0211] The Fig. The monolithic layer stack structure 200 shown in Figure 4 can be equally described by the Fig. 1a-b, Fig. 2 and Fig. 3 for the monolithic layer stack structure 200. In this case, a plurality of functional material regions 210-A, 220-A and a plurality of sacrificial material regions 210-B, 220-B are now provided in the individually applied semiconductor layer structures 210-#, 220-# by the respectively applied SiO2 layer structure 208 in order to obtain the plurality of through openings 270 during the etching process 150 (etching into the layer stack arrangement). In the etching step 150, the semiconductor substrate 200, which has been opened at the back (in step 145), is etched (e.g. isotropically) into the layer stack arrangement in order to remove the sacrificial material regions 210-B, 220-B of the different semiconductor thick-film structures 210-# and semiconductor thin-film structures 220-#, respectively, wherein the applied insulation layer structures 208, e.g.the trenches and / or vias 212 filled with the insulating material 208-2 form a lateral (vertically extending) etch stop layer structure.

[0212] The Fig. The electrodes 215 shown as examples in Figure 4 can be designed as multi-pole or ring electrodes. The applied conductive semiconductor thin-film structures 220-# can be designed as conductive traces or as wiring connections. As shown in Fig. 4, the applied semiconductor thick-film structures 210-1, 210-3, 210-5, which have no electrode structure adjacent to the through-openings 260, can be formed as conductive base layers (semiconductor thick-film structures). Fig. 4 can be introduced into the (conductive) base layers 210-2, 210-4 (semiconductor thick-film structures) and can generally be arranged electrically separated from the further conductive material of the associated base layer (semiconductor thick-film structure) 210-2, 210-4.

[0213] Fig. 4 thus shows a simplified example of the monolithic multi-aperture plate 200 in cross-section. The monolithic multi-aperture plate 200 is predominantly formed, i.e., more than 50%, more than 70%, or even more than 80%, from a conductive material, for example, doped silicon. In this conductive material, individual conductive structures, such as regions of the semiconductor thick-film structures 210-# (e.g., electrodes 215) and regions of the semiconductor thin-film structures 220-# (e.g., conductor tracks), are surrounded by an insulating material 208, e.g., SiO2, and are thus electrically separated from one another. Individual conductive structures are completely surrounded by insulating material or a surface area of at least one inner wall of an aperture 260. As a result, individual conductive structures that are electrically insulated are formed in the conductive material 208, for example, the structures consisting of electrodes 215 and electrical connection channels orLines 210-#, 220-#.

[0214] A plurality of electrical connection channels connects each electrode 215 to an associated connection contact 230-1, which are provided, for example, in the first functional layer 230 on the top side of the monolithic multi-aperture plate 200, for example, for electrical connection to the control unit. Voltage differences can be applied between the different electrodes (in different planes) at the same aperture opening 260 to achieve beam deflection or stigmatization of individual beams 270 or, for example, a focusing effect of individual beams 270.

[0215] The diameters of the apertures 260 can vary in the individual functional layers. The diameter D1 in the uppermost functional layer (shielding layer) 230 is smaller than the diameter D2 in an active functional layer 210-2, 210-4 (with electrodes 215). In contrast, the diameter D3 in a passive functional layer 210-1, 210-3 (without electrodes) is designed to be larger than the diameter D2. This prevents electrons from the individual electron beams 270 from touching the inner aperture walls of the apertures 270 below the first functional layer 230.

[0216] The monolithic layer stack structure 200 can thus be used, for example, as a monolithic multi-beam micro-optics system for a particle-optical system. Due to the functionality of the micro-optics 200 as a monolithic multi-aperture plate, several individual beams can be generated from a wide incident particle beam, for example, whereby beam shaping (stigmization, focusing, lateral deflection) can also be achieved for the individual beams (using the lateral electrodes 215).

[0217] In the manufacturing method 100, a microchip with the membrane 200 (= the monolithic layer stack structure) or a thin microchip can be obtained over the entire surface. The basic structure of the membrane 200 now comprises a monolithic (= gap-free) stack of conductive layers 210-1, ..., 210-#, and 220-1, ..., 220-# alternating with insulating layers 208, 208-1, 208-2, wherein the uppermost layer 230, e.g., acts as a cover or diaphragm layer, absorbing particles (electrically charged particles) and / or X-rays.

[0218] Particle beams, for example, can pass through the through aperture(s) 260 in the microchip 200. In the layer stack structure 200, insulating structures 208, 208-1, 208-2, which are formed, for example, as lines, trenches, surface areas, etc., are embedded in the conductive layers 210-#, 220-#, wherein the conductive layers 210-#, 220-# are in turn provided for forming electrodes 215, e.g., ring or octopole electrodes, and conductor tracks. Furthermore, local electrical connections 206 are provided between the conductive layers 210-# and / or 220-#, which are provided as so-called vias (conductive feedthroughs) through the insulating layers 208.

[0219] Since the opening (aperture) in the metallic cover layer 230 has a smaller diameter, e.g., a diameter at least half smaller than the subsequent structures in the through-opening 260, direct lines of sight between insulating surfaces and individual beams (of the incident particle beams) 270 as well as between voltage-carrying conductor tracks 210-#, 220-# and individual beams (of the incident particle radiation) can be avoided.

[0220] In Fig. 4 is again to Fig. from Fig. 2 illustrates the optional dielectric covering layer (surface passivation) 234 of the monolithic layer stack structure 200. According to one embodiment, the dielectric covering layer 234 may be removed from main surface areas of the monolithic layer stack structure 200 that are adjacent to the aperture openings 230-4 and between the aperture openings 230-4. For further details on the resulting monolithic layer arrangement 200, reference is further made to the figures of Fig. 2 and the corresponding description.

[0221] Fig. 5a-d now show exemplary embodiments of further details of the manufactured monolithic layer stack structure 200 according to further embodiments.

[0222] The Fig. 5a-d further details or structures of the manufactured monolithic layer stack structure 200 can be equally based on the Fig. 1a-b, Fig. 2 and Fig. 3 for the monolithic layer stack structure 200. In this case, the functional material regions 210-A, 220-A and the sacrificial material regions 210-B, 220-B are now provided in the individual applied semiconductor layer structures 210-1, ..., 210-#, 220-1, ..., 220-# by the respectively applied insulation layer structure (SiO2 layer structure) 208 in order to form the Fig. 5a-d to obtain further structures of the manufactured monolithic layer stack structure 200.

[0223] In the etching step 150, etching is performed through the semiconductor substrate 200, which is opened at the back (in step 145) (e.g., isotropic) into the layer stack arrangement in order to remove the sacrificial material regions 210-B, 220-B of the different semiconductor thick-film structures 210-1, ..., 210-# or semiconductor thin-film structures 220-1, ..., 220-#, respectively, wherein the applied insulation layer structures 208, e.g., the trenches and / or through openings 212 filled with the insulation material 208-2, form a lateral (vertically extending) etch stop layer structure.

[0224] In the manufacturing step 150 described above, for example, the layer stack arrangement 204 can be etched isotropically (e.g., by means of DRIE processes) through the monocrystalline silicon substrate 204 opened at the rear in step 145 in order to remove the sacrificial material regions 210-B, 220-B of the poly-Si thick-film structures 210-# and the poly-Si thin-film structures 220-#, wherein the applied oxide layer structures 208 (208-1, 208-2) form a lateral (side) etch stop layer structure.

[0225] In the subsequent step 155, the etch stop layer structure can now be removed in regions, that is to say, for example, an insulating material etching back can be carried out in order to expose surface regions of the functional material regions 210-A, 220-A adjacent to the etch stop layer structure in order to obtain the monolithic layer stack structure 220.

[0226] In step 155 of removing the etch stop layer structure in regions, an oxide etching back can be carried out, for example, in order to expose the surface regions of the functional material regions of the poly-Si thick-film structures and poly-Si thin-film structures adjacent to the etch stop layer structure in order to obtain the monolithic layer stack structure 200 with the further structures, as shown in the Fig. 5a-d.

[0227] As now exemplified in Fig. 5a, the insulation material etching back (oxide etching back in step 155) may be performed such that a "pin" 510 is obtained between two opposing semiconductor thin-film structures 220-1, 220-2, which does not comprise any insulation material or semiconductor material. As shown in Fig. 5a, the semiconductor thin-film structures 220-1, 220-2 can serve as leads for the deflection electrode 215.

[0228] As shown in the partial section of the monolithic layer stack arrangement 200 of Fig. 5a, the semiconductor thin-film structures 220-1, 220-2 (leads) are arranged between two semiconductor thick-film structures 210-1, 210-2 (plate 1, plate 2). As shown in Fig. 5a, the lateral length L of the pin 510 is designed to be greater than the vertical height h of the pin 510 (L / h > 1) so that the direct line of sight between the isolation structures 208 and the incident particle beam 270 can be avoided.

[0229] As now exemplified in Fig. 5b, the insulation material 208 can further be removed during the etch-back process (step 155) such that, in addition to the lateral material removal, a vertical section of the insulation material structure 208 is also removed in order to obtain a so-called "labyrinth structure" (L-shape) of the removed insulation material 208. Here, too, the lateral extent (length) L of the removed insulation material is, for example, greater than the height h of the removed insulation material (= L / h > 1).

[0230] The electrode arrangement 215 of the monolithic multi-aperture plate 200 can, for example, be designed as a ring-shaped (single) electrode to form a single lens. As shown in Fig. 5c-d, the electrode arrangement 215 can also be designed as a multipole electrode, with a plurality of electrode elements 215-1, ..., 215-#, wherein in Fig. 5c, for example, eight partial electrodes 215-1, ..., 215-8 are shown, which are surrounded by the insulating structure 208. The Fig. 5c-d now show an embodiment of an electrode arrangement 215 with eight embedded partial electrodes 215-1, ..., 215-8 around the aperture (through-opening) 260. Between each two separate, embedded partial electrodes 215-#, there is a free space (an exposed surface) 520 in which the material of the insulation structure 208 has been removed. In order to prevent, for example, scattered electrons of the electron beam 270 from reaching the exposed surface of the insulation structure 208, the spaces 520 between the partial electrodes 215-# are formed as a labyrinth-shaped gap (vacuum gap) 520, e.g., in an L- or double-L shape. A (thin) metal layer or metallization 530 may also be present on the inner sides of the partial electrode elements 215-# that border the through-opening 260.

[0231] The thin sidewall metallization 530 can contribute to making the electrode structure 215 less sensitive to charging effects due to incident charged particles of the particle beam 270. The thin sidewall metallization 530 of the electrode structure 215 can be produced, for example, using a sputtering process.

[0232] By forming the "labyrinth structure" 520, 530 and by forming the deflection electrodes from doped polysilicon material with coverage of the insulation structure 208, a direct line of sight from the electrode beam to the lower regions of the insulation structure 208 can be avoided. When the length-to-height ratio of the labyrinth (pin) 510 is applied with L / h > 1, electrical voltages inside the leads do not influence the electron beam 270 within the aperture opening 260.

[0233] This minimizes scattering effects, as the labyrinth structure 510, 520 shields the electrode beam from electrical charges on the insulator surface 208 and also intercepts stray electrodes, thus reducing electrical charges on the insulator surface (insulator structure 208). This reduces electron-induced deposits on the insulator structure, which also prevents or reduces leakage currents.

[0234] Although some aspects of the present disclosure have been described as features in the context of an apparatus, it is to be understood that such a description may also be considered a description of corresponding method features. Although some aspects have been described as features in the context of a method, it is to be understood that such a description may also be considered a description of corresponding features of an apparatus or the functionality of an apparatus. Some or all of the method steps may be performed by (or using) a hardware apparatus, such as a microprocessor, a programmable computer, or electronic circuitry. In some embodiments, some or more of the method steps may be performed by such an apparatus.Depending on particular implementation requirements, embodiments of the invention may be implemented in hardware or in software, or at least partially in hardware or at least partially in software.

[0235] In the foregoing Detailed Description, various features have been grouped together in examples in order to streamline the disclosure. This manner of disclosure should not be interpreted as intending that the claimed examples include more features than are expressly recited in each claim. Rather, as the following claims reflect, the subject matter may lie in fewer than all of the features of a single disclosed example. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim being capable of standing as its own separate example.While each claim may stand as its own separate example, it should be noted that although dependent claims in the claims refer to a specific combination with one or more other claims, other examples also include a combination of dependent claims with the subject matter of any other dependent claim or a combination of any feature with other dependent or independent claims. Such combinations are intended to be encompassed unless it is stated that a specific combination is not intended. Furthermore, it is intended to encompass a combination of features of a claim with any other independent claim, even if that claim is not directly dependent on the independent claim.

[0236] Although specific embodiments have been illustrated and described herein, it will be apparent to one skilled in the art that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and illustrated therein without departing from the scope of the present application. This application text is intended to cover all adaptations and variations of the specific embodiments described and discussed herein. Therefore, the present application subject matter is limited only by the language of the claims and equivalent embodiments thereof. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] Oxide layer structure 208 (208-1, 208-2

[0121]

Claims

[1] Method (100) for producing a monolithic layer stack structure (200), comprising the following steps: Providing (110) a semiconductor substrate (204) provided with a structured insulation layer (202), Executing (120, 130) a first or second manufacturing module, wherein the execution (120) of the first manufacturing module comprises the following steps: structured application (120-1) of a semiconductor thick-film structure (210-#), wherein trenches and / or through-openings (212) are arranged in the semiconductor thick-film structure (210-#), and structured application (120-2) of an insulation layer structure (208) onto the semiconductor thick-film structure (210-#) for filling the trenches and / or through-openings (212) in the semiconductor thick-film structure (210-#) and for providing an insulating surface layer (208-1) on the semiconductor thick-film structure (210-#), wherein the semiconductor thick-film structure (210-#) is further structured such that the applied insulating layer structure (208) divides the semiconductor thick-film structure (210-#) into a functional material region (210-A) and a sacrificial material region (210-B), wherein the execution (130) of a second manufacturing module comprises the following steps: structured application (130-1) of a highly doped semiconductor thin-film structure (220-#), wherein trenches and / or through-openings (222) are arranged in the highly doped semiconductor thin-film structure (220-#), and structured application (130-2) of a further insulation layer structure (208) onto the highly doped semiconductor thin-film structure (220-#) for filling the trenches and / or through-openings (222) in the highly doped semiconductor thin-film structure (220-#) and for providing an insulating surface layer (208-1) on the highly doped semiconductor thin-film structure (220-#), wherein the highly doped semiconductor thin-film structure (220-#) is further structured such that the applied further insulation layer structure (208) divides the semiconductor thin-film structure (220-#) into a functional material region (220-A) and a sacrificial material region (220-B), Repeating (135) the execution of the first and / or second manufacturing module (120, 130) to obtain a layer stack arrangement (201), wherein the sacrificial material regions (210-B, 220-B) define a through-opening through the layer stack arrangement (201), structured application (140) of an etching mask structure (250) to the exposed, rear main surface area (204-B) of the semiconductor substrate (204), back-side etching (145) through the semiconductor substrate (204), Etching (150) into the layer stack arrangement (201) to remove the sacrificial material regions and to create the through-opening (260) through the layer stack arrangement (201), wherein the applied insulation layer structures (208, 208-1, 208-2) form an etch stop layer structure, and removing (155) the etch stop layer structure in regions to expose surface regions of the functional material regions (210-A, 220-A) adjacent to the etch stop layer structure in order to obtain the monolithic layer stack structure (200). [2] The method (100) of claim 1, further comprising the step of: structured application of a semiconductor thick-film structure (210-1) to the semiconductor substrate (204) provided with the structured insulation layer (202), wherein trenches and / or through-openings (212) are arranged in the semiconductor thick-film structure (210-1), and Applying an insulation layer structure (208) to the semiconductor thick-film structure (210-1) for filling the trenches and / or through-openings (212) in the semiconductor thick-film structure (210-1) and for providing an insulating surface layer (208) on the semiconductor thick-film structure (210-1) in order to further structure the semiconductor thick-film structure (210-1) such that the applied insulation layer structure (208) divides the semiconductor thick-film structure (210-1) into a functional material region (210-A) and a sacrificial material region (210-B). [3] Method (100) according to one of the preceding claims, further comprising the following step: Applying (165) a conformal polymer-based protective coating (240) to the layer stack arrangement (201). [4] Method (100) according to one of the preceding claims, further comprising the following step: Applying (160) a metallic, structured cover layer (250) in contact with the uppermost semiconductor thin-film structure (220-#). [5] Method (100) according to claim 4, wherein in the step (160) of applying the metallic, structured cover layer (230), the metallic, structured cover layer (230) is applied as a layer sequence with a base layer (231) and a metal layer (232) arranged thereon. [6] The method (100) of claim 5, further comprising the step of: Structuring (161) the base layer (231) and structuring (162) the metal layer (232) to form contact areas (230-1) for contacting the semiconductor thin-film structures (220-#) (semiconductor conductor tracks). [7] The method (100) of claim 6, wherein in the structuring step (161), circumferential trench structures (230-3) are formed around the contact regions (230-1) through the covering layer (230). [8] Method (100) according to one of claims 5 to 7, wherein in the step (160) of applying the layer sequence comprising the base layer (231) and the metal layer (232), a tungsten titanium material is applied for the base layer and a gold material is applied for the metal layer. [9] Method (100) according to one of claims 6 to 8, further comprising the following step: Applying (163) a dielectric covering layer (234) at least in regions to the layer stack arrangement (201) and structuring (164) the applied dielectric covering layer (234), wherein during the structuring (164) of the dielectric covering layer (234) the contact regions (230-1) are exposed such that circumferential edge surface regions of the contact regions (230-1) remain covered with a width of at least 1 µm. [10] Method (100) according to claim 9, wherein further regions (230-2, 230-3) on the layer stack arrangement (201) adjacent to the contact regions (230-1) are covered at least in regions with the dielectric covering layer (234). [11] Method (100) according to claim 9 or 10, wherein the dielectric covering layer (234) is applied conformally to the layer stack arrangement (201) by means of an ALD process (ALD = atomic layer deposition). [12] Method (100) according to one of the preceding claims, wherein the region-wise removal (155) of the etch stop layer structure comprises a sidewall etching of the insulation layer structure (208-2) and an undercutting into the insulation layer structure (208-1). [13] Method (100) according to one of claims 3 to 12, further comprising the following step: Removing (155-1) the conformal polymer-based protective coating (240) from the layer stack assembly (201). [14] Method (100) according to one of the preceding claims, further comprising the following step: Removing (155-2) the etching mask structure (250) from the semiconductor substrate (204). [15] Method (100) according to one of the preceding claims, wherein the structured application (120-1; 130-1) of a semiconductor thick-film structure (210-#) and a semiconductor thin-film structure (220-#) comprises a deposition process, a lithography process and an etching process. [16] Method (100) according to one of the preceding claims, wherein trenches and / or through-openings (206) are provided during the structured application of the insulation layer structure (208) in order to obtain vertical electrical connections or vias between adjacent semiconductor levels in the subsequent step of the structured application (120-1) of a semiconductor thick-film structure (210-#) or the structured application (120-1) of a semiconductor thin-film structure (220-#). [17] Method (100) according to one of the preceding claims, wherein the execution (120) of the first manufacturing module is carried out several times or several times in succession. [18] Method (100) according to one of the preceding claims, wherein the execution (130) of the second manufacturing module is carried out several times or several times in succession. [19] Method (100) according to one of the preceding claims, wherein a successive execution (120, 130) of the first and second manufacturing modules is carried out several times. [20] Method according to one of the preceding claims, further comprising the following step: Performing a CMP treatment of the deposited semiconductor thick film structures (210-#) and / or semiconductor thin film structures (220-#). [21] Method according to one of the preceding claims, wherein the monolithic layer stack structure (200) is formed as a stigmator or a monolithic multi-aperture plate, wherein the sacrificial material regions (210-B, 220-B) define the through-opening (260) through the layer stack structure (200). [22] A method according to any one of the preceding claims, wherein: wherein the monolithic layer stack structure (200) is formed as an inertial sensor, wherein the sacrificial material regions (210-B, 220-B) define the cavity (260) with a movable element in the layer stack structure (200). [23] Method according to one of the preceding claims, further comprising the following step: Separating the monolithic layer arrangement (200) into individual functional elements or chips (200').

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