LINEAR AND PROBABILISTIC LOGARITHMIC COUNTER

Abstract

One aspect provides a dual-scale counter circuit that includes a counter logic unit for storing the current counter value, a range determination logic unit for determining the operating range of the dual-scale counter circuit based on the current counter value and a predetermined threshold, and a counter increment logic unit. The counter increment logic unit is used to linearly increment the current counter value for an increment event in response to the dual-scale counter circuit operating in a linear range, and to probabilistically increment the current counter value for the increment event in response to the dual-scale counter circuit operating in a probabilistic range.The dual-scale counter circuit also includes a linear feedback shift register for generating a random binary bit sequence, on the basis of which the counter increment logic unit is to determine whether the current counter value should be increased for the increment event when the dual-scale counter circuit is operating in the probabilistic range.

Description

STATEMENT ON GOVERNMENT FUNDING

[0001] This invention was made with government support under contract number H98230-23-C-0350, awarded by the Maryland Procurement Office. The government holds certain rights to this invention. BACKGROUND area

[0002] This revelation refers generally to the construction of counters. More specifically, this revelation refers to the construction of a two-scale counter that counts small numbers accurately and large numbers approximately. BRIEF DESCRIPTION OF THE FIGURES Fig. Figure 1 shows the increment probability of different count ranges according to one aspect of the present application. Fig. Figure 2 shows an example of the count ranges according to one aspect of the present application. Fig. Figure 3 shows the block diagram of an exemplary two-scale counter according to one aspect of the present application. Fig. Figure 4 shows a flowchart illustrating an example procedure for incrementing a two-scale counter according to one aspect of the present application. Fig. Figure 5 shows a computer system that facilitates the operation of a two-scale counter according to one aspect of the present application. Fig. Figure 6 shows a computer-readable medium that facilitates the operation of a two-scale counter, according to one aspect of the present application.

[0003] In the illustrations, identical numbers refer to the same elements of the illustration. DETAILED DESCRIPTION

[0004] Aspects of the present application offer a solution to the problem of reducing the chip area occupied by counters. More precisely, a dual-scale counter is described that has a much smaller footprint than linear counters. The dual-scale counter can count small numbers accurately (e.g., linearly incrementing) and count large numbers approximately (e.g., probabilistically incrementing).

[0005] The area of ​​a silicon chip is often a problem in the development of computer systems, as a larger chip area increases the overall system cost because fewer chips can be built on a single silicon wafer. Furthermore, a larger chip area can lead to a lower yield, since the larger area contains more transistors, thus increasing the probability of a defective transistor. Chip designers often have a strong incentive to reduce the chip area occupied by individual components in order to lower component costs.

[0006] Counter circuits are essential components in network devices. For example, an application-specific standard integrated circuit (ASIC) for a switch might contain multiple counters for debugging and network telemetry purposes. When a network device is operational, the counters can collect data on network traffic, bandwidth utilization, latency, packet loss, and other performance metrics. This telemetry data can be used to detect network congestion and is invaluable to network administrators and architects. However, counter circuits are very area-intensive, especially when counting large numbers of data. Reducing the chip area occupied by the counter circuits can lower the overall cost of the network device.

[0007] Counters that use an approximate counting algorithm typically require less space on the chip (e.g., by reducing the number of bits needed to record the count value). However, approximate counting is only suitable for large count values ​​and can lead to unacceptable inaccuracies when counting small numbers. Some counter applications (e.g., telemetry data acquisition) require accurate counts at low count values ​​but can tolerate less accurate counters at high count values. At high count values ​​(e.g., counting the number of packets arriving at a port), it is sufficient to track the magnitude of the values. To take advantage of the relaxed accuracy requirements at large count values ​​without sacrificing accuracy at small count values, aspects of this revelation provide a dual-scale counter that can count small numbers accurately and large numbers approximately.

[0008] Depending on certain aspects, counter values ​​can be divided into a linear range and a probabilistic range. If the counter values ​​are below a predetermined threshold, the counter can be configured to count linearly (i.e., the change in the counter value is directly proportional to the number of counted events). In other words, the probability of the counter value increasing is one for each occurrence of the event. The occurrence of the event being counted can also be called an increment event. In the example of counting packets arriving at a port, the counter value can increase by a fixed number (e.g., one or two) for each packet.

[0009] If the occurrence of the event is above the predetermined threshold (i.e., in the probabilistic range), the counter can be configured to count approximately, meaning that an occurrence of the event does not increment the counter value. In some examples, the probability of the counter value increasing on a logarithmic scale (e.g., a logarithmic scale to base 2) can decrease linearly. Based on other considerations, the probability range based on the counter values ​​can be divided into a plurality of sub-ranges (e.g., n sub-ranges), with each sub-range corresponding to a specific increment probability. The larger the counter value, the lower the increment probability (i.e., the less likely it is that an increment event will result in an increment of the counter value). In some examples, the increment probability in the i tenSub-area of ​​the probabilistic area 2 (-i) The increment probability can be calculated as follows: i is a positive integer representing the index of the subrange. In alternative examples, the increment probability in i can be... -ten Sub-area 10 -i be.

[0010] Fig. Figure 1 shows the increment probability of different count ranges according to one aspect of the present application. The horizontal axis represents the count value, starting at zero. The count values ​​can be divided into a linear range and a probabilistic range. Low count values ​​belong to the linear range. As the count increases, it can exceed the linear range and enter the probabilistic range, which in turn can be divided into several subranges. For example, when the count value leaves the linear range, it can fall into the first probabilistic subrange, the second probabilistic subrange, and so on. The vertical axis represents the increment probability in each range / subrange. More precisely, the vertical axis is drawn on a logarithmic scale to base 2. As shown in Figure 1, the increment probability is calculated using the logarithmic scale to base 2. Fig. As represented by 1, the increment probability in the linear domain is 1, meaning that the counter increments by a fixed value each time an increment event is detected. On the other hand, the increment probability in the probabilistic domain is less than 1, i.e., there is a non-zero probability that the counter will not increment when an increment event is detected. The increment probability varies for the different subdomains. In the Fig. In the example shown, the increment probability in the first probabilistic sub-area is 2 (-1) (or 1 / 2); in the second probabilistic subdomain, the increment probability is 2 (-2) ( or 1 / 4) etc. In this example, the increment probability decreases exponentially depending on the subrange index i (i.e., the increment probability is 2 -ifor the i ten (Sub-area).

[0011] According to some aspects, the count value ranges can be assigned arbitrarily. Fig. Figure 2 shows an example of the count ranges according to one aspect of the present application. In the Fig. In the example shown, Table 200 contains four columns. The first column corresponds to the name of each count range or subrange (e.g., linear range, probabilistic subrange 1, probabilistic subrange 2, etc.). The second column contains the actual or estimated count values ​​within each range or subrange. The third column corresponds to the increment probability in each range or subrange. For example, the increment probability in linear range 1 is [missing value], and the increment probability in probabilistic subrange 2 is [missing value]. ten probabilistic sub-area 2 -iThe fourth column corresponds to the count value in each range or subrange. Note that the count values ​​are the number of counted increment events (in decimal representation), while the counter values ​​represent the readings of the two-scale counter (in hexadecimal representation). In the linear domain, there is a one-to-one mapping between the count values ​​and counter values. However, in the probabilistic domain, each counter value can represent multiple count values ​​because the increment probability is less than one.

[0012] In this example, a 16-bit counter can increment linearly (e.g., the counter can advance by one on each increment event) until it reaches a predetermined threshold (e.g., 0x7FFF, or nearly half its maximum value). The remaining half of the counter values ​​(e.g., from 0x8000 to 0xFFFF) can be divided into 32 probabilistic subranges, with the increment probability for each subrange being defined as 2 -i, i = 1, 2, ..., 32. is configured. As soon as the counter moves from the linear range into the probabilistic subrange 1 (e.g., past 0x7FFF), the increment probability drops to 1 / 2, meaning that the probability of the counter advancing on each increment event is 50%. When the counter moves from one probabilistic subrange to the next, the increment probability is halved. The lower increment probability means lower counting accuracy. As mentioned earlier, such inaccuracies are acceptable for large count values.

[0013] Table 2 also shows that the two-scale counter uses a small number of bits (e.g., 16 bits) for counting very large numbers (e.g., up to 8.79 × 10⁻⁶). 12). In contrast, a linear counter would require 48 bits to count such large numbers. Reducing the number of bits in a counter can reduce the chip area. A typical counter circuit can contain several cascaded flip-flop circuits, with each flip-flop storing one bit. If the number of counter bits is reduced by two-thirds (e.g., from 48 to 16), the counter's footprint can be reduced by two-thirds. Implementing dual-scale counters in network devices therefore reduces component costs.

[0014] Various mechanisms can be used to determine the operating range (e.g., linear or probabilistic range) of a dual-scale counter during the counting process. Depending on some aspects, a table lookup mechanism can be used to determine the counter's current operating range. In one example, the system can perform a table lookup using the information provided in Fig. The system performs the following steps, as shown in Table 200. More precisely, the system can read the current counter value and compare it to the counter value ranges / subranges shown in the fourth column of Table 200. Once the counter value range / subrange is determined, the system can determine the corresponding increment probability in the third column of Table 200. For example, if the current counter value is 0x8811, the system can determine that the counter is operating in probabilistic subrange 3, and the corresponding increment probability should be 2 -3 = 1 / 8. In another example, the instantaneous counter value is 0x95AF, the system can determine that the counter is operating in the probabilistic subrange 6, and the corresponding increment probability should be 2 -6 = 1 / 64.

[0015] According to some aspects, if the system operates in a probabilistic subset with a predetermined increment probability, it can determine whether the counter should be incremented based on the output of a random number generator. According to other aspects, the random number generator can be implemented using a linear feedback shift register (LFSR), which can output a random binary bit sequence with a plurality of bits. Depending on the increment probability, a subset of bits from the LFSR output is evaluated. More precisely, with an increment probability of 2, -iA total of i bits of the LFSR output are evaluated. In probabilistic subset 1, with an increment probability of 1 / 2, for example, only one bit (e.g., bit 0) of the LFSR output is evaluated to determine whether the counter value should be incremented. When an increment event is detected (e.g., an incoming packet that meets a predetermined criterion), the system can determine whether bit 0 of the LFSR output is 1. If so, the counter is incremented; otherwise, the counter is not incremented (i.e., the counter value remains unchanged). Similarly, in probabilistic subset 2, with an increment probability of 1 / 4, two bits (e.g., bit 0 and bit 1) would be evaluated. On each increment event, the counter is incremented if both bits are 1.

[0016] Other types of random number generators can also be used. For example, the system can use a software-based random number generator to control the counter increment. If the increment probability is 32, for instance, the random number generator can randomly generate a number between 0 and 31, and the counter will be incremented on an increment event if the randomly generated number matches a target number (e.g., 0).

[0017] Fig. Figure 3 shows the block diagram of an exemplary two-scale counter according to one aspect of the present application. Fig. A dual-scale counter 300 can comprise a counter logic unit 302, an event detection logic unit 304, a range determination logic unit 306, a counter increment logic unit 308, a random number generation logic unit 310, and a counter value output unit 312. Depending on the configuration, the dual-scale counter 300 can be part of a network device and used to collect specific types of network telemetry data. The various units of the dual-scale counter 300 can be implemented using software components, hardware components, or a combination of both.

[0018] The counter logic unit 302 can be used to count the number of events (e.g., the number of packets arriving at a port). The counter logic unit 302 can be implemented using various techniques (e.g., as a synchronous or asynchronous counter) and can incorporate various digital logic units (e.g., flip-flops). The scope of this disclosure is not limited by the actual implementation of the counter logic unit 302.

[0019] The event detection logic 304 is responsible for detecting incremental events. In situations where the dual-scale counter 300 is used for network telemetry, the event detection logic unit 304 can detect an incremental event by comparing it to one or more header fields of an incoming packet, including but not limited to source and destination IP (Internet Protocol) addresses, source and destination MAC (Media Access Control) addresses, source and destination port numbers (e.g., Transmission Control Protocol (TCP) and / or Universal Datagram Protocol (UDP) port numbers), Virtual Local Area Network (VLAN) tags, Virtual Network Identifiers (VNIs), flow labels, Differentiated Services Code Point (DSCP) values, etc. In addition to network events (i.e.,In addition to sending and receiving packets, the event detection logic unit 304 can be used, depending on the use case, to detect other types of events that can trigger the increment of the counter logic unit 302. The scope of this disclosure is not limited by the type of event detected by the event detection logic unit 304. Furthermore, although depicted as part of the dual-scale counter 304, in some examples the event detection logic unit 304 can be part of the packet processing pipeline outside of the dual-scale counter 304.

[0020] The range determination logic unit 306 is responsible for determining the operating range of the dual-scale counter 300. Depending on certain aspects, the range determination logic unit 306 can receive the current counter value from the counter logic unit 302 and determine the operating range accordingly. For example, the range determination logic unit 306 can determine that the operating range of the dual-scale counter 300 is the linear range if the current counter value is less than a predetermined threshold. The range determination logic unit 306 can further determine that the operating range is the probabilistic range if the current counter value is equal to or greater than the predetermined threshold.According to further aspects, the probabilistic range can be divided into a plurality of subranges, and the range determination logic unit 306 can perform a table lookup to determine a specific probabilistic subrange based on the current counter value. The lookup table can be accessed in . Fig. The table shown in Table 200 should be similar to the table shown in Table 2.

[0021] The counter increment logic unit 308 is responsible for controlling the counter increment of the counter logic unit 302. In some cases, the counter increment logic unit 308 can receive a signal from the event detection logic unit 304 indicating that an increment event has been detected. The counter increment logic unit 308 can also receive the output signal from the range determination logic unit 306, which indicates the operating range of the dual-scale counter 300. When the dual-scale counter 300 is operating in its linear range, the counter increment logic unit 308 can send a trigger signal to the counter logic unit 302, causing it to increment its value. In some cases, the counter increment logic unit 308 can increment the value of the counter logic unit 302 by one with each increment event.In alternative examples, the counter increment logic unit 308 can increase the value of the counter logic unit 302 by other positive values ​​(e.g., two or three) at each increment event.

[0022] When the dual-scale counter 300 operates in the probabilistic range, the counter increment logic unit 308 can receive a random number generated by the random number generation logic unit 310 and, based on this random number, determine whether to send the trigger signal to the counter logic unit 302. Depending on the specific probabilistic range in which the dual-scale counter 300 operates, a subset of the bits from the LFSR output is evaluated. More precisely, a total of i bits from the LFSR output are evaluated when the current counter value approaches i. tenbelongs to the probabilistic sub-area. In one example, if all evaluated bits are "1", the counter increment logic unit 308 can send the trigger signal to the counter increment logic unit 302 for an increment event. In another example, if all evaluated bits are "0", the counter increment logic unit 308 can send the trigger signal to the counter increment logic unit 302 for an increment event. According to alternative aspects, the logic unit 310 for generating random numbers can contain software components configured to generate a random number with a predetermined probability (e.g., 2). -i ). The counter increment logic unit 308 can send the trigger signal to the counter increment logic unit 302 for an increment event when the output of the random number generation logic unit 310 matches a predetermined number (e.g. 0).

[0023] The counter output unit 312 is responsible for outputting the actual counter value of the increment events detected by the event detection logic unit 304 based on the counter value of the counter logic unit 302. More precisely, the counter output unit 312 can map the counter value to an actual or estimated counter value. As mentioned earlier, there is a one-to-one mapping between the counter value and the actual counter value when the dual-scale counter 300 operates in the linear range. However, when the dual-scale counter 300 operates in the probabilistic range, any counter value can be mapped to a plurality of actual counter values ​​due to the uncertainty of the probabilistic counter. In such a case, the counter output unit 312 can estimate the actual counter value based on the counter value.

[0024] According to some aspects, the counter output unit 312 can have a lookup table (e.g., the one in Fig. 2 shown in Table 200) to estimate the actual count value. For example, the count output unit 312 can determine the probabilistic subrange corresponding to the count value. Based on the determined subrange, the count output unit 312 can determine the lower bound of the subrange's count value, the lower bound of the subrange's count value (also called the counter offset value), and the subrange's increment probability. The count output unit 312 can then estimate the actual count value by calculating the difference between the current count value and the subrange's lower bound, multiplying the difference by the inverse of the increment probability (which gives an estimated number of increment events counted within the probabilistic subrange), and then taking the result of the multiplication to obtain the counter offset value (i.e.,the lower limit of the actual count value) added.

[0025] For example, if the counter logic unit 302 outputs a counter value of 0x9009, which falls within probabilistic subrange 5, the counter output unit 312 can determine, based on Table 200, that for probabilistic subrange 5 the lower limit of the counter value is 0x9000, the counter offset value is 63488, and the increment probability is 1 / 32. Accordingly, the counter output unit 312 can calculate the difference between the current counter value and the lower limit of probabilistic subrange 5 to obtain a number 9, which is the number of increments made by the dual-scale counter 300 while operating within probabilistic subrange 5. The count output unit 312 can then multiply the number of increments (i.e., 9) by the inverse of the increment probability (i.e., 1 / 32), which gives the estimated number of counted events (i.e.,288) results when the two-scale counter operates in probabilistic subrange 5. Finally, the count output unit can add 312 288 to 63488 (i.e., the lower bound of the actual count value of probabilistic subrange 5) and output the result (i.e., 63776) as an estimate of the actual count value.

[0026] As mentioned previously, the dual-scale counter 300 has a much smaller footprint compared to a linear counter capable of outputting counts in similar ranges, because the counter logic unit 302 contains significantly fewer flip-flop circuits. The only additional complexity in the dual-scale counter 300 is the logic unit 310 for generating random numbers, which is much smaller compared to the additional flip-flop circuits required by the linear counter.

[0027] Fig. Figure 4 shows a flowchart illustrating an example procedure for incrementing a two-scale counter according to one aspect of the present application. Although in Fig. Although a specific sequence of operations is depicted, the procedures are not restricted to this sequence. For example, the operations shown sequentially in the flowcharts can be executed in a different order, simultaneously, partially simultaneously, or in combinations thereof. During operation, the dual-scale counter can detect an increment event (operation 402). Depending on the use case, different logical units in a network device can detect the increment event. In one example, the Fig. The event detection logic shown in Figure 304 detects the increment event. In network telemetry applications, increment event detection can involve performing a comparison with one or more header fields of an incoming packet.

[0028] The dual-scale counter can determine the operating range of a counting circuit based on a current counter value and a predetermined threshold (operation 404). In some examples, the dual-scale counter may include a comparator circuit that compares the current counter value with the predetermined threshold. In some examples, the dual-scale counter may include a logic unit with a table query that retrieves a counter range table (e.g., the one in Fig. Table 200 (shown) can be used to determine the operating range of the counting circuit. The counting circuit can operate in a linear or a probabilistic range. If the current counter value is less than the predetermined threshold, the counting circuit operates in the linear range. If the current counter value is equal to or greater than the predetermined threshold, the counting circuit operates in the probabilistic range. Furthermore, the probabilistic range can also be subdivided into several probabilistic subranges. By comparing the current counter value with the lower and / or upper limit of each range and subrange, the logic unit for table search can determine the operating range / subrange of the counting circuit.

[0029] If the counter operates in the linear range, the counter value can be incremented linearly for each increment event (Operation 406). In one example, the counter value can be increased by one with each increment event. In other examples, the counter value can be increased by other positive numbers (e.g., two or three) with each increment event.

[0030] If the counter operates in the probabilistic range, the counter value can be incremented probabilistically based on a randomly generated binary bit sequence for the increment event (Operation 408). According to some considerations, the increment probability can be determined based on the probabilistic subrange to which the current counter value belongs. In particular, a higher counter value can lead to a lower increment probability. Based on the in Fig. The increment probability for the following is shown in Table 200 (2). i-ten probabilistic sub-area 2 -i , i = 1, 2, ..., 32.. In addition to the logarithmic base 2, the probabilistic range can also be divided by another logarithmic base, e.g. the logarithmic base 10.

[0031] According to some aspects, the two-scale counter can contain a LFSR that can output a randomly generated binary bit sequence. Depending on the increment probability, a subset of the bits in the randomly generated binary bit sequence can be evaluated to determine whether the counter value of the counter circuit should be incremented. In one example, the counter circuit is incremented if all evaluated bits are "1" or "0".

[0032] Fig. Figure 5 shows a computer system that facilitates the operation of a dual-scale counter, according to one aspect of the present application. The computer system 500 comprises a processing resource 502, a memory 504, and a storage device 506. Furthermore, the computer system 500 can be coupled with peripheral input / output user devices 510 (e.g., a display device 512, a keyboard 514, and a pointing device 516). The storage device 506 comprises a non-transitory, computer-readable storage medium and stores an operating system 518, a dual-scale counter control system 518, and data 540. The computer system 500 can be implemented on a network device (e.g., a switch, a router, a network interface card (NIC), etc.) and can have fewer or more units than those shown in Figure 5. Fig. 5 are included.

[0033] In the examples described here, the processing resource may include, for example, one or more processors contained in a single computer device or distributed across multiple computer devices. As used here, a "processor" may be at least one central processing unit (CPU), a semiconductor-based microprocessor, a graphics processing unit (GPU), a field-programmable gate array (FPGA) configured to retrieve and execute instructions, any other electronic circuit capable of retrieving and executing instructions stored on a computer-readable storage medium, or a combination thereof. In the examples described here, the processing resource may retrieve, decode, and execute the instructions stored on a storage medium to perform the functions described with respect to the instructions stored on the computer-readable medium.In other examples, the functions described in relation to the instructions presented here can be implemented as electronic circuits, as executable instructions encoded on a computer-readable medium, or as a combination of both. The computer-readable storage medium can be located either within the computer device that executes the instructions, or it can be remote from the computer device but accessible for execution (e.g., via a computer network). In the examples presented here, the node can be implemented using one or more computer-readable storage media.

[0034] Dual-scale counter control system 520, which, when executed by the computer system 500 (or by the processing resource 502 of the computer system 500), can cause the computer system 500 to perform the procedures and / or processes described in this disclosure. In particular, the dual-scale counter control system 520 may include instructions 522 to detect an increment event, as described above in relation to the one in Fig. The process described in section 402 is shown in section 4. According to some aspects, the detection of the increment event may involve performing a comparison with one or more header fields of an incoming packet.

[0035] The dual-scale counter control system 520 can include instructions 524 to determine the operating range of a counting circuit based on a current counter value and a predetermined threshold, as described above in relation to the one in Fig. The process described in section 404 is described. According to some aspects, determining the operating range of the counter circuit can involve obtaining the current counter value and comparing it with the predetermined threshold. According to other aspects, determining the operating range of the counter circuit can involve looking up the values ​​in a range table (e.g., in the one described in Fig. 2 (Table 200 shown).

[0036] The 520 dual-scale counter control system can include instructions 526 to linearly increment the counter value when it is determined that the counting circuit is operating in the linear range, as described above in relation to the one in Fig. The process described in section 406 is shown in section 4. If the counter operates in the linear range, the counter value can be increased by a predetermined amount (e.g., by one) for each detected increment event.

[0037] The dual-scale counter control system 520 can include instructions 528 to probabilistically increment the counter value based on a randomly generated binary bit sequence in response to the finding that the dual-scale event counter circuit is operating in the probabilistic range, as described above in relation to the Fig. The process described in section 408 is shown in section 4. When operating in the probabilistic range, the counter value for each increment event can be incremented based on an increment probability that corresponds to a probabilistic subrange to which the current counter value belongs.

[0038] The dual-scale counter control system 520 can include instructions 530 to output an estimate of the actual number of events based on the counter value, as above in relation to the in Fig. The 312 count output unit shown is described.

[0039] The data 540 can contain a counter value range table 542, as above in relation to the one in Fig. The two-scale counter control system 520 is described in Table 200. It can handle more commands than those shown in Table 200. Fig. The 520 two-scale counter control system can also store instructions for generating a binary random bit sequence or a random number.

[0040] Fig. Figure 6 shows a computer-readable medium that facilitates the operation of a two-scale counter, according to one aspect of the present application. CRM 600 can be a non-transitory computer-readable medium or device that stores instructions which, when executed by a computer or processing resource, cause the computer or processing resource to perform a procedure.

[0041] CRM 600 can issue instructions 610 for detecting an increment event, as above in relation to the one in Fig. 4. Operation 402 shown, described, instructions 620 for determining the operating range of a counter circuit based on a current counter value and a predetermined threshold, as above in relation to the in Fig. 4. Operation 404, as described, instructions 630 for linear incrementing of the counter value in response to the determination that the counting circuit operates in the linear range, as above with respect to the in Fig. 4 depicted operation 406; instructions 640 for probabilistic incrementing of the counter value based on a randomly generated binary bit sequence in response to the finding that the two-scale event counter circuit operates in the probabilistic range, as above in relation to the in Fig. 4. Operation 408 is described; and instructions 650 for outputting an estimate of the actual number of events based on the counter value, as above in relation to the in Fig. The 312 count output unit shown is described.

[0042] CRM 600 can perform more commands than those in Fig. The 6 shown contain them. For example, CRM 600 can also store instructions for generating a binary random bit sequence or a random number.

[0043] A "computer-readable storage medium" can be any electronic, magnetic, optical, or other physical storage medium that contains or stores information such as executable instructions, data, or the like. For example, any computer-readable storage medium described here can be RAM, EEPROM, volatile memory, non-volatile memory, flash memory, a storage drive (e.g., an HDD, an SSD), any type of storage disk (e.g., a compact disc, a DVD, etc.), or the like, or a combination thereof. Furthermore, any computer-readable storage medium described here can be non-transient.

[0044] A circuit can be implemented in any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logic components, software routines, or other mechanisms can be implemented to form a circuit. In implementation, the various circuits described herein can be implemented as discrete circuits, or the described functions and features can be partially or completely distributed across one or more circuits. Even if various features or functional elements are individually described or claimed as separate circuits, these features and functions can be shared by one or more common circuits, and such a description is not intended to require or imply that separate circuits are necessary to implement such features or functions.If a circuit is implemented wholly or partly using software, that software may be implemented in such a way as to operate with a computer or processing system capable of performing the functionality described in relation thereto, such as the Computer System 500.

[0045] In general, the described features provide a dual-scale counter capable of accurately counting small numbers and approximately counting large numbers. When an increment event is detected, the counter control logic reads the current counter value and determines the counter's operating range based on this value. If the current counter value is below a predetermined threshold, the counter operates in the linear range, and the control logic can increment the counter linearly (e.g., the counter value is incremented by one with each event). If the current counter value is above the predetermined threshold, the counter operates in the probabilistic range, and the control logic can increment the counter value based on a predetermined probability. The larger the counter value, the lower the probability of incrementing.The counter control logic can include a low-frequency response generator (LFSR) that generates a pseudo-random sequence of binary bits and determines whether the counter value should be incremented based on a subset of bits output by the LFSR. The dual-scale counter has a much smaller footprint than linear counters with the same counting range and can accurately count small numbers.

[0046] One aspect of the present application provides a dual-scale counter circuit that includes a counter logic unit for storing a current counter value, a range determination logic unit for determining an operating range of the dual-scale counter circuit based on the current counter value and a predetermined threshold, and a counter increment logic unit. The counter increment logic unit is designed to linearly increment the current counter value for an increment event if the range determination logic unit determines that the dual-scale counter circuit is operating in a linear range, and to probabilistically increment the current counter value for the increment event if the range determination logic unit determines that the dual-scale counter circuit is operating in a probabilistic range.The dual-scale counter circuit further includes a linear feedback shift register to generate a random binary bit sequence, on the basis of which the counter increment logic unit is to determine whether the current counter value should be incremented for the increment event when the dual-scale counter circuit is operating in the probabilistic range.

[0047] In one variant of this aspect, the range determination logic unit further determines that the two-scale counter circuit operates in the linear range when the current counter value is less than the predetermined threshold, and that the two-scale counter circuit operates in the probabilistic range when the current counter value is equal to or greater than the predetermined threshold.

[0048] In one variation of this aspect, the logic unit for range determination can include a logic unit for looking up the counter value range in a table based on the current counter value.

[0049] In another variant, the counter value range table can contain a plurality of rows, with each row corresponding to a counter value range with a range start value, a range end value, and a probability for the increment of the current counter value for the increment event.

[0050] In another variant, the probability can decrease if the current count value increases from a first count value range to a second count value range.

[0051] In another variant, the probability can decrease exponentially with a power of two.

[0052] In another variation, the dual-scale counter circuit can include a counter output unit to provide an estimate of the total number of increment events based on the current counter value and the counter range table. Compared to a linear counter that outputs the total number of increment events, the dual-scale counter has a smaller footprint.

[0053] In another variant, each line can also specify a counter offset value for the count range. The count output unit can determine from the plurality of lines a line corresponding to the count range to which the current count belongs; subtract the range start value specified by the specified line from the current count to obtain a number of increments made within the count range; multiply the number of increments by the inverse of the probability specified by the specified line to obtain an estimated number of increment events counted within the count range; and add the counter offset value specified by the specified line to the estimated number of increment events.

[0054] In one variant of this aspect, the binary random bit sequence can contain a plurality of bits, and the counter increment logic can evaluate a subset of the bits based on a probabilistic subset corresponding to the current counter value.

[0055] In another variant, the counter increment logic unit can increase the current counter value if all bits in the subset are set to one.

[0056] One aspect of the present application provides a system and a method for incrementing a dual-scale counter circuit. During operation, the system can detect an incrementing event, determine an operating range of the dual-scale counter circuit based on a current counter value and a predetermined threshold, linearly increment the current counter value in response to the determination that the dual-scale counter circuit is operating in a linear range, and probabilistically increment the current counter value based on a randomly generated binary bit sequence in response to the determination that the dual-scale counter circuit is operating in a probabilistic range.

[0057] The foregoing description is intended to enable the person skilled in the art to produce and use the aspects and examples and is given in connection with a specific application and its requirements. Various modifications of the disclosed aspects will be readily apparent to the person skilled in the art, and the general principles defined herein can be applied to other aspects and applications without departing from the spirit and scope of the present disclosure. Therefore, the aspects described here are not limited to those shown but have the broadest possible scope consistent with the principles and features disclosed herein.

[0058] Furthermore, the foregoing descriptions of the aspects serve only for illustration and description. They do not claim to be exhaustive and do not limit the aspects described herein to the disclosed forms. Accordingly, many modifications and variations will be obvious to those skilled in the art. Moreover, the above disclosure is not intended to limit the aspects described herein. The scope of the aspects described herein is defined by the attached claims.

Claims

[1] A two-scale counter circuit comprising the following: a counter logic unit for storing a current counter value; a range determination logic unit to determine an operating range of the two-scale counter circuit based on the current counter value and a predetermined threshold value; a counter increment logic unit for: linear incrementing of the current counter value for an increment event in response to the range determination logic unit determining that the dual-scale counter circuit is operating in a linear range; and probabilistic incrementing of the current counter value for the increment event in response to the range determination logic unit determining that the dual-scale counter circuit is operating in a probabilistic range; and A linear feedback shift register for generating a random binary bit sequence, on the basis of which the counter increment logic unit is to determine whether the current counter value should be increased for the increment event when the two-scale counter circuit operates in the probabilistic range. [2] Two-scale counter circuit according to claim 1, wherein the range determination logic unit further serves to: Determine that the dual-scale counter circuit operates in the linear range in response to the current counter value being less than the predetermined threshold; and Determine that the dual-scale counter circuit operates in the probabilistic range in response to the current counter value being equal to or greater than the predetermined threshold. [3] Two-scale counter circuit according to claim 1, wherein the range determination logic unit comprises a table lookup logic unit for looking up in a counter value range table based on the current counter value. [4] Two-scale counter circuit according to claim 3, wherein the counter value range table comprises a plurality of rows, each row corresponding to a counter value range with a range start value, a range end value and a probability for the increment of the current counter value for the increment event. [5] Two-scale counter circuit according to claim 4, wherein the probability decreases when the current counter value increases from a first counter value range to a second counter value range. [6] Two-scale counter circuit according to claim 5, wherein the probability decreases exponentially according to a power of two. [7] Dual-scale counter circuit according to claim 4, further comprising a counter output unit to output an estimate of a total number of increment events based on the current counter value and the counter range table, wherein the dual-scale counter has a smaller footprint compared to a linear counter that outputs the total number of increment events. [8] Two-scale counter circuit according to claim 7, wherein each line further specifies a counter offset value for the counter value range and the counter value output unit is determined for: Determine a row from the plurality of rows that corresponds to the counter value range to which the current counter value belongs; Subtracting the range start value specified by the given row from the current counter value to obtain a number of increments made within the counter value range; Multiplying the number of increments by the inverse of the probability specified by the given row to obtain an estimated number of increment events that will be counted within the counter value range; and Adding the counter offset value specified by the particular row to the estimated number of increment events. [9] Two-scale counter circuit according to claim 1, wherein the binary random bit sequence comprises a plurality of bits and wherein the counter increment logic is to evaluate a subset of the bits on the basis of a probabilistic subrange corresponding to the current counter value. [10] Two-scale counter circuit according to claim 9, wherein the counter increment logic unit serves to increase the current counter value when all bits in the subset are set to one. [11] A procedure comprising the following: Detecting an increment event; Determining an operating range of a two-scale counter circuit based on a current counter value and a predetermined threshold value; linear incrementing of the current counter value in response to the determination that the dual-scale counter circuit operates in a linear range; and Probabilistic incrementing of the current counter value based on a randomly generated binary bit sequence in response to the determination that the two-scale counter circuit operates in a probabilistic range. [12] The method of claim 11, comprising: Determine that the dual-scale counter circuit operates in the linear range in response to the current counter value being less than the predetermined threshold; and Determine that the dual-scale counter circuit operates in the probabilistic range in response to the current counter value being equal to or greater than the predetermined threshold. [13] The method of claim 11, further comprising looking up in a counter value range table based on the current counter value, wherein the counter value range table comprises a plurality of rows, each row corresponding to a counter value range with a range start value, a range end value and a probability for the increment of the current counter value for the increment event. [14] Method according to claim 13, wherein the probability decreases as the current counter value increases from a first counter range to a second counter range. [15] Method according to claim 14, wherein the probability decreases exponentially according to a power of two. [16] The method of claim 13, further comprising estimating a total number of increment events based on the current counter value and the counter value range table. [17] Method according to claim 16, wherein each row further specifies a count offset value for the counter value range, and wherein the estimation of the total number of increment events comprises: Determine a row from the plurality of rows that corresponds to the counter range to which the current counter value belongs; Subtracting the range start value specified by the given row from the current counter value to obtain a number of increments made within the counter value range; Multiplying the number of increments by the inverse of the probability specified by the given row to obtain an estimated number of increment events that will be counted within the counter value range; and Adding the counter offset value specified by the particular row to the estimated number of increment events. [18] Method according to claim 11, wherein the random binary bit sequence comprises a plurality of bits, and wherein the probabilistic incrementing of the current counter value comprises evaluating a subset of the bits based on a probabilistic subrange corresponding to the current counter value. [19] A non-transitory, machine-readable storage medium that stores instructions that can be executed by a processing resource to: Detecting an increment event; Determining an operating range of a two-scale counter circuit based on a current counter value and a predetermined threshold value; linear incrementing of the current counter value in response to the determination that the dual-scale counter circuit operates in a linear range; and Probabilistic incrementing of the current counter value based on a randomly generated binary bit sequence in response to the determination that the current counter value is equal to or greater than the predetermined threshold. [20] Non-transitory machine-readable storage medium according to claim 19, wherein the instructions further serve to look up in a counter value range table based on the current counter value, wherein the counter value range table comprises a plurality of rows, each row corresponding to a counter value range with a range start value, a range end value and a probability for the incrementing of the current counter value for the increment event.

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