Ethernet Collision Detection

Abstract

A digital PHY 302 transmits a signal comprising a multitude of symbols to an Ethernet transceiver 310 for transmission on the Ethernet line 120. A copy of the signal is stored in the buffer 340. A collision detector 344 compares the signals received on the RX line 316 with those stored in the buffer 340 and signals a collision if the received symbols do not match the transmitted symbols, or if the bits of the received symbols do not match the corresponding bits of the transmitted symbols. A gate array 350 allows configuration for various scenarios with different devices connected to the Ethernet line 120.

Description

Field of invention

[0001] A collision detection system for Ethernet communication, a device implementing such a collision detection system, and a method for collision detection are described. Background of the invention

[0002] Many different Ethernet communication standards are defined by the IEEE for various applications, transmission distances, and approaches. Conventional Ethernet uses four wires, but two-wire Ethernet standards such as 10BaseT1L and 10BaseT1S are also defined. The latter standard also enables multidrop Ethernet, in other words, an Ethernet connection with more than two devices connected to the Ethernet cabling.

[0003] To enable multidrop communication, a means must be provided to avoid collisions on the network; in other words, to prevent multiple devices from attempting to transmit on the network simultaneously and to handle collisions should they occur. The IEEE 10Base T1S standard defines such a system, known as Physical Layer Collision Avoidance (PLCA).

[0004] In 10Base T1S PLCA, as defined by IEEE Standard 802.3cg, each device connected to a link has a unique integer ID starting from 0, so that for N devices, each has a unique ID from 0 to (N-1). A beacon signal is transmitted by device 0 and synchronizes the time for devices connected to the link. Each device then counts upwards independently from 0. When the count reaches the device ID, if the device has data to transmit, it acknowledges this and transmits the data; while data is being transmitted, the count is paused in each device. After the data has been transmitted, the device signals this, and the count resumes. If the device has no data to transmit when the count reaches the device ID, the count simply continues.

[0005] In such a system, it is important to detect a collision, i.e., to detect the case where multiple devices are transmitting, so that such cases can be handled properly.

[0006] With reference to Fig. In the 10 Base T1S system, as proposed by IEEE Standard 802.3cg, an operating host 100 implements a data link layer, which in particular includes a media access control, MAC 102. A physical layer device, PHY, 110 contains a physical coding sublayer, PCS 114, a physical medium attachment, PMA 116, and an autonegotiation block, AN, 118, which in turn is connected to the two-wire Ethernet medium 120. A Media-Independent-Interface (MII) bus 104 connects the MAC 102 to the PCS 114. A Physical-Layer-Collision-Avoidance (PLCA) block 112 is provided, which is connected between the MAC 102 and the PCS 114, which are connected to both via the MII bus 104.

[0007] The 802.3cg standard defines that the PLCA 112 is located in the PHY 110 and is configured to communicate with a suitable host that has a MAC layer, such as a microcontroller or other device, using a conventional MII bus 104. However, the MII bus defines a relatively high number of communication lines, which increases costs in some applications, such as automobiles.

[0008] Accordingly specified with reference to Fig. 2. The Open Alliance, OA, TC14 subgroup transceiver interface document with the specification “10BASE-T1S PMD Transceiver Interface” describes an alternative arrangement with a host 200, a 10Base T1S PMD transceiver 210, and an Open Alliance three-wire link 220 that connects the host 200 to the PMD transceiver 210 using a PMD transceiver interface in the host 200. In other words, this alternative arrangement requires only three wires.The three-wire connection 220 includes a transmit (TX) line 222 for transmitting data from the PMD transceiver interface to the PMD transceiver 210, from where it is transmitted to the Ethernet line 120, a receive (RX) line 224 for receiving data from the PMD transceiver 210 and transmitting it to the PMD transceiver interface in the host, and an energy detection (ED) line 226, which transmits an indication from the PMD transceiver 210 to the PMD transceiver interface in the host, the signal being generated using a window comparator that indicates whether the differential voltage on the medium 120 is contained within a specific amplitude band centered on zero.

[0009] The PLCA 230 can be deployed in the host 200 and the PCS / PMA layer 232 can also be deployed in the host 200.

[0010] As mentioned above, collision detection is an important feature of such networks. Both the IEEE 802.3cg standard and the OA standard enable collision detection functionality at a variety of different layers, namely the PLCA layer, the PCS layer, and the PMD layer. However, how these different collision detection mechanisms operate, and especially how they interact, is omitted from the scope of the standards. In other words, it is not defined how to handle the fact that collision detection might occur at different layers within the stack. Different collision detection mechanisms can have different effects and lead to interoperability problems, resulting in different decisions being made in different devices.

[0011] US 2019 / 0261210 A1 describes a PHY device compliant with the IEEE 802.3 standard that uses CSMA / CD for MAC to a shared medium. The PHY device includes a Physical Coding Sublayer Sender, a Physical Medium Attachment Sender, a Physical Coding Sublayer Receiver, a Physical Medium Attachment Receiver, and a Media Access Priority Manager configured to initiate the transmission of a priority cue for a frame to be transmitted on the shared medium.

[0012] US 2020 / 0067727 A1 also describes a PHY with a Media Access Priority Manager, where the frame priority indicator contains more than three bits of frame priority information.

[0013] EP 4 297 348 A1 relates to a PHY, a communication node, a communication network, and a method. The method comprises an initial advertising phase, which includes the identification of a priority level for the next frame to be transmitted to the shared medium by the communication node, the transmission of a signal indicating the priority level of the next frame from the communication node for transmission to the shared medium, and the receipt of signal indicating the priorities of the next frames to be transmitted on the shared medium from the multiple communication nodes connected to the shared medium.

[0014] US 11,616,861 B1 describes a 10BASE-T1S-PHY method and corresponding device for receiving an analog MDI signal, transmitting DME-coded data to a receiver comparator to generate a digital output signal. The digital output signal is processed by a pulse encoder to generate a pulse-coded output signal with pulses generated at each rising or falling transition in the digital output signal. The pulse-coded output signal is then processed by an output driver to generate a pulse-coded driver output signal. The driver output signal is transmitted to a receiver interface pin RX. The pulse-coded driver output signal is processed by an input comparator to generate a pulse-coded comparator output signal. The pulse-coded comparator output signal is then processed by a pulse decoder.This generates a DME-coded PMA input signal in which time asymmetries caused by processing at the receiver comparator and / or output driver have been eliminated, and is then used to process the DME-coded PMA input signal at a digital PHY circuit in the Ethernet PHY.

[0015] US 2019 / 0182109 A1 describes a first device of several devices that communicate with each other in an in-vehicle Ethernet communication system using an Ethernet scheme, wherein the device comprises: a central processor and a physical layer processor configured to connect the central processor to a second device, which is another of the several devices. The physical layer processor includes a counter configured to output a first count-end signal after performing a count for a first predetermined duration in response to receiving an operating current source, and a signal transmitter configured to transmit a first master request signal requesting that the first device operate continuously in a master mode with respect to the second device.In response to receiving at least one of a mode signal and the first count-end signal, a signal receiver configured to output a master recognition signal transmitted by the second device indicating whether a second master request signal is received requesting that the second device operate continuously in master mode, and an operating mode controller configured to determine an operating mode of the first device in response to receiving at least one of the first count-end signal and the master recognition signal and to generate the mode signal indicating the determined operating mode.

[0016] DE 10 2019 213 322 A1 describes a physical layer transceiver configured for transmitting and receiving Ethernet data frames over a two-wire bus shared by several network devices. The transceiver includes a driver circuit configured to actively switch each of the two wires of the two-wire bus to one of at least two electrical states for data transmission. These at least two electrical states represent signals by which the data is encoded. The physical layer transceiver also includes a receiver circuit configured to sample the electrical states present on the two wires of the two-wire bus and derive signals from them that encode received data. Furthermore, the physical layer transceiver includes a logic circuit configured to perform priority-oriented arbitration of an active bus access.The logic circuit is designed to control the driver circuit and the receiver circuit to perform arbitration at a first data rate that allows the resolution of collisions between signals from two network devices transmitting simultaneously.

[0017] Therefore, there is a need for a robust collision detection method. Summary of the invention

[0018] In one aspect, an Ethernet Digital Physical Layer (PHY) is revealed comprehensively: a Physical Medium Attachment (PMA) layer transmitter arranged to transmit data in the form of sequential symbols towards an Ethernet line, a Physical Coding Sublayer (PCS) transmitter that has an output connected to an input of the PMA layer transmitter, a PMA layer receiver arranged to receive data as a sequence of symbols from the Ethernet line; a PCS receiver having an input connected to the output of the PMA layer receiver; a collision detection system comprising a buffer, wherein the buffer is connected to the output of the PCS transmitter to store the symbols transmitted by the PCS transmitter, and a collision detector having an input connected to the output of the PMA layer receiver and an input connected to the buffer, wherein the collision detector is arranged to compare, when the Ethernet digital PHY is in a transmit state, the symbols received from the PMA layer receiver with those stored in the buffer and to signal a collision if the symbols do not match.

[0019] In another aspect, a comprehensive system is revealed: a digital PHY as outlined above, an Ethernet MAC connected to the PLCA; and an Ethernet transceiver connected to the three-wire connection and an Ethernet cable.

[0020] A method for operating such a system is also disclosed, comprising: Transmitting a signal comprising a multitude of symbols from the digital PHY to the Ethernet transceiver; Transmitting the signal back from the Ethernet transceiver to the digital PHY as received signals;

[0021] Signaling a collision when the received symbols do not match the transmitted symbols, or when the bits of the received symbols do not match the corresponding bits of the transmitted symbols. Brief description of the drawings

[0022] Examples of the invention will now be described purely by way of example with reference to the accompanying drawings, in which: Fig. Figure 1 illustrates a 10-based T1S approach according to an IEEE standard; Fig. 2 illustrates a 10-based T1S approach according to an OA standard; and Fig. Figure 3 illustrates a digital PHY connected via an Ethernet line through a transceiver. Detailed description

[0023] An example from the Book of Revelation is presented purely as an example.

[0024] It was noted that the simple idea of ​​detecting a collision by checking whether signals arrive at a receive port (RX) on a host with a three-wire connection according to the Open Alliance standard during transmission does not work in practice, because some implementations of 10BaseT1S transceivers sample the line and reflect received transmissions back to the host. In such cases, data transmitted at the TX port is reflected back to the PMD layer's RX port, regardless of whether a collision occurs or not.

[0025] With reference to Fig. 3. A Digital-PHY 300 is provided, which is embedded in the Host 302. In the example of Fig. 3. The host 302 is a microcontroller; alternatively, the host can be any device that uses the provision of an Ethernet connection.

[0026] Host 302 contains an Ethernet MAC 304 communicating with the digital PHY using an MII bus 306. A separate transceiver 310 is provided, which is connected to Host 302 using a three-wire connection 312 with a TX line 314, an RX line 316, and an ED line 318, in this example, according to the Open Alliance standard. Host 302 is provided with a three-wire connector 370, which includes a TX output terminal 374 for connection to TX line 314, an RX input terminal 376 for connection to RX line 316, and an ED input terminal 378 for connection to ED line 318.

[0027] In use, the transceiver 310 is connected to the two-wire Ethernet connection 120.

[0028] In the approach described above, both the MAC 304 and the Digital-PHY 300 are implemented in the host 302. Alternatively, the Digital-PHY 300 can be implemented as a separate silicon component connected to a host using an external MII bus. Alternatively or additionally, the Transceiver 310 can be implemented on the same silicon as the Digital-PHY 300.

[0029] A PLCA 320 is provided connected to the MII bus 306 on both the input and output sides. It should be noted that this allows the PLCA to be deactivated if it is not required, for example, if the Ethernet medium 120 is only connected to two devices and can therefore operate in half-duplex mode.

[0030] A PCS transmitter 322 has its input, which is connected to the MAC 304 and the PLCA 320 via the MII bus 306, and an output, which is connected to the PMA transmitter 324. The output of the PMA transmitter 324 is connected to the TX output terminal 374 for connection to the TX line 314 for transmitting data from the host to the transceiver 310 and then on to the Ethernet connection 120.

[0031] A PMA receiver 332 has its input, which is connected to the RX input terminal 376 for receiving signals from the transceiver 310, and its output, which is connected to the input of the PCS receiver 334. The output of the PCS receiver 334 is connected to the MII bus 306 and, via the MII bus 306, to the PLCA 320 and the MAC 304.

[0032] The output of the PCS transmitter 322 is also connected to the buffer 340, in this example a FIFO buffer with a buffer size of 2 to 5 symbols. In this example, each symbol is a 5-bit transmission symbol defined by IEEE 302.3cg according to 4b5b encoding (4 data bits encoded as 5 bits). Those skilled in the art will recognize that alternative symbol sizes can be used.

[0033] The buffer 340 is also connected to the collision detector 342, which has an input connected to the buffer 340 and an input connected to the output of the PMA receiver 332.

[0034] The buffer 340 and the collision detector 342 form part of the collision detection system 344.

[0035] Furthermore, a gate arrangement 350 is provided, which in this example includes an OR gate 352 with inputs connected to the output of the PCS AND gate 354 and the output of the PMD AND gate 356. The PCS AND gate 354 has one input connected to a PCS collision activation line 358 and the other input connected to the output of the collision detector 342. The PMD AND gate 356 has one input connected to the PMD collision activation line 360 ​​and one input connected to the output of the ED filter block 362. The input of the ED filter block 362 is connected to the ED input terminal 378 for connection via the ED line 318 to the output of the transceiver 310. It is understood that such gate arrangements can be equipped with different arrangements of gates, for example NAND gates, NOR gates as well as AND gates, OR gates and / or inverters.Such functionality can also be provided in alternative approaches.

[0036] In operation, the described system works by comparing the symbols received on RX line 316 with those transmitted on TX line 312. In the event of a collision, the received signals will not match the transmitted symbols. The transceiver 310 is configured to relay signals received on TX line 314 back to RX line 316.

[0037] The collision detector 342 can, for example, signal a collision by activating its output to the PCS-AND gate 354 when one of the following conditions is true.

[0038] The first condition is that the received RX symbol does not match the TX symbol at the top of buffer 340. In this case, after the comparison, the TX symbol at the top of the buffer is removed.

[0039] A second condition, which can be used as an alternative to the first condition, is that the RX data bit does not match the TX data bit at the top of the buffer. In this alternative case, only the first TX data bit is removed after the comparison. Thus, in this case, the comparison is bit by bit. It should be noted that the digital PHY can be configured to use either the first or the second condition selectively.

[0040] In either bitwise or symbolwise comparison modes, the collision detector 342 can also signal a collision in a third condition when the buffer 340 is full; this may be a symptom of a collision on the line.

[0041] A fourth condition that can also trigger a collision signal is that no RX symbol or bit is received after a predetermined period, and that buffer 340 is not empty. This allows for the detection of a collision of only the last symbol of a transmission. The predetermined period can be a minimum of 2 MII clock cycles, up to, for example, a minimum of 4 MII clock cycles. Using a standard MII configuration, this corresponds to 800 ns for the predetermined period. To provide a safety buffer, a longer predetermined period can be used, for example, in the range of 800 ns to 2000 ns.

[0042] The OA standard defines the maximum propagation delay as 50 ns on the transmitting (TX) side and 80 ns on the receiving (RX) side. The two-bit transmission time is 160 ns, meaning the buffer size can be very small: two 5-bit symbols containing 10 bits, resulting in a total transmission time of 800 ns. This means a collision can be detected within this 800 ns timeframe.

[0043] In the alternative arrangement, where the second condition is used and the collision detector compares the individual bits rather than the symbols as a whole, detection can be performed in the transmission time for three bits, namely 240 ns.

[0044] In both alternatives, the detection time is much better than the required time of 4500 ns.

[0045] It should be noted that some symbols transmitted by the PCS transmitter block 322 and the PMA transmitter block 324 to the transceiver 310 are not symbols for transmission, but symbols used to control the transceiver 310. These symbols are not transmitted along line 120 and are also reflected back, and therefore should not be used for collision detection.

[0046] In the illustrated example, the PCS collision activation signal line 358 is only activated when symbols, not control signals, are transmitted. Thus, in this case, the PCS AND gate 354 filters out detections during control signal transmission. In an alternative or additional configuration, such symbols can be filtered out and not stored in buffer 340.

[0047] For robustness, buffer 340 is cleared upon entering a transfer state. Although not essential, this prevents false positive collisions from being detected as a result of previous transfers not being properly terminated.

[0048] It should be noted that the ED line can also report a failure or a collision condition. In the example, the OR gate 352 effectively reports a collision, either when the collision detection system 344 detects a fault or when the output of the ED filter block 362 outputs a collision condition. It should be noted that the PMD AND gate 356 and the PMD collision enable line 360 ​​are used similarly to the PCS AND gate 354 and the PCS collision enable line 358 to prevent the output of the ED filter block 362 from being fed into the OR gate 352 when the PMD collision enable line 360 ​​is not enabled. This ensures that the signal on ED line 318 is not transmitted further when Digital PHY 300 or Transceiver 310 is not in a sensing state.Thus, depending on the state of the PCS collision activation line 358 and the PMD collision activation line 360, collision detection by the collision detector 344, ED filter 362, either none or both can be activated.

[0049] By providing collision detection in the host 302, the need for collision detection in the transceiver 310 can be avoided. This is advantageous because many transceiver designs are simple and subject to tight cost constraints. However, if the transceiver 310 provides full collision detection, the PCS collision enable line can be permanently disabled and the PMD collision enable line 360 ​​can be permanently enabled. Such enable settings can be programmed in registers, for example, during a boot process that loads the host 302.

[0050] This flexibility allows the digital PHY to be configured in different environments and with different transceivers. This, in turn, allows the device to be operated with hardware that operates differently, simply by adjusting the tests for activating the collision turn-on lines 358 and 360, without requiring any additional hardware. Despite its simplicity, the collision detector 344 can be implemented without excessive use of silicon area.

[0051] Although specific embodiments / examples / aspects have been illustrated and described herein, the person skilled in the art will recognize that a multitude of alternative and / or equivalent implementations can replace the specific examples shown and described without departing from the scope of protection of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention is limited only by the claims and their equivalents.

[0052] For example, although the above arrangement suggests a gate arrangement 350 with one OR gate and two AND gates, the person skilled in the art will recognize that alternative gate arrangements can be used, for example an arrangement that simply uses NAND gates.

[0053] In a first example, there is an Ethernet Digital Physical Layer (PHY) comprising: a Physical Medium Attachment (PMA) layer transmitter arranged to transmit data in the form of sequential symbols towards an Ethernet line, a Physical Coding Sublayer (PCS) transmitter that has an output connected to an input of the PMA layer transmitter, a PMA layer receiver arranged to receive data as a sequence of symbols from the Ethernet line; a PCS receiver having an input connected to the output of the PMA layer receiver; a collision detection system comprising a buffer, wherein the buffer is connected to the output of the PCS transmitter to store the symbols transmitted by the PCS transmitter, and a collision detector having an input connected to the output of the PMA layer receiver and an input connected to the buffer, wherein the collision detector is arranged to compare, when the Ethernet digital PHY is in a transmit state, the symbols received from the PMA layer receiver with those stored in the buffer and to signal a collision if the symbols do not match.

[0054] The digital PHY according to claim 1 may further comprise a three-wire connector for connection to a transceiver.

[0055] The three-wire connection can include: a TX output connected to the PMA layer transmitter, an RX input connected to the PMA layer receiver, and an ED, energy detection, input.

[0056] The digital PHY may further include a gate arrangement having a collision detection output, an input connected to the output of the collision detector, and an input connected to the ED input, such that the collision detection output reports a collision when it is detected by the collision detector or when it is reported by the transceiver via the ED input.

[0057] The digital PHY may also contain: a PCS collision detection lead, and a PMD collision detection lead, wherein the gate arrangement is configured to report a collision on the collision detection output only when the PCS collision enable line is activated and the collision detector detects a collision, or when the PMD collision detection line is activated and the ED input is activated.

[0058] The Digital PHY also includes: a Physical Layer Collision Avoidance (PLCA) block, which has an output connected to the PCS transmitter, an input connected to the PCS receiver, and an input connected to the output of the gate arrangement.

[0059] The digital PHY can be configured to clear the buffer upon entering a transfer state.

[0060] The digital PHY can be configured to suppress collision reporting if the symbols are configuration data.

[0061] The digital PHY can be configured to remove each symbol from the buffer when it matches a received symbol, and the collision detector is configured to report a collision when the buffer is full.

[0062] The collision detector can be configured to report a collision if the buffer is not empty and no symbol is received from the PMA layer receiver within a predetermined time.

[0063] The buffer size can be less than 10 symbols.

[0064] A comprehensive system is also described: a digital PHY as outlined above, an Ethernet MAC connected to the PLCA; and an Ethernet transceiver connected to the three-wire connection and an Ethernet cable.

[0065] A method for operating such a system is also described, comprising: Transmitting a signal comprising a multitude of symbols from the digital PHY to the Ethernet transceiver; Transmission of the signal back from the Ethernet transceiver to the digital PHY as received signals; and

[0066] Signaling a collision when the received symbols do not match the transmitted symbols, or when the bits of the received symbols do not match the corresponding bits of the transmitted symbols.

[0067] It should be noted that the examples presented in this document can be used independently or in combination with the other methods and systems disclosed herein. Furthermore, features described in connection with a device are also applicable to a corresponding method, and vice versa. Moreover, all aspects of the methods and devices described in this document can be combined in any way. In particular, the features of the claims can be combined with one another in any manner.

[0068] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. A person skilled in the art will be able to implement various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are contained within its meaning and scope of protection. Furthermore, all examples and embodiments set forth in this document are expressly intended only for explanatory purposes, to assist the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein that provide principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include equivalents thereof.

Claims

[1] Ethernet Digital Physical Layer, PHY, (300) comprising: a Physical Medium Attachment (PMA) layer transmitter (324) arranged to transmit data in the form of sequential symbols towards an Ethernet line (120), a Physical Coding Sublayer, PCS, Transmitter (322) having an output connected to an input of the PMA Layer Transmitter (324), a PMA layer receiver (332) arranged to receive data as a sequence of symbols from the Ethernet line (120); a PCS receiver (334) having an input connected to the output of the PMA layer receiver (332); a collision detection system (344) comprising a buffer (340), wherein the buffer (340) is connected to the output of the PCS transmitter (322) to store the symbols transmitted by the PCS transmitter (322), and a collision detector (342) having an input connected to the output of the PMA layer receiver (332) and an input connected to the buffer (340), wherein the collision detector (342) is arranged to compare, when the Ethernet digital PHY (300) is in a transmit state, the symbols received from the PMA layer receiver (332) with those stored in the buffer (340) and to signal a collision if the symbols do not match. [2] Digital PHY (300) according to claim 1, further comprising: a three-wire connector (370) for connection to a transceiver (310), wherein the three-wire connector (370) comprises: a TX output (374) which is connected to the PMA layer transmitter (324), an RX input (376) which is connected to the PMA layer receiver (332), and an ED, energy detection, input (378); and The digital PHY further comprises a gate arrangement (350) which has a collision detection output, an input connected to the output of the collision detector (342), and an input connected to the ED input (378), such that the collision detection output reports a collision when it is detected by the collision detector (342) or when it is reported by the transceiver (310) via the ED input (378). [3] Digital PHY (300) according to claim 2, further comprising: a PCS collision detection line (358), and a PMD collision detection line (360), wherein the gate arrangement (350) is arranged to report a collision only on the collision detection output when the PCS collision enable line (358) is enabled and the collision detector (342) detects a collision, or when the PMD collision enable line (360) is enabled and the ED input (378) is enabled. [4] Digital PHY (300) according to claim 2 or 3, further comprising: a Physical Layer Collision Avoidance, PLCA, block (320) having an output connected to the PCS transmitter (322), an input connected to the PCS receiver (334), and an input connected to the output of the gate arrangement (350). [5] Digital PHY (300) according to any of the preceding claims, wherein the Digital PHY (300) is arranged to clear the buffer (340) upon entering a transfer state. [6] Digital-PHY (300) according to any of the preceding claims, which is arranged to suppress the reporting of a collision when the symbols are configuration data. [7] Digital PHY (300) according to any of the preceding claims, which is arranged to remove each symbol from the buffer (340) when it matches a received symbol, wherein the collision detector is arranged to report a collision when the buffer (340) is full. [8] Digital PHY (300) according to one of the preceding claims, wherein the collision detector (342) is arranged to report a collision when the buffer (340) is not empty and no symbol is received from the PMA layer receiver (332) within a predetermined time. [9] Digital PHY (300) according to any of the preceding claims, wherein the buffer size is less than 10 symbols. [10] System, encompassing: a digital PHY (300) according to claim 4, an Ethernet MAC (304) connected to the PLCA (320); and an Ethernet transceiver (310) which is connected to the three-wire connection (312) and to an Ethernet line (120). [11] Method for operating a system according to claim 10, comprising: Transmitting a signal comprising a multitude of symbols from the digital PHY (300) to the Ethernet transceiver (310); Transmission of the signal back from the Ethernet transceiver (310) to the digital PHY (300) as received signals; and Signaling a collision when the received symbols do not match the transmitted symbols, or when the bits of the received symbols do not match the corresponding bits of the transmitted symbols.

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