Attenuating idle tones using clock jitter

Abstract

A circuit comprises: a capacitive microelectromechanical system (MEMS) microphone configured to generate a voltage signal in response to a sound signal, a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone, the VCO configured to generate a frequency-modulated signal having a frequency proportional to the voltage signal, a frequency-to-digital converter (FTD) converter coupled to an output terminal of the VCO, a random number generator configured to generate random numbers, and a phase modulator configured to generate a phase-modulated clock signal by modulating a phase of a system sampling clock signal according to the random numbers, the FTD converter configured to generate a digital signal according to the frequency-modulated signal and the phase-modulated clock signal, and configuredto sample the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter.,

Description

[0001] The present invention relates generally to circuits, and in certain embodiments, to circuits comprising a capacitive microelectromechanical system (MEMS) microphone and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC) coupled to the MEMS microphone.

[0002] Microelectromechanical system (MEMS) microphones are widely used in electronic devices today due to their small form factors and low cost. Traditionally, the analog output of a microphone is converted into a digital output signal by a voltage-encoding-based system that converts the microphone's output voltage into a digital output signal using an analog-to-digital converter (ADC).

[0003] Voltage-controlled oscillator-based ADCs (VCO-ADCs) are promising alternatives to conventional voltage-encoding-based systems and are well-suited for low-cost digital microphone (e.g., MEMS microphone) applications. For example, in a capacitive MEMS microphone system equipped with a VCO-ADC readout circuit, a voltage is generated by the MEMS microphone in response to sound pressure. The voltage modulates the oscillator frequency of the VCO in the VCO-ADC readout circuit. A frequency-to-digital converter (FTD) then measures the oscillator frequency at a sampling rate defined by a system sampling clock signal. While VCO-ADCs offer advantages over conventional voltage-encoding-based systems, challenges remain for the use of VCO-ADCs in MEMS microphone systems.

[0004] The object of the present invention is to provide a circuit or a method for operating a microelectromechanical system (MEMS) microphone system with improved properties.

[0005] This object is achieved by a circuit according to claim 1 or 8 and a method according to claim 17.

[0006] According to one embodiment, a circuit comprises a capacitive microelectromechanical system (MEMS) microphone configured to output a voltage signal in response to a sound signal, and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC) coupled to the capacitive MEMS microphone and configured to generate a digital output signal proportional to the voltage signal, wherein the VCO-ADC comprises a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone and configured to output a frequency-modulated signal having a frequency proportional to the voltage signal, a frequency-to-digital converter (FTD) coupled to an output terminal of the VCO, a random number generator configured to generate random numbers, and a phase modulator.which is configured to generate a phase-modulated clock signal by modulating a phase of a system sampling clock signal with the random numbers, wherein the FTD converter is configured to generate a digital signal according to the frequency-modulated signal and the phase-modulated clock signal, and is configured to generate the digital output signal of the FTD converter by sampling the digital signal using the phase-modulated clock signal.,

[0007] According to one embodiment, a circuit comprises: a capacitive microelectromechanical system (MEMS) microphone configured to generate a voltage signal in response to a sound signal, a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone, the VCO configured to generate a frequency-modulated signal having a frequency proportional to the voltage signal, a frequency-to-digital converter (FTD) coupled to an output terminal of the VCO, a random number generator configured to generate random numbers, and a phase modulator configured to generate a phase-modulated clock signal by modulating a phase of a system sampling clock signal according to the random numbers, the FTD converter configured to generate a digital signal according to the frequency-modulated signal and the phase-modulated clock signal, and configuredto sample the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter.,

[0008] According to one embodiment, a method for operating a microelectromechanical system (MEMS) microphone system comprises the following steps: generating, by a MEMS microphone, a voltage signal in response to an acoustic signal; generating, by a voltage-controlled oscillator (VCO) coupled to the MEMS microphone, a frequency-modulated signal having a frequency proportional to the voltage signal; converting, by a frequency-to-digital converter (FTD) coupled to the VCO, the frequency-modulated signal into a digital signal; generating, by a random number generator, random numbers; modulating, by a phase modulator, a phase of a system sampling clock signal according to the random numbers to generate a phase-modulated clock signal; and sampling the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter.

[0009] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. In the drawings: Fig. 1 illustrates a microelectromechanical system (MEMS) microphone system including a capacitive MEMS microphone and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC), in one embodiment; Fig. 2 a random number generator in one embodiment; Fig. 3A shows a phase modulator in one embodiment; Fig. 3B shows the operation of the phase modulator Fig. 3A in one embodiment; Fig. 4A shows a frequency-to-digital converter (FTD converter) in one embodiment; Fig. 4B an output of the FTD converter Fig. 4A in one embodiment; Fig. 5A shows a phase modulator in another embodiment; Fig. 5B Clock signals generated in the phase modulator from Fig. 5A may be used in one embodiment; Fig. 6 illustrates the output of a MEMS microphone system in response to a mechanical shock in one embodiment; Fig. 7A and Fig. 7B illustrates the performance of the disclosed MEMS microphone system in one embodiment; Fig. 8 shows the performance of the disclosed MEMS microphone system in another embodiment; and Fig. 9 is a flowchart of a method for operating a MEMS microphone system in one embodiment.

[0010] The making and using of the presently disclosed examples are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be practiced in a wide variety of specific contexts. The specific examples discussed merely illustrate specific ways in which the invention may be made and used and do not limit the scope of the invention. Throughout the discussion herein, unless otherwise indicated, like or similar reference numerals in different figures refer to the same or similar component. For simplicity, details of components with the same or similar reference numerals may not be described again.

[0011] The present disclosure is described with reference to examples in a specific context, and more particularly, a MEMS microphone system including a capacitive MEMS microphone and a VCO-ADC readout circuit.

[0012] Fig. Figure 1 illustrates a system diagram of a MEMS microphone system 100 including a capacitive MEMS microphone and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC), in one embodiment. Note that for simplicity, not all features of the MEMS microphone system 100 are illustrated.

[0013] As in Fig. 1, the MEMS microphone system 100 includes a capacitive MEMS microphone 103 configured to provide an output voltage V g in response to a sound signal. In the example of Fig. 1, the capacitive MEMS microphone 103 is or comprises a capacitor, wherein one or more membranes of the capacitor vibrate in response to the sound pressure to generate the output voltage V gto generate. A high voltage bias (e.g., +12 V voltage) is supplied to the capacitive MEMS microphone 103 to bias the capacitive MEMS microphone 103. The high voltage bias may be provided by a voltage supply 101 (e.g., a charge pump circuit) coupled between the capacitive MEMS microphone 103 and a reference node 129, wherein the reference node 129 is configured to be coupled to a reference voltage, such as electrical ground. An output terminal of the capacitive MEMS microphone 103 is coupled to a node 104. A high-value resistor 105 (e.g., having a resistance on the order of gigaohms) is coupled between the node 104 and a node 106. In the illustrated embodiment, a bias voltage V biasprovided at node 106 to set an operating point (e.g., a rest frequency) of the MEMS microphone system 100. As an example, the bias voltage V bias at node 106 by a bias circuit 107. The bias circuit 107 serves to generate a suitable bias voltage for the capacitive MEMS microphone 103. Bias circuits are known and used in MEMS microphone systems; details are not discussed here.

[0014] In Fig. 1, an input stage circuit 109 is coupled between node 104 and an input terminal of a voltage controlled oscillator (VCO) 113. In the example of Fig. 1, the input stage circuit 109 is a source-follower circuit comprising a transistor. A gate terminal of the transistor is coupled to node 104.

[0015] A drain terminal of the transistor is coupled to a supply voltage node 111 configured to receive a supply voltage (e.g., +3 V, +5 V, or the like) for the MEMS microphone system 100. A source terminal of the transistor is coupled to the input terminal of the VCO 113. In some embodiments, the input stage circuit 109 (e.g., a source follower circuit) provides a buffered voltage to the VCO 113, wherein the buffered voltage has a voltage value proportional to the output voltage V g of the capacitive MEMS microphone 103.

[0016] The VCO 113 is configured to provide an output signal f vco to generate. The frequency of the output signal f vco is determined by the output voltage V g of the capacitive MEMS microphone 103. In some embodiments, the frequency of the output signal f vco, which is generated by the VCO 113, proportional to the output voltage V g , and therefore the output signal f vco of the VCO 113 also as a frequency modulated signal f vco The VCO 113 is a ring oscillator in an exemplary embodiment, although any other suitable type of VCO may also be used as the VCO 113. Voltage-controlled oscillators, such as ring oscillators, are known and used in the art; therefore, no details will be discussed here.

[0017] With further reference to Fig. 1, an output terminal 114 of the VCO 113 is coupled to an input terminal of a frequency-to-digital converter (FTD converter) 115. The FTD converter 115 is configured to convert the frequency-modulated signal f vcointo a digital output signal y[n] (e.g., a digital multi-bit signal) at an output terminal 116 of the FTD converter 115. In some embodiments, the FTD converter 115 is configured to convert a digital signal (see, e.g., 430 in Fig. 4B) according to the frequency-modulated signal f vco and a phase-modulated clock signal f clk_jittered and is configured to generate the digital output signal y[n] by sampling the digital signal using the phase-modulated clock signal f clk_jittered Details of the phase-modulated clock signal f clk_jittered and the FTD converter 115 are discussed below.

[0018] In Fig. 1, the MEMS microphone system 100 further includes a random number generator 121 and a phase modulator 123. The random number generator 121 is configured to generate random numbers. The generated random numbers are sent to the phase modulator 123. The phase modulator 123 receives the random numbers and a system sampling clock signal f clk and modulates the phase of the system sampling clock signal f clk according to the random numbers to generate the phase-modulated clock signal f clk_jittered to generate. The phase-modulated clock signal f clk_jittered is then sent to a clock input terminal of the FTD converter 115. Further details are discussed below.

[0019] In some embodiments, the components are within the range shown in Fig. 1 is defined by the dashed line 150, integrated into a semiconductor chip, e.g., in an application-specific integrated circuit (ASIC) or part of an ASCI. The input stage circuit 109, the VCO 113, the FTD converter 115, the random number generator 121, the phase modulator 123, and the system clock source 125 may collectively be referred to as a VCO-ADC, a VCO-ADC readout circuit, or a VCO-ADC circuit with a phase modulator.

[0020] Fig. 2 illustrates a random number generator 200 in one embodiment. The random number generator 200 may be referred to as the random number generator 121 in Fig. 1. The random number generator 200 is a linear feedback shift register (LFSR) random number generator that includes a plurality of registers 201 connected in series. The output terminals of some of the registers 201 are combined by a logic circuit 203, and the output of the logic circuit 203 is used as a feedback bit sent to an input terminal of the leftmost register 201. At the beginning of operation, each of the registers 201 of the LFSR random number generator 200 is initialized with a respective initial value (e.g., a "0" bit or a "1" bit), and the values ​​of the registers 201 shift right during operation. The LFSR random number generator 200 can be used to generate random binary sequences or multi-bit random numbers, as will be readily apparent to those skilled in the art. The LFSR random number generator 200 in Fig. 2 is merely a non-limiting example. Other LFSR random number generators and other non-LFSR type random number generators are also possible and can be used as the random number generator 121 in Fig. 1. These and other variations are intended to be fully included within the scope of the present disclosure.

[0021] Fig. 3A shows a phase modulator 300 in one embodiment. The phase modulator 300 can be used as the phase modulator 123 in Fig. 1. As in Fig. 3A, the phase modulator 300 comprises a delay chain 303 having a plurality of delay circuits 305 (e.g., buffers, inverters, or the like) connected in series, wherein an input terminal 301 of the delay chain 303 is connected to the system sampling clock signal f clk (see also Fig. 1) generated by the system clock source 125. In embodiments where inverters are used in the delay circuits, two inverters connected in series may be used as a delay circuit 305. The system clock source 125 may comprise an oscillator, a phase-locked loop (PLL), combinations thereof, or the like, and is configured to generate a high-accuracy digital clock signal (e.g., f clk ) at a specified frequency. In some embodiments, the system clock source 125 is omitted from the VCO-ADC, and the system sampling clock signal f clk is provided by another clock source outside the VCO-ADC.

[0022] The phase modulator 300 further comprises a multiplexer 307. Input terminals of the multiplexer 307 are coupled to output terminals of the plurality of delay circuits 305. For example, the delay chain 303 may comprise M delay circuits 305, and the output terminals of the M delay circuits 305 are connected to respective input terminals of the multiplexer 307. In other words, M delayed versions of the system sampling clock signal f clk , each having the same frequency as the system sampling clock signal f clk , but with different phases, in some embodiments, are sent to input terminals of the multiplexer 307.

[0023] A control terminal 302 of the multiplexer 307 is connected to an output terminal of the random number generator 121 in Fig. 1. The control signal (e.g., random numbers) applied to the control terminal 302 may have N bits, such that N = log2M. In some embodiments, the multiplexer 307 is configured to select a clock signal at one of the input terminals of the multiplexer 307 based on the random numbers at the control terminal 302 and to provide the selected clock signal at an output terminal 309 as the phase-modulated clock signal f clk_jittered The output terminal 309 in Fig. 3A corresponds to the output terminal 124 of the phase modulator 123 in Fig. 1.

[0024] Fig. Figure 3B illustrates the operation of the phase modulator 300 in Fig. 3A in an embodiment. In Fig. 3B, the system sampling clock signal f clk represented by the clock signal 311, which has a period T. In the example of Fig. 3B, it is assumed without loss of generality that the active edges of the system sampling clock signal f clk are the rising edges. One of the rising edges of the system sampling clock signal f clk is marked with an upward-pointing arrow. The delay chain 303 of the phase modulator 300 generates M delayed versions of the system sampling clock signal f clk , each with a different delay (or equivalently a different phase). To avoid confusing the illustration, a plurality of dashed lines 313 are Fig. 3B to show the positions of the rising edges of the M delayed versions of the system sampling clock signal f clk corresponding to the rising edge of the system sampling clock signal f clk, which is marked with the upward-pointing arrow. Based on the random number at the control terminal 302, one of the delayed versions of the system sample clock signal f clk selected and used as the phase-modulated clock signal f clk_jittered used.

[0025] It should be noted that the random number generator 121 generates the random numbers at the same frequency as the frequency of the system sampling clock signal f clk In other words, the random number generator 121 generates for each rising edge in the system sampling clock signal f clk a corresponding random number, and based on this corresponding random number, one of the delayed versions of the system sampling clock signal f clk as the phase-modulated clock signal f clk_jittered As a result, each rising edge of the phase-modulated clock signal f clk_jittereda random phase delay (e.g. jitter) with respect to a respective rising edge of the system sampling clock signal f clk In other words, the phase modulator 300 generates the phase-modulated clock signal f clk_jittered by introducing a random phase delay (e.g. jitter) into each rising edge of the system sampling clock signal f clk .

[0026] In some embodiments, the maximum delay D max the delay chain 303, calculated as D max = M × D, where M is the number of delay circuits 305 and D is the time delay of each delay circuit 305, smaller than the period T of the system sampling clock signal f clk . For example D max < T or D max < T / 2. It should be noted that some of the dashed lines 313 in Fig. 3B earlier than the corresponding rising edge of the system sampling clock signal f clk, which is marked with the upward-pointing arrow, such an apparent “non-causality” can be avoided in the hardware design by delaying the system sampling clock signal f clk and handling the delayed system sampling clock signal f clk as the system sampling clock signal f clk during the injection of the original (non-delayed) system sampling clock signal f clk into the delay chain 303 of the phase modulator 300.

[0027] Fig. 4A illustrates a frequency-to-digital converter (FTD converter) 400 in one embodiment. The FTD converter 400 may be used as the FTD converter 115 in Fig. 1. It should be noted that the VCO 113 is made of Fig. 1 in Fig. 4A to illustrate the connection of the FTD converter 400, with the understanding that the VCO 113 is not part of the FTD converter 400.

[0028] As in Fig. 4A, the FTD converter 400 comprises a counter 401 and a register 403. An input terminal of the counter 401 is connected to the frequency-modulated signal f generated by the VCO 113. vco A RESET terminal of the counter 401 is connected to the phase-modulated clock signal f clk_jittered The counter 401 is configured to count the number of cycles (may also be referred to as oscillator cycles) in the frequency-modulated signal f vco between adjacent active edges (e.g. rising edges or falling edges) of the phase-modulated clock signal f clk_jittered to count.

[0029] The output of counter 401, which is a digital multi-bit signal, is sent to register 403. A clock terminal of register 403 is connected to the phase-modulated clock signal f clk_jitteredThe register 403 is configured to generate the digital multi-bit signal at the output of the counter 401 on active edges of the phase-modulated clock signal f clk_jittered In other words, the digital multi-bit signal at the output of the counter 401 is buffered at the active edges of the phase-modulated clock signal f clk_jittered sampled and the sampled value is output as the digital output signal y[n] of the FTD converter 400.

[0030] Fig. 4B represents an output of the FTD converter Fig. 4A in an embodiment. In Fig. 4B, the signal 410 in the upper part of the diagram represents the output of the VCO 113, which generates the frequency-modulated signal f vco The signal 420 in the middle part of the diagram represents the output of the phase modulator 123, which generates the phase-modulated clock signal f clk_jittered The signal 430 represents the output of the counter 401 in the FTD converter 400. As in Fig. As shown in Figure 4B, the counter output is set on the rising edges of the phase-modulated clock signal f clk_jittered to zero and then increases when the counter 401 counts the cycles in the frequency-modulated signal f vco counts. On the next rising edge, the output signal of counter 401 is latched in register 403 and counter 401 is reset to zero.

[0031] Fig. 5A illustrates a phase modulator 300A in another embodiment. The phase modulator 300A may be used as the phase modulator 123 in Fig. 1. The phase modulator 300A includes a plurality of clock signal generators 511 (e.g., 511_1, 511_2, ..., and 511_M). Each of the clock signal generators 511 generates a clock signal having the same frequency as the system sampling clock signal f clk, but with different duty cycles. The clock signals generated by the clock signal generators 511 are Fig. 5A as f clk1 , f clk2 , ..., f clkM designated.

[0032] Fig. 5B shows the clock generators 511 in Fig. 5A generated clock signals f clk , f clk2 , ..., f clkM in an exemplary embodiment. As in Fig. As shown in Figure 5B, the clock signals f clk , f clk2 , ..., f clkM the same frequency. However, due to the different duty cycles, the active edges (e.g. rising edges) of the clock signals f clk1 , f clk2 , ..., f clkM not aligned, and instead there are time delays between the active edges of the clock signals f clk1 , f clk2 , ..., f clkM .

[0033] With further reference to Fig. 5A, the phase modulator 300A further comprises a multiplexer 517. The output terminals 512 (e.g., 512_1, 512_2, ..., 512_M) of the clock signal generators 511 are connected to the input terminals of the multiplexer 517. A control terminal 516 of the multiplexer is connected to the output terminal of the random number generator 121 in Fig. 1. Similar to the above discussion for the phase modulator 300, the random number generator 121 generates random numbers at the same frequency as the frequency of the system sampling clock signal f clk , so that for each active edge of the system sample clock signal f clk a random number is generated. The random number is used to generate one of the clock signals f clk1 , f clk2 , ..., f clkM and the selected clock signal is output at an output terminal 518 of the multiplexer 517 as the phase-modulated clock signal f clk_jitteredTherefore, the random numbers are used to introduce random delays (e.g., random phase delays or jitter) into the active edges of the system sampling clock signal f clk to introduce the phase-modulated clock signal f clk_jittered to generate.

[0034] During operation of the MEMS microphone system 100, when no sound is applied to the capacitive MEMS microphone 103, the VCO 113 oscillates at a rest frequency determined by the bias voltage V biaswhich sets the operating point of the VCO 113 through the high-value resistor 105. In the event of a mechanical shock or a very strong audio signal, the MEMS membrane of the capacitive MEMS microphone 103 may collapse, and as a result, the VCO 113 is suddenly taken out of the operating point. Given the long time constant imposed by the high-value resistor 105 together with the MEMS capacitance, it may take several seconds for the MEMS microphone 103 to return to the correct bias point.

[0035] Fig. Figure 6 illustrates the output of the MEMS microphone system 100 in response to a mechanical shock or a very strong audio signal in one embodiment. Fig. 6, curve 601 shows the output voltage V g of the capacitive MEMS microphone 103. Curve 603 shows the output signal f vcoof the VCO 113 and the curve 605 shows the digital output signal y[n] of the FTD converter 115. At a time T1, which is indicated by the arrow in Fig. 6, a mechanical shock or a strong audio signal causes the MEMS membrane to temporarily collapse, resulting in the output voltage V g of the capacitive MEMS microphone 103 drops to zero. After time T1, the output voltage V g gradually to the nominal bias point, and as a result the output signal f vco of the VCO 113 also slowly in frequency through a large frequency range.

[0036] During this frequency sweep, the VCO 113 can operate for a few milliseconds at frequencies close to integer multiples (N1, N2, ...) of the frequency of the system sampling clock signal f clk When this happens, a low-frequency tone resulting from the beat between the system sampling clock signal f clkand the VCO output signal f vco results, denoted as f beat = f vco - N i × f clk , fall into the audio band and produce an audible whistling sound. This audible whistling is unpleasant for the listener and should be suppressed. It should be noted that in the above equation for the beat signal f vco and f clk used to denote the frequencies of their respective namesake signals.

[0037] There are various solutions to the problem of audible whistling. The currently disclosed MEMS microphone system 100 offers advantages over other solutions. To appreciate the advantages of the embodiment disclosed here, a reference MEMS microphone system is considered that is similar to the MEMS microphone system 100 in Fig. 1, but without the random number generator 121 and without the phase modulator 123. The reference MEMS microphone system sends the system sampling clock signal fclk to the clock input terminal of the FTD converter 115. To suppress the audible whistling, the reference MEMS microphone system dithers the output signal V g of the MEMS microphone 103 by adding a random, noise-shaped, low-level analog signal to the output signal V g In this way, the VCO 113 is slightly modulated by the random noise, and after sampling using the system sampling clock signal f clk the distorted sound (e.g. the audible whistling) is masked by noise, thereby minimizing the psychoacoustic effect of the sound.

[0038] However, the above dither solution for the reference MEMS microphone system has many disadvantages. For example, it requires a digital-to-analog converter (DAC) to generate the analog random noise signal, and the DAC may also require a coupling circuit to the highly sensitive input node of the reference MEMS microphone system, which can degrade the sensitivity and overall noise budget. In addition, the dither solution reduces the dynamic range of the MEMS microphone because a noise signal is always present in the reference MEMS microphone system during operation. Furthermore, the dither solution requires a spectrally shaped white noise generator.

[0039] The embodiment disclosed here is based on the observation that low-frequency tones (e.g., audible whistling) do not occur in the VCO 113 itself, but rather in the sampling process. The dither solution modulates the VCO 113 with an analog white noise signal to attenuate the low-frequency tones during sampling. In contrast, the embodiment disclosed here does not alter the operation of the VCO 113, but samples the output of the FTD converter 115 with a clock signal (e.g., f clk_jittered), the phase of which has been intentionally modulated by a random sequence. In the illustrated embodiment, the random number generator 121 introduces random errors into the digital output signal y[n] of the MEMS microphone system 100 through the phase modulator 123. These errors decorrelate the sweeping VCO frequency with the system sampling clock, which has the effect of randomizing the whistling, which now appears as noise. The errors introduced by modulating the phase of the system sampling clock signal result in a noise-shaped first-order error sequence at the output of the FTD converter 115, independent of the spectral content of the random sequence. Therefore, the embodiment disclosed here avoids the disadvantages of the dither solution of the reference MEMS microphone system, thereby suppressing the audible whistling without adversely affecting the sensitivity, overall noise budget, and dynamic range of the MEMS microphone system.In addition, no DAC circuit or noise shaping circuit is required for the disclosed embodiment, thereby saving production costs and power consumption.

[0040] Fig. 7A and Fig. 7B illustrate the performance of the disclosed MEMS microphone system 100 in one embodiment. The disclosed VCO-ADC is implemented in an application-specific integrated circuit (ASIC) and tested in a MEMS microphone system with a capacitive MEMS microphone. Fig. 7A and Fig. 7B shows the obtained ASIC level noise compared to a system clock sweep when no sound signal is applied to the capacitive MEMS microphone. For comparison, Fig. 7A and Fig. 7B the performance of the MEMS microphone system without and with the phase jitter added to the system sampling clock signal f clk . In Fig. 7A and Fig. 7B, the x-axis shows the sweep range of the system sampling clock signal f clk The y-axis shows the integrated noise in the application bandwidth (which in this case is the audio bandwidth) at the ASIC output, measured in dBFS for each sampling frequency in the frequency sweep range. Fig. 7A, the clock jitter (e.g. phase jitter) is not applied, and the system sampling clock signal f clk is sent to the clock input terminal of the FTD converter 115. In Fig. 7B, the clock jitter is applied using the phase modulator 123 and the random number generator 121 to generate the phase-modulated clock signal f clk_jettered and the phase-modulated clock signal f clk_jettered is sent to the clock input terminal of the FTD converter 115.

[0041] In Fig. 7A, it is observed that for certain values ​​of the system sampling clock frequency, noise peaks occur (e.g., due to an integer multiple relationship between fvco and f clk , as mentioned previously) if no phase jitter is applied. In Fig. 7B when the jitter is added to the phase of the system sampling clock signal f clk is added, the noise peaks are significantly attenuated. Therefore, the possible audible whistling caused by a microphone shock or a strong audio signal is suppressed by the disclosed embodiment.

[0042] Fig. Figure 8 illustrates the performance of the disclosed MEMS microphone system 100 in another embodiment. Fig. Figure 8 shows the obtained ASIC level noise compared to the input signal level. In the test of Fig. 8, an input signal (e.g., a 1 kHz tone) is applied to the capacitive MEMS microphone input. A defined system sampling clock frequency is set. The input signal level is swept from 40 dBSPL to 130 dBSPL. The integrated noise in the application bandwidth (which in this case is the audio bandwidth) at the ASIC output is measured in dBFS for each input signal level. The measured noise level at the VCO-ADC output (e.g., the digital output of the FTD converter 115) represents the noise contribution from various noise sources, such as flicker noise, thermal noise, or the like. Fig. 8, curve 803 shows the measured noise level when the phase jitter is not added to the system sampling clock signal f clk is added, and curve 801 shows the measured noise level when the jitter is added to the system sampling clock signal f clk is added. From Fig. 8 it is observed that curves 801 and 803 overlap above the normal operating range for the input signal level and there are only some differences between curves 801 and 803 at extremely large input signal levels that are outside the normal operating range. Therefore, Fig. 8, that adding the phase jitter to the system sampling clock signal f clk using the disclosed circuit has a negligible effect on the measured noise level over the normal operating range.

[0043] Fig. 9 illustrates a flowchart of a method 1000 for operating a MEMS microphone system in one embodiment. It is understood that the Fig. 9 is merely one example of many possible embodiments. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as shown in Fig. 9 may be displayed, added, removed, replaced, rearranged or repeated.

[0044] With reference to Fig.9, at block 1010, a voltage signal is generated by a MEMS microphone in response to an acoustic signal. At block 1020, a frequency-modulated signal having a frequency proportional to the voltage signal is generated by a voltage-controlled oscillator (VCO) coupled to the MEMS microphone. At block 1030, the frequency-modulated signal is converted to a digital signal by a frequency-to-digital converter (FTD converter) coupled to the VCO. At block 1040, random numbers are generated by a random number generator. At block 1050, a phase of a system sampling clock signal is modulated by a phase modulator according to the random numbers to generate a phase-modulated clock signal. At block 1060, the digital signal is sampled by the phase-modulated clock signal to generate a digital output signal of the FTD converter.

[0045] Embodiments may achieve advantages as described below. The disclosed VCO-ADC circuit with phase modulator can be implemented as a compact, all-digital circuit, and there is no need to disturb the sensitive analog circuitry of the MEMS interface. The dynamic range of the VCO-ADC circuit is not affected by the injection of random phase jitter into the system sample clock signal. The random sequence generated by the random number generator does not need to be noise-shaped, and therefore a simple random number generator, such as an LFSR register, is sufficient. Compared to the dither solution, the disclosed embodiment achieves reduced area and power consumption.

[0046] Examples of the present invention are summarized herein. Other examples may also be understood from the entirety of the specification and claims filed herein.

[0047] Example 1. In one embodiment, a circuit comprises: a capacitive microelectromechanical system (MEMS) microphone configured to output a voltage signal in response to a sound signal, and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC) coupled to the capacitive MEMS microphone and configured to generate a digital output signal proportional to the voltage signal, wherein the VCO-ADC comprises: a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone and configured to output a frequency-modulated signal having a frequency proportional to the voltage signal, a frequency-to-digital converter (FTD) coupled to an output terminal of the VCO, a random number generator configured to generate random numbers, and a phase modulator configured toto generate a phase-modulated clock signal by modulating a phase of a system sampling clock signal with the random numbers, wherein the FTD converter is configured to generate a digital signal according to the frequency-modulated signal and the phase-modulated clock signal, and is configured to generate the digital output signal of the FTD converter by sampling the digital signal using the phase-modulated clock signal.

[0048] Example 2. The circuit of Example 1, further comprising: an input stage circuit coupled between a first terminal of the capacitive MEMS microphone and the VCO, a resistor coupled between the first terminal of the capacitive MEMS microphone and a node, the node configured to receive a bias voltage for the capacitive MEMS microphone, and a charge pump circuit coupled to a second terminal of the capacitive MEMS microphone.

[0049] Example 3. The circuit of example 1, wherein the phase-modulated clock signal has a same frequency as the system sampling clock signal, wherein active edges of the phase-modulated clock signal are shifted from respective active edges of the system sampling clock signal by a different time duration according to the random numbers.

[0050] Example 4. The circuit of example 3, wherein the random number generator is configured to generate the random numbers at a frequency of the phase-modulated clock signal.

[0051] Example 5. The circuit of example 3, wherein the FTD converter comprises a counter configured to count the number of cycles in the frequency-modulated signal between adjacent active edges of the phase-modulated clock signal, the digital signal generated by the FTD converter being the output of the counter.

[0052] Example 6. The circuit of Example 5, wherein the phase modulator comprises: a delay chain comprising a plurality of delay circuits connected in series, wherein an input terminal of the delay chain is coupled to the system sample clock signal, and a multiplexer, wherein input terminals of the multiplexer are coupled to output terminals of the plurality of delay circuits, wherein a control terminal of the multiplexer is coupled to an output terminal of the random number generator, wherein the multiplexer is configured to select a clock signal at one of the input terminals of the multiplexer as the phase-modulated clock signal based on the random numbers at the control terminal.

[0053] Example 7. The circuit of Example 5, wherein the phase modulator comprises: a plurality of clock signal generators configured to generate a plurality of clock signals, wherein the plurality of clock signals have a same frequency as the system sampling clock signal but different duty cycles, and a multiplexer, wherein input terminals of the multiplexer are coupled to output terminals of the plurality of clock signal generators, wherein a control terminal of the multiplexer is coupled to an output terminal of the random number generator, wherein the multiplexer is configured to select a clock signal at one of the input terminals of the multiplexer as the phase-modulated clock signal based on the random numbers at the control terminal.

[0054] Example 8. In one embodiment, a circuit comprises: a capacitive microelectromechanical system (MEMS) microphone configured to generate a voltage signal in response to an acoustic signal, a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone, the VCO configured to generate a frequency-modulated signal having a frequency proportional to the voltage signal, a frequency-to-digital converter (FTD) converter coupled to an output terminal of the VCO, a random number generator configured to generate random numbers, and a phase modulator configured to generate a phase-modulated clock signal by modulating a phase of a system sampling clock signal according to the random numbers, the FTD converter configured to generate a digital signal according to the frequency-modulated signal and the phase-modulated clock signal, and configuredto sample the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter.,

[0055] Example 9. The circuit of Example 8, wherein the capacitive MEMS microphone comprises a capacitor.

[0056] Example 10. The circuit of Example 9, further comprising: a source follower circuit coupled between a first terminal of the capacitive MEMS microphone and the VCO, a charge pump circuit coupled to a second terminal of the capacitive MEMS microphone, and a resistor coupled between the first terminal of the capacitive MEMS microphone and a node, the node configured to receive a bias voltage for the capacitive MEMS microphone.

[0057] Example 11. The circuit of example 8, wherein the phase modulator is configured to generate the phase-modulated clock signal by shifting active edges of the system sample clock signal by a different amount of time determined by the random numbers.

[0058] Example 12. The circuit of Example 11, wherein the FTD converter is configured to generate the digital signal by counting the number of cycles in the frequency-modulated signal between adjacent active edges of the phase-modulated clock signal.

[0059] Example 13. The circuit of example 12, wherein the random number generator is configured to generate the random numbers at a frequency equal to a frequency of the system sample clock signal.

[0060] Example 14. The circuit of Example 8, wherein the phase modulator is configured to generate the phase-modulated clock signal by selecting, from a plurality of candidate clock signals having a same frequency as the system sampling clock signal but different duty cycles, a candidate clock signal as the phase-modulated clock signal on active edges of the system sampling clock signal based on the random numbers.

[0061] Example 15. The circuit of example 14, wherein the random number generator is configured to generate a random number for a respective active edge of the system sample clock signal.

[0062] Example 16. The circuit of Example 15, wherein the random number generator is a linear feedback shift register (LFSR) random number generator.

[0063] Example 17. In one embodiment, a method of operating a microelectromechanical system (MEMS) microphone system comprises the steps of: generating, by a MEMS microphone, a voltage signal responsive to an acoustic signal, generating, by a voltage-controlled oscillator (VCO) coupled to the MEMS microphone, a frequency-modulated signal having a frequency proportional to the voltage signal, converting, by a frequency-to-digital converter (FTD) converter coupled to the VCO, the frequency-modulated signal into a digital signal, generating, by a random number generator, random numbers, modulating, by a phase modulator, a phase of a system sampling clock signal according to the random numbers to generate a phase-modulated clock signal, and sampling the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter.

[0064] Example 18. The method of example 17, wherein the modulating comprises shifting, by the phase modulator, active edges of the system sample clock signal by a different amount of time determined by the random numbers.

[0065] Example 19. The method of example 18, wherein converting comprises counting, by a counter of the FTD converter, the number of cycles in the frequency-modulated signal between adjacent active edges of the phase-modulated clock signal.

[0066] Example 20. The method of example 19, wherein generating the random number comprises generating, by the random number generator, the random numbers at a frequency same as a frequency of the system sample clock signal.

[0067] Although this invention has been described with reference to illustrative examples, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative examples, as well as other examples of the invention, will become apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass such modifications or examples.

Claims

[1] A circuit having the following features: a capacitive microelectromechanical system (MEMS) microphone configured to output a voltage signal in response to a sound signal, and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC) coupled to the capacitive MEMS microphone and configured to generate a digital output signal proportional to the voltage signal, the VCO-ADC having the following features: a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone and configured to output a frequency-modulated signal having a frequency proportional to the voltage signal, a frequency-to-digital converter (FTD converter) coupled to an output terminal of the VCO, a random number generator configured to generate random numbers, and a phase modulator configured to generate a phase-modulated clock signal by modulating a phase of a system sampling clock signal with the random numbers, wherein the FTD converter is configured to generate a digital signal according to the frequency-modulated signal and the phase-modulated clock signal, and is configured to generate the digital output signal of the FTD converter by sampling the digital signal using the phase-modulated clock signal. [2] The circuit according to claim 1, further comprising: an input stage circuit coupled between a first terminal of the capacitive MEMS microphone and the VCO, a resistor coupled between the first terminal of the capacitive MEMS microphone and a node, the node being configured to receive a bias voltage for the capacitive MEMS microphone, and a charge pump circuit coupled to a second terminal of the capacitive MEMS microphone. [3] The circuit according to claim 1 or 2, wherein the phase-modulated clock signal has a same frequency as the system sampling clock signal, wherein active edges of the phase-modulated clock signal are shifted from respective active edges of the system sampling clock signal by a different time duration according to the random numbers. [4] The circuit of claim 3, wherein the random number generator is configured to generate the random numbers at a frequency of the phase-modulated clock signal. [5] The circuit of claim 3 or 4, wherein the FTD converter comprises a counter configured to count the number of cycles in the frequency-modulated signal between adjacent active edges of the phase-modulated clock signal, the digital signal generated by the FTD converter being the output of the counter. [6] The circuit according to claim 5, wherein the phase modulator has the following features: a delay chain comprising a plurality of delay circuits connected in series, an input terminal of the delay chain being coupled to the system sampling clock signal, and a multiplexer, wherein input terminals of the multiplexer are coupled to output terminals of the plurality of delay circuits, wherein a control terminal of the multiplexer is coupled to an output terminal of the random number generator, wherein the multiplexer is configured to select a clock signal at one of the input terminals of the multiplexer as the phase-modulated clock signal based on the random numbers at the control terminal. [7] The circuit according to claim 5 or 6, wherein the phase modulator has the following features: a plurality of clock signal generators configured to generate a plurality of clock signals, wherein the plurality of clock signals have a same frequency as the system sampling clock signal but different duty cycles, and a multiplexer, wherein input terminals of the multiplexer are coupled to output terminals of the plurality of clock signal generators, wherein a control terminal of the multiplexer is coupled to an output terminal of the random number generator, wherein the multiplexer is configured to select a clock signal at one of the input terminals of the multiplexer as the phase-modulated clock signal based on the random numbers at the control terminal. [8] A circuit having the following features: a capacitive microelectromechanical system (MEMS) microphone configured to generate a voltage signal in response to a sound signal, a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone, the VCO configured to generate a frequency-modulated signal having a frequency proportional to the voltage signal, a frequency-to-digital converter (FTD converter) coupled to an output terminal of the VCO, a random number generator configured to generate random numbers, and a phase modulator configured to generate a phase-modulated clock signal by modulating a phase of a system sampling clock signal according to the random numbers, wherein the FTD converter is configured to generate a digital signal according to the frequency-modulated signal and the phase-modulated clock signal, and is configured to sample the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter. [9] The circuit of claim 8, wherein the capacitive MEMS microphone comprises a capacitor. [10] The circuit according to claim 9, further comprising: a source follower circuit coupled between a first terminal of the capacitive MEMS microphone and the VCO, a charge pump circuit coupled to a second terminal of the capacitive MEMS microphone, and a resistor coupled between the first terminal of the capacitive MEMS microphone and a node, the node configured to receive a bias voltage for the capacitive MEMS microphone. [11] The circuit of any one of claims 8 to 10, wherein the phase modulator is configured to generate the phase-modulated clock signal by shifting active edges of the system sample clock signal by a different time period determined by the random numbers. [12] The circuit of claim 11, wherein the FTD converter is configured to generate the digital signal by counting the number of cycles in the frequency-modulated signal between adjacent active edges of the phase-modulated clock signal. [13] The circuit of claim 12, wherein the random number generator is configured to generate the random numbers at a frequency equal to a frequency of the system sampling clock signal. [14] The circuit according to any one of claims 8 to 13, wherein the phase modulator is configured to generate the phase-modulated clock signal by selecting, from a plurality of candidate clock signals having a same frequency as the system sampling clock signal but different duty cycles, a candidate clock signal as the phase-modulated clock signal at active edges of the system sampling clock signal based on the random numbers. [15] The circuit of claim 14, wherein the random number generator is configured to generate a random number for a respective active edge of the system sample clock signal. [16] The circuit of claim 15, wherein the random number generator is a linear feedback shift register (LFSR) random number generator. [17] A method of operating a microelectromechanical system (MEMS) microphone system, the method comprising the steps of: Generating, by a MEMS microphone, a voltage signal in response to a sound signal, Generating, by a voltage-controlled oscillator (VCO) coupled to the MEMS microphone, a frequency-modulated signal with a frequency proportional to the voltage signal, Converting, by a frequency-to-digital converter (FTD converter) coupled to the VCO, the frequency-modulated signal into a digital signal, Generating, by a random number generator, random numbers, Modulating, by a phase modulator, a phase of a system sampling clock signal according to the random numbers to generate a phase-modulated clock signal, and Sampling the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter. [18] The method of claim 17, wherein the modulating comprises shifting, by the phase modulator, active edges of the system sample clock signal by a different time duration determined by the random numbers. [19] The method of claim 18, wherein converting comprises counting, by a counter of the FTD converter, the number of cycles in the frequency-modulated signal between adjacent active edges of the phase-modulated clock signal. [20] The method of claim 19, wherein generating the random number comprises generating, by the random number generator, the random numbers at a frequency same as a frequency of the system sampling clock signal.

Images