Isolation structure with layout to increase image sensitivity performance

Abstract

Various embodiments of the present disclosure relate to an integrated chip (IC). The IC comprises a first pixel region, which includes a first photodetector in a substrate. A second pixel region, which includes a second photodetector, is located in the substrate and adjacent to the first pixel region. An isolation structure in the substrate comprises a first isolation structure element between the first and the second pixel regions. In a top view, the first isolation structure element comprises a first pair of opposing straight sidewall segments and a first pair of opposing curved sidewall segments adjacent to the first pair of opposing straight sidewall segments. A first distance between the first pair of opposing straight sidewall segments is greater than a second distance between the first pair of opposing curved sidewall segments.

Description

REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority over the preliminary US patent application No. 63 / 703,347 filed on October 4, 2024, the contents of which are hereby incorporated in full into the present text by reference. BACKGROUND

[0002] Many modern electronic devices (for example, digital cameras, optical imaging devices, etc.) incorporate image sensors. An image sensor comprises an array of pixel regions, and each pixel region has a photodiode configured to capture optical signals (for example, light) and convert them into digital data (for example, a digital image). Complementary metal-oxide-semiconductor (CMOS) image sensors are often used instead of CCD image sensors due to their many advantages, such as lower power consumption, faster data processing, and lower manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. The figures were drawn to clearly illustrate relevant aspects of the embodiments. The figures may illustrate relationships between different structures and / or elements within the embodiments. It should be noted that the figures are not necessarily drawn to scale. In some cases, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in the discussion. Fig. Figures 1A-1C illustrate different views of some embodiments of an image sensor comprising multiple pixel regions and an isolation structure with a layout designed to enhance the performance of the image sensor. Fig. Figures 2A-2C illustrate different views of some other embodiments of the image sensor. Fig. 1A-1C. Fig. Figure 3 illustrates a top view of some other embodiments of the image sensor of Fig. 2A. Fig. Figure 4 illustrates a cross-sectional view of some embodiments of the image sensor of Fig. 3 along line AA' from Fig. 3. Fig. Figure 5 illustrates a top view of some other embodiments of the image sensor. Fig. 1A-1C. Fig. Figure 6 illustrates a cross-sectional view of some embodiments of the image sensor of Fig. 5 along line AA' from Fig. 5. Fig. Figures 7-15 illustrate various views of some embodiments of a method for forming an image sensor comprising multiple pixel regions and an isolation structure with a layout designed to enhance the performance of the image sensor. Fig. Figure 16 illustrates a flowchart according to some embodiments of a method for forming an image sensor comprising multiple pixel regions and an isolation structure with a layout designed to enhance the performance of the image sensor. DETAILED DESCRIPTION

[0004] The present disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or facilities discussed.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.In some embodiments, the terms "approximately" and / or "about" can be interpreted as + / - 10% or + / - 5%, while in other embodiments, the terms "approximately" and / or "about" can be interpreted as being within the normal manufacturing tolerances of a given Fab production flow.

[0006] An integrated circuit (IC) can include an image sensor with multiple pixel regions arranged in an array. Each pixel region includes a photodetector (for example, a photodiode) located within a substrate and configured to convert incident radiation (for example, visible light) into charge carriers. The converted charge carriers can be transferred to a potential-free diffusion node in the substrate to enable digital readout of the incident radiation. Multiple pixel regions can share a potential-free diffusion node, with the node located at the intersection of adjacent pixel regions.For example, the image sensor comprises several pixel sensor units, each of which can have a shared two-by-two-pixel layout, with a potential-free diffusion node located in a central region of four adjacent photodetectors.

[0007] An isolation structure is positioned within the substrate between adjacent pixel regions and is designed to mitigate optical and electrical crosstalk between these regions. Forming the isolation structure may involve: performing an etching process on a back face of the substrate to create a trench extending into the substrate between the pixel regions, and depositing the isolation structure within that trench. In a top view, the isolation structure exhibits a grid layout, with sidewalls of the isolation structure defining a portion of each pixel region.

[0008] In an attempt to increase the sensor area of ​​the image sensor and improve device density, the width of the trench between adjacent pixel regions is reduced. As a result, the area available to the photodetector of each pixel region is increased, and the distance between adjacent pixel regions is reduced. However, reducing the trench width can increase the dark current and / or the number of white pixels in the image sensor. For example, the isolation structure can include a first isolation structure segment located in a first trench segment aligned with the potential-free diffusion node, and a second isolation structure segment located in a second trench segment surrounding the pixel regions. The first isolation structure segment can have a first depth, and the second isolation structure can have a second depth greater than the first.Reducing the width of the first trench segment between adjacent pixel regions, in which the first insulation structure segment is located, can lead to variations in the etchant flow (e.g., due to etching stress) during the etching process at the intersection of adjacent pixel regions for each pixel sensor unit. As a result, the substrate may be over-etched in a region aligned with the center of each potential-free diffusion node, while raised sections of the substrate remain at the intersection of adjacent pixel regions. These raised sections provide a path for charge carrier flow (e.g., electrons), thereby increasing the leakage current. Furthermore, a polymer can be used during the etching process to mitigate damage to the substrate's sidewalls.However, if the width of the trench is reduced, polymer can accumulate in regions of deeper segments of the second trench segment at an intersection between adjacent pixel sensor units. As a result, the substrate can develop multiple protrusions around the deeper segments of the trench, providing additional pathways for charge carrier flow between pixel regions and further increasing leakage current. Consequently, problems with dark current and / or white pixels on the image sensor can be exacerbated, thus reducing the overall performance of the IC.

[0009] In various embodiments, the present application relates to an IC comprising an image sensor, wherein the image sensor includes an isolation structure with a layout configured to improve the performance of the image sensor. The image sensor comprises multiple pixel sensor units arranged on a substrate. Each pixel sensor unit can have multiple pixel regions and a potential-free diffusion node at an intersection of the multiple pixel regions. The isolation structure is arranged in a trench defined by the sidewalls of the substrate and comprises a first isolation structure segment with a first depth and a second isolation structure segment with a second depth greater than the first depth. The first isolation structure segment is arranged at the intersection of the multiple pixel regions of an individual pixel sensor unit.The first isolation structure segment comprises several curved sidewall segments facing each other at the intersection, and straight sidewall segments connected to the curved sidewall segments. The first lateral distance between opposing straight sidewalls within the multiple straight sidewall segments is greater than the second lateral distance directly between adjacent curved sidewall segments within the multiple curved sidewall segments. Because of the first isolation structure, which includes both curved and straight sidewall segments, etchants used during the etching process to create the trench in the substrate can flow more evenly at the intersection of the multiple pixel regions. This mitigates or prevents problems caused by the etching stress at the intersection of the multiple pixel regions of each pixel sensor unit, thereby reducing leakage current in the image sensor.Furthermore, the second insulation structure segment features several curved sidewall segments facing each other at the intersections of the multiple pixel regions. The layout of these curved sidewall segments is designed to mitigate polymer buildup at the intersections of the multiple pixel regions during the etching process. As a result, leakage current in the image sensor is further reduced, thereby improving the overall performance of the image sensor.

[0010] Fig. Figures 1A-1C illustrate different views 100a-100c of some embodiments of an image sensor comprising multiple pixel regions 104 and an isolation structure 112, having first isolation structure segments 114 and a second isolation structure segment 116, with a layout designed to increase the performance of the image sensor. Fig. Figure 1A illustrates a top view 100a of the image sensor from a rear surface 102b of a substrate 102. Fig. Figure 1B illustrates a cross-sectional view 100b along line AA' of the top view 100a of Fig. 1A. Fig. 1C illustrates a cross-sectional view 100c along line BB' of the top view 100a of Fig. 1A.

[0011] As shown in the top view 100a of Fig. As shown in Figure 1A, the image sensor comprises multiple pixel sensor units 103 arranged on a substrate 102. In some embodiments, the pixel sensor units 103 each have a shared pixel layout structure and comprise multiple pixel regions 104 and a potential-free diffusion node 108 located at an intersection of the multiple pixel regions 104. The multiple pixel regions 104 each comprise an individual photodetector 106 located in the substrate 102. For example, the multiple pixel sensor units 103 comprise a first pixel sensor unit 103a, which has a first plurality of pixel regions 104a-d. The first plurality of pixel regions 104a-d comprises a first pixel region 104a, a second pixel region 104b, a third pixel region 104c, and a fourth pixel region 104d.The second pixel region 104b is located diagonally opposite the first pixel region 104a, and the third pixel region 104c is located diagonally opposite the fourth pixel region 104d. It can be seen that the potential-free diffusion nodes 108 and the photodetectors 106 are located in the top view 100a of . Fig. 1A are shown in phantom lines for easier illustration.

[0012] The substrate 102 can be, for example, silicon, CMOS bulk material, silicon-germanium, silicon-on-insulator (SOI), or another suitable semiconductor material. The substrate 102 can have a first doping type (for example, p-type). In some embodiments, the photodetectors 106 are or comprise a doped region in the substrate 102 with a second doping type (for example, n-type) opposite to the first doping type (for example, p-type). In various embodiments, the first doping type is p-type, and the second doping type is n-type, or vice versa. The potential-free diffusion nodes 108 have the second doping type (for example, n-type) and are each arranged at the center and / or intersection of a corresponding pixel sensor unit 103.

[0013] The isolation structure 112 is arranged within the substrate 102 between adjacent pixel regions 104. The isolation structure 112 is configured to enhance the electrical and optical isolation between the pixel regions 104 across the image sensor. In some embodiments, the substrate 102 comprises side walls that define a trench located within the substrate 102 between the adjacent pixel regions 104, with the isolation structure 112 positioned within the trench. The isolation structure 112 comprises a plurality of first isolation structure segments 114 and a second isolation structure segment 116. The first isolation structure segments 114 are arranged at a corresponding intersection of the multiple pixel regions 104 of each pixel sensor unit 103. The second isolation structure segment 116 is arranged on opposite sides of each of the first isolation structure segments 114 and is positioned between adjacent pixel regions 104.In some embodiments, the second insulation structure segment 116 extends continuously laterally around an outer circumference of each pixel sensor unit in the multiple pixel sensor units 103. In various embodiments, the first insulation structure segments 114 have a first depth (for example, d1 of ). Fig. 1B), and the second insulation structure segment 116 has a second depth (for example, d2 of Fig. 1B), which is greater than the first depth. In some embodiments, the isolation structure 112 can be referred to as a dual deep trench isolation structure (DTI structure), the first isolation structure segments 114 can be referred to as partial deep trench isolation structures (PDTI structures) or PDTI segments, and the second isolation structure segment 116 can be referred to as a full deep trench isolation structure (FDTI structure) or FDTI segment.

[0014] As can be seen at the intersection of the first plurality of pixel regions 104a-d of the first pixel sensor unit 103a, the substrate 102 comprises curved sidewall segments projecting from a corresponding pixel region in the first plurality of pixel regions 104a-d toward the potential-free diffusion node 108. The first isolation structure segment 114 has several curved sidewall segments 150 that follow the shape of the curved sidewall segments of the substrate 102. The shape, position, and / or size of the several curved sidewall segments 150 of the first isolation structure segment 114 are configured to reduce the distance between diagonally separated pixel regions in the first plurality of pixel regions 104a-d in a region oriented toward the potential-free diffusion node 108.For example, the multiple curved sidewall segments 150 are configured to reduce a first diagonal distance 141 between the first pixel region 104a and the second pixel region 104b. Furthermore, the first isolation structure segment 114 comprises a first pair of opposing straight sidewall segments 152, 154, which extend elongated in a first direction (for example, along the y-axis) and are separated from each other by a first lateral distance 140 that is greater than a lateral distance 139 between directly adjacent curved sidewall segments in the multiple curved sidewall segments 150.The first insulation structure segment 114 comprises a second pair of opposing straight side wall segments 156, 158, which extend elongately in a second direction (for example, along the x-axis) and are separated from each other by a second lateral distance 144, which is greater than a lateral distance 142 between other directly adjacent curved side wall segments in the multiple curved side wall segments 150. In some embodiments, the first direction (for example, along the y-axis) is orthogonal to, or substantially orthogonal to, the second direction (for example, along the x-axis).

[0015] By reducing the first diagonal distance 141 and increasing the first and second lateral distances 140, 144 compared to another isolation structure (not shown) with sidewalls that define a simple rectangular shape in plan view over an individual pixel region, one or more etchants used to form the trench in the substrate 102 can flow more uniformly at the intersection of the first plurality of pixel regions 104a-d. As a result, the etching of the substrate 102 at the intersection of the multiple pixel regions 104 of each of the pixel sensor units 103 across the image sensor can be more uniform and / or easier to control. This partially reduces one or more leakage current paths in the substrate 102 between the pixel regions 104, thereby reducing problems caused by dark current and / or white pixels and improving the dynamic range of the image sensor.

[0016] As can be seen at an intersection 160 of the multiple pixel sensor units 103, the substrate 102 comprises other curved sidewall segments projecting from a corresponding pixel region of the multiple pixel sensor units 103. The second isolation structure segment 116 comprises curved sidewall segments 162 that follow the shape of the other curved sidewall segments of the substrate 102. The shape, position, and / or size of the curved sidewall segments 162 of the second isolation structure segment 116 are configured to increase a distance between diagonally separated pixel regions in the multiple pixel sensor units 103. For example, the multiple curved sidewall segments 162 of the second isolation structure segment 116 are configured to increase a second diagonal distance 164 between the second pixel region 104b and a diagonally separated pixel region 104 of another pixel sensor unit 103.By increasing the second diagonal distance 164, it is less likely that a polymer used during the etching process, which serves to form the trench in the substrate 102, will accumulate at the intersection 160 of the multiple pixel sensor units 103. Accordingly, the substrate 102 can be etched more uniformly at the intersection 160 of the multiple pixel sensor units 103, further reducing leakage current paths in the substrate 102 between the pixel regions 104. This further reduces problems caused by dark current and / or white pixels and further improves the dynamic range of the image sensor. Thus, thanks to the isolation structure 112, the layout as shown in the top view 100a of [reference missing] can be used. Fig. 1A is set up and / or illustrated, structural element sizes of the pixel sensor units 103 are reduced, while a leakage current in the image sensor is reduced, thereby increasing the overall performance of the image sensor.

[0017] In various embodiments, the multiple pixel regions 104 are arranged in an array comprising multiple columns and multiple rows. Inner sidewalls of the isolation structure 112 bound and / or define the outer perimeters of each of the pixel regions 104. The trench of the substrate 102 comprises a first elongated trench segment 107a extending along the first direction (for example, along the y-axis) between a first column and a second column of the array of pixel regions 104. The width of the first isolation structure segment 114 within the first elongated trench segment 107a and on opposite sides of the potential-free diffusion node 108 is equal to the first lateral distance 140. In various embodiments, the first lateral distance 140 is greater than the lateral distance 139 between curved sidewall segments 150 of the first isolation structure segment 114 within the first elongated trench segment 107a.In further embodiments, the first lateral distance 140 is greater than a lateral distance 143 between opposing side wall segments of the second insulation structure segment 116 in the first elongated trench segment 107a. In some embodiments, the first lateral distance 140 lies within a range of about 80 to 240 nanometers (nm), within a range of about 240 to 400 nm, within a range of about 80 to 400 nm, or has another suitable value.

[0018] The trench of the substrate 102 comprises a second elongated trench segment 107b, which extends along the second direction (for example, along the x-axis) between a first row and a second row of the array of pixel regions 104. The width of the first isolation structure segment 114 in the second elongated trench segment 107b and on opposite sides of the potential-free diffusion node 108 is equal to the second lateral distance 144. In various embodiments, the second lateral distance 144 is greater than the lateral distance 142 between curved side wall segments 150 of the first isolation structure segment 114 in the second elongated trench segment 107b and is greater than a lateral distance 145 between opposite side wall segments of the second isolation structure segment 116 in the second elongated trench segment 107b.In some embodiments, the second lateral distance 144 lies within a range of approximately 80 to 240 nm, within a range of approximately 240 to 400 nm, within a range of approximately 80 to 400 nm, or has another suitable value. In further embodiments, the first lateral distance 140 is greater than the second lateral distance 144, which can help reduce problems associated with etching stress while increasing the read area of ​​the pixel regions 104, thereby increasing the full-well capacity of the photodetectors 106. In still further embodiments, the first lateral distance 140 is equal to the second lateral distance 144, which can help reduce problems associated with etching stress while decreasing design complexity.

[0019] In various embodiments, the first diagonal distance 141 between diagonally separated pairs of curved sidewall segments in the first plurality of curved sidewall segments 150 lies within a range of approximately 100 to 250 nm, within a range of approximately 250 to 400 nm, within a range of approximately 100 to 400 nm, or has another suitable value. In some embodiments, the first plurality of curved sidewall segments 150 is configured to reduce the first diagonal distance 141, which mitigates etch variation at the intersection of the first plurality of pixel regions 104a-d and increases a read area of ​​the pixel regions 104, thereby improving etch control and increasing the overall performance of the image sensor. In various embodiments, the first diagonal distance 141 can be greater than the first lateral distance 140 and / or greater than the second lateral distance 144.This can partially support the improvement of etch control at the intersection of the first majority of pixel regions 104a-d, while simultaneously ensuring that the first isolation structure segment is sufficiently wide to possess good structural integrity and reduce damage (e.g., delamination and / or cracking) to the isolation structure 112.

[0020] The trench of the substrate 102 includes a third elongated trench segment 107c extending along the first direction (for example, along the y-axis) between the second column and a third column of the array of pixel regions 104. In some embodiments, the width of the second isolation structure segment 116 in the third elongated trench segment 107c and on opposite sides of the intersection 160 of the multiple pixel sensor units 103 is equal to the third lateral distance 166. In some embodiments, the third lateral distance 166 is less than a distance 170 between the second plurality of curved sidewall segments 162 of the second isolation structure segment 116 along the third elongated trench segment 107c. This can partially support the increase of the second diagonal distance 164 between diagonally separated pixel regions 104 along the third elongated trench segment 107c.As a result, etchants can flow more uniformly at intersection 160, and it is less likely that a polymer used during the etching process, which serves to form the trench in the substrate 102, will accumulate at intersections of pixel regions 104 along the third elongated trench segment 107c, further increasing etch uniformity across the substrate 102. Accordingly, leakage current paths in the substrate 102 between pixel regions 104 can be further reduced, further decreasing leakage current across the image sensor and further increasing the overall performance of the image sensor.

[0021] The second diagonal distance 164 can, for example, be within a range of approximately 120 to 200 nm, within a range of approximately 200 to 480 nm, or within a range of approximately 120 to 480 nm, or have another suitable value. In some embodiments, the second diagonal distance 164 is greater than the first diagonal distance 141. Because the second isolation structure segment 116 has a greater depth than the first isolation structure segment 114, the polymer used during the etching process may be more prone to accumulating at the intersection 160 in the greater depth of the second isolation structure segment 116.Thus, in some embodiments, the fact that the second diagonal distance 164 is larger than the first diagonal distance 141 mitigates etching variation near the potential-free diffusion node and reduces polymer accumulation at the intersection 160 during the etching process, while maximizing and / or enlarging the read areas of the pixel regions 104. In further embodiments, the third lateral distance 166 is smaller than the first lateral distance 140 and / or the second lateral distance 144. In still other embodiments, the shapes and / or sizes of the curved sidewall segments 150 of the first insulation structure segment 114 differ from the shapes and / or sizes of the curved sidewall segments 162 of the second insulation structure segment 116.

[0022] As shown in cross-sectional views 100b and 100c of Fig. 1B and Fig. 1C along lines AA' and BB' in Fig. As illustrated in Figure 1A, several transfer gate structures 124 are arranged on and / or in the substrate 102. The transfer gate structures 124 are aligned with a corresponding photodetector 106 and are located next to the potential-free diffusion node 108. The transfer gate structures 124 comprise a gate dielectric layer 120 and a gate electrode 122. The gate dielectric layer 120 is arranged between the gate electrode 122 and the substrate 102. Furthermore, the transfer gate structures 124 comprise a projection 122p that extends into the substrate 102 and over a corresponding photodetector 106. A sidewall spacer 126 is arranged on opposite sidewalls of the gate dielectric layer 120 and opposite sidewalls of the gate electrode 122.

[0023] The photodetectors 106 are configured to absorb incident radiation (e.g., photons) and generate corresponding electrical signals. For example, the photodetectors 106 can generate electron-hole pairs from the incident radiation. The transfer-gate structures 124 are configured to control a current flow between the potential-free diffusion node 108 and corresponding photodetectors 106. For example, the transfer-gate structures 124 are configured to selectively form a conductive channel in the substrate 102 between the potential-free diffusion node 108 and adjacent photodetectors 106 in order to transfer charge accumulated in the photodetectors 106 to the potential-free diffusion node 108. A trough region 110 is arranged in the substrate 102 below the potential-free diffusion node 108.The trough region 110 is arranged between the potential-free diffusion node 108 and the first insulation structure segment 114. The trough region 110 has the first doping type (for example, p-type) and is configured to increase the electrical insulation between the pixel regions 104. In some embodiments, the trough region 110 has the same layout as the first insulation structure segment 114 in a top view.

[0024] A doped contact region 118 is arranged in the substrate 102 of each pixel region 104. The doped contact region 118 comprises the first doping type (for example, p-type) and can have a higher doping concentration than the well region 110. In various embodiments, the doped contact region 118 can be configured to electrically couple a bulk material of the substrate 102 of each of the pixel regions 104 to a reference voltage (for example, ground). The doped contact region 118 can, for example, be referred to as a reference voltage node or a ground node.

[0025] In some embodiments, an interconnect structure 105 is located over a front surface 102f of the substrate 102. The interconnect structure 105 comprises a dielectric structure 128 and several conductive vias 130 and several conductive wires 132 arranged within the dielectric structure 128. The multiple conductive vias and wires 130, 132 are configured to enable the readout of the photodetectors 106.

[0026] The isolation structure 112 extends vertically throughout a rear surface 102b of the substrate 102. The first isolation structure segment 114 has a first depth d1, defined from the rear surface 102b to a first point above the rear surface 102b. The second isolation structure segment has a second depth d2, defined from the rear surface 102b to a second point above the first point. In various embodiments, the first depth d1 is less than the second depth d2. In some embodiments, the second depth d2 is equal to the height of the substrate 102. The second isolation structure segment 116, with a second depth d2 greater than the first depth d1, helps to increase the optical and / or electrical isolation between adjacent pixel regions 104.Furthermore, the first isolation structure segment 114 with the first depth d1, which is less than the second depth d2, reduces damage to the potential-free diffusion node 108 during the manufacturing of the image sensor, while providing optical and / or electrical isolation between adjacent pixel regions 104.

[0027] In some embodiments, the insulation structure 112 can be, for example, silicon dioxide, silicon carbide, silicon nitride, aluminum oxide, hafnium oxide, another suitable material, or any combination thereof. It is further understood that although the first insulation structure segment 114 and the second insulation structure segment 116 are hatched differently, they can both comprise the same material and / or be part of the same structure. In some embodiments, the different hatching of the first and second insulation structure segments 114, 116 serves for better differentiation. In further embodiments, the insulation structure 112 can comprise one or more lining layers (not shown) that line the trench of the substrate 102, and one or more trench fill materials (not shown) on the one or more lining layers.The one or more lining layers may be, for example, polysilicon, a dielectric material (e.g., silicon dioxide, aluminum oxide, hafnium oxide, etc.), a conductive material (e.g., titanium nitride, tantalum nitride, etc.), or the like. The one or more trench fill materials may be, for example, a dielectric material (e.g., silicon dioxide, silicon carbide, silicon carbide, aluminum oxide, hafnium oxide, etc.), a conductive material (e.g., aluminum, tungsten, titanium, or another suitable metal), another material, or any combination thereof.

[0028] Fig. 2A illustrates a top view 200a of some other embodiments of the image sensor of the Fig. 1A-1C.

[0029] In some embodiments, the lateral distance 142 between opposite side walls of the second isolation structure segment 116 in the first elongated trench segment 107a can be equal to the first lateral distance 140. Furthermore, the width of the second isolation structure segment 116 along the third elongated trench segment 107c can vary along an elongated side of each of the pixel regions 104. For example, as can be seen on an elongated side of the second pixel region 104b, the second isolation structure segment 116 has first opposite straight side wall segments 204, 206 separated by a fourth lateral distance 208, second opposite straight side wall segments 210, 212 separated by a third lateral distance 166, and third opposite straight side wall segments 216, 218 separated by a fourth lateral distance 208.In various embodiments, the fourth lateral distance 208 is larger than the third lateral distance 166 and is larger than the distance 170. Furthermore, the second insulation structure segment 116 has opposite side walls on opposite sides of the intersection 160 along the second direction (for example, along the x-axis), which are separated from each other by a fifth lateral distance 220. The fifth lateral distance 220 is larger than the distance 170 and / or the third lateral distance 166.

[0030] Due to the fact that the second isolation structure segment 116 has a varying width across the third elongated trench segment 107c, etchants can flow more uniformly as they form the trench in the substrate 102 that defines the width of the second isolation structure segment 116, thereby increasing the reading areas of the pixel regions 104. For example, the fact that the fourth lateral distance 208 is larger than the distance 170 increases the etch uniformity at the intersection 160, thus reducing polymer buildup at the intersection 160. Furthermore, the fact that the third lateral distance 166 is smaller than the fourth lateral distance 208 and is located in a central region of the elongated side of the second pixel region 104b increases the reading area of ​​the second pixel region 104b. Thus, the second isolation structure segment 116, with the [missing information] Fig. 2A further illustrated and / or described the leakage current in the image sensor.

[0031] In some embodiments, the fourth lateral distance 208 and the fifth lateral distance 220 can each be within a range of approximately 80 to 240 nm, within a range of approximately 240 to 400 nm, or within a range of approximately 80 to 400 nm, or have another suitable value. In further embodiments, the fourth lateral distance 208 and the fifth lateral distance 220 are each smaller than the second diagonal distance 164. Furthermore, the multiple pixel regions 104 are arranged in an array spaced 202 apart, where the space 202 is defined as the distance between the outer corner of an individual pixel region and a corresponding outer corner of an adjacent pixel region. In various embodiments, the distance 202 lies within a range of about 200 to 500 nm, within a range of about 500 to 800 nm, within a range of about 200 to 800 nm, or has another suitable value.Because the isolation structure 112 is in . Fig. As illustrated and / or described in Figure 2A, the spacing 202 of the multiple pixel regions 104 can be reduced, while the leakage current across the image sensor is mitigated. Furthermore, the layout of the isolation structure 112 enlarges the areas (for example, the reading areas) of the pixel regions 104, thereby increasing the full-well capacity of the photodetectors 106.

[0032] In various embodiments, a distance 222 between opposing curved side wall segments of the second insulation structure segment 116 in a region laterally offset from the curved side wall segments 150 is greater than the lateral distance 139. In further embodiments, the distance 222 is greater than the distance 170 at the intersection 160 and is less than the fourth lateral distance 208.

[0033] It goes without saying that when describing the layout of the isolation structure 112 in Fig. 1A and Fig. 2B Although the discussions are directed towards sidewall segments and distances between sidewall segments of the insulation structure 112, these distances and / or the layout of sidewall segments also apply to sidewalls of the substrate 102 that define the trench in which the insulation structure 112 is arranged. The substrate 102 comprises sidewall segments whose shape follows the sidewall segments of the insulation structure 112. For example, the substrate 102 comprises first curved sidewall segments that follow the shapes and / or sizes of the multiple curved sidewall segments 150, first opposing straight sidewall segments whose shape follows the first opposing straight sidewall segments 204, 206, and so on.

[0034] Fig. Figure 2B illustrates a cross-sectional view of Figure 200b of some embodiments of the image sensor of Fig. 2A along line AA' from Fig. 2A. In some embodiments, the substrate 102 comprises projections located beneath a corresponding potential-free diffusion node 108 and extending in one direction from the front surface 102f of the substrate 102. In various embodiments, the first depth d1 of the first insulation structure segment 114 is less than a height of the substrate 102 between the front surface 102f of the substrate 102 and the rear surface 102b. Fig. 1B) of the substrate 102. The first depth d1 can, for example, be approximately 0.35 micrometers (µm), 0.4 µm, within a range of approximately 0.25 to 1.5 µm, or have another suitable value. In further embodiments, the second depth d2 of the second insulation structure segment 116 can, for example, be approximately 3.6 µm, 3.8 µm, within a range of approximately 3 to 3.8 µm, or have another suitable value. In various embodiments, the second depth d2 is equal to the height of the substrate 102. In further embodiments, the second depth d2 is greater than the height of the substrate 102.

[0035] Fig. Figure 2C illustrates a cross-sectional view of Figure 200c of some embodiments of the image sensor of Fig. 2A along line BB' from Fig. 2A. In various embodiments, the depth of the second isolation structure segment 116 can be determined along a length of a corresponding pixel region (104 of Fig. 2A) lower and at intersections of the pixel regions (104 of Fig. 2A) be larger.

[0036] Fig. Figure 3 illustrates a top view of 300 of some other embodiments of the image sensor of Fig. 2A.

[0037] In some embodiments, the second insulation structure segment 116 has opposing side walls along the third elongated trench segment 107c, which are arranged along corresponding elongated sides of the pixel regions 104 and separated from each other by a fourth lateral distance 208. Furthermore, the doped region of each photodetector 106 in the substrate 102 follows a shape and / or layout of a corresponding pixel region 104. In various embodiments, the shapes and / or layouts of the photodetectors 106 can be defined during the fabrication of the image sensor by an ion implantation mask and can follow the layout of the insulation structure 112. By having the photodetectors 106 follow a shape and / or layout of the corresponding pixel region 104, the full-well capacity of each of the photodetectors 106 is increased. Furthermore, it is understood that while Fig. 3 the photodetectors are illustrated with a shape and / or layout that follows the shape and / or layout of a corresponding pixel region 104, but that the photodetectors are one of the Fig. 1A, Fig. 2A or Fig. 5. They may also have a shape and / or layout that corresponds to the relevant pixel regions in Fig. 1A, Fig. 2A or Fig. 5 correspond.

[0038] Fig. Figure 4 illustrates a cross-sectional view of 400 some alternative embodiments of the image sensor of Fig. 3, wherein the insulation structure 112 comprises a lining layer 302 and a trench fill material 304. In some embodiments, the cross-sectional view 400 extends from Fig. 4 along line AA' from Fig. 3.

[0039] In various embodiments, the first insulation structure segment 114 and the second insulation structure segment 116 comprise segments of the lining layer 302 and the trench backfill material 304. It is understood that the first insulation structure segment 114 and the second insulation structure segment 116 are shown in cross-sectional view 400 of Fig. Figure 4 is shown as phantom lines. The lining layer 302 can be, for example, polysilicon, a dielectric material (for example, silicon dioxide, aluminum oxide, hafnium oxide, etc.), a conductive material (for example, titanium nitride, tantalum nitride, etc.), or the like. In various embodiments, the lining layer 302 can comprise a first lining layer (not shown) and a second lining layer (not shown), the first lining layer being arranged between the substrate 102 and the second lining layer. In various embodiments, the first lining layer can be, for example, polysilicon, silicon dioxide, aluminum oxide, hafnium oxide, or the like, and the second lining layer can comprise titanium nitride, tantalum nitride, or the like.The trench fill material 304 may, for example, be or comprise a dielectric material (e.g., silicon dioxide, silicon carbide, silicon carbide, aluminum oxide, hafnium oxide, etc.), a conductive material (e.g., aluminum, tungsten, titanium or another suitable metal), another material or any combination thereof.

[0040] Fig. 5 and Fig. Figure 6 illustrates a top view 500 and a cross-sectional view 600 of some alternative embodiments of the image sensor of Fig. 1A, wherein the substrate 102 may comprise several column structures 502 beneath the second isolation structure segment 116 at locations near and / or at intersections of the multiple pixel regions 104. The top view 500 of Fig. 5 can be along line AA' from Fig. 6 runs. The cross-sectional view 600 of Fig. 6 can be along line AA' from Fig. 5 proceed.

[0041] As seen in the top view 500 of Fig. As illustrated in Figure 5, in some embodiments the substrate 102 can comprise the multiple column structures 502 at intersections of the multiple pixel regions 104 beneath the second isolation structure segment 116. As shown in the cross-sectional view 600 of Fig. As illustrated in Figure 6, the multiple column structures 502 protrude in a direction that points away from the front surface 102f of the substrate 102. The multiple column structures 502 can extend continuously laterally between directly adjacent photodetectors 106. In some embodiments, the substrate 102 can encompass the multiple column structures 502 because the second diagonal distance (164 of Fig. 5) is relatively small (for example, less than about 120 nm) and / or is smaller than the first diagonal distance (141 of Fig. 5) In such embodiments, a polymer used in the etching process that defines the trench in the substrate 102 can accumulate in the trench of the substrate 102 at the intersections of the multiple pixel regions 104, where the second isolation structure segment 116 is subsequently formed. This can occur because the depth of the trench in the substrate 102 at the intersections of the multiple pixel regions 104, where the second isolation structure segment 116 is formed, is relatively deep, and this can lead to an accumulation of the polymer in these deeper regions.

[0042] Fig. Figures 7-15 illustrate various views of some embodiments of a method for forming an image sensor comprising multiple pixel regions and an isolation structure with a layout designed to enhance the performance of the image sensor. Although the embodiments shown in the Fig. The different views shown in 7-15 regarding the procedure are described; it is understood that the views shown in the Fig. The structures shown in Figures 7-15 are not limited to the procedure, but can also exist independently of the procedure. Furthermore, the Fig. Although Figures 7-15 describe a series of actions, it is understood that these actions are not restrictive insofar as the order of the actions can be changed in other embodiments and the disclosed methods are also applicable to other structures. In other embodiments, some of the actions that are illustrated and / or described can be omitted entirely or partially.

[0043] As shown in the cross-sectional view 700 of Fig. As shown in Figure 7, multiple photodetectors 106 are formed in a substrate 102. The substrate 102 can be, for example, silicon, CMOS bulk material, silicon-germanium, an SOI, or another suitable semiconductor material, and can have a first doping type (for example, p-type). In some embodiments, forming the multiple photodetectors 106 includes: forming a masking layer (not shown) over a front face 102f of the substrate 102; performing a doping process to implant dopants into the substrate 102 having a second doping type (for example, n-type); and removing the masking layer.

[0044] As shown in the cross-sectional view 800 of Fig. As shown in Figure 8, several doped contact regions 118 and a trough region 110 are formed within the substrate 102. In some embodiments, the several doped contact regions 118 and the trough region 110 can each be formed by: forming a masking layer (not shown) over the front surface 102f of the substrate 102; performing a doping process to implant dopants into the substrate 102 having the first doping type (for example, p-type); and removing the masking layer. In various embodiments, the several doped contact regions 118 can be formed by a doping process that differs from another doping process used to form the trough region 110.

[0045] As shown in the cross-sectional view 900 of Fig. As shown in Figure 9, several transfer gate structures 124 and a potential-free diffusion node 108 are formed in and / or on the substrate 102. In some embodiments, the formation of the several transfer gate structures 124 comprises: performing a first structuring process on the front surface 102f of the substrate 102 to form gate protrusion grooves in the substrate 102; depositing (for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) a gate dielectric layer 120 over the substrate 102 and lining the gate protrusion grooves; depositing (for example, by CVD, PVD, ALD, etc.) a gate electrode 122 on the gate dielectric layer 120; and performing a second structuring process on the gate dielectric layer 120 and the gate electrode 122.The potential-free diffusion node 108 is formed in the substrate 102, for example, by a doping process. The potential-free diffusion node 108 has the second doping type (for example, n-type) and lies directly above the trough region 110. Furthermore, a sidewall spacer 126 is formed along the outer sidewalls of the gate electrode 122 and the outer sidewalls of the gate dielectric layer 120.

[0046] The gate dielectric layer 120 can be, for example, silicon dioxide, aluminum oxide, tantalum oxide, hafnium oxide, another dielectric material, or any combination thereof. The gate electrode 122 can be, for example, polysilicon, tungsten, titanium nitride, aluminum, tantalum, another conductive material, or any combination thereof.

[0047] As shown in the cross-sectional view 1000 of Fig. As shown in Figure 10, an interconnect structure 105 is formed on the front surface 102f of the substrate 102. The interconnect structure 105 comprises a dielectric structure 128, multiple conductive vias 130, and multiple conductive wires 132. The dielectric structure 128 can be formed, for example, by one or more deposition processes, such as a CVD process, a PVD process, an ALD process, or another suitable growth or deposition process. In various embodiments, the multiple conductive vias 130 and the multiple conductive wires 132 can be formed by a single-damascene process, a dual-damascene process, or another suitable process.

[0048] As shown in cross-sectional view 1100a of Fig. 11A and the top view 1100b of Fig. As shown in 11B, the structure of Fig. 10 is turned over, and a first masking layer 1102 is formed on a rear surface 102b of the substrate 102. The cross-sectional view 1100a of Fig. 11A runs along line AA' in plan view 1100b from Fig. 11B. In some embodiments, prior to the formation of the first masking layer 1102, a thinning process (not shown) is carried out into the back face 102b of the substrate 102 to reduce the thickness of the substrate 102. The thinning process may, for example, be or include a mechanical grinding process, a chemical-mechanical planarization (CMP) process, or the like. In various embodiments, as in Fig. As shown in Figure 11B, the first masking layer 1102 is formed over each potential-free diffusion node 108 at the intersections of the multiple photodetectors 106. The first masking layer 1102 can be, for example, a photoresist, a dielectric material (e.g., silicon nitride, silicon dioxide, etc.), a metal (e.g., titanium, aluminum, etc.), or the like. In some embodiments, the first masking layer 1102 is formed by a photolithography process.

[0049] As shown in cross-sectional view 1200a of Fig. 12A and the top view 1200b of Fig. As shown in Figure 12B, a first dielectric layer 1202 is formed on the back surface 102b of the substrate 102 over the first masking layer 1102, and a second masking layer 1204 is formed on the first dielectric layer 1202. The cross-sectional view 1200a of Fig. 12A runs along line AA' in plan view 1200b from Fig. 12B. It is understood that the first dielectric layer 1202 is shown in plan view 1200b of Fig. 12B is at least partially transparent to show a layout of the first masking layer 1102 relative to the second masking layer 1204.

[0050] The first dielectric layer 1202 can, for example, be silicon dioxide or another suitable dielectric material. The first dielectric layer 1202 can, for example, be formed on the back surface 102b by a CVD process, a PVD process, an ALD process, or another suitable growth or deposition process. The second masking layer 1204 can, for example, be a photoresist, a dielectric material (for example, silicon nitride, silicon dioxide, etc.), a metal (for example, titanium, aluminum, etc.), or the like. In some embodiments, the second masking layer 1204 is formed by a photolithography process. The second masking layer 1204 comprises sidewalls that define multiple openings 1206 above the first dielectric layer 1202.

[0051] As in Fig. As shown in Figure 12B, in some embodiments the second masking layer 1204 comprises several masking segments that lie directly above a corresponding photodetector of the multiple photodetectors 106, each masking segment comprising a layout corresponding to a layout of the subsequently formed and / or defined pixel regions (for example, 103 of the Fig. 13A-13B). In various embodiments, the second masking layer 1204 is formed such that it has a layout in which the layout of the openings 1206 corresponds to a layout of a subsequently formed insulation structure (for example, 112 of the Fig. 14A-14B). For example, the second masking layer can have 1204 sidewall segments separated by one or more distances to match the sidewall segments of the insulation structure (112 of Fig. 2A) are separated, as in Fig. 2A illustrates and / or describes. It is understood that the second masking layer 1204, for example, can be formed with such a structure that the layout of the openings 1206 corresponds to the layout of the insulation structure of one of the Fig. 1A, Fig. 3 or Fig. 5 corresponds to.

[0052] As shown in cross-sectional view 1300a of Fig. 13A and the top view 1300b of Fig. As shown in Figure 13B, an etching process is carried out into the rear surface 102b of the substrate 102 to form an isolation trench 1302, comprising a plurality of first trench components 1302a with a first depth d1 and a second trench component 1302b with a second depth d2. The cross-sectional view 1300a of Fig. 13A runs along line AA' in plan view 1300b from Fig. 13B. In various embodiments, the etching process forms sidewalls in the substrate 102 that define the isolation trench 1302 and define and / or delimit several pixel regions 104, each comprising a corresponding photodetector 106 and being part of several pixel sensor units 103.

[0053] The fact that sections of the first masking layer 1102 are directly below sections of the openings (1206 of Fig. The arrangement of the first trench components 12A) helps to form a shallower depth d1 than a shallower depth d2. In some embodiments, the substrate 102 is etched faster than the first masking layer 1102 during the etching process, which helps to form the first trench components 1302a with a depth of d1 while simultaneously forming the second trench component 1302b with a depth of d2. In various embodiments, the etch rate ratio of the substrate 102 to the first masking layer 1102 is within a range of approximately 1.5:1 to 20:1 or has another suitable value.

[0054] In some embodiments, the etching process comprises performing dry etching, wet etching, reactive ionic deep etching, plasma etching, another suitable etching, or any combination thereof. In various embodiments, the etching process comprises: performing a first etching (for example, plasma dry etching) that introduces one or more first etchants into the rear face 102b of the substrate 102 while the first and second masking layers 1102, 1204 are in place, and defines one or more sidewalls in the substrate 102 that define the isolation trench 1302; and performing a second etching (for example, wet etching) that brings the substrate into contact with one or more second etchants. In some embodiments, the one or more first etchants comprise chlorine-based etchants (for example, Cl₂, HCl, etc.).), fluorine-based etchants (for example, CF4, CHF3, etc.), or the like. In further embodiments, while the first etchant(s) flow into the rear surface 102b, one or more passivation gases can be passed over the substrate, wherein the one or more passivation gases are configured to deposit a sidewall protective layer (comprising, for example, a polymer) on the sidewalls of the substrate 102 that define the isolation trench 1302 during the first etching. The one or more passivation gases can be, for example, octafluorocyclobutane (C4F8), a fluorocarbon (for example, C4F6, C5F5, etc.), another suitable gas, or any combination thereof. In various embodiments, the second etching is carried out after the first etching and is configured to remove the sidewall protective layer from the sidewalls of the substrate 102.The one or more second etchants may be, for example, tetramethylammonium hydroxide or other suitable etchants, or may include such.

[0055] In various embodiments, due to the fact that the second masking layer 1204 is connected to the one in Fig. The structure illustrated and / or described in Figures 12A-12B forms a more uniform flow of one or more first etchants during the first etching in the first trench components 1302a. As a result, over- or under-etching of the substrate in areas aligned with the potential-free diffusion nodes 108 across the multiple pixel sensor units 103 is prevented or mitigated. This partially counteracts the formation of leakage current paths in the substrate 102 between adjacent pixel regions 104. Furthermore, the flow of one or more first etchants and / or the flow of one or more passivation gases in the second trench component 1302b is more uniform at intersections of the multiple pixel regions 104.Accordingly, the accumulation of a material (for example, polymer) of the sidewall protection layer at the intersections of the multiple pixel regions 104 in the second trench component 1302b is mitigated, thereby reducing the formation of column or pillar structures in the substrate 102 at and / or near the intersections of the multiple pixel regions 104 in the second trench component 1302b. As a result, leakage current across the multiple pixel regions 104 is further reduced.

[0056] As shown in cross-sectional view 1400a of Fig. 14A and the top view 1400b of Fig. As shown in Figure 14B, an isolation structure 112 is located in the isolation trench (1302 of the Fig. 13A-13B). The insulation structure 112 comprises first insulation structure segments 114 with a first depth d1 and a second insulation structure segment 116 with a second depth d2. In some embodiments, forming the insulation structure 112 includes: depositing (for example, by CVD, PVD, ALD, etc.) one or more trench fill materials in the insulation trench (1302 of Fig. 13A-13B) and performing a planarization process into one or more trench backfill materials. The one or more trench backfill materials may be, for example, a dielectric material (e.g., silicon dioxide, silicon carbide, silicon carbide, aluminum oxide, hafnium oxide, or another suitable dielectric material), a metallic material (e.g., aluminum, tungsten, titanium, or another suitable metal), another material, or any combination thereof. In various embodiments, the one or more trench backfill materials may comprise one or more lining layers (e.g., comprising silicon dioxide, aluminum oxide, hafnium oxide, etc.) and a trench backfill material (e.g., a dielectric material or a metallic material).In some embodiments, the planarization process can be, for example, an etching process, a CMP process, another suitable process, or any combination thereof. In various embodiments, the first insulation structure segments 114 and the second insulation structure segment 116 comprise the same material.

[0057] The second masking layer (1204 of Fig. 12A-12B) with the in Fig. The layout illustrated and / or described in 12A-12B enables the isolation structure 112 with the in Fig. 2A illustrated and / or described layout. It is understood that the second masking layer (1204 of Fig. 12A-12B) may have a different layout to allow the isolation structure 112, which has a layout that is in one of Fig. 1A, Fig. 3 or Fig. 5 is illustrated and / or described. As a result, problems (for example, due to etching stress) can occur during the etching process of Fig. 13A-13B are mitigated, thereby reducing leakage current across the multiple pixel sensor units 103 and increasing the dynamic range of the image sensor.

[0058] As shown in the cross-sectional view 1500 of Fig. As illustrated in Figure 15, a lattice structure 1502, several light filters 1504, and several microlenses 1506 are formed over the rear surface 102b of the substrate 102. The formation of the lattice structure 1502 can include depositing a lattice material over the substrate 102 and subsequently structuring the lattice material. The formation of the several light filters 1504 can include depositing and structuring individual light filter layers. Furthermore, the formation of the several microlenses 1506 can include depositing a microlens material over the several light filters 1504 and structuring the microlens material.

[0059] Fig. Figure 16 illustrates a flowchart of some embodiments of a method 1600 for forming an image sensor comprising multiple pixel regions and an isolation structure with a layout designed to enhance the image sensor's performance. Although the method 1600 is illustrated and / or described as a series of actions or events, it is understood that the method 1600 is not limited to the illustrated sequence or actions. Thus, in some embodiments, the actions can be performed in sequences other than those shown and / or simultaneously. Furthermore, in some embodiments, the illustrated actions or events can be subdivided into multiple actions or events that can be performed at different times or simultaneously with other actions or sub-actions.In some embodiments, some illustrated actions or events may be omitted, and other non-illustrated actions or events may be included.

[0060] In action 1602, several photodetectors are formed in a substrate. Fig. Figure 7 illustrates a cross-sectional view 700, which corresponds to some embodiments of Action 1602.

[0061] In action 1604, a potential-free diffusion node is formed at a junction of the multiple photodetectors. Fig. Figure 9 illustrates a cross-sectional view 900, which corresponds to some embodiments of Action 1604.

[0062] In action 1606, several transfer gate structures are formed on a front surface of the substrate. Fig. Figure 9 illustrates a cross-sectional view 900, which corresponds to some embodiments of Action 1606.

[0063] In action 1608, an interconnect structure is formed on the front surface of the substrate. Fig. Figure 10 illustrates a cross-sectional view 1000, which corresponds to some embodiments of Action 1608.

[0064] In action 1610, a first masking layer is formed on a rear surface of the substrate. The first masking layer includes a component that is aligned with the potential-free diffusion node. Fig. 11A and Fig. Figure 11B illustrates a cross-sectional view 1100a and a top view 1100b, which correspond to some embodiments of Action 1610.

[0065] In action 1612, a second masking layer is formed over the first masking layer. The second masking layer includes sidewalls that define openings above the first masking layer and around the photodetectors. Fig. 12A and Fig. Figure 12B illustrates a cross-sectional view 1200a and a top view 1200b, which correspond to some embodiments of Action 1612.

[0066] In action 1614, an etching process is performed on the substrate to form an isolation trench in the substrate, with the etching process defining multiple pixel regions in the substrate. Fig. 13A and Fig. Figure 13B illustrates a cross-sectional view 1300a and a top view 1300b corresponding to some embodiments of Action 1614.

[0067] In action 1616, an isolation structure is formed in the isolation trench. The isolation structure comprises a first isolation structure segment with a first depth above the potential-free diffusion node and a second isolation structure segment with a second depth greater than the first depth. In some embodiments, in a top view, the first isolation structure segment has first opposing curved sidewall segments configured to decrease a first diagonal distance between a first pair of diagonally separated pixel regions. Furthermore, the second isolation structure segment has second opposing curved sidewall segments configured to increase a second diagonal distance between a second pair of diagonally separated pixel regions. Fig. 14A and Fig. Figure 14B illustrates a cross-sectional view 1400a and a top view 1400b, which correspond to some embodiments of Action 1616.

[0068] In action 1618, a grid structure, several light filters and several microlenses are formed over the rear surface of the substrate. Fig. Figure 16 illustrates a cross-sectional view 1500, which corresponds to some embodiments of the action 1618.

[0069] Accordingly, in some embodiments, the present disclosure relates to an image sensor comprising an isolation structure arranged between several pixel regions in a substrate. In a top view, the isolation structure has first opposing straight sidewall segments separated by a first distance and connected to first opposing curved sidewall segments via a potential-free diffusion node, wherein a second distance between the first opposing curved sidewall segments is less than the first distance.

[0070] In some embodiments, the present application provides an integrated chip (IC). The IC comprises a first pixel region including a first photodetector in a substrate; a second pixel region including a second photodetector in the substrate adjacent to the first pixel region; and an isolation structure in the substrate comprising a first isolation structure element between the first and the second pixel region, wherein, in a top view, the first isolation structure element has a first pair of opposing straight sidewall segments and a first pair of opposing curved sidewall segments adjacent to the first pair of opposing straight sidewall segments, wherein a first distance between the first pair of opposing straight sidewall segments is greater than a second distance between the first pair of opposing curved sidewall segments.In one embodiment, the first pair of opposing straight sidewall segments and the first pair of opposing curved sidewall segments are arranged directly between the first pixel region and the second pixel region. In another embodiment, the first pair of opposing straight sidewall segments is arranged on a first side of the first pixel region, wherein the first isolation structure element comprises a second pair of opposing straight sidewall segments arranged on a second side of the first pixel region, wherein a third distance between the second pair of opposing straight sidewall segments is greater than the second distance.In one embodiment, the insulation structure comprises a second insulation element located in the substrate and at least partially surrounding the first and second pixel regions, wherein the first insulation element has a first depth and the second insulation element has a second depth greater than the first depth. In another embodiment, the second insulation element comprises a second pair of opposing straight sidewall segments arranged laterally between the first and second pixel regions, wherein a third distance between the second pair of opposing straight sidewall segments is less than the first distance. In another embodiment, the first pair of opposing straight sidewall segments and the second pair of opposing straight sidewall segments are each elongated in a first direction.In one embodiment, the IC further comprises a third pixel region, which includes a third photodetector in the substrate and laterally adjacent to the second pixel region; wherein the second insulation structure element comprises a second pair of opposing curved sidewall segments spaced between the second pixel region and the third pixel region, the third distance between the second pair of opposing curved sidewall segments being greater than the second distance. In another embodiment, the second insulation structure element comprises a second pair of opposing straight sidewall segments adjacent to the second pair of opposing curved sidewall segments, the fourth distance between the second pair of opposing straight sidewall segments being greater than the third distance.

[0071] In some embodiments, the present application provides an integrated circuit (IC). The IC comprises a first pixel region in a substrate; and a second pixel region in the substrate and adjacent to the first pixel region. In a top view, the substrate comprises a first rounded sidewall segment, a first elongated sidewall segment connected to the first rounded sidewall segment, a second rounded sidewall segment adjacent to the first rounded sidewall segment, and a second elongated sidewall segment connected to the second rounded sidewall segment and adjacent to the first elongated sidewall segment, wherein the first rounded sidewall segment and the first elongated sidewall segment define a portion of an outer circumference of the first pixel region, and the second rounded sidewall segment and the second elongated sidewall segment define a portion of an outer circumference of the second pixel region.wherein a first lateral distance between the first and the second elongated sidewall segment is greater than a second lateral distance between the first and the second rounded sidewall segment. In one embodiment, the IC further comprises a potential-free diffusion node in the substrate and laterally spaced between the first pixel region and the second pixel region, wherein the first and the second rounded sidewall segments are at least partially laterally aligned with the potential-free diffusion node and the first and the second elongated sidewall segments are laterally offset from the potential-free diffusion node. In one embodiment, the IC further comprises a third pixel region in the substrate and diagonally opposite the first pixel region, wherein, in a top view, a portion of the substrate forms a third rounded sidewall segment defining a first corner of the third pixel region.and a fourth rounded sidewall segment defining a second corner of the third pixel region, wherein the third rounded sidewall segment is offset from the first rounded sidewall segment by a first diagonal distance; and a fourth pixel region in the substrate and diagonally opposite the third pixel region, wherein, in a top view, the substrate comprises a fifth rounded sidewall segment defining a first corner of the fourth pixel region, the first corner of the fourth pixel region being adjacent to the second corner of the third pixel region, wherein the fourth rounded sidewall segment is offset from the fifth rounded sidewall segment by a second diagonal distance,which is greater than the first diagonal distance. In one embodiment, a first shape of the third rounded sidewall segment differs from a shape of the fourth rounded sidewall segment. In one embodiment, the IC further comprises a third pixel region in the substrate and adjacent to the second pixel region; and an insulation structure in the substrate and laterally surrounding the first, second, and third pixel regions, wherein the insulation structure comprises a first insulation component extending over a first side of the second pixel region and spaced between the second pixel region and the third pixel region.wherein the width of the first isolation component changes discretely at least four times along the first side of the second pixel region. In one embodiment, the second rounded sidewall segment and the second elongated sidewall segment of the substrate portion are arranged on a second side of the second pixel region opposite the first side, the first lateral distance being greater than the width of the first isolation component at the midpoint of its length. In another embodiment, the isolation structure has a first depth adjacent to the first and second rounded sidewall segments of the substrate, and the first isolation component has a second depth greater than the first depth.

[0072] In some embodiments, the present application provides a method for forming an integrated circuit (IC). The method comprises: forming multiple photodetectors in a substrate, wherein the substrate has a first face opposite a second face; forming a potential-free diffusion node at a first intersection of a first subset of the multiple photodetectors; performing an etching process on the substrate to form an isolation trench defined by sidewalls of the substrate extending into the second face of the substrate, wherein the isolation trench comprises a first trench segment located at the first intersection and aligned with the potential-free diffusion node, and a second trench segment offset from the first trench segment and around the multiple photodetectors, wherein the first trench segment has a first depth.which is less than a second depth of the second trench segment; and forming an isolation structure in the isolation trench, wherein the isolation structure comprises a first isolation structure segment in the first trench segment and a second isolation structure segment in the second trench segment, wherein the first isolation structure segment comprises a first pair of opposing curved sidewall segments above the potential-free diffusion node, wherein the second isolation structure segment comprises a second pair of opposing curved sidewall segments arranged at a second intersection of a second subset of the multiple photodetectors,wherein a first distance between the first pair of opposing curved sidewall segments is less than a second distance between the second pair of opposing curved sidewall segments. In one embodiment, the method further comprises: forming a first masking layer on the second surface of the substrate, wherein the first masking layer is aligned with the potential-free diffusion node and offset laterally from the second intersection; and forming a second masking layer over the first masking layer, wherein the second masking layer comprises sidewalls defining an opening directly above the first masking layer, the etching process being carried out while the first and second masking layers are arranged on the substrate. In one embodiment, the first insulation structure segment comprises a first pair of opposing straight sidewall segments,which are connected to the first pair of opposing curved sidewall segments, wherein a third distance between the first pair of opposing straight sidewall segments is greater than the first distance. In one embodiment, the second insulation structure segment comprises a first pair of opposing straight sidewall segments adjacent to the second pair of opposing curved sidewalls and a second pair of opposing straight sidewall segments adjacent to the first pair of opposing straight sidewall segments, wherein a third distance between the first pair of opposing straight sidewall segments is greater than a fourth distance between the second pair of opposing straight sidewall segments. In one embodiment, the third distance is greater than the second distance.

[0073] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 703,347

[0001]

Claims

[1] Integrated chip (IC) comprising: a first pixel region comprising a first photodetector in a substrate; a second pixel region comprising a second photodetector in the substrate and adjacent to the first pixel region; and an isolation structure in the substrate and comprising a first isolation structure element between the first and the second pixel region, wherein, in a top view, the first isolation structure element has a first pair of opposite straight sidewall segments and a first pair of opposite curved sidewall segments adjacent to the first pair of opposite straight sidewall segments, wherein a first distance between the first pair of opposite straight sidewall segments is greater than a second distance between the first pair of opposite curved sidewall segments. [2] IC according to claim 1, wherein the first pair of opposing straight sidewall segments and the first pair of opposing curved sidewall segments are arranged directly between the first pixel region and the second pixel region. [3] IC according to claim 1 or 2, wherein the first pair of opposing straight sidewall segments is arranged on a first side of the first pixel region, wherein the first insulation structure element comprises a second pair of opposing straight sidewall segments arranged on a second side of the first pixel region, wherein a third distance between the second pair of opposing straight sidewall segments is greater than the second distance. [4] IC according to one of claims 1 to 3, wherein the isolation structure comprises a second isolation structure element in the substrate and arranged at least partially around the first and second pixel regions, wherein the first isolation structure element has a first depth and the second isolation structure element has a second depth which is greater than the first depth. [5] IC according to claim 4, wherein the second insulation structure element comprises a second pair of opposing straight sidewall segments arranged laterally between the first pixel region and the second pixel region, wherein a third distance between the second pair of opposing straight sidewall segments is less than the first distance. [6] IC according to claim 5, wherein the first pair of opposing straight side wall segments and the second pair of opposing straight side wall segments are each elongated in a first direction. [7] IC according to any one of claims 4 to 6, further comprising: a third pixel region comprising a third photodetector in the substrate and laterally adjacent to the second pixel region; and wherein the second isolation structure element comprises a second pair of opposing curved sidewall segments spaced between the second pixel region and the third pixel region, wherein a third distance between the second pair of opposing curved sidewall segments is greater than the second distance. [8] IC according to claim 7, wherein the second insulation structure element comprises a second pair of opposing straight side wall segments adjacent to the second pair of opposing curved side wall segments, wherein a fourth distance between the second pair of opposing straight side wall segments is greater than the third distance. [9] Integrated chip (IC) comprising: a first pixel region in a substrate; and a second pixel region in the substrate and next to the first pixel region; wherein, in a top view, a part of the substrate comprises: a first rounded sidewall segment, a first elongated sidewall segment connected to the first rounded sidewall segment, a second rounded sidewall segment adjacent to the first rounded sidewall segment, and a second elongated sidewall segment connected to the second rounded sidewall segment and adjacent to the first elongated sidewall segment, wherein the first rounded sidewall segment and the first elongated sidewall segment define a section of an outer circumference of the first pixel region, and the second rounded sidewall segment and the second elongated sidewall segment define a section of an outer circumference of the second pixel region, wherein a first lateral distance between the first and the second elongated sidewall segment is greater than a second lateral distance between the first and the second rounded sidewall segment. [10] IC according to claim 9, further comprising: a potential-free diffusion node in the substrate and laterally spaced between the first pixel region and the second pixel region, wherein the first and second rounded side wall segments are at least partially laterally aligned with the potential-free diffusion node and the first and second elongated side wall segments are laterally offset from the potential-free diffusion node. [11] IC according to claim 9 or 10, further comprising: a third pixel region in the substrate and diagonally opposite the first pixel region, wherein, in a top view, the substrate comprises a third rounded side wall segment defining a first corner of the third pixel region, and a fourth rounded side wall segment defining a second corner of the third pixel region, the third rounded side wall segment being offset from the first rounded side wall segment by a first diagonal distance; and a fourth pixel region in the substrate and diagonally opposite the third pixel region, wherein, in a top view, the substrate comprises a fifth rounded side wall segment defining a first corner of the fourth pixel region, the first corner of the fourth pixel region being adjacent to the second corner of the third pixel region, the fourth rounded side wall segment being offset from the fifth rounded side wall segment by a second diagonal distance greater than the first diagonal distance. [12] IC according to claim 11, wherein a first shape of the third rounded side wall segment differs from a shape of the fourth rounded side wall segment. [13] IC according to any one of claims 9 to 12, further comprising: a third pixel region in the substrate and adjacent to the second pixel region; and an isolation structure in the substrate and placed laterally around the first, second and third pixel regions, wherein the isolation structure comprises a first isolation component extending over a first side of the second pixel region and spaced between the second pixel region and the third pixel region, wherein a width of the first isolation component changes discretely at least four times along the first side of the second pixel region. [14] IC according to claim 13, wherein the second rounded side wall segment and the second elongated side wall segment of the part of the substrate are arranged on a second side of the second pixel region opposite the first side, wherein the first lateral distance is greater than the width of the first isolation component at the midpoint of a length of the first isolation component. [15] IC according to claim 13, wherein the insulation structure has a first depth adjacent to the first and second rounded sidewall segment of the substrate and the first insulation component has a second depth greater than the first depth. [16] Method for forming an integrated chip (IC), comprising: Forming multiple photodetectors in a substrate, wherein the substrate has a first surface opposite a second surface; Forming a potential-free diffusion node at a first intersection of a first subset of the multiple photodetectors; Performing an etching process on the substrate to form an isolation trench defined by sidewalls of the substrate extending into the second surface of the substrate, the isolation trench comprising a first trench segment located at the first intersection and aligned with the potential-free diffusion node, and a second trench segment offset from the first trench segment and around the multiple photodetectors, the first trench segment having a first depth less than a second depth of the second trench segment; and Forming an isolation structure in the isolation trench, wherein the isolation structure comprises a first isolation structure segment in the first trench segment and a second isolation structure segment in the second trench segment, wherein the first isolation structure segment comprises a first pair of opposite curved sidewall segments above the potential-free diffusion node, wherein the second isolation structure segment comprises a second pair of opposite curved sidewall segments arranged at a second intersection of a second subset of the multiple photodetectors, wherein a first distance between the first pair of opposite curved sidewall segments is less than a second distance between the second pair of opposite curved sidewall segments. [17] The method of claim 16, further comprising: Forming a first masking layer on the second surface of the substrate, wherein the first masking layer is aligned with the potential-free diffusion node and offset laterally from the second intersection; and Forming a second masking layer over the first masking layer, wherein the second masking layer includes side walls that define an opening directly above the first masking layer, with the etching process being carried out while the first and second masking layers are positioned on the substrate. [18] Method according to claim 16 or 17, wherein the first insulation structure segment comprises a first pair of opposing straight side wall segments connected to the first pair of opposing curved side wall segments, wherein a third distance between the first pair of opposing straight side wall segments is greater than the first distance. [19] Method according to any one of claims 16 to 18, wherein the second insulation structure segment comprises a first pair of opposing straight side wall segments adjacent to the second pair of opposing curved side walls and a second pair of opposing straight side wall segments adjacent to the first pair of opposing straight side wall segments, wherein a third distance between the first pair of opposing straight side wall segments is greater than a fourth distance between the second pair of opposing straight side wall segments. [20] Method according to claim 19, wherein the third distance is greater than the second distance.

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