SELF-ALIGNED GATE CUT

Abstract

This document provides techniques for forming semiconductor devices that include one or more gate cuts self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure can be interrupted, for example, between two transistors by a gate cut that extends through at least one section of the total thickness of the gate structure and includes dielectric material to electrically isolate the sections of the gate structure on both sides of the gate cut. A dielectric plug contacts an upper surface of the gate cut to separate the gate structure on both sides of the dielectric plug.The gate cut is self-aligned between the adjacent semiconductor devices such that it is essentially equidistant between the semiconductor devices along the gate trench.

Description

BACKGROUND

[0001] As the size of integrated circuits continues to scale down, a number of challenges arise. For example, reducing the size of memory and logic cells becomes increasingly difficult, as does reducing device spacing on the device layer. With increasingly dense transistor packing, the formation of certain device structures used to isolate adjacent transistors becomes challenging. Accordingly, a number of non-trivial challenges related to semiconductor device design remain. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A and Fig. 1B are cross-sectional or top views of some semiconductor devices having self-aligned gate sections within the gate trench between the devices, according to an embodiment of the present disclosure. Fig. 2A and Fig. Figure 2B are cross-sectional and top views illustrating a first stage in an exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 3A and Fig. Figure 3B are cross-sectional and top views illustrating a further phase in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 4A and Fig. Figure 4B are cross-sectional and top views illustrating a further phase in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 5A and Fig. Figure 5B are cross-sectional and top views illustrating a further phase in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 6A and Fig. Figure 6B are cross-sectional and top views illustrating a further stage in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 7A and Fig. Figure 7B are cross-sectional and top views illustrating a further stage in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 8A and Fig. Figure 8B are cross-sectional and top views illustrating a further stage in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 9A and Fig. Figure 9B are cross-sectional and top views illustrating a further stage in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 10A and Fig. Figure 10B are cross-sectional and top views illustrating a further phase in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 11A and Fig. Figure 11B are cross-sectional and top views illustrating a further stage in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 12A and Fig. Figure 12B are cross-sectional and top views illustrating a further phase in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 13A and Fig. Figure 13B are cross-sectional and top views illustrating a further stage in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 14A and Fig. Figure 14B are cross-sectional and top views illustrating a further stage in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 15A and Fig. Figure 15B are cross-sectional and top views illustrating a further stage in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. 16A and Fig. Figure 16B are cross-sectional and top views illustrating a further stage in the exemplary process for forming semiconductor devices having self-aligned gate cuts confined within the gate trench between the devices, according to some embodiments of the present disclosure. Fig. Figure 17 is a cross-sectional view illustrating a self-aligned gate section bounded within the gate trench between forksheet devices, according to some embodiments of the present disclosure. Fig. Figure 18 illustrates a cross-sectional view of a chip package containing one or more semiconductor dies, according to some embodiments of the present disclosure. Fig. Figure 19 is a flowchart of a manufacturing process for semiconductor devices having a self-aligned gate cut that is confined within the gate trench between the devices, according to an embodiment of the present disclosure. Fig. Figure 20 illustrates a computing system comprising one or more integrated circuits, as described herein in various ways, according to one embodiment of the present disclosure.

[0002] Although the following detailed description continues with reference to illustrative embodiments, many alternatives, modifications, and variations are obvious in light of the present disclosure. Furthermore, it is understood that the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For example, although some figures generally depict perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may not have perfectly straight lines and right angles (e.g., some features may have tapered side walls and / or rounded corners), and some features may have a surface topology or otherwise be uneven due to real limitations of the machining equipment and techniques used. DETAILED DESCRIPTION

[0003] This document provides techniques for forming semiconductor devices that include one or more gate cuts self-aligned within the gate trench between adjacent devices. These techniques can be used in a wide range of integrated circuit applications and are particularly useful for device-layer transistors, such as FinFETs or gate-all-around transistors (e.g., ribbonFETs and nanowire FETs) or forksheet transistors (e.g., nanosheet FETs). In one example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (also called a channel region).The semiconductor region can be, for example, a fin made of a semiconductor material extending from a source region to a drain region, or one or more nanowires, nanoribbons, or nanosheets made of a semiconductor material extending from a source region to a drain region. The gate structure includes a gate dielectric (e.g., a high-k dielectric gate material) and a gate electrode (e.g., a conductive material such as exit work material and / or gate filler). The gate structure can be interrupted, for example, between two transistors by a gate cut that extends through at least one section of the total thickness of the gate structure and includes dielectric material to electrically isolate the sections of the gate structure on both sides of the gate cut.A dielectric plug contacts an upper surface of the gate cut to separate the gate structure on both sides of the dielectric plug. In one example, the gate cut is confined within the gate trench, so that it does not extend beyond the walls of the gate trench as defined by gate spacer structures. In some examples, the gate cut is self-aligned between the adjacent semiconductor devices, such that a distance from a first side of the gate cut to a first semiconductor device adjacent to the first side of the gate cut is essentially the same (e.g., within 0 to 20 angstroms) as a distance from a opposite second side of the gate cut to a second semiconductor device adjacent to the second side of the gate cut. Numerous configurations and variations become apparent in light of this revelation. General overview

[0004] As mentioned above, a number of non-trivial challenges remain regarding the fabrication of integrated circuits. Specifically, as devices become smaller and more densely packed, many structures become more difficult to manufacture because critical dimensions (CDs) of the structures push the limits of current manufacturing technology. For example, gate cuts are used in integrated circuit design to isolate gate structures from one another. Such gate cuts can be formed in various ways, but there are drawbacks to existing gate cut formation techniques.For example, gate cuts formed prior to the fabrication of the gate structures can suffer from uneven heights across multiple devices on a substrate, while gate cuts formed by etching trenches through several different materials can adversely affect the formation of other conductive features, such as source or drain contacts, potentially leading to poor yield. An alignment error can also cause gate cuts to be misaligned at cell boundaries, resulting in fluctuations in device performance at those boundaries.

[0005] Thus, and according to one embodiment of the present disclosure, techniques are provided herefor forming self-aligned gate cuts between devices (e.g., at a cell boundary) within the gate trench. The gate cuts can be formed before gate metallization but after the formation of the gate dielectric within the gate trench. The gate cuts can be self-aligned between any type of transistor device, such as FinFETs, gate-all-around (GAA) devices, and forksheet devices. In the case of forksheet devices, the self-aligned gate cuts can be formed at a different time than the dielectric ridge between the nanosheet devices.In some embodiments, a sacrificial material is deposited over adjacent semiconductor devices within the gate trench after the formation of a gate dielectric over the semiconductor material of the devices, leaving a gap within the gate trench between the devices. This gap generally defines the position of the gate cut and has a controllable width depending on the thickness of the deposited sacrificial material. A section of the sacrificial material along the bottom of the gate trench between the devices is etched away to form a depression, and a dielectric material forms within the gap between the devices and within the depression.After removal of the sacrificial material, the dielectric material, according to some embodiments, remains as a gate cut within the gate trench between the two devices and is self-aligned between them. Following the formation of a gate electrode on the gate dielectric, a section of the gate electrode above the gate cut is removed, and a dielectric plug is formed in its place to ensure complete separation of the gate structures on both sides of the self-aligned gate cut.

[0006] According to one embodiment, an integrated circuit comprises a first semiconductor device and a second semiconductor device. The first semiconductor device has a first semiconductor region extending in a first direction from a first source or drain region, and a first gate structure extending in a second direction over the first semiconductor region, the second direction being different from the first direction. The second semiconductor device has a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction over the second semiconductor region.The spacer structures are located on the sidewalls of the first and second gate structures and extend along the second direction with the first and second gate structures. A gate cut is located between the first and second semiconductor devices and separates the first gate structure from the second gate structure along the second direction. A dielectric plug is located on the upper surface of the gate cut. The gate cut extends along a third direction through at least a portion of the total height of the first and second gate structures. An upper surface of the gate cut is located below an upper surface of the spacer structures. The dielectric plug also separates the first gate structure from the second gate structure along the second direction.

[0007] According to another embodiment, an integrated circuit comprises a first semiconductor device and a second semiconductor device. The first semiconductor device has a first semiconductor region extending in a first direction from a first source or drain region, and a first gate structure extending in a second direction across the first semiconductor region, the second direction being different from the first direction. The second semiconductor device has a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction across the second semiconductor region.Furthermore, the spacer structures are located on the sidewalls of the first and second gate structures and extend along the second direction with the first and second gate structures. A gate cut is located between the first and second semiconductor devices and separates the first gate structure from the second gate structure along the second direction. The gate cut extends along a third direction through at least one section of the total height of the first and second gate structures. The gate cut includes a first section that directly contacts a first spacer structure, a second section that directly contacts a second spacer structure, and a third section between the first and second sections. The third section extends beyond the first and second sections along the second direction.

[0008] According to a further embodiment, a method for forming an integrated circuit comprises: forming at least two adjacent fins comprising semiconductor material, the fins extending above a substrate and each extending parallel to each other in a first direction; forming a sacrificial gate extending above the semiconductor material in a second direction different from the first direction; forming spacer structures on sidewalls of the sacrificial gate; removing the sacrificial gate; forming a gate dielectric on the semiconductor material of each of the adjacent fins; forming a sacrificial structure over the adjacent fins; forming a masking material over the sacrificial structure between the spacer structures; etching a trench through the masking material between the adjacent fins such that a portion of the sacrificial structure is exposed at the bottom of the trench;Removing a section of the sacrificial structure within the trench to form a depression; removing the masking material and forming a dielectric filling between the adjacent fins and within the depression; removing the sacrificial structure; forming a gate electrode over the gate dielectric on the semiconductor material of each of the adjacent fins, with a section of the gate electrode extending over an upper surface of the dielectric filling; and forming a dielectric plug through the section of the gate electrode such that the dielectric plug contacts the upper surface of the dielectric filling.

[0009] The techniques can be used with any type of non-planar transistor, including FinFETs (sometimes called tri-gate transistors), nanowire and nanoband transistors (sometimes called gate-all-around transistors), or forksheet transistors, to name just a few. The source and drain regions can be epitaxial areas deposited during an etch-and-replacement process to form the source / drain. The type of dopant used in the source and drain regions depends on the polarity of the corresponding transistor. The gate structure can be implemented using a gate-last (or last) process (sometimes called a replacement metal gate or RMG process). Any number of semiconductor materials, such as group IV materials (e.g., silicon, germanium, silicon germanium) or group III-V materials (e.g., silicon dioxide, silicon dioxide, silicon dioxide), can be used in forming the transistors.Gallium arsenide, indium gallium arsenide).

[0010] The use of the techniques and structures provided herein may be detectable using tools such as electron microscopy, including scanning / transmission electron microscopy (SEMITEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (SEM); composition mapping; X-ray crystallography or diffraction (XRD); energy-dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high-resolution physical or chemical analysis, to name a few suitable exemplary analytical tools. For example, in some embodiments, such tools may be used to detect the presence of a gate cut between devices that does not extend outside the gate trench (e.g.,within the spacer structures) and is essentially equidistant (e.g., within 1–2 nm) between adjacent semiconductor devices. In some examples, such tools can also be used to show that the gate dielectric may be in contact with the gate section around the semiconductor regions but does not extend upwards onto the sidewalls of the gate section. Furthermore, a dielectric plug is visible extending above an upper surface of the gate section to separate an upper portion of the gate structures. Numerous configurations and variations become apparent in light of this revelation.

[0011] It should be clear that the meanings of "above" and "over" in this disclosure should be interpreted as broadly as possible, so that "above" and "over" do not only mean "directly on" something, but also include the meaning of "over" something with an intervening feature or layer. Furthermore, spatial terms such as "below," "under," "lower," "over," "upper," "top," "bottom," and the like may be used here to simplify the description and to describe a relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatial terms are to be understood as encompassing various orientations of the device in use or operation in addition to the orientation shown in the figures.The device may be oriented differently (rotated by 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0012] As used herein, the term "layer" refers to a section of material that includes a region of thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entirety of an underlying or overlying structure, or it may have a lesser extent than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure, wherein the layer has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or on top of an upper surface and a lower surface of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface.A layer can conform to a given surface (whether flat or curved) with a relatively uniform thickness across the entire layer.

[0013] Materials that are “different in composition” or “different in composition,” as used herein, refer to two materials that have different chemical compositions. This difference in composition might consist, for example, of an element being present in one material but not the other (e.g., SiGe differs in composition from silicon), or of one material having all the same elements as another material, but at least one of these elements being intentionally provided in a different concentration relative to the other material (e.g., SiGe with 70 atomic percent germanium differs in composition from SiGe with 25 atomic percent germanium). In addition to such a difference in chemical composition, the materials might also contain different dopants (e.g.,Gallium and magnesium) or the same dopants, but in different concentrations. In further embodiments, materials with different compositions can also refer to two materials that have different crystallographic orientations. For example, (110)-silicon is different in composition from (100)-silicon. Creating a stack with different orientations could be achieved, for example, by full-surface wafer transfer. If two materials are elementally different, then one of the materials has an element that is not present in the other material. architecture

[0014] Fig. Figure 1A is a cross-sectional view across several semiconductor devices 101, according to an embodiment of the present disclosure. Fig. 1B is a cross-sectional view of the semiconductor devices 101 from above through the in Fig. 1A shown dashed line 1B-1B, and Fig. 1A illustrates the cross-section through the in Fig. 1B, shown as dashed line 1A-1A. It should be noted that some of the material layers (such as the gate cap 119) are not visible in the top view of Fig. 1B are not visible due to the position of the depicted cross-section. Each of the semiconductor devices 101 can be a non-planar metal-oxide-semiconductor (MOS) transistor, such as tri-gate (e.g., FinFET), gate-all-around (GAA), or forksheet transistors, although other transistor topologies and types could also benefit from the techniques provided herein. The exemplary embodiments illustrated herein use the GAA structure. The semiconductor devices 101 represent a section of an integrated circuit that may include any number of similar semiconductor devices.

[0015] As can be seen, the semiconductor devices 101 are formed on a substrate 102. Any number of semiconductor devices can be formed on the substrate 102, but three are illustrated here as an example. The substrate 102 can, for example, be a bulk substrate containing a group IV semiconductor material (such as silicon, germanium, or silicon germanium), a group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, the substrate 102 can be a semiconductor-on-insulator substrate, having a desired semiconductor layer over a buried insulator layer (e.g., silicon over silicon dioxide). Alternatively, the substrate 102 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g.,alternating layers of silicon and SiGe or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some embodiments, a lower section (or the entirety) of substrate 102 is removed and replaced by one or more backside interconnect layers to form backside signal and power routing.

[0016] Each of the semiconductor devices 101 includes one or more nanoribbons 104 that run parallel to each other along a direction between a source region and a drain region (e.g., a first direction into and out of the sheet in the cross-sectional view of Fig. 1A). The nanoribbons 104 are an example of semiconductor regions or semiconductor bodies that extend between source and drain regions. The term nanoribbon can also include other similar forms, such as nanowires or nanosheets. The semiconductor material of the nanoribbons 104 can be formed from the substrate 102. In some embodiments, the semiconductor devices 101 can each include semiconductor regions in the form of fins, which can be, for example, native to the substrate 102 (formed from the substrate itself), such as silicon ribs etched from a silicon substrate. Alternatively, the fins can also be formed from a material deposited onto an underlying substrate.In one such exemplary case, a silicon germanium (SiGe) cover layer can be deposited onto a silicon substrate and then structured and etched to form a multitude of SiGe fins extending from that substrate. In another such example, non-native fins can be formed in an aspect ratio trapping process, in which native fins are etched away to leave fin-shaped grooves that can then be filled with an alternative semiconductor material (e.g., from the IV or III-V material groups). In still other embodiments, the fins incorporate alternating layers of material (e.g.,Alternating layers of silicon and SiGe enable the formation of the illustrated nanoribbons 104 during a gate formation process, wherein one type of alternating layer is selectively etched away to expose the other type of alternating layer within the channel region, allowing a gate-all-around process (GAA process) or forksheet process to be performed subsequently. Again, according to some examples, the alternating layers can be deposited over the entire surface and then etched into fins or deposited into fin-shaped grooves.

[0017] As can be further seen, adjacent semiconductor devices are separated by a dielectric layer 106, which may contain silicon dioxide. The dielectric layer 106 provides shallow trench insulation (STI) between any adjacent semiconductor devices and adjacent subfin regions 108. The dielectric layer 106 can be any suitable dielectric material, such as silicon dioxide, aluminum oxide, or silicon oxycarbonitride.

[0018] In this example, the semiconductor devices 101 each include a subfin region 108. According to some embodiments, the subfin region 108 comprises the same semiconductor material as the substrate 102 and is adjacent to the dielectric layer 106. In some embodiments, the nanoribbons 104 (or other semiconductor bodies) extend between a source and a drain region in the first direction to provide an active region for a transistor (e.g., the semiconductor region under the gate). The source and drain regions have a cross-sectional area of Fig. 1A not shown, but are visible in the top view of Fig. 1B shows where nanoribbons 104 of each semiconductor device 101 extend between first source or drain regions 110. Fig. Figure 1B also illustrates a dielectric filling 114 between source or drain regions 110 of a given source / drain trench, extending along a second direction (e.g., across the sheet in Fig. 1A). The dielectric filling 114 can comprise any suitable dielectric material, such as silicon dioxide. According to some embodiments, the spacer structures 112 extend around the ends of the nanoribbons 104 and along the sidewalls of the gate structures between the spacer structures 112. The spacer structures 112 can comprise a dielectric material, such as silicon nitride, and can be deposited in a conformal manner or in another suitable deposition process and etched to a desired thickness (e.g., 2 nm to 10 nm).

[0019] In some embodiments, the source and drain regions 110 are epitaxial regions provided by an etch-and-replace process. Any semiconductor materials suitable for the source and drain regions can be used (e.g., group IV and III-V semiconductor materials). The source and drain regions 110 may include multiple layers, such as liners and cover layers, to improve contact resistance. In each of these cases, the composition and doping of the source and drain regions 110 can be the same or different, depending on the polarity of the transistors. For example, phosphorus-doped silicon can be used for n-type source or drain regions, while boron-doped silicon germanium can be used for p-type source or drain regions. Any number of source and drain configurations and materials can be used.

[0020] According to some embodiments, each semiconductor device 101 includes a gate structure extending across nanobands 104 along the second direction across the sheet of Fig. 1A extends. The second direction can be orthogonal to the first direction. Each gate structure includes a respective gate dielectric 116 and a gate electrode 118. The gate dielectric 116 represents any number of dielectric layers located between the nanobands 104 and the gate electrode 118. The gate dielectric 116 can also be present on the surfaces of other structures within the gate trench, such as subfin regions 108. The gate dielectric 116 can include one or more suitable gate dielectric materials. In some embodiments, the gate dielectric 116 includes a layer of native oxide material (e.g., silicon dioxide) on the nanobands or other semiconductor regions forming the channel region of the devices, and a layer of a high-k dielectric material (e.g., hafnium oxide) on top of the native oxide.

[0021] The gate electrode 118 can represent any number of conductive layers, such as any metal, metal alloy, or doped polysilicon layers. In some embodiments, the gate electrode 118 includes one or more exit work metals surrounding the nanobands 104. In some embodiments, one of the semiconductor devices 101 is a p-channel device containing a titanium exit work metal surrounding its nanobands 104. In some embodiments, one of the semiconductor devices 101 is an n-channel device containing a tungsten exit work metal surrounding its nanobands 104. The gate electrode 118 can also include a filler metal or another conductive material (e.g., tungsten, ruthenium, molybdenum, cobalt) surrounding the exit work metals to provide the entire gate electrode structure.In some embodiments, a gate cap 119 can be formed over the gate electrode 118 to protect the underlying material during processing. The gate cap 119 can be any suitable dielectric material, such as silicon nitride.

[0022] In some embodiments, adjacent gate structures can be separated along the second direction (e.g., across the sheet) by a gate cut 120, which acts like a dielectric barrier or wall between the gate structures. The gate cut 120 extends vertically (e.g., in a third direction) through a section of the entire thickness of the adjacent gate structures on both sides of the gate cut 120. In some embodiments, the gate cut 120 rests on an upper surface of the dielectric layer 106 (e.g., does not extend into the dielectric layer 106). In some embodiments, the gate cut 120 is formed from different dielectric materials. In one example, the gate cut 120 includes a dielectric lining along an outer edge of the gate cut 120 and a dielectric filling on the dielectric lining.In some embodiments, the dielectric lining comprises a high-k dielectric material, such as silicon nitride, and the dielectric filling comprises a medium-k or low-k dielectric material (e.g., a dielectric with a dielectric constant of about 4.5 or less), such as silicon dioxide, porous silicon dioxide, or flowable oxide. In other examples, the gate section 120 comprises a single dielectric material, such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride. In some embodiments, the gate section 120 includes one or more air gaps or cavities, which may further reduce the dielectric constant of the gate section 120.

[0023] In some embodiments, the gate cut 120 is self-aligned within the gate trench between adjacent devices such that a distance (d) between each edge of the gate cut 120 and the corresponding nanobands 104 along a common plane is substantially the same (e.g., the distance d on one side is within 1 nm of the distance d on the other side). The distance (d) can vary depending on the device density but can generally be between about 5 nm and about 20 nm. In some embodiments, the gate cut 120 extends in the first direction over the entire width of the gate trench, as shown in Fig. Figure 1B shows the gate section, but this is limited to the gate trench. Accordingly, the gate section 120 does not extend beyond the spacer structures 112 along the first direction. As discussed in more detail here, the gate section 120 is formed after the formation of the gate dielectric 116 but before the formation of the gate electrode 118, so the gate dielectric 116 does not extend along the side walls of the gate section 120, although ends of the gate dielectric 116 may abut the side walls of the gate section 120. Consequently, the side walls of the gate section 120 extending along the first direction can directly contact the gate electrode 118, and the side walls of the gate section 120 extending along the second direction can directly contact the spacer structures 112.

[0024] Due to the manufacturing process used to form the gate section 120, as described in more detail herein, the gate section 120 comprises a first section with a first width w1 along the second direction and a second section with a second width w2 along the second direction. The first width w1 of the first section is larger than the second width w2 of the second section, although the exact dimensions may vary. In some embodiments, the first width w1 is 50%, at least 75%, or at least 100% larger than the second width w2. As described in Fig. As can be seen in Figure 1B, the gate section 120 can also include narrower end sections along the first direction, with the wider section being provided between the narrower end sections. According to some embodiments, the narrower end sections of the gate section 120 directly contact the spacer structures 112.

[0025] As noted above, the gate section 120 may not extend through the entire thickness of the adjacent gate structures. To complete the insulation of the gates, a dielectric plug 122 may extend between a top surface of the gate trench and a top surface of the gate section 120. The dielectric plug 122 may contain any suitable dielectric material. In some examples, the dielectric plug 122 contains the same dielectric material as the gate section 120. The combination of gate section 120 and dielectric plug 122 extends through the entire height of the adjacent gate structures within the gate trench to insulate the adjacent gate structures. Accordingly, the dielectric plug 122 extends across the entire width of the gate trench in the first direction between the spacer structures 112. Manufacturing methodology

[0026] Fig. Figures 2A-16A and 2B-16B include cross-sectional and top views respectively, which together illustrate an exemplary process for forming an integrated circuit with semiconductor devices having self-aligned gate sections bounded within the gate trench between the devices, according to an embodiment of the present disclosure. Fig. 2A - 16A represent a similar cross-sectional view to that of Fig. 1A via a series of semiconductor devices, while Fig. Figures 2B-16B represent the corresponding top view at each stage of manufacturing. Each set of figures sharing the same letter shows an exemplary structure resulting from the process flow up to that point, so that the depicted structure evolves as the process progresses, culminating in the structure shown in the Fig. 16A to 16B is shown and is similar to the structure shown in the Fig. 1A and Fig. Figure 1B shows such a structure. Such a structure can be part of a larger integrated circuit (such as a processor or a memory chip) that includes, for example, digital logic cells and / or memory cells and an analog mixed-signal circuit arrangement. Therefore, the illustrated integrated circuit structure can be part of a larger integrated circuit that includes other integrated circuit arrangements not shown. Exemplary materials and process parameters are given, but other materials and process parameters may also be used, as is clear from this disclosure. Although the fabrication of two gate cuts is illustrated in the aforementioned figures, it is understood that any number of similar gate cuts can be fabricated across the integrated circuit using the same processes discussed herein.

[0027] Fig. 2A and Fig. Figures 2B illustrate a cross-sectional view through a substrate 201 and a top view of the substrate 201 with a series of material layers formed on top of the substrate according to an embodiment of the present disclosure. Alternating material layers can be deposited on the substrate 201, including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form GAA transistor structures. Any number of alternating semiconductor layers 204 and sacrificial layers 202 can be deposited on the substrate 201. The above description for the substrate 102 applies equally to the substrate 201. The top view from Fig. Figure 2B illustrates the top semiconductor layer 204 of the layer stack.

[0028] In some embodiments, the sacrificial layers 202 have a different material composition than the semiconductor layers 204. In some embodiments, the sacrificial layers 202 are silicon germanium (SiGe), while the semiconductor layers 204 comprise a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or III-V materials such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in both the sacrificial layers 202 and the semiconductor layers 204, the germanium concentration differs between the sacrificial layers 202 and the semiconductor layers 204. For example, the sacrificial layers 202 may contain a higher proportion of germanium compared to the semiconductor layers 204.In some examples, the semiconductor layers 204 can be doped with either n-type dopants (to produce a p-channel transistor) or with p-type dopants (to produce an n-channel transistor).

[0029] Although the dimensions may vary from one exemplary embodiment to the next, the thickness of each sacrificial layer 202 can be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is essentially the same (e.g., within 1–2 nm). The thickness of each of the semiconductor layers 204 can be approximately the same as the thickness of each sacrificial layer 202 (e.g., about 5–20 nm). Each of the sacrificial layers 202 and semiconductor layers 204 can be deposited using any known or proprietary material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0030] Fig. 3A and Fig. 3B shows the cross-sectional view or top view of the in Fig. The structure shown in Figures 2A and 2B is represented after the formation of a cap layer 302 and the subsequent formation of fins below the cap layer 302 according to one embodiment. The cap layer 302 can be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The cap layer 302 is structured in rows to form corresponding rows of fins from the stack of alternating layers of the sacrificial layers 202 and the semiconductor layers 204. The rows of fins extend longitudinally in a first direction (e.g., into the sheet of Fig. 3A in and out of this one).

[0031] In some embodiments, an anisotropic etching process is continued through the layer stack into at least one section of the substrate 201. The etched section of the substrate 201 can be filled with a dielectric layer 304, which acts as a shallow trench insulation (STI) between adjacent fins. The dielectric layer 304 can be any suitable dielectric material, such as silicon dioxide. The subfin regions 306 represent remaining sections of the substrate 201 between the dielectric layer 304 in some embodiments. The dielectric layer 304 can be formed by overlying deposition of dielectric material across the structure, followed by isotropic back-etching of the dielectric material to a final thickness adjacent to the subfin regions 306.According to some embodiments, an upper surface of the dielectric layer 304 is recessed below an upper surface of the subfin regions 306, as shown in . Fig. 3A illustrates this.

[0032] Fig. 4A and Fig. Figure 4B shows the cross-sectional view or top view of the [unclear text]. Fig. The structure shown in Figures 3A and 3B is shown after the formation of a sacrificial gate 402, which extends across the fins in a second direction different from the first, according to some embodiments. The sacrificial gate 402 can extend across the fins in a second direction that is orthogonal to the first direction. According to some embodiments, the sacrificial gate material is formed in parallel strips across the integrated circuit and removed in all areas not protected by a gate masking layer. The sacrificial gate 402 can be any suitable material that can be selectively removed without damaging the semiconductor material of the fins. In some examples, the sacrificial gate 402 includes polysilicon.

[0033] After the formation of the sacrificial gate 402, spacer structures 404 can be formed on the side walls of the sacrificial gate 402. In some embodiments, a dielectric material is deposited over the entire surface of the structure and back-etched to form the spacer structures 404 on the side walls of all structures extending above the substrate 201. The spacer structures 404 extend along the sides of the sacrificial gate 402 in the second direction, as shown in Fig. Figure 4B illustrates this. In some embodiments, spacer structures may not form under the sacrificial gate 402, even on the sides of the fins. The spacer structures 404 can be any suitable dielectric material, such as silicon nitride.

[0034] Fig. 5A and Fig. 5B the cross-sectional view or top view of the in Fig. The structure shown in Figures 4A and 4B after the removal of any exposed fins and the subsequent formation of source or drain regions 502 at the fin ends, according to some embodiments, is depicted. The exposed fin sections (which, for example, are not protected by the sacrificial gate 402 or spacer structures 404) can be removed using any anisotropic etching process, such as reactive ion etching (RIE). According to some embodiments, the removal of the exposed fin sections creates source or drain grooves that alternate with gate grooves (currently filled with sacrificial gates 402) along the first direction.

[0035] In some embodiments, source or drain regions 502 can be formed from the exposed ends of the fins within the source / drain trench. The source or drain regions can be formed in the areas previously occupied by the exposed fins adjacent to the spacer structures 404. In some embodiments, the source or drain regions 502 are epitaxially grown from the exposed semiconductor material at the ends of the semiconductor layers 204. In some embodiments, any of the source or drain regions 502 can be NMOS source or drain regions (e.g., epitaxial silicon) or PMOS source or drain regions (e.g., epitaxial SiGe).

[0036] In some embodiments, a dielectric filling 504 is provided within the source / drain trench. In some examples, the dielectric filling 504 occupies a remaining volume within the source / drain trench around and possibly extending over the source or drain regions 502. The dielectric filling 504 can be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filling 504 extends to and is planar with a top surface of the spacer structures 404 (e.g., after a polishing process).

[0037] Fig. 6A and Fig. 6B shows the cross-sectional view or top view of the in Fig. The structure shown in Figures 5A and 5B is revealed after the removal of the sacrificial gate 402 and the sacrificial layers 202, according to some embodiments. In examples where gate masking layers are still present, they can also be removed at this time. Once the sacrificial gate 402 has been removed, the fins that were located beneath the sacrificial gate 402 are exposed.

[0038] In the example where the fins comprise alternating semiconductor layers, sacrificial layers 202 are selectively removed to expose nanoribbons 602 extending between corresponding source or drain regions 502. Each vertical set of nanoribbons 602 represents the semiconductor or channel region of another semiconductor device. It is understood that the nanoribbons 602 can also be nanowires or nanosheets (e.g., from a forksheet array) or fins (e.g., for a FinFET array). The sacrificial gate 402 and the sacrificial layers 202 can be removed using the same isotropic etching process or different isotropic etching processes.It should also be noted that the source or drain regions 502 are located at the respective ends of the nanobands 602 below the spacer structures 404 or otherwise touching to provide a transistor conduction path from the source region to the drain region when the gate is properly biased (as in . Fig. 1B shown, where source and drain regions 110 are adjacent to semiconductor regions 104).

[0039] Fig. 7A and Fig. 7B shows the cross-sectional view or top view of the in Fig. The structure shown in Figures 6A and 6B is shown after the formation of a gate dielectric 702 over any exposed surfaces within the gate trench, according to some embodiments. The gate dielectric 702 can comprise any suitable dielectric material (such as silicon dioxide and / or a dielectric material with a high dielectric constant). Examples of dielectric materials with a high dielectric constant include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc cniobate, to name just a few. According to some embodiments, the gate dielectric 702 comprises a layer of hafnium oxide with a thickness between approximately 1 nm and approximately 5 nm.In some embodiments, the gate dielectric 702 can comprise one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some cases, the gate dielectric 702 includes a first layer on the nanobands 602 and a second layer on the first layer. The first layer can, for example, be an oxide of the semiconductor material of the nanobands 602 (e.g., silicon dioxide), and the second layer can be a high-k dielectric material (e.g., hafnium oxide). More generally, the gate dielectric 702 can comprise any number of dielectric layers. According to some embodiments, the gate dielectric 702 forms along all surfaces exposed within the gate trench, such as along the inner walls of the spacer structures (as in [reference]). Fig. 7B) and along the upper surfaces of the dielectric layer 304 and the subfin regions 306. In some embodiments, the gate dielectric 702 can be annealed together with another deposited material layer (e.g., a layer of titanium nitride) to influence the threshold voltage of the transistors.

[0040] Fig. 8A and Fig. 8B shows the cross-sectional view or top view of the in Fig. The structure shown in Figures 7A and 7B is obtained after the formation of a sacrificial structure 802 within the gate trench and over the semiconductor material of the transistors according to some embodiments. The sacrificial structure 802 can comprise any suitable material that can be safely removed at a later time without damaging surrounding materials, such as the gate dielectric 702 or the nanoribbons 602. In some examples, the sacrificial structure 802 comprises a layer of aluminum oxide. In other examples, the sacrificial structure 802 comprises a dielectric lining, such as a thin lining of silicon dioxide over the aluminum oxide layer. Generally, the sacrificial structure 802 is conformally deposited over the transistor structures, leaving space between the transistor structures within the gate trench. Accordingly, the sacrificial structure 802 can be deposited using CVD or ALD.The thickness of the sacrificial structure 802 directly influences the resulting width of the gate cuts to be formed between the devices, as described in more detail herein. In some examples, the thickness of the sacrificial structure 802 is between approximately 5 nm and approximately 15 nm.

[0041] Fig. 9A and Fig. 9B shows the cross-sectional view or top view of the in Fig. The structure shown in Figures 8A and 8B is obtained after the formation of a mask material 902 within the gate trench according to some embodiments. The mask material 902 can be deposited within the gate trench and subsequently polished until an upper surface of the mask material 902 is substantially coplanar with an upper surface of the spacer structures 404. The mask material 902 can be any suitable hard mask material with a high degree of etch selectivity compared to the surrounding materials. In some examples, the mask material 902 is a carbon hard mask (CHM).

[0042] Fig. 10A and Fig. Figure 10B shows the cross-sectional view or top view of the in Fig. The structure shown in Figures 9A and 9B after the formation of depressions 1002 by the mask material 902 according to some embodiments. The depressions 1002 can be trench-shaped depressions extending along the first direction across the gate trench between the sacrificial structure 802 on the side walls of the spacer structures 404, as shown in Figures 9A and 9B. Fig. Figure 10B shows that the depressions 1002 can extend to a depth through the entire height of the mask material 902 to expose a portion of the sacrificial structure 802 at the bottom of the gate trench between adjacent semiconductor devices. A RIE process can be used to etch through the mask material 902 while pausing at the sacrificial structure 802. According to some embodiments, the orientation of the depressions 1002 is not critical, so the depressions 1002 need not be centered along the second direction between the adjacent semiconductor devices. For example, depressions 1002 can be formed by the mask structure 902 anywhere between adjacent semiconductor devices along the second direction.

[0043] Fig. 11A and Fig. Figure 11B shows the cross-sectional view or top view of the [document / image]. Fig. The structure shown in Figures 10A and 10B after an additional etching process to remove the exposed sacrificial structure 802 within the recesses 1002, according to some embodiments. A directed RIE process can be used to remove the sacrificial structure 802 from the underside of the recesses 1002 (as shown in Figures 10A and 10B). Fig. 11A) and at both ends of the depressions 1002 (as shown in Fig. (shown in Figure 11B). In some embodiments, the same etching can also be used to remove exposed sections of the gate dielectric 702 within the recesses 1002 after the removal of the sacrificial structure 802 within the recesses 1002. In some examples, a different RIE process is used to remove the gate dielectric 702. In some examples, isotropic etching (e.g., a wet etching process) is used to remove the sidewall sections of the sacrificial structure 802 and / or the sidewall sections of the gate dielectric 702 within the recesses 1002.

[0044] Fig. 12A and Fig. Figure 12B shows the cross-sectional view or top view of the [image / structure]. Fig. The structure shown in Figures 11A and 11B is revealed after removal of the mask material 902 according to some embodiments. The mask material 902 can be removed using any suitable isotropic etching process. In some examples, the mask material 902 is removed using an ashing process. The removal of the mask material 902 exposes cavities 1202 through the entire thickness of the sacrificial structure 802. As discussed above, the cavities 1202 can extend along the bottom of the gate trench (exposing, for example, an upper surface of the dielectric filling 304) and also along the sides of the gate trench (exposing, for example, sidewall surfaces of the spacer structures 404).

[0045] Fig. 13A and Fig. Figure 13B shows the cross-sectional view or top view of the [structure / image]. Fig. The structure shown in Figures 12A and 12B is obtained after the formation of gate sections 1302 within the gate trench between semiconductor devices according to some embodiments. The gate sections 1302 can comprise any suitable dielectric material, such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride. The dielectric material of the gate sections 1302 can be deposited using any suitable deposition technique, such as CVD, PECVD, flowable dielectric, or spin-on dielectric. According to some embodiments, the dielectric material of the gate sections 1302 is deposited within the gate trench and subsequently deepened using any suitable isotropic etching process until the upper surface of the sacrificial structure 802 is exposed. Accordingly, an upper surface of the gate cuts 1302 may be recessed below the upper surface of the sacrificial structure 802 within the gate trench.Since the dielectric material of the gate cuts 1302 fills the space between the sacrificial structure 802, the gate cuts 1302 are directly self-aligned between adjacent semiconductor devices along the gate trench.

[0046] In some embodiments, the dielectric material of the gate cuts 1302 also fills cavities 1202, such that the gate cuts 1302 extend across the entire width of the gate trench from one spacer structure 404 to the opposite spacer structure 404. A lower surface of the gate cuts 1302 may also contact the dielectric filling 304. The wider section of gate cuts 1302 between the nanoribbons 602 has a first width w1, and the narrower section of gate cuts 1302 within the cavities along the bottom and sides of the structure has a second width w2. In some embodiments, the first width w1 is at least 25%, at least 50%, at least 75%, or at least 100% larger than the second width w2.

[0047] Fig. 14A and Fig. Figure 14B shows the cross-sectional view or top view of the [structure]. Fig. The structure shown in Figures 13A and 13B is shown after the removal of the sacrificial structure 802 according to some embodiments. The sacrificial structure 802 can be removed using any suitable isotropic etching process. According to some embodiments, the gate dielectric 702 remains around the nanoribbons 602 and over the subfin sections 306. However, the gate dielectric 702 does not extend over the sidewalls of the gate sections 1302.

[0048] Fig. 15A and Fig. Figure 15B shows the cross-sectional view or top view of the [item]. Fig. The structure shown in Figures 13A and 13B is obtained after the formation of a gate electrode 1502 around nanoribbons 602 and via gate cuts 1302 within the gate trench, according to some embodiments. The gate electrode 1502 can include any number of conductive layers. The conductive gate electrode 1502 can be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD, to name a few examples. In some embodiments, the gate electrode 1502 includes doped polysilicon, a metal, or a metal alloy. Exemplary suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and carbides and nitrides thereof. The gate electrode 1502 can, for example, include a metal filler material together with one or more exit-work layers, resistivity-reducing layers, and / or barrier layers.The exit work layers can, for example, consist of p-type exit work materials (e.g., titanium nitride) for PMOS gates or n-type exit work materials (e.g., titanium aluminum carbide) for NMOS gates. After the gate structure is formed, the entire structure can be polished or planarized so that the top surface of the gate structure (e.g., the top surface of the gate electrode 1502) is essentially coplanar with the top surface of other semiconductor elements, such as the spacer structures 404 that define the gate trench.

[0049] Fig. 16A and Fig. Figure 16B shows the cross-sectional view or top view of the [document / structure]. Fig. The structure shown in Figures 15A and 15B is obtained after the formation of a dielectric plug 1602 on a corresponding gate section 1302a according to some embodiments. A depression can be etched through a section of the gate electrode 1502 to expose an upper surface of the gate section 1302a. The depression can be filled with one or more dielectric materials to form the dielectric plug 1602. The upper surface of the dielectric plug 1602 can be polished so that it is substantially coplanar with an upper surface of the gate electrode 1502. In some other examples, the upper surface of the dielectric plug 1602 is substantially coplanar with an upper surface of a dielectric cap layer over the gate electrode 1502. The dielectric plug 1602 extends over the entire width of the gate trench (e.g.,between spacer structures 404 along the first direction), such that the combined structure of gate cut 1302a and dielectric plug 1602 insulates the gate structures on both sides of gate cut 1302a. The dielectric plug 1602 can comprise a single dielectric material, such as silicon nitride, or a dielectric lining and a dielectric filling on the dielectric lining. The dielectric lining can comprise any suitable high-k dielectric material (e.g., silicon nitride), while the dielectric filling can comprise any suitable low-k dielectric material (e.g., silicon dioxide).

[0050] In some embodiments, another gate section 1302b lacks a dielectric plug formed over it, so that the gate electrode 1502 extends over the top of gate section 1302b within the gate groove. Accordingly, the gates of the adjacent semiconductor devices on both sides of gate section 1302b are interconnected. This can be a common circuit configuration for connecting the gate of an NMOS device to the gate of a PMOS device. Furthermore, gate section 1302a can be arranged along a cell boundary.

[0051] As discussed above, the techniques described herein can be used with any type of transistor architecture, such as FinFET or Forksheet, to provide isolation between adjacent devices. Fig. Figure 17 illustrates an exemplary section of an integrated circuit with forksheet devices separated by a gate cut 1302 with a corresponding dielectric plug 1602, according to some embodiments. In the forksheet example, the nanosheets 1701 extend from a dielectric ridge 1702 to form closely adjacent devices. Typically, the nanosheets 1701 on one side of the dielectric ridge 1702 are part of an NMOS device, and the nanosheets 1701 on the opposite side of the dielectric ridge 1702 are part of a PMOS device. A gate dielectric 1704 and a gate electrode 1706 provide the gate structure around the nanosheets 1701. The gate cut 1302 can be positioned at a cell boundary between adjacent forksheet devices.In some embodiments, the dielectric ridge 1702 comprises one or more dielectric materials, such as a dielectric lining and a dielectric filling on the dielectric lining. The dielectric ridge 1702 can be formed prior to the formation of the gate dielectric 1704, so that the gate dielectric 1702 is formed over all exposed surfaces of the dielectric ridge 1702.

[0052] Fig. Figure 18 illustrates an exemplary embodiment of a chip package 1800 according to an embodiment of the present disclosure. As can be seen, the chip package 1800 has one or more dies 1802. One or more dies 1802 can have at least one integrated circuit with semiconductor devices, such as any of the semiconductor devices disclosed herein. In some exemplary configurations, one or more dies 1802 can have any other circuit arrangement used to form an interface with other devices formed on the dies or other devices connected to the chip package 1800.

[0053] As can be further seen, the chip package 1800 has an enclosure 1804 bonded to a package substrate 1806. The enclosure 1804 can be any standard or proprietary enclosure and can, for example, provide electromagnetic shielding and environmental protection for the components of the chip package 1800. The one or more dies 1802 can be conductively coupled to a package substrate 1806 using connections 1808, which can be implemented with any number of standard or proprietary connection mechanisms, such as solder pads, a ball grid array (BGA), pins, or wire bonds, to name a few examples. The package substrate 1806 can be any standard or proprietary package substrate, but in some cases it has a dielectric material with conductive paths (e.g.,including conductive vias and conductors) extending through the dielectric material between the faces of the housing substrate 1806 or between different positions on each face. In some embodiments, the housing substrate 1806 may have a thickness of less than 1 millimeter (e.g., between 0.1 millimeters and 0.5 millimeters), although any number of housing geometries may be used. Additional conductive contacts 1812 may be arranged on an opposite face of the housing substrate 1806 for conductive contacting, for example, a printed circuit board (PCB). One or more vias 1810 extend through a thickness of the housing substrate 1806 to provide conductive paths between one or more connections 1808 and one or more contacts 1812.The vias 1810 are illustrated for the sake of simplicity as single straight pillars through the housing substrate 1806, although other configurations can be used (e.g., Damascene, dual-Damascene, silicon vias, or an intermediate interconnect structure that meanders through the thickness of the substrate 1806 to make contact with one or more intermediate positions within it). In still other embodiments, the vias 1810 are made by several smaller, stacked vias or are staggered at different positions across the housing substrate 1806. In the illustrated embodiment, the contacts 1812 are solder balls (e.g., for contact-bump-based connections or a ball-grid array arrangement), but any suitable housing bonding mechanism can be used (e.g.,Pins in a pin grid array arrangement or contact spots in a contact spot grid array arrangement). In some embodiments, a solder mask is arranged between the contacts 1812 to prevent a short circuit.

[0054] In some embodiments, a potting compound 1814 can be arranged around one or more dies 1802 contained within the housing 1804 (e.g., between the dies 1802 and the housing substrate 1806 as an underfilling material, and between the dies 1802 and the housing 1804 as an overfilling material). Although the dimensions and properties of the potting compound 1814 may vary from one embodiment to another, in some embodiments the thickness of the potting compound 1814 is less than 1 millimeter. Exemplary materials that can be used for the potting compound 1814 include, optionally, epoxy potting compounds. In some cases, the potting compound 1814 is thermally conductive in addition to being electrically insulating. methodology

[0055] Fig. Figure 19 is a flowchart of a method 1900 for forming at least one section of an integrated circuit according to one embodiment. Various operations of the method 1900 can be described in Fig. Figures 2A-16A and 2B-16B are illustrated. However, the correlation of the various operations of Method 1900 with the specific components illustrated in the aforementioned figures is not intended to imply any structural and / or application-related limitations. Rather, the aforementioned figures provide an exemplary embodiment of Method 1900. Other operations may be performed before, during, or after any of the operations of Method 1900. For example, Method 1900 does not explicitly describe all the processes that are performed to form common transistor structures. Some of the operations of Method 1900 may be performed in a different order than the one illustrated.

[0056] According to some embodiments, method 1900 begins with process 1902, in which any number of parallel semiconductor fins are formed. The semiconductor material in the fins can be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins can be formed from a material deposited onto an underlying substrate. In one such exemplary case, a cover layer of silicon germanium (SiGe) can be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from that substrate. In another such example, the fins comprise alternating layers of material (e.g.,Alternating layers of silicon and SiGe enable the formation of nanowires and nanoribbons during a gate formation process. One type of alternating layer is selectively etched away to expose the other type of alternating layer within the channel region, allowing for a subsequent gate-all-around (GAA) process. The alternating layers can be deposited over the entire surface and then etched into fins or deposited into fin-shaped grooves. The fins can also include a cap structure over each fin, which is used to define the fin positions during, for example, a RIE process. The cap structure can be a dielectric material, such as silicon nitride.

[0057] In some embodiments, a dielectric layer is formed around subfin sections of one or more fins. In some embodiments, the dielectric layer extends between each pair of adjacent parallel fins and runs longitudinally in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a section of the substrate, and the dielectric layer can form within the recessed sections of the substrate. Accordingly, the dielectric layer acts as shallow trench insulation (STI) between adjacent fins. The dielectric layer can be any suitable dielectric material, such as silicon dioxide.

[0058] Procedure 1900 continues with step 1904, in which a sacrificial gate and spacer structures are formed over adjacent fins. The sacrificial gate can be structured using a gate masking layer in a strip running orthogonally across the fins (multiple gate masking layers and corresponding sacrificial gates can be formed parallel to each other (e.g., forming a hatched pattern with the fins)). The gate masking layer can be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate can be formed from any suitable material that can be selectively removed at a later time without damaging the semiconductor material of the fins. In one example, the sacrificial gate features polysilicon.The spacer structures can be deposited and then etched back, so that they remain primarily on the sidewalls of any exposed structures. According to some embodiments, the spacer structures can be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0059] Method 1900 continues with step 1906, in which source or drain regions are formed at the ends of the semiconductor regions of each of the fins. Any portions of the fins not protected by the sacrificial gate and the spacer structures can be removed, for example, by using an anisotropic etching process followed by epitaxial growth of the source or drain regions from the exposed ends of the semiconductor layers in the fins. In some embodiments, the source or drain regions are NMOS source or drain regions (e.g., epitaxial silicon) or PMOS source or drain regions (e.g., epitaxial SiGe). An additional dielectric filling can be formed adjacent to the various source or drain regions for additional electrical insulation between adjacent regions. The dielectric filling can also extend over a top surface of the source or drain regions.In some embodiments, conductive top-side contacts can be formed by the dielectric filling to contact one or more of the source or drain regions.

[0060] Procedure 1900 continues with step 1908, in which the sacrificial gate is removed and a gate dielectric is formed. The sacrificial gate can be removed using an isotropic etching process that selectively removes all of the material from the sacrificial gate, thereby exposing the various fins between the set of spacer structures. In the exemplary case using GAA transistors, any sacrificial layers within the exposed fins between the spacer structures can also be removed to expose nanoribbons, nanosheets, or nanowires of semiconductor material.

[0061] The gate dielectric can be formed over the exposed semiconductor regions between the spacer structures. The gate dielectric can have any number of dielectric layers deposited using a CVD process, such as ALD. One or more annealing processes can also be used to influence the elemental composition of the gate dielectric.

[0062] Method 1900 continues with step 1910, where a sacrificial structure is formed over the adjacent fins within the gate trench. The sacrificial structure can comprise any suitable material that can be safely removed at a later time without damaging surrounding materials, such as the gate dielectric. In some examples, the sacrificial structure comprises a layer of aluminum oxide. In other examples, the sacrificial structure comprises a dielectric lining, such as a thin lining of silicon dioxide over the aluminum oxide layer. Generally, the sacrificial structure is conformally deposited over the transistor structures, leaving space between the transistor structures within the gate trench, according to some embodiments. Accordingly, the sacrificial structure can be deposited using CVD or ALD to a final thickness between approximately 5 nm and approximately 15 nm.

[0063] Procedure 1900 continues with Procedure 1912, where a mask material is formed over the sacrificial structure within the gate trench. The mask material can be deposited within the gate trench and subsequently polished until an upper surface of the mask material is substantially coplanar with an upper surface of the spacer structures on either side of the gate trench. In some examples, the mask material is CHM.

[0064] Procedure 1900 continues with Procedure 1914, where a trench is etched through the mask material between adjacent fins, and an exposed section of the sacrificial structure within the trench is further etched. The etched trench can extend through the entire height of the mask material to a depth sufficient to expose a section of the sacrificial structure at the bottom of the trench. Furthermore, the trench spans the entire width of the gate trench to also expose sidewall sections of the sacrificial structure at the edges of the gate trench. A RIE process can be used to etch through the mask material while pausing at the sacrificial structure. The trench can be formed through the mask structure anywhere between adjacent fins along the second direction.

[0065] Once the trench has reached its full depth through the mask material, an additional RIE process can be used to remove the exposed portions of the sacrificial structure within the trench. In some embodiments, the same etching can also be used to remove exposed portions of the gate dielectric within the trench after the removal of the sacrificial structure. In some examples, a different RIE process is used to remove the gate dielectric. In some examples, one or more isotropic etchings are performed to provide more complete removal of the sacrificial structure and / or the gate dielectric on the sidewalls within the trench. The isotropic etching can be a wet etching process or can be performed using RIE.

[0066] Process 1900 continues with Process 1916, where the mask material is removed and a dielectric structure is formed between the adjacent fins. The mask material can be removed using any suitable isotropic etching process, such as an ashing process. The dielectric structure can comprise any suitable dielectric material, such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride. The dielectric structure can be deposited using any suitable deposition technique, such as ALD, CVD, PECVD, flowable dielectric, or spin-on dielectric. In some examples, the dielectric structure comprises a dielectric liner containing silicon nitride or silicon carbonitride and a dielectric filling on the dielectric liner containing silicon dioxide.In some embodiments, the dielectric structure is deposited within the gate trench and subsequently deepened using any suitable isotropic etching process until the upper surface of the sacrificial structure is exposed. Since the dielectric structure fills the space between the sacrificial structure within the gate trench, the dielectric structure is directly self-aligned between the adjacent fins.

[0067] Method 1900 continues with step 1918, where the sacrificial structure is removed and a gate electrode is formed within the gate trench. The sacrificial structure can be removed using any suitable isotropic etching process. The gate electrode can include any number of conductive layers deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD, to name a few examples. In some embodiments, the gate electrode includes a metal filler material along with one or more exitwork layers, resistance-reducing layers, and / or barrier layers. The exitwork layers can, for example, include p-type exitwork materials (e.g., titanium nitride) for PMOS gates or n-type exitwork materials (e.g., titanium aluminum carbide) for NMOS gates.After the formation of the gate structure, the entire structure can be polished or planarized so that the top surface of the gate structure (e.g., the top surface of the gate electrode) is essentially coplanar with the top surface of other semiconductor elements, such as the spacer structures that define the gate trench.

[0068] Method 1900 continues with Process 1920, where a dielectric plug is formed over an upper surface of the dielectric structure. In some embodiments, a depression is etched through a section of the gate electrode to expose an upper surface of the dielectric structure. The depression may be filled with one or more dielectric materials to form the dielectric plug. The upper surface of the dielectric plug may be polished so that it is substantially coplanar with an upper surface of the gate electrode or a dielectric layer above the gate electrode. For example, in some such examples, the upper surface of the dielectric plug is located within a few angstroms of the upper surface of the gate electrode or the dielectric layer above the gate electrode, or is perfectly coplanar.The dielectric plug extends across the entire width of the gate trench (e.g., between the spacer structures along the first direction). The dielectric plug can consist of a single dielectric material, such as silicon nitride, or a dielectric lining and a dielectric filling on the dielectric lining. The dielectric lining can consist of any suitable high-k dielectric material (e.g., silicon nitride), while the dielectric filling can consist of any suitable low-k dielectric material (e.g., silicon dioxide). Exemplary system

[0069] Fig.Figure 20 is an exemplary computing system implemented with one or more of the integrated circuit structures disclosed herein, according to some embodiments of the present disclosure. As can be seen, the computing system 2000 incorporates a mainboard 2002. The mainboard 2002 may include a number of components, including, among others, a processor 2004 and at least one communication chip 2006, each of which may be physically and electrically connected to or otherwise integrated into the mainboard 2002. It is understood that the mainboard 2002 may, for example, be any printed circuit board (PCB), be it a mainboard, a daughterboard mounted on a mainboard, or the only board of the system 2000, etc.

[0070] Depending on its applications, the Computing System 2000 may include one or more other components, which may or may not be physically and electrically coupled to the Mainboard 2002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, power amplifiers, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a loudspeaker, a camera, and a mass storage device (such as a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), and so on).Any of the components included in the Computing System 2000 may include one or more integrated circuit structures or devices configured according to an exemplary embodiment, such as a module containing an integrated circuit on a substrate, the substrate having semiconductor devices including one or more gate cuts that are self-aligned within the gate trench between adjacent devices. In some embodiments, several functions may be integrated into one or more chips (for example, the Communications Chip 2006 may be part of or otherwise integrated into the Processor 2004).

[0071] The Communications Chip 2006 enables wireless communication for transferring data to and from the Computing System 2000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain wires, although in some embodiments they may not. The Communications Chip 2006 can implement any number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), and IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and beyond. The Computing System 2000 can incorporate a variety of communication chips. For example, a first communication chip can be dedicated to wireless communications at closer range, such as WiFi and Bluetooth, and a second communication chip can be dedicated to wireless communications at farther range, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0072] The Processor 2004 of the Computing System 2000 includes an integrated circuit die that is enclosed within the Processor 2004. In some embodiments, the processor's integrated circuit die features an on-board circuit arrangement implemented with one or more semiconductor devices, as described here in various ways. The term "processor" can refer to any device or any part of a device that, for example, processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory.

[0073] The 2006 communication chip can also include an integrated circuit die that is enclosed within the 2006 communication chip. According to some such embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices, as described herein in various ways. In light of this disclosure, it is understood that a multi-standard wireless capability can be directly integrated into the 2004 processor (e.g., if the functionality of any 2006 chips is integrated into the 2004 processor instead of having separate communication chips). It should also be noted that the 2004 processor can be a chipset with such wireless capability. In short, any number of the 2004 processor and / or the 2006 communication chips can be used. Likewise, any chip or chipset can have multiple functions integrated therein.

[0074] In various implementations, the Computing System 2000 can be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal data organizer (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or utilizes one or more integrated circuit structures or devices formed using the disclosed techniques as described herein in various ways.

[0075] It is understood that in some embodiments, the various components of the Computing System 2000 may be combined with or integrated into a system-on-a-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software. Further examples of implementation

[0076] The following examples relate to further embodiments, from which numerous permutations and configurations become apparent.

[0077] Example 1 is an integrated circuit comprising a first semiconductor device and a second semiconductor device. The first semiconductor device has a first semiconductor region extending in a first direction from a first source or drain region, and a first gate structure extending in a second direction across the first semiconductor region, the second direction being different from the first direction. The second semiconductor device has a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction across the second semiconductor region.The spacer structures are located on the sidewalls of the first and second gate structures and extend along the second direction with the first and second gate structures. A gate cut is located between the first and second semiconductor devices and separates the first gate structure from the second gate structure along the second direction. A dielectric plug is located on the upper surface of the gate cut. The gate cut extends along a third direction through at least a portion of the total height of the first and second gate structures. An upper surface of the gate cut is located below an upper surface of the spacer structures. The dielectric plug also separates the first gate structure from the second gate structure along the second direction.

[0078] Example 2 includes the integrated circuit from Example 1, where the gate cut comprises silicon and nitrogen.

[0079] Example 3 includes the integrated circuit of Example 1 or 2, wherein a first distance between the gate cut and an edge of the first semiconductor region closest to the gate cut along the second direction is substantially the same as a second distance between the gate cut and an edge of the second semiconductor region closest to the gate cut along the second direction.

[0080] Example 4 includes the integrated circuit of one of Examples 1-3, where the gate cut does not extend beyond the spacing structures along the first direction.

[0081] Example 5 includes the integrated circuit of one of Examples 1-4, wherein the first gate structure comprises a first gate electrode on a first gate dielectric and the second gate structure comprises a second gate electrode on a second gate dielectric.

[0082] Example 6 includes the integrated circuit of Example 5, wherein the first gate electrode contacts a first side wall of the gate cut and the second gate electrode contacts a second side wall of the gate cut opposite the first side wall, the first and second side walls extending along the first direction.

[0083] Example 7 includes the integrated circuit of Example 6, wherein a third and a fourth side wall of the gate section, extending along the second direction, contact the spacer structures.

[0084] Example 8 includes the integrated circuit of one of Examples 1-7, wherein the first and second semiconductor regions each comprise a plurality of semiconductor nanoribbons.

[0085] Example 9 includes the integrated circuit from Example 8, wherein the multitude of semiconductor nanoribbons comprise germanium, silicon or a combination thereof.

[0086] Example 10 includes the integrated circuit of one of Examples 1-9, wherein the first semiconductor device is a first forksheet device and the second semiconductor device is a second forksheet device.

[0087] Example 11 includes the integrated circuit of one of Examples 1-10, wherein the gate cut comprises a first section directly contacting a first spacing structure of the spacing structures, a second section directly contacting a second spacing structure of the spacing structures, and a third section between the first and second sections, the third section extending beyond the first and second sections along the second direction.

[0088] Example 12 includes the integrated circuit according to one of Examples 1-11, wherein the dielectric plug comprises silicon and oxygen.

[0089] Example 13 includes the integrated circuit according to one of Examples 1-12, wherein an upper surface of the dielectric plug is essentially coplanar with an upper surface of the spacer structures.

[0090] Example 14 is a printed circuit board that incorporates the integrated circuit according to one of Examples 1-13.

[0091] Example 15 is an electronic device comprising a chip package having one or more dies. At least one of the one or more dies comprises a first semiconductor region extending in a first direction from a first source or drain region, a first gate structure extending in a second direction over the second semiconductor region, the second direction being different from the first direction, a second semiconductor region extending in the first direction from a second source or drain region, a second gate structure extending in the second direction over the second semiconductor region, spacer structures on sidewalls of the first and second gate structures extending along the second direction with the first and the spacer gate structures, and a gate interface between the first and second semiconductor devices.The gate section separates the first gate structure from the second gate structure along the second direction, and a dielectric plug is located on the upper surface of the gate section. The gate section extends along a third direction through at least a portion of the total height of the first and second gate structures. An upper surface of the gate section is located below an upper surface of the spacer structures. The dielectric plug also separates the first gate structure from the second gate structure along the second direction.

[0092] Example 16 includes the electronic device according to claim 15, wherein the gate cut comprises silicon and nitrogen.

[0093] Example 17 includes the electronic device of Example 15 or 16, wherein a first distance between the gate cut and an edge of the first semiconductor region closest to the gate cut along the second direction is substantially the same as a second distance between the gate cut and an edge of the second semiconductor region closest to the gate cut along the second direction.

[0094] Example 18 includes the electronic device of one of Examples 15-17, wherein the gate cut does not extend beyond the spacer structures along the first direction.

[0095] Example 19 includes the electronic device of one of Examples 15-18, wherein the first gate structure comprises a first gate electrode on a first gate dielectric and the second gate structure comprises a second gate electrode on a second gate dielectric.

[0096] Example 20 includes the electronic device of Example 19, wherein the first gate electrode contacts a first side wall of the gate cut and the second gate electrode contacts a second side wall of the gate cut opposite the first side wall, the first and second side walls extending along the first direction.

[0097] Example 21 includes the electronic device of Example 20, wherein a third and a fourth side wall of the gate section, extending along the second direction, contact the spacer structures.

[0098] Example 22 includes the electronic device of one of Examples 15-21, wherein the first and second semiconductor regions each comprise a plurality of semiconductor nanoribbons.

[0099] Example 23 includes the electronic device of Example 22, wherein the plurality of semiconductor nanoribbons comprise germanium, silicon or a combination thereof.

[0100] Example 24 includes the electronic device of one of Examples 15-23, wherein the first semiconductor area is part of a first forksheet device and the second semiconductor area is part of a second forksheet device.

[0101] Example 25 includes the electronic device of one of Examples 15-24, wherein the gate section comprises a first section directly contacting a first spacer structure of the spacer structures, a second section directly contacting a second spacer structure of the spacer structures, and a third section between the first and second sections, the third section extending beyond the first and second sections along the second direction.

[0102] Example 26 includes the electronic device according to one of Examples 15-25, wherein the dielectric plug comprises silicon and oxygen.

[0103] Example 27 includes the electronic device according to one of Examples 15-26, wherein an upper surface of the dielectric plug is substantially coplanar with an upper surface of the spacer structures.

[0104] Example 28 includes the electronic device according to one of Examples 15-27, which further comprises a printed circuit board, wherein the chip package is coupled to the printed circuit board.

[0105] Example 29 is a method for forming an integrated circuit. The method includes: forming at least two adjacent fins comprising semiconductor material, the fins extending above a substrate and each extending parallel to each other in a first direction; forming a sacrificial gate extending above the semiconductor material in a second direction different from the first direction; forming spacer structures on sidewalls of the sacrificial gate; removing the sacrificial gate; forming a gate dielectric on the semiconductor material of each of the adjacent fins; forming a sacrificial structure over the adjacent fins; forming a masking material over the sacrificial structure between the spacer structures; etching a trench through the masking material between the adjacent fins such that a portion of the sacrificial structure is exposed on the underside of the trench;Removing a section of the sacrificial structure within the trench to form a depression; removing the masking material and forming a dielectric filling between the adjacent fins and within the depression; removing the sacrificial structure; forming a gate electrode over the gate dielectric on the semiconductor material of each of the adjacent fins, with a section of the gate electrode extending over an upper surface of the dielectric filling; and forming a dielectric plug through the section of the gate electrode such that the dielectric plug contacts the upper surface of the dielectric filling.

[0106] Example 30 includes the procedure of Example 29, wherein forming the sacrificial structure comprises: forming a sacrificial material on the semiconductor material of each of the adjacent fins; and forming a sacrificial lining on the sacrificial material.

[0107] Example 31 includes the method of Example 30, wherein the sacrificial material comprises aluminium and oxygen and the sacrificial lining comprises silicon and oxygen.

[0108] Example 32 includes the procedure of one of Examples 29-31, wherein forming the depression involves using an isotropic etching process to remove the section of the sacrificial structure.

[0109] Example 33 includes the procedure of one of Examples 29-32, wherein the formation of the gate dielectric includes the formation of a dielectric high-k layer.

[0110] Example 34 includes the method of one of Examples 29-33, wherein the formation of the dielectric plug comprises: forming a cavity through the section of the gate electrode; forming a dielectric lining inside the cavity; and forming a dielectric filling on the dielectric lining.

[0111] Example 35 is an integrated circuit comprising a first semiconductor device and a second semiconductor device. The first semiconductor device has a first semiconductor region extending in a first direction from a first source or drain region, and a first gate structure extending in a second direction across the first semiconductor region, the second direction being different from the first direction. The second semiconductor device has a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction across the second semiconductor region.Furthermore, the spacer structures are located on the sidewalls of the first and second gate structures and extend along the second direction with the first and second gate structures. A gate cut is located between the first and second semiconductor devices and separates the first gate structure from the second gate structure along the second direction. The gate cut extends along a third direction through at least one section of the total height of the first and second gate structures. The gate cut includes a first section that directly contacts a first spacer structure, a second section that directly contacts a second spacer structure, and a third section between the first and second sections. The third section extends beyond the first and second sections along the second direction.

[0112] Example 36 includes the integrated circuit of Example 35, wherein the gate cut comprises silicon and nitrogen.

[0113] Example 37 includes the integrated circuit of Example 35 or 36, wherein a first distance between the third section of the gate cut and an edge of the first semiconductor region closest to the third section of the gate cut along the second direction is substantially the same as a second distance between the third section of the gate cut and an edge of the second semiconductor region closest to the third section of the gate cut along the second direction.

[0114] Example 38 includes the integrated circuit of one of Examples 35-37, wherein the gate cut does not extend beyond the spacing structures along the first direction.

[0115] Example 39 includes the integrated circuit of one of Examples 35-38, wherein the first gate structure comprises a first gate electrode on a first gate dielectric and the second gate structure comprises a second gate electrode on a second gate dielectric.

[0116] Example 40 includes the integrated circuit of Example 39, wherein the first gate electrode contacts a first side wall of the gate cut and the second gate electrode contacts a second side wall of the gate cut opposite the first side wall, the first and second side walls extending along the first direction.

[0117] Example 41 includes the integrated circuit of Example 40, wherein a third and a fourth side wall of the gate section, extending along the second direction, contact the spacer structures.

[0118] Example 42 includes the integrated circuit of one of Examples 35-41, wherein the first and second semiconductor regions each comprise a plurality of semiconductor nanoribbons.

[0119] Example 43 includes the integrated circuit of Example 42, wherein the multitude of semiconductor nanoribbons comprise germanium, silicon or a combination thereof.

[0120] Example 44 includes the integrated circuit of one of Examples 35-43, wherein the first semiconductor device is a first forksheet device and the second semiconductor device is a second forksheet device.

[0121] Example 45 includes the integrated circuit of one of Examples 35-44, which further comprises a dielectric plug on an upper surface of the gate cut, wherein the dielectric plug also separates the first gate structure from the second gate structure along the second direction.

[0122] Example 46 includes the integrated circuit of Example 45, wherein the dielectric plug comprises silicon and oxygen.

[0123] Example 47 includes the integrated circuit of Example 45 or 46, wherein an upper surface of the dielectric plug is essentially coplanar with an upper surface of the spacer structures.

[0124] Example 48 is a printed circuit board that incorporates the integrated circuit according to one of Examples 35-47.

[0125] The foregoing description of the embodiments of the disclosure has been set forth for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. In view of this disclosure, many modifications and variations are possible. It is intended that the scope of the disclosure is not limited by this detailed description, but rather by the accompanying claims.

Claims

[1] Integrated circuit comprising: a first semiconductor device comprising a first semiconductor region extending in a first direction from a first source or drain region, and a first gate structure extending in a second direction over the first semiconductor region, wherein the second direction is different from the first direction; a second semiconductor device comprising a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction over the second semiconductor region; Spacing structures on side walls of the first and second gate structures, extending along the second direction with the first and second gate structures; a gate cut between the first and the second semiconductor device, separating the first gate structure from the second gate structure along the second direction, wherein the gate cut extends along a third direction through at least a section of the total height of the first and the second gate structures, with an upper surface of the gate cut located below an upper surface of the spacer structures; and a dielectric plug on the upper surface of the gate cut, wherein the dielectric plug also separates the first gate structure from the second gate structure along the second direction. [2] Integrated circuit according to claim 1, wherein the gate cut comprises silicon and nitrogen. [3] Integrated circuit according to claim 1 or 2, wherein a first distance between the gate cut and an edge of the first semiconductor region closest to the gate cut along the second direction is substantially the same as a second distance between the gate cut and an edge of the second semiconductor region closest to the gate cut along the second direction. [4] Integrated circuit according to one of claims 1 to 3, wherein the gate cut does not extend beyond the spacer structures along the first direction. [5] Integrated circuit according to any one of claims 1 to 4, wherein the first gate structure comprises a first gate electrode on a first gate dielectric and the second gate structure comprises a second gate electrode on a second gate dielectric. [6] Integrated circuit according to claim 5, wherein the first gate electrode contacts a first side wall of the gate section and the second gate electrode contacts a second side wall of the gate section opposite the first side wall, wherein the first and the second side wall extend along the first direction. [7] Integrated circuit according to claim 6, wherein a third and a fourth side wall of the gate section, extending along the second direction, contact the spacer structures. [8] Integrated circuit according to any one of claims 1 to 7, wherein the first and second semiconductor regions each comprise a plurality of semiconductor nanoribbons. [9] Integrated circuit according to any one of claims 1 to 8, wherein the first semiconductor device is a first forksheet device and the second semiconductor device is a second forksheet device. [10] Integrated circuit according to any one of claims 1 to 9, wherein the gate section comprises a first section directly contacting a first spacing structure of the spacing structures, a second section directly contacting a second spacing structure of the spacing structures, and a third section between the first and second sections, wherein the third section extends beyond the first and second sections along the second direction. [11] Integrated circuit according to any one of claims 1 to 10, wherein the dielectric plug comprises silicon and oxygen. [12] Integrated circuit according to any one of claims 1 to 11, wherein an upper surface of the dielectric plug is substantially coplanar with an upper surface of the spacer structures. [13] Printed circuit board comprising the integrated circuit according to any one of claims 1 to 12. [14] Electronic device comprising: a chip package comprising one or more dies, wherein at least one of the one or more dies comprises: a first semiconductor region extending in a first direction from a first source or drain region; a first gate structure extending in a second direction over the first semiconductor region, the second direction being different from the first direction; a second semiconductor region extending in the first direction from a second source or drain region; a second gate structure extending in the second direction across the second semiconductor region; Spacing structures on side walls of the first and second gate structures, extending along the second direction with the first and second gate structures; a gate cut between the first and the second semiconductor region, separating the first gate structure from the second gate structure along the second direction, wherein the gate cut extends along a third direction through at least a section of the total height of the first and second gate structures, with an upper surface of the gate cut located below an upper surface of the spacer structures; and a dielectric plug on the upper surface of the gate cut, wherein the dielectric plug also separates the first gate structure from the second gate structure along the second direction. [15] Electronic device according to claim 14, wherein a first distance between the gate cut and an edge of the first semiconductor region closest to the gate cut along the second direction is substantially the same as a second distance between the gate cut and an edge of the second semiconductor region closest to the gate cut along the second direction. [16] Electronic device according to claim 14 or 15, wherein the first gate structure comprises a first gate electrode on a first gate dielectric and the second gate structure comprises a second gate electrode on a second gate dielectric. [17] Electronic device according to claim 16, wherein the first gate electrode contacts a first side wall of the gate section and the second gate electrode contacts a second side wall of the gate section opposite the first side wall, the first and the second side wall extending along the first direction. [18] Electronic device according to claim 17, wherein a third and a fourth side wall of the gate section, extending along the second direction, contact the spacer structures. [19] Electronic device according to one of claims 14 to 18, wherein the gate section comprises a first section directly contacting a first spacer structure of the spacer structures, a second section directly contacting a second spacer structure of the spacer structures, and a third section between the first and second sections, wherein the third section extends beyond the first and second sections along the second direction. [20] Integrated circuit comprising: a first semiconductor device comprising a first semiconductor region extending in a first direction from a first source or drain region, and a first gate structure extending in a second direction over the first semiconductor region, wherein the second direction is different from the first direction; a second semiconductor device comprising a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction over the second semiconductor region; Spacing structures on side walls of the first and second gate structures, extending along the second direction with the first and second gate structures; and a gate cut between the first and the second semiconductor device, which separates the first gate structure from the second gate structure along the second direction, wherein the gate cut extends along a third direction through at least a section of the total height of the first and the second gate structures, and wherein the gate cut comprises: a first section that directly contacts a first spacing structure of the spacing structures, a second section that directly contacts a second spacing structure of the spacing structures, and a third section between the first and second sections, the third section extending beyond the first and second sections along the second direction. [21] Integrated circuit according to claim 20, wherein a first distance between the third section of the gate cut and an edge of the first semiconductor region that is closest to the third section of the gate cut along the second direction is substantially the same as a second distance between the third section of the gate cut and an edge of the second semiconductor region that is closest to the third section of the gate cut along the second direction. [22] Integrated circuit according to claim 20 or 21, wherein the first gate structure comprises a first gate electrode on a first gate dielectric and the second gate structure comprises a second gate electrode on a second gate dielectric. [23] Integrated circuit according to claim 22, wherein the first gate electrode contacts a first side wall of the gate section and the second gate electrode contacts a second side wall of the gate section opposite the first side wall, wherein the first and the second side wall extend along the first direction. [24] Integrated circuit according to claim 23, wherein a third and a fourth side wall of the gate section, extending along the second direction, contact the spacer structures. [25] Integrated circuit according to one of claims 20 to 24, further comprising a dielectric plug on an upper surface of the gate section, wherein the dielectric plug also separates the first gate structure from the second gate structure along the second direction.

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