DATA STORAGE DEVICE AND METHOD FOR MATHEMATICAL ON-THE-FLY PROCESSING OF DATA READ FROM THE DATA STORAGE DEVICE

Abstract

A data storage device is provided, comprising one or more memories and one or more processors. The one or more processors are configured, individually or in combination, to: receive from a host a record and configuration information for the record, wherein the configuration information includes an identification of logical addresses of values ​​in the record; store the record and the configuration information in one or more memories; receive a read request for the record from the host, wherein the record contains a missing value; and, in response to receiving the read request: perform an on-the-fly interpolation of a value for the missing value from neighboring values ​​of the missing value, identified using the configuration information; and send the record with the interpolated value back to the host.Other embodiments are disclosed.

Description

BACKGROUND

[0001] A data storage device can store a database (or other data structure) that can be read by a host. When processing the database for data analysis, the host may need to perform a value substitution operation (for example, completing and / or replacing missing values ​​in the database if "Not a Number (NaN)" is written instead of a value). After the host has read the database from the data storage device, it can replace the NaN values ​​with some default values, such as 0 or an average column value. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A is a block diagram of a data storage device of one embodiment. Fig. Figure 1B is a block diagram illustrating a storage module of one embodiment. Fig. 1C is a block diagram illustrating a hierarchical storage system of one embodiment. Fig. 2A is a block diagram showing the components of the controller in Fig. Figure 1A illustrates a data storage device according to one embodiment. Fig. 2B is a block diagram showing components of the Fig. Figure 1A illustrates a data storage device according to one embodiment. Fig. Figure 3 is a block diagram of a host and a data storage device of an embodiment. Fig. Figure 4 is an illustration of an architecture of an embodiment. Fig. 5 is a flowchart for a writing operation of one embodiment. Fig. 6 is a flowchart for a reading operation of an embodiment. Fig. Figure 7 is an illustration of an architecture of an embodiment. Fig. Figure 8 is a flowchart of a process of one embodiment. Fig. 9 is a flowchart of a process of one embodiment. DETAILED DESCRIPTION

[0002] The following embodiments generally relate to a data storage device and a method for mathematically processing data read from the data storage device on the fly. In one embodiment, a data storage device is provided comprising one or more memories and one or more processors.The one or more processors are configured individually or in combination to: receive, from a host, a data record and configuration information for the data record, wherein the configuration information includes an identification of logical addresses of values ​​in the data record; store the data record and the configuration information in one or more memories; receive a read request for the data record from the host, wherein the data record contains a missing value; and, in response to receiving the read request: perform an on-the-fly interpolation of a value for the missing value from neighboring values ​​of the missing value, which are identified using the configuration information; and send the data record with the interpolated value back to the host.

[0003] In some embodiments, interpolation is performed using an interpolation method identified by the host.

[0004] In some implementations, the interpolation method is identified by the host in the configuration information.

[0005] In some embodiments, the interpolation method is identified by the host in the read request.

[0006] In some implementations, the configuration information also identifies a format of the data set.

[0007] In some embodiments, the data set and the configuration information are stored in the same memory of one or more storage devices.

[0008] In some embodiments, the data set and the configuration information are stored in different memories of one or more memories.

[0009] In some embodiments, one or more processors are further configured, individually or in combination, to perform a filtering operation on the data set.

[0010] In some embodiments, the configuration information also includes at least one property for the filtering process.

[0011] In some embodiments, the one or more storage devices comprised a three-dimensional storage device.

[0012] In another embodiment, a method is provided that is executed in a data storage device comprising a memory. The method comprises: storing a data record received from a host in the memory; receiving a read request for the data record and a condition for sending the data record to the host from the host; and, in response to receiving the read request: performing an on-the-fly analysis of the data record to determine whether the condition is met; and sending the data record to the host only if the condition is met.

[0013] In some embodiments, on-the-fly analysis involves comparing values ​​in the data set with a threshold to generate discrete values ​​from continuous data.

[0014] In some embodiments, the method further includes performing an on-the-fly interpolation of a missing value in the data set from neighboring values ​​identified using logical address information of values ​​in the data set.

[0015] In some embodiments, interpolation is performed using an interpolation method that is identified by the host when the data set is sent to the data storage device for storage.

[0016] In some embodiments, the interpolation method is identified by the host in the read request.

[0017] In some embodiments, the method further includes performing a filtering process on the data set.

[0018] In some embodiments, the on-the-fly analysis is performed by a mathematical operation module in the data storage device.

[0019] In some embodiments, the sending of the data set is performed by a storage data processing control module in the data storage device.

[0020] In some embodiments, the memory includes a three-dimensional memory.

[0021] In yet another embodiment, a data storage device is provided comprising: a memory; and means for performing an on-the-fly interpolation of a missing value in a data record stored in memory from neighboring values ​​identified using logical address information of values ​​in the data record.

[0022] Other embodiments are possible, and each embodiment can be used alone or in combination with the others. Accordingly, various embodiments will now be described with reference to the accompanying drawings. Designs

[0023] The following embodiments relate to a data storage device (DSD). As used herein, “data storage device” means a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), tape drives, hybrid drives, etc. Details of example DSDs are provided below.

[0024] Examples of data storage devices suitable for use in implementing aspects of these embodiments are given in the Fig. Examples 1A to 1C are shown. Please note that these are only examples and other implementations can also be used. Fig. Figure 1A is a block diagram illustrating the data storage device 100 according to one embodiment. Referring to Fig. 1A The data storage device 100 includes a controller 102 coupled to a non-volatile memory, which may consist of one or more non-volatile memory dies 104. As used herein, the term "die" refers to the collection of non-volatile memory cells and associated switching logic for handling the physical operation of these non-volatile memory cells, formed on a single semiconductor substrate. The controller 102 is connected to a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory die 104. As used herein, the expression "in association with" or "coupled with" may also mean directly connected / coupled with or indirectly connected / coupled with by one or more components, which may or may not be shown or described herein. The communication / coupling may be wired or wireless.

[0025] The Controller 102 (which may be a non-volatile memory controller (e.g., a flash controller, a resistive random-access memory (ReRAM) controller, a phase-change memory (PCM) controller, or a magnetoresistive random-access memory (MRAM) controller)) may include one or more components configured individually or in combination to perform specific functions, including but not limited to those described herein and illustrated in the flowcharts. As shown in Fig. As shown in Figure 2A, the controller 102 can, for example, comprise one or more processors 138, configured individually or in combination to perform functions such as, but not limited to, those described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-transient memories 139 within the controller 102 and / or outside the controller 102 (e.g., in random-access memory (RAM) 116 or fixed-space memory (ROM) 118). As another example, the one or more components can include switching logic, such as, but not limited to, logic gates, switches, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller.

[0026] In one embodiment, the non-volatile memory controller 102 is a device that manages data stored in non-volatile memory and communicates with a host, such as a computer or electronic device, running any suitable operating system. A non-volatile memory controller 102 may have various functionalities in addition to the specific functionality described herein. For example, the non-volatile memory controller may format the non-volatile memory to ensure that the memory functions properly, detect faulty non-volatile memory cells, and allocate replacement cells to replace future failed cells.A portion of the spare cells can be used to store firmware (and / or other metadata used for management and tracking) to operate the non-volatile memory controller and implement other functions. When a host needs to read data from or write data to the non-volatile memory, it can communicate with the non-volatile memory controller. If the host provides a logical address for reading / writing data, the non-volatile memory controller can translate the logical address received from the host into a physical address within the non-volatile memory.The non-volatile memory controller can also perform various memory management functions, such as wear leveling (distributing write operations to avoid the wear and tear of certain memory blocks that would otherwise be repeatedly written to) and automatic memory cleanup (when a block is full, only the valid data pages are moved to a new block so that the full block can be deleted and reused).

[0027] The non-volatile memory die 104 can include any suitable non-volatile storage medium, including resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells can be in the form of solid-state memory cells (e.g., flash memory cells) and can be programmable once, multiple times, or many times. The memory cells can also be single-level cells (SLC), multiple-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or utilize technologies with other memory cell levels now known or later developed. Furthermore, the memory cells can be fabricated in two or three dimensions.

[0028] The interface between controller 102 and non-volatile memory 104 can be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, the data storage device 100 can be a card-based system, such as a Secure Digital card (SD card) or a Micro Secure Digital card (Micro SD card). In an alternative embodiment, the data storage device 100 can be part of an embedded data storage device.

[0029] Although in the Fig. As illustrated in Example 1A, the data storage device 100 (hereafter sometimes referred to as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104. However, the subject matter described here is not limited to having a single storage channel. For example, in some architectures (such as those in the Fig. 1B and Fig. Depending on the controller functions (as shown in Figure 1C), two, four, eight, or more memory channels may be present between the controller and the memory device. In all embodiments described here, more than one channel may be present between the controller and the memory die, even if only a single channel is shown in the drawings.

[0030] Fig. Figure 1B illustrates a storage module 200 that includes multiple non-volatile data storage devices 100. As such, the storage module 200 can include a storage controller 202, which is connected to a host, and to the data storage device 204, which includes a plurality of data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 can be a bus interface, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Double Data Rate (DDR) interface, or a Serial Attached Small-Scale Compute (SAS / SCSI) interface.The storage module 200 can in one embodiment be a solid-state drive (SSD) or a non-volatile dual in-line storage module (NVDIMM), such as those found in server PCs or portable computing devices such as laptops and tablet computers.

[0031] Fig. Figure 1C is a block diagram illustrating a hierarchical storage system. A hierarchical storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding data storage device 204. Host systems 252 can access storage within the storage system 250 via a bus interface. In one embodiment, the bus interface can be a Non-Volatile Memory Express (NVMe) interface or a Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the Fig. System 1C illustrated is a frame-mountable mass storage system that can be accessed by multiple host computers, such as those found in a data center or other location where mass storage is needed.

[0032] With renewed reference to Fig. 2A In this example, the controller 102 also includes a front-end module 108, which provides an interface to a host, a back-end module 110, which provides an interface to one or more non-volatile memory die(s) 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module, which manages buffers in RAM 116 and controls the internal bus arbitration of the controller 102. A module can contain one or more processors or components, as described above. The ROM 118 can store the system startup code. Although they are in Fig. In Figure 2A, the RAM 116 and ROM 118 are shown to be arranged separately from the controller 102. In other embodiments, one or both of the RAM 116 and ROM 118 may be located inside the controller 102. In still other embodiments, parts of the RAM 116 and ROM 118 may be located both inside and outside the controller 102.

[0033] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122, which provide the electrical interface with the host or the next-level storage controller. The choice of host interface 120 type can depend on the type of storage used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serially Attached Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. The host interface 120 typically facilitates the transmission of data, control signals, and timing signals.

[0034] The back-end module 110 includes an error correction code engine (ECC engine) 124, which encodes the data bytes received from the host and decodes the data bytes read from the non-volatile memory, correcting errors. A command sequencer 126 generates command sequences, such as program and erase command sequences, to be transferred to the non-volatile memory die 104. A RAID module (redundant array of independent drives module) 128 manages the generation of RAID parity and the recovery of corrupted data. RAID parity can be used as an additional layer of integrity protection for the data written to the storage device 104. In some cases, the RAID module 128 may be part of the ECC engine 124. A memory interface 130 provides the instruction sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104.In one embodiment, the storage interface 130 can be a double data rate (DDR) interface, such as a toggle mode 200, 400, or 800 interface. In this example, the controller 102 also includes a media management layer 137 and a flash control layer 132, which controls the overall operation of the back-end module 110.

[0035] The data storage device 100 also includes other separate components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may be connected to the controller 102. In alternative embodiments, one or more of the physical layer interface 122, the RAID module 128, the media management layer 138, and the buffer management / bus controller are optional components that are not required in the controller 102.

[0036] Fig. Figure 2B is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes a peripheral switching logic 141 and a non-volatile memory array 142. The non-volatile memory array 142 comprises the non-volatile memory cells used to store data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 further includes a data cache 156, which temporarily stores data and address decoders 148 and 150. The peripheral switching logic 141 in this example includes a state machine 152, which provides status information to the controller 102.The peripheral switching logic 141 can also include one or more components that are configured individually or in combination to perform specific functions, including, but not limited to, those described herein and illustrated in the flowcharts. As in . Fig. As shown in Figure 2B, the memory die 104 can, for example, comprise one or more processors 168, configured individually or in combination to execute computer-readable program code stored in one or more non-transient memories 169 located in the memory array 142 or outside the memory die 104. As another example, the one or more components can include switching logic, such as, but not limited to, logic gates, switches, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller.

[0037] In addition to or instead of the one or more processors 138 (or more generally, components) in the controller 102 and the one or more processors 168 (or more generally, components) in the storage device 104, the data storage device 100 may include another set of one or more processors (or more generally, components). In general, one or more processors (or more generally, components) in the data storage device 100, regardless of their location and number, may be configured individually or in combination to perform various functions, including, but not limited to, those described herein and illustrated in the flowcharts. For example, the one or more processors (or components) may be located in the controller 102, in the storage device 104, and / or elsewhere in the data storage device 100.Furthermore, different functions can be performed using different processors (or components) or combinations of processors (or components). Additionally, means for performing a function can be implemented using a controller that includes one or more components (e.g., processors or the other components described above).

[0038] Referring again to Fig. 2A, the Flash Control Layer 132 (referred to here as the Flash Translation Layer (FTL)) handles flash errors and is connected to the host. Specifically, the FTL, which may be an algorithm in the firmware, is responsible for internal memory management operations and translates write operations from the host into writes to memory 104. The FTL may be necessary because memory 104 may have a limited lifespan, be writeable only in multiples of pages, and / or be unwriteable unless erased as a block. The FTL understands these potential limitations of memory 104, which may not be visible to the host. Accordingly, the FTL attempts to translate write operations from the host into writes to memory 104.

[0039] The FTL can include a logical-physical address mapping (L2P mapping) (sometimes referred to herein as a table or data structure) and allocated cache memory.

[0040] In this way, the FTL translates logical block addresses (“LBAs”) from the host into physical addresses in memory 104. The FTL may include other functions, such as, but not limited to, power-off recovery (so that the FTL's data structures can be restored in the event of a sudden power loss) and wear leveling (so that wear is even across the memory blocks to prevent certain blocks from wearing excessively, which would lead to a higher probability of failure).

[0041] Referring again to the drawings, Fig. Figure 3 shows a block diagram of a host 300 and a data storage device 100 of an embodiment. The host 300 can take any suitable form, including, but not limited to, a computer, a mobile phone, a tablet, a portable device, a digital video recorder, a surveillance system, etc. The host 300 in this embodiment (here a computing device) comprises one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures the one or more processors 330 to perform the actions described herein as being performed by the host 300. Therefore, actions performed by the host 300 are sometimes considered herein to be performed by an application (computer-readable program code) running on the host 300.For example, host 300 can be configured to send data (which may initially be stored in memory 340 of the host) to data storage device 100 for storage in memory 104 of the data storage device.

[0042] As mentioned above, a data storage device can be used to store a database (or other data structure) that can be read by a host. When processing the database for data analysis, the host may need to perform value substitution (for example, completing and / or replacing missing values ​​within the database if "no number (NaN)" is written instead of a value). After the host has read the database from the data storage device, it can replace the NaN values ​​with some default values, such as 0 or an average column value. However, if the host performs the substitution only after the database has been loaded from the data storage device, this can be overhead-intensive and result in latency.Furthermore, the database is rarely saved after the replacement, as it makes sense to keep the original data without replacement in order to distinguish between actual and replaced values.

[0043] In the following embodiments, the controller 102 of the data storage device 100 is configured to optimize this replacement operation by preprocessing missing values ​​of a data structure (e.g., a database) stored in the memory 104 of the data storage device 100. These embodiments can reduce the latency and computational overhead of the value replacement operation. In one example implementation (other implementations may also be used), the controller 102 is configured to optimize the replacement of certain patterns in the stored data structure. The following examples of this embodiment are illustrated using a database; however, it is understood that data structures other than a database may also be used.

[0044] In one example, the controller 102 of the data storage device 100 is configured to mark written interchangeable patterns, enabling the controller 102 to perform an on-the-fly pattern exchange during a read operation. Patterns can take any suitable form, such as, but not limited to, specific characters, regular expressions, or a predefined bit sequence that is not otherwise used in a structure permanently stored in the memory 104 of the data storage device 100. For simplicity, a special character substitute is used in this example; however, it is understood that the claims are not limited in this way unless expressly stated therein.

[0045] Fig. 4 is an example architecture of one embodiment. As in Fig. As shown in Figure 4, the host 300 in this example includes a database write control module 400, which can be provided individually or in combination by one or more processors 330 of the host and executes instruction code stored in one or more memories 340 of the host. As shown in Fig. As also shown in Figure 4, the controller 102 of the data storage device in this example includes a database replacement optimization control module 410, which can be provided by one or more processors 168 of the controller, executing instruction code individually or in combination, stored in memory of the data storage device 100. It is understood that the database write control module 400 and the database replacement optimization control module 410 may be located elsewhere (e.g., in a link layer between the controller 102 and the host 300).

[0046] In this example, if the host writes 300 special characters belonging to the database, the database replacement optimization control module 410 can insert the positions of these special characters as metadata. The positions can be stored in a page-plus-offset format or in a compressed format (for example, if there is a large number of special characters). Specifying the positions of the special characters can speed up the replacement process when reading these characters. Note that in this example, the original data is stored entirely in memory 104, and the replacement is optional. The original data can be read if the database read / write control does not request a replacement. This can also be referred to as a "computer-assisted" read with replacement or a "normal" read without replacement.

[0047] The database write control module 400 can define the special characters or patterns to be used. For example, the sequence for "NaN" in an integer field can be used to indicate a value that is not a number, and the substitute to be used can be a 0 or a 1.

[0048] Fig. Figure 5 is a flowchart 500 illustrating a writing operation of one embodiment. As shown in Fig. As shown in Figure 5, when host 300 writes data to data storage device 100, controller 102 identifies special characters in the data (act 510) and writes metadata regarding the position of the special characters (act 520). Special characters can be defined by host 300 via database write control module 400. The replacement character for each special character, as well as the granularity of the data defined as "characters," can also be defined via this interface.

[0049] Fig. Figure 6 is a flowchart 600 illustrating a writing operation of one embodiment. As shown in Fig. As shown in Figure 6, when the host 300 reads database data from the data storage device 100, the controller 102 (e.g., using the database replacement module 410) identifies special characters based on the previously written metadata (step 610) and replaces the special characters on-the-fly with replacement characters (step 620). In this example, if the database data is set to read, the database replacement module 410 can read the metadata and replace each of the special characters in the read data with the replacement character. The metadata can be stored in non-volatile memory 104 and loaded when the database read / write control module 400 indicates that the database is being read.

[0050] These embodiments offer several advantages. For example, their use can reduce power consumption, latency, and host overhead when reading large databases. Computational storage is in high demand, and these improvements are beneficial.

[0051] There are many alternatives that can be used with these implementations. For example, the database substitution module 410 can be integrated with the values ​​of a key-value database (KV). The special characters can be represented as values ​​of KV pairs, and their substitution can be performed while reading the database.

[0052] If the replacement changes the payload length, the replacement algorithm can indicate this as part of the read operation. For example, it may be necessary to allocate additional buffers during a database read if the payload size increases due to the replacement. Since logical block addresses (LBAs) have a fixed length, padding replacement can be used in this case. For example, whitespace defined in a CSV (Comma-Separated Values) file can be reduced to allow variable-length replacements in a field. If the replacement does not fit in the buffer provided by Host 300, the computation log can specify additional buffer spaces that can be used for this purpose. Additionally, computational reads can be performed with a different memory buffer than standard reads. Implementations are described in the NVMe Computational Programs Command Set Specification, Revision 1.0a, 9.July 2024, to address the communication between the host 300 and the data storage device 100.

[0053] The above embodiments illustrate the concept of internally replacing certain characters / patterns stored in a data storage device. This internal replacement can be part of data preprocessing, which is very common in statistics, data analysis, and machine learning applications. As described above, patterns can be replaced on-the-fly during a host read operation, and these patterns can be special characters, regular expressions, and / or a predefined bit sequence that is not otherwise used in a structure permanently stored in a data storage device.

[0054] A common use case for these embodiments is the completion and / or replacement of missing values ​​within a data structure (e.g., a database), such as replacing NaNs (representing missing values ​​in the database) with either a default value (e.g., 0) or an average column value. Previously, the host performed the replacement after loading the database, resulting in CPU overhead and increased latency. The embodiments described above provided a method for internally completing these values ​​in memory, thereby reducing the latency and computational effort of this common operation. These embodiments were presented in U.S. Application No. 18 / 640,166, which is hereby incorporated by reference.

[0055] However, more complex non-singular preprocessing operations may be required in the host, such as computations performed on multiple data points simultaneously, as well as other mathematical data transformations (e.g., interpolation of missing data points based on the values ​​of neighboring data points (imputation) and filtering of neighboring pixels). The preprocessing of data and its impact on machine learning using the described imputation process have been analyzed, and the effects of different imputation methods may be significant for training and inferencing machine learning models. This issue could become even more critical with the development of the field of artificial intelligence.

[0056] The following embodiments illustrate the concept of applying mathematical transformations to stored data on-the-fly (e.g., during a read operation) within the data storage device during a data read operation. This can include interpolation / extrapolation and threshold comparison. Previously, interpolation, filtering, and other mathematical data processing operations required the involvement of the host, which could lead to additional overhead and require more computing resources.

[0057] While the embodiments above generally served to optimize the replacement of certain patterns by marking written replaceable patterns so that their replacement was readily available on-the-fly in the read path, patterns in the following embodiments can be either special characters, regular expressions, or a predefined bit sequence that is otherwise not used in a structure permanently stored in the data storage device. These embodiments extend the concept described in the embodiments above, enabling not only one-to-one data point conversions but also on-the-fly manipulations of data in memory that affect multiple adjacent data points.

[0058] More specifically, these embodiments can be used to replace missing values ​​(i.e., NANs) with interpolated values ​​from neighboring data points. Furthermore, these embodiments apply on-the-fly data filtering within the data storage device while data is being read from its memory. These embodiments exploit the fact that the data storage device's controller maps physical memory to logical addresses in a way that allows for continuous tracking of related data points and offline imputation based on similarities.

[0059] In an example implementation, the controller 102 of the data storage device 100 can be used for the following embodiments: (1) completing missing values ​​in a data record by imputation based on data in nearby logical addresses within the same logical block address (LBA), (2) smoothing / filtering serial data (e.g., time series, audio signals, images, videos), and (3) generating discrete values ​​from continuous data (e.g., sampling and distorting data based on thresholds from a host-defined range). These embodiments can be used alone or in combination. The relevant data can be either tabular / unstructured data (e.g., for embodiments (1) and (3)) or structured / serial data (e.g., for embodiments (1) and (2)).In embodiments (1) and (2), it may be necessary for the controller 102 of the data storage device to know the original structure of the data. This may involve the cooperation of the host 300 to inform the controller 102 about the format and structure of the data. This notification—together with the controller 102's accessibility to the internal logic-physical (L2P) address tables—can enable the controller 102 to locate the original neighboring data points in order to apply the interpolation / filtering operations mentioned above. Methods for transmitting such structures to the data storage device 100 are defined in the NVMe Computational Programs Command Specification.

[0060] Referring again to the drawings, Fig. 7 a representation of an architecture 700 of an embodiment. As in Fig. As shown in Figure 7, the host 300 in this embodiment comprises a host data processing control module 710 and a destination memory for read results 720. The one or more processors 330 of the host can be used individually or in combination to implement the host data processing control module 710 by executing computer-readable program code / instructions stored in one or more memories 340 of the host 300. The destination memory 720 can be part of one or more memories 340 of the host. The controller 102 of the data storage device 100 comprises a memory data processing control module 730 and a mathematical operation module 740.The one or more processors 138 of the data storage device can be used individually or in combination to implement these modules 730, 740 by executing computer-readable program code / instructions stored in a memory of the data storage device 100.

[0061] In embodiment (1), the imputation of missing data values ​​can be performed based on a method provided by the host 300. Common imputation methods include, for example, linear interpolation, median, mean, and others. When the host 300 writes this numerical data to the data storage device 100, it can specify the properties in a defined configuration (e.g., how many bits each value has, what the fixed-point convention is (sign + magnitude, two's complement), and other relevant properties). The LBA memory location belonging to each data record can also be specified. The host 300 can inform the controller 102, either in this configuration or before reading, which imputation method it wants to apply to the data. The controller 102 can use a small table (e.g.,The relevant property data is stored in memory 104 or in another memory location in the data storage device 100. When the host 300 reads the data, the storage data processing control module 730 in the controller 102 can detect that the LBA area is such that numerical imputation is required. The controller 102 can then read the appropriate configuration and use the mathematical operation module 740 to impute the values ​​accordingly. The process is shown in flowchart 800. Fig. 8 summarized.

[0062] As in Fig. As shown in Figure 8, the host data processing control module 710 defines the configuration for the numeric data set (810) when numeric data is written to memory 104 of the data storage device 100. The storage data processing control module 730 then stores the configuration in a dedicated table (or other data structure) for this LBA area (820). When the host 300 reads the numeric data, the storage data processing control module 730 recognizes that an imputation is required (830), and the mathematical operation module 740 completes the missing values ​​on-the-fly according to the specified configuration (840). The storage data processing control module 730 then writes the read and imputed values ​​to the target memory 720 in the host 300 (850).In embodiment (2), signal processing techniques such as finite impulse response filtering (FIR filtering), smoothing, and various image processing filters can be applied (here collectively referred to as "filtering"). As in the embodiment above, a configuration provided by the Host 300 can include properties relevant to the processing task, such as, but not limited to, the expected resolution, filter type, filter coefficients, and input size.

[0063] In embodiment (3), discrete values ​​can be created from continuous data (e.g., by comparing against thresholds and marking discrete values ​​depending on whether the original value is greater / less / within a predefined range) and transmitted to the host 300. This can be particularly useful when a clause is set by the host 300 (e.g., using the Computational Programs Command Set mentioned above). For example, the host 300 can send a command to generate all data within a given data record that is less than 0. This saves transmissions from the controller 102 to the host 300 and conserves processing power on the host side. There can be different implementations for how exactly the host memory can be filled. One example could be to write zeros into all fields where the data would be less than 0. This effectively implements `written_data = max(0,data)`.Another example might be to leave the host storage spaces empty that are allocated data not matching the clause. In this case, it might also be necessary for the host 300 to initialize the storage spaces to a specified value, with the controller 102 of the data storage device 100 exceeding these values, thus indicating that the read value is above the threshold. The process is shown in flowchart 900. Fig. 9 summarized.

[0064] As in Fig.As shown in Figure 9, the host data processing control module 710 defines the configuration for the numeric data record (910) when numeric data is written to memory 104 of the data storage device 100. The storage data processing control module 730 then stores the configuration in a dedicated table for this LBA area (920). When the host 300 reads the numeric data, the host data processing control module 710 sends a condition to the controller 102 to either transfer or skip data (930). The mathematical operation module 740 checks the state of all data elements and gives a hint to the storage data processing control module 730 (940). The storage data processing control module 730 then writes the data to the host 300 or skips the data to the host memory according to the received indication (950).

[0065] These embodiments offer several advantages. For example, they can be used to reduce power consumption, latency, and host overhead when reading large databases of numerical values. Computational storage is a high-demand area, and the improvements provided by these embodiments are beneficial.

[0066] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices such as dynamic random-access memory (“DRAM”) or static random-access memory (“SRAM”), non-volatile memory devices such as resistive random-access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random-access memory (“FRAM”), and magnetoresistive random-access memory (“MRAM”), as well as other semiconductor devices capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in a NAND or NOR configuration.

[0067] The memory devices can be composed of passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching storage element, such as an antifuse, a phase-change material, etc., and optionally a control element, such as a diode, etc. As another non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0068] Multiple memory elements can be configured to be cascaded or to allow individual access to each element. As a non-restrictive example, flash memory devices in a NAND configuration (NAND memory) typically contain cascaded memory elements. A NAND memory array can be configured to consist of multiple memory strings, where a string comprises multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured to allow individual access to each element, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways as well.

[0069] The semiconductor memory elements, which are located within and / or above a substrate, can be arranged in two or three dimensions, for example as a two-dimensional memory structure or as a three-dimensional memory structure.

[0070] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., in a plane in the xz direction) that is substantially parallel to a major surface of a substrate that supports the memory elements. The substrate can be a wafer over or in which the layer of memory elements is formed, or it can be a support substrate that is attached to the memory elements after they have been formed. As a non-restrictive example, the substrate can contain a semiconductor such as silicon.

[0071] The memory elements can be arranged in an ordered array within a single storage device level, such as in a multitude of rows and / or columns. However, the memory elements can also be arranged in irregular or non-orthogonal configurations. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines.

[0072] A three-dimensional storage array is arranged such that storage elements occupy multiple levels or multiple storage device levels, thereby forming a structure in three dimensions (i.e. in the x, y, and z directions, with the y direction being essentially perpendicular and the x and z directions being essentially parallel to the main surface of the substrate).

[0073] As a non-restrictive example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-restrictive example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column containing multiple memory elements. The columns can be arranged in a two-dimensional configuration, e.g., in an xz-plane, resulting in a three-dimensional array of memory elements with elements on multiple vertically stacked memory levels. Other configurations of memory elements in three dimensions can also form a three-dimensional memory array.

[0074] As a non-restrictive example, in a three-dimensional NAND memory array, the memory elements can be coupled to form a NAND string within a single horizontal (e.g., xz) memory device layer. Alternatively, the memory elements can be coupled to form a vertical NAND string spanning multiple horizontal memory device layers. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory layer, while other strings contain memory elements spanning multiple memory layers. Three-dimensional memory arrays can also be designed in a NOR configuration and in a ReRAM configuration.

[0075] Typically, in a monolithic three-dimensional storage array, one or more storage device layers are formed on top of a single substrate. Optionally, the monolithic three-dimensional storage array can also have one or more storage layers that are at least partially located within the single substrate. As a non-restrictive example, the substrate can be a semiconductor such as silicon. In a monolithic three-dimensional array, the layers that form each storage device layer of the array are usually formed on top of the layers of the underlying storage device layers of the array. However, layers of adjacent storage device layers in a monolithic three-dimensional storage array can be shared, or there can be intermediate layers between the storage device layers.

[0076] On the other hand, two-dimensional arrays can be formed separately and then arranged together to create a non-monolithic, multi-layered storage device. For example, non-monolithic stacked storage devices can be constructed by forming storage layers on separate substrates and then stacking the storage layers on top of each other. The substrates can be made thinner or removed from the storage device layers before stacking, but because the storage device layers are initially formed on separate substrates, the resulting storage arrays are not monolithic three-dimensional storage arrays. Furthermore, multiple two-dimensional or three-dimensional storage arrays (monolithic or non-monolithic) can be formed on separate chips and then bundled together to form a stacked-chip storage device.

[0077] Operating and communicating with memory elements typically requires associated switching logic. Non-restrictive examples include switching logic used to control and manage memory elements to perform functions such as programming and reading. This associated circuitry may reside on the same substrate as the memory elements and / or on a separate substrate. For instance, a memory read / write controller may reside on a separate controller chip and / or on the same substrate as the memory elements.

[0078] The person skilled in the art will recognize that this invention is not limited to the two-dimensional and three-dimensional structures described, but covers all relevant storage structures within the meaning and scope of the invention as described here and understood by the person skilled in the art.

[0079] The foregoing detailed description is to be understood as an illustration of selected forms that the invention may take, and not as a definition of the invention. Only the following claims, including all equivalents, are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any embodiment described herein may be used alone or in combination with one another. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 640,166

[0054] Cited non-patent literature

[0000] the NVMe Computational Programs Command Set Specification, Revision 1.0a, July 9, 2024

[0052]

Claims

[1] Data storage device comprising: one or more storage devices; and one or more processors, individually or in combination, configured to: Receiving a data set and configuration information for the data set from a host, wherein the configuration information includes an identification of logical addresses of values ​​in the data set; Storing the data set and configuration information in one or more storage locations; Receiving a read request for the record from the host, where the record contains a missing value; and in response to receiving the read request: Performing an on-the-fly interpolation of a value for the missing value from neighboring values ​​of the missing value, which are identified using the configuration information; and Sending the data set with the interpolated value to the host. [2] Data storage device according to claim 1, wherein the interpolation is performed using an interpolation method identified by the host. [3] Data storage device according to claim 2, wherein the interpolation method is identified by the host in the configuration information. [4] Data storage device according to claim 2, wherein the interpolation method is identified by the host in the read request. [5] Data storage device according to claim 1, wherein the configuration information further identifies a format of the data set. [6] Data storage device according to claim 1, wherein the data set and the configuration information are stored in the same memory of one or more memory locations. [7] Data storage device according to claim 1, wherein the data set and the configuration information are stored in different storage locations of the one or more storage locations. [8] Data storage device according to claim 1, wherein the one or more processors, individually or in combination, are further configured to perform a filtering operation on the data set. [9] Data storage device according to claim 8, wherein the configuration information further comprises at least one property for the filtering process. [10] Data storage device according to claim 1, wherein one or more storage devices comprise a three-dimensional storage device. [11] Procedure, encompassing: Performing in a data storage device that includes a memory: Storing a data record received from a host in memory; Receiving a read request for the record and a condition to send the record to the host from the host; and in response to receiving the read request: Performing an on-the-fly analysis of the dataset to determine whether the condition is met; and Send the data record to the host only if the condition is met. [12] Method according to claim 11, wherein the on-the-fly analysis comprises comparing values ​​in the data set with a threshold value to generate discrete values ​​from continuous data. [13] The method of claim 11, further comprising performing an on-the-fly interpolation of a value missing in the data set from neighboring values ​​identified using logical address information of values ​​in the data set. [14] Method according to claim 13, wherein the interpolation is performed using an interpolation method that is identified by the host when the data set is sent to the data storage device for storage. [15] Method according to claim 13, wherein the interpolation method is identified by the host in the read request. [16] Method according to claim 11, further comprising performing a filtering process on the data set. [17] Method according to claim 11, wherein the on-the-fly analysis is performed by a mathematical operations module in the data storage device. [18] Method according to claim 11, wherein the sending of the data set is carried out by a storage data processing control module in the data storage device. [19] Method according to claim 11, wherein the memory comprises a three-dimensional memory. [20] Data storage device comprising: a storage facility; and Means of performing on-the-fly interpolation of a missing value in a data set stored in memory from neighboring values ​​identified using logical address information of values ​​in the data set.

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