SEMICONDUCTOR DEVICE

Abstract

A first gate pattern 4 and a first source pattern 6 are linearly parallel to each other along a first edge of an insulating substrate 1. A second gate pattern 5 is rectangular in plan view and extends from the first edge of the insulating substrate 1 to a second edge facing the first edge. A drain pattern 8 is formed to surround at least three edges of the rectangular shape of the second gate pattern 5. A second source pattern 7 is formed along an edge other than the first edge of the insulating substrate 1 to surround the drain pattern 8. A first and a second semiconductor chip group 11, 12 are arranged at positions adjacent to the second source pattern 7. The first and second semiconductor chip groups 11, 12 and the second source pattern 7 are connected via several first source wires 23.

Description

BACKGROUND OF THE INVENTION Area of ​​the invention

[0001] The present disclosure relates to a semiconductor device. Description of the state of the art

[0002] For example, in a semiconductor device described in Japanese patent application no. 2018-117054, a collector wiring on a ceramic substrate and a plurality of sets of an insulated-gate bipolar transistor (IGBT) chip (equivalent to a semiconductor chip) and a diode chip (equivalent to a semiconductor chip) are bonded together by a lower sintered bonding layer above the ceramic substrate. Above the IGBT chip and the diode chip, separate conductive elements are connected by an upper sintered bonding layer, an emitter wiring on the ceramic substrate, the emitter of the IGBT chip and the anode of the diode chip are connected by a bonding wire, and the IGBT chip and the emitter sensing wiring on the ceramic substrate are connected by another bonding wire.The sintered bond layer includes a lower layer and an upper layer, and these layers are separated from each other, resulting in a semiconductor device in which hardly any excessive voltage is generated in a gate wiring section and characteristic defects are reduced.

[0003] In a semiconductor device where a gate, collector (or drain), and emitter (or source) of a semiconductor chip are connected in parallel, a positive feedback circuit is formed by a parasitic capacitance and floating inductance of the semiconductor chip, and parasitic oscillation can occur. Parasitic oscillation is particularly noticeable when the source impedance is large, that is, when the source wire path is long.

[0004] In the semiconductor device described in Japanese patent application 2018-117054, the emitter wiring on the ceramic substrate, the diode chip, and the IGBT chip are arranged in that order, and the distance between the emitter wiring on the ceramic substrate and the IGBT chip is longer, resulting in a longer path for the bond wire connecting the emitter wiring on the ceramic substrate and the IGBT chip (corresponding to the source wire). Therefore, there is a high probability that variations in inductance between the semiconductor chips will cause parasitic oscillations between them, which has proven problematic. SUMMARY

[0005] One objective of the present disclosure is to provide a semiconductor device capable of attenuating a parasitic oscillation caused by an inductance occurring between semiconductor chips.

[0006] A semiconductor device according to the present disclosure comprises an insulating substrate and a first and a second semiconductor chip group. The insulating substrate is configured in a top view as a quadrilateral shape and has a first gate pattern, a second gate pattern, a first source pattern, a second source pattern, and a drain pattern formed on its upper surface. The first and second semiconductor chip groups are mounted on the drain pattern. The first gate pattern and the first source pattern are linearly parallel to each other along the first edge of the insulating substrate. The second gate pattern is configured in a top view as a quadrilateral shape and extends from the first edge of the insulating substrate to the second edge facing the first edge. The drain pattern is configured to surround at least three sides of the quadrilateral shape of the second gate pattern.The second source pattern is formed along a different side than the first side of the insulating substrate to surround the drain pattern. The first and second semiconductor chip groups are positioned adjacent to the second source pattern. The first gate pattern and the second gate pattern are connected via a first gate wire. The second gate pattern and the first and second semiconductor chip groups are connected via multiple second gate wires. The first and second semiconductor chip groups and the second source pattern are connected via multiple first source wires. The first and second semiconductor chip groups are connected via multiple second source wires. The first and second semiconductor chip groups and the first source pattern are connected via multiple third source wires. The semiconductor chips contained in the first and second semiconductor chip groups are connected via multiple fourth source wires.A drain main connection and a source main connection are connected to the drain pattern and the second source pattern, respectively.

[0007] Since the first and second semiconductor chip groups are positioned adjacent to the second source pattern, the lengths of the multiple first source wires connecting the first and second semiconductor chip groups and the second source pattern are reduced. This configuration makes it possible to reduce variations in inductance occurring between the semiconductor chips contained in the first and second semiconductor chip groups, thereby attenuating parasitic oscillation caused by inductance between the semiconductor chips.

[0008] These and other tasks, features, aspects and advantages of the present disclosure will become clearer from the following detailed description of the present disclosure in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic cross-sectional view to illustrate the overall structure of a semiconductor device according to a first preferred embodiment; Fig. Figure 2 is a top view of an insulating substrate contained in the semiconductor device according to the first preferred embodiment; Fig. 3 is an enlarged top view of a first and a second semiconductor chip group mounted on the insulating substrate and a periphery thereof in the first preferred embodiment; Fig. Figure 4 is a top view of an insulating substrate to illustrate the positions of the first and second semiconductor chip groups, the length of a first source wire and the length of a second source wire in the first preferred embodiment; Fig. Figure 5 is a top view of an insulating substrate contained in a semiconductor device according to a second preferred embodiment; Fig. Figure 6 is a top view of an insulating substrate contained in a semiconductor device according to a third preferred embodiment; Fig. Figure 7 is a top view of an insulating substrate contained in a semiconductor device according to a fourth preferred embodiment; Fig. Figure 8 is a top view of an insulating substrate contained in a semiconductor device according to a fifth preferred embodiment; and Fig. Figure 9 is a top view of an insulating substrate contained in a semiconductor device according to a sixth preferred embodiment. DESCRIPTION OF PREFERRED EXECUTION FORMS<Erste Bevorzugte Ausführungsform>

[0009] A first preferred embodiment is described below with reference to the drawings. Fig. Figure 1 is a schematic cross-sectional view to illustrate the overall structure of a semiconductor device 100 according to a first preferred embodiment. Fig. Figure 2 is a top view of an insulating substrate 1 contained in the semiconductor device 100 according to the first preferred embodiment. Fig. Figure 3 is an enlarged top view of a first and a second semiconductor chip group 11, 12 which are mounted on the insulating substrate 1 and the periphery thereof in the first preferred embodiment.

[0010] As in Fig. As shown in Figure 1, the semiconductor device 100 comprises an insulating substrate 1, the first semiconductor chip group 11, the second semiconductor chip group 12, a drain main terminal 31, a source main terminal 32, a housing 41, a sealing material 42, and a cover 43. It should be noted that Fig. Figure 1 shows a schematic cross-section to describe the overall structure of the semiconductor device 100, and not a top view of Fig. 2 corresponds.

[0011] As in Fig. 1 and Fig. As shown in Figure 2, the insulating substrate 1 is formed in a rectangular shape in a top view and comprises a base plate 2, an insulating layer 3 formed on the base plate 2, and a circuit pattern formed on the insulating layer 3. As shown in Fig. As shown in Figure 2, the circuit pattern is made of metal such as copper and includes a first gate pattern 4, a second gate pattern 5, a first source pattern 6, a second source pattern 7 and a drain pattern 8.

[0012] The first gate pattern 4 and the first source pattern 6 are along the first edge (the bottom edge in Fig. 2) of the insulating substrate 1 are formed linearly parallel to each other. The first source pattern 6 and the first gate pattern 4 are arranged in this order from the first side of the insulating substrate 1 to the second edge (the upper edge in Fig. 2), which faces the first edge.

[0013] The second gate pattern 5 is formed in a top view as an elongated quadrilateral shape and extends from the first edge to the second edge of the insulating substrate 1. The second gate pattern 5 is arranged closer to the second edge than the first gate pattern 4.

[0014] Drain pattern 8 is designed such that it surrounds at least three edges of the quadrilateral shape of the second gate pattern 5. More precisely, drain pattern 8 is designed such that it surrounds all four edges of the quadrilateral shape of the second gate pattern 5.

[0015] The second source pattern 7 is formed along a different edge than the first edge of the insulating substrate 1 to surround the drain pattern 8. More precisely, the second source pattern 7 is formed along the second, third, and fourth edges of the insulating substrate 1 to surround the drain pattern 8. A section of the second source pattern 7 on the first edge side and a section of the drain pattern 8 on the first edge side face the first gate pattern 4. Here, the third edge is an edge (left edge in Fig. 2), which connects the first edge and the second edge, and the fourth edge is an edge (right edge in Fig. 2), which faces the third edge.

[0016] As in Fig. As shown in Figure 1, the first and second semiconductor chip groups 11, 12 are mounted on the drain pattern 8 via a bonding material 13, such as solder. More precisely, as shown in Figure 1, Fig. 2 and Fig. Figure 3 shows the first and second semiconductor chip groups 11, 12 arranged at positions adjacent to the second source pattern 7 on the drain pattern 8. The first and second semiconductor chip groups 11, 12 face each other via the second gate pattern 5. More precisely, the first semiconductor chip group 11 is arranged on the third edge and the second semiconductor chip group 12 is arranged on the fourth edge.

[0017] The first and second semiconductor chip groups 11, 12 each comprise several semiconductor chips. The semiconductor chip is made of a wide-bandgap semiconductor such as SiC and is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor chip can be an insulated-gate bipolar transistor (IGBT) or a reverse-conducting IGBT (RC-IGBT), in which an IGBT and a freewheeling diode are formed within a semiconductor substrate.

[0018] As in Fig. As shown in Figure 1, the housing 41 is formed in a rectangular frame shape in plan view and is bonded to the periphery of the insulating substrate 1 with an adhesive (not shown). One end face of the drain main terminal 31 and the source main terminal 32 are attached to the housing 41. The housing 41 is filled with a sealing material 42. The sealing material 42 seals the upper surface of the insulating substrate 1, the first and second semiconductor chip groups 11, 12, and the like. The sealing material 42 is, for example, an epoxy resin. The cover 43, which covers the upper surface of the sealing material 42, is attached to the upper section of the housing 41.

[0019] Next, the connection between the first and second semiconductor chip groups 11, 12 and each circuit pattern is described.

[0020] As in Fig. As shown in Figure 2, the first gate pattern 4 and the second gate pattern 5 are connected via a first gate wire 21. The second gate pattern 5 and the first and second semiconductor chip groups 11, 12 are connected via several second gate wires 22.

[0021] The first and second semiconductor chip groups 11, 12 and the second source pattern 7 are connected via several first source wires 23. The first semiconductor chip group 11 and the second semiconductor chip group 12 are connected in parallel via several second source wires 24. The first and second semiconductor chip groups 11, 12 and the first source pattern 6 are connected via several third source wires 25. The semiconductor chips contained in the first and second semiconductor chip groups 11, 12 are connected via several fourth source wires 26.

[0022] The drain main terminal 31 and the source main terminal 32 are connected to the drain pattern 8 and the second source pattern 7 respectively via a bonding material (not shown), such as solder, a wire (not shown) or the like.

[0023] Next, the positional relationship between the first and second semiconductor chip groups 11, 12 and the length of the associated source wire is described. Fig. Figure 4 is a top view of the insulating substrate 1 to illustrate the positions of the first and second semiconductor chip groups 11, 12, the length of the first source wire 23 and the length of the second source wire 24 in the first preferred embodiment.

[0024] As in Fig. As shown in Figure 4, the semiconductor chips contained in the first semiconductor chip group 11 and the semiconductor chips contained in the second semiconductor chip group 12 have the same structure. The first semiconductor chip group 11 is arranged rotated 180° laterally with respect to the second semiconductor chip group 12. In other words, the first semiconductor chip group 11 is arranged laterally in the opposite direction with respect to the second semiconductor chip group 12. Furthermore, the first semiconductor chip group 11 is arranged with a displacement from the second semiconductor chip group 12 by a length a, which corresponds to 20% of the length of the third edge, in a direction parallel to the third edge of the insulating substrate 1. In the case where the first semiconductor chip group 11 is not arranged with a displacement from the second semiconductor chip group 12, the length of the multiple second source wires 24 is longer.However, since the first semiconductor chip group 11 is arranged with a shift, the several second source wires 24 can be connected in a very short time.

[0025] The lengths b of the several first source wires 23 are equal or, taking into account manufacturing variations, deviate within ± 3%. The lengths c of the several second source wires 24 are equal or, taking into account manufacturing variations, deviate within ± 3%.

[0026] As described above, in the first preferred embodiment, the semiconductor device 100 comprises the insulating substrate 1, which is rectangular in plan view and includes the first gate pattern 4, the second gate pattern 5, the first source pattern 6, the second source pattern 7, and the drain pattern 8, which are formed on the upper surface, and the first and second semiconductor chip groups 11, 12, which are mounted on the drain pattern 8. The first gate pattern 4 and the first source pattern 6 are linearly parallel to each other along the first edge of the insulating substrate 1. The second gate pattern 5 extends from the first edge of the insulating substrate 1 to the second edge facing the first edge and is rectangular in plan view. The drain pattern 8 is configured to surround at least three edges of the rectangular shape of the second gate pattern 5.The second source pattern 7 is formed along a different edge than the first edge of the insulating substrate 1 to surround the drain pattern 8. The first and second semiconductor chip groups 11, 12 are arranged at positions adjacent to the second source pattern 7. The first gate pattern 4 and the second gate pattern 5 are connected via the first gate wire 21. The second gate pattern 5 and the first and second semiconductor chip groups 11, 12 are connected via several second gate wires 22. The first and second semiconductor chip groups 11, 12 and the second source pattern 7 are connected via several first source wires 23. The first semiconductor chip group 11 and the second semiconductor chip group 12 are connected via several second source wires 24. The first and second semiconductor chip groups 11, 12 and the first source pattern 6 are connected via several third source wires 25.The semiconductor chips contained in the first and second semiconductor chip groups 11, 12 are connected via several fourth source wires 26. A drain main connection 31 and a source main connection 32 are connected to the drain pattern 8 and the second source pattern 7, respectively.

[0027] More precisely, the drain pattern 8 is designed to surround the four edges of the square shape of the second gate pattern 5.

[0028] Therefore, the first and second semiconductor chip groups 11, 12 are arranged in positions adjacent to the second source pattern 7, thereby shortening the lengths of the multiple first source wires 23 that connect the first and second semiconductor chip groups 11, 12 and the second source pattern 7. With this configuration, it is possible to reduce variations in inductance occurring between the semiconductor chips contained in the first and second semiconductor chip groups 11, 12, thereby attenuating a parasitic oscillation caused by inductance occurring between the semiconductor chips.

[0029] When multiple second gate wires 22 are used and the second gate pattern 5 is connected to the first and second semiconductor chip groups 11 and 12, respectively, via the two second gate wires 22, it is less likely that an induction will be received than if stitching is performed with a single wire. This can improve the effect as a countermeasure against vibrations.

[0030] The first semiconductor chip group 11 is arranged with a displacement from the second semiconductor chip group 12 by a length corresponding to 20% of the length of the third edge connecting the first and second edges of the insulating substrate 1, in a direction parallel to the third edge. Therefore, the multiple second source wires 24 can be shortened compared to a case in which the first semiconductor chip group 11 is not arranged with a displacement from the second semiconductor chip group 12.

[0031] The lengths of the multiple first source wires 23 are equal or vary within ± 3%. Similarly, the lengths of the multiple second source wires 24 are equal or vary within ± 3%. Therefore, it is possible to further reduce variations in inductance occurring between the semiconductor chips, thereby further attenuating parasitic oscillation caused by inductance occurring between the semiconductor chips.

[0032] Each of the semiconductor chips contained in the first and second semiconductor chip groups 11, 12 is formed from a wide-bandgap semiconductor. Since the semiconductor chip formed from the wide-bandgap semiconductor is driven at high speed, a variation in inductance between the semiconductor chips is likely to occur. However, since the variation in inductance can be reduced by the configuration of the semiconductor device 100 according to the first preferred embodiment, an excellent effect can be demonstrated in this case. <Zweite Bevorzugte Ausführungsform>

[0033] Next, a second preferred embodiment will be described. Fig. Figure 5 is a top view of an insulating substrate 1 contained in a semiconductor device 100 according to the second preferred embodiment. In the second preferred embodiment, the same components as those described in the first preferred embodiment are designated with the same reference numerals, and a description thereof is omitted.

[0034] As in Fig. As shown in Figure 5, in the second preferred embodiment the first gate pattern 4 and the second gate pattern 5 are integrally formed instead of the first gate wire 21. That is, the first gate wire 21 is not used. The drain pattern 8 is configured to surround three edges of the quadrilateral shape of the second gate pattern 5.

[0035] As described above, effects similar to those of the first preferred embodiment can be obtained in the second preferred embodiment. Since the first gate wire 21 can be eliminated, the manufacturing process of the semiconductor device 100 can additionally contribute to a reduction in labor hours. <Dritte Bevorzugte Ausführungsform>

[0036] Next, a third preferred embodiment will be described. Fig. Figure 6 is a top view of an insulating substrate 1 contained in a semiconductor device 100 according to the third preferred embodiment. In the third preferred embodiment, the same components as those described in the first and second preferred embodiments are designated with the same reference numerals, and a description thereof is omitted.

[0037] As in Fig. As shown in Figure 6, in the third preferred embodiment, two configurations of the first preferred embodiment are arranged in parallel. In particular, when the second gate pattern 5 and the drain pattern 8 are formed as a single block, the insulating substrate 1 has two blocks 51, 52 that are adjacent to each other. The two blocks 51, 52 are arranged parallel to the first edge in one direction. The first and second semiconductor chip groups 11, 12 are mounted on the two blocks 51, 52. The second source pattern 7 is formed along a different edge than the first edge to surround the two blocks 51, 52 and extends to a region between the two blocks 51, 52.

[0038] The semiconductor chip groups 11, 12 adjacent to the area on both sides below the first and second semiconductor chip groups 11, 12, and a section extending to the area in the second source pattern 7, are each connected via several sixth source wires 28 and several fifth source wires 27 instead of the several first source wires 23. Therefore, the several first source wires 23 connect the second source pattern 7 and the semiconductor chip groups 11, 12 that are not adjacent to the area below the first and second semiconductor chip groups 11, 12.

[0039] As described above, in the third preferred embodiment not only effects similar to those of the first preferred embodiment can be achieved, but also a large capacity can be achieved. <Vierte Bevorzugte Ausführungsform>

[0040] Next, a fourth preferred embodiment will be described. Fig. Figure 7 is a top view of an insulating substrate 1 contained in a semiconductor device 100 according to the fourth preferred embodiment. In the fourth preferred embodiment, the same components as those described in the first to third preferred embodiments are designated with the same reference numerals, and a description thereof is omitted.

[0041] As in Fig. As shown in Figure 7, in the fourth preferred embodiment, two blocks 51, 52 in the third preferred embodiment are replaced by the configuration of the second preferred embodiment. In particular, in the two blocks 51, 52, the first gate pattern 4 and the second gate pattern 5 are integrally formed instead of the first gate wire 21. The drain pattern 8 is configured to surround three edges of the quadrilateral shape of the second gate pattern 5.

[0042] As described above, effects similar to those of the third preferred embodiment can be obtained in the fourth preferred embodiment. Since the first gate wire 21 can be eliminated, the manufacturing process of the semiconductor device 100 can additionally contribute to a reduction in labor hours. (Fifth Preferred Embodiment>

[0043] Next, a fifth preferred embodiment will be described. Fig. Figure 8 is a top view of an insulating substrate 1 contained in a semiconductor device 100 according to the fifth preferred embodiment. In the fifth preferred embodiment, the same components as those described in the first to fourth preferred embodiments are designated with the same reference numerals, and a description thereof is omitted.

[0044] As in Fig. Figure 8 shows that, in the fifth preferred embodiment, where the second gate pattern 5 and the drain pattern 8 are formed as one block, the insulating substrate 1 comprises three first blocks 53, 54, 55 formed side by side on the first edge side, and three second blocks 56, 57, 58 formed side by side on the second edge side. The three first blocks 53, 54, 55 and the three second blocks 56, 57, 58 face each other.

[0045] The first semiconductor chip group 11 is mounted on each of the first three blocks 53, 54, 55, and the second semiconductor chip group 12 is mounted on each of the second three blocks 56, 57, 58. Therefore, the first and second semiconductor chip groups 11, 12 are also facing each other, and the first and second semiconductor chip groups 11, 12, which are facing each other, are connected in series.

[0046] A first drain main connection 31a is connected to the first three blocks 53, 54, 55. A second drain main connection 31b, which serves as a first source main connection 32a, and a second source main connection 32b are connected to the second three blocks 56, 57, 58.

[0047] As described above, a half-bridge circuit can be configured in the fifth preferred embodiment. By arranging the semiconductor devices 100 in parallel according to the fifth preferred embodiment, a multiphase inverter can also be easily configured. <Sechste Bevorzugte Ausführungsform>

[0048] Next, a sixth preferred embodiment will be described. Fig. Figure 9 is a top view of an insulating substrate 1 contained in a semiconductor device 100 according to the sixth preferred embodiment. In the sixth preferred embodiment, the same components as those described in the first to fifth preferred embodiments are designated with the same reference numerals, and a description thereof is omitted.

[0049] As in Fig. As shown in Figure 9, in the sixth preferred embodiment, the insulating substrate 1 comprises a first ceramic substrate 3a and a second ceramic substrate 3b instead of the insulating layer 3. In other words, the insulating layer 3 is divided into two ceramic substrates 3a, 3b.

[0050] The first three blocks 53, 54, 55 are formed on the first ceramic substrate 3a, and the second three blocks 56, 57, 58 are formed on the second ceramic substrate 3b. The first ceramic substrate 3a and the second ceramic substrate 3b are connected by several first drain wires 35, several second drain wires 36, and several third drain wires 37.

[0051] As described above, in the sixth preferred embodiment, since the insulating layer 3 of the insulating substrate 1 is divided into the two ceramic substrates 3a, 3b, the heat dissipation of the insulating substrate 1 is improved, which can contribute to improving the power cycle lifetime.

[0052] It should be noted that the embodiments can be freely combined and modified or omitted accordingly.

[0053] The following are various aspects of the present revelation described together as appendices. (Appendix 1)

[0054] Semiconductor device, comprising: an insulating substrate formed in a square shape in a top view and featuring a first gate pattern, a second gate pattern, a first source pattern, a second source pattern and a drain pattern formed on a top surface; and a first and a second semiconductor chip group mounted on the drain pattern, where the first gate pattern and the first source pattern are formed linearly parallel to each other along a first edge of the insulating substrate, the second gate pattern is formed in a square shape in the top view and extends from the first edge side of the insulating substrate to a second edge side facing the first edge, the drain pattern is designed in such a way that it surrounds at least three sides of the square shape of the second gate pattern, the second source pattern is formed along a different edge than the first edge of the insulating substrate in order to surround the drain pattern, the first and second semiconductor chip groups are arranged in positions adjacent to the second source pattern, the first gate pattern and the second gate pattern are connected via a first gate wire, the second gate pattern and the first and second semiconductor chip groups are connected via several second gate wires, the first and second semiconductor chip groups and the second source pattern are connected via several first source wires, the first semiconductor chip group and the second semiconductor chip group are connected via several second source wires, the first and second semiconductor chip groups and the first source pattern are connected via several third source wires, the semiconductor chips contained in the first and second semiconductor chip groups are connected via several fourth source wires, and a drain main connection and a source main connection are connected to the drain pattern and the second source pattern, respectively. (Appendix 2)

[0055] Semiconductor device according to Appendix 1, wherein the drain pattern is configured to surround four sides of the square shape of the second gate pattern. (Appendix 3)

[0056] Semiconductor device according to Appendix 1, wherein the first gate pattern and the second gate pattern are integrally formed in place of the first gate wire, and The drain pattern is designed in such a way that it surrounds three edges of the square shape of the second gate pattern. (Appendix 4)

[0057] Semiconductor device according to one of claims 1 to 3, wherein the first semiconductor chip group is arranged in a direction parallel to the third edge with a displacement from the second semiconductor chip group by a length corresponding to 20% of the length of a third edge, wherein the third edge connects the first edge and the second edge of the insulating substrate. (Appendix 5)

[0058] Semiconductor device according to one of claims 1 to 4, wherein the lengths of the several first source wires are equal or have a deviation within ± 3%. (Appendix 6)

[0059] Semiconductor device according to any one of claims 1 to 5, wherein the lengths of the multiple second source wires are equal or have a deviation within ± 3%. (Appendix 7)

[0060] Semiconductor device according to Appendix 1, wherein the second gate pattern and the drain pattern are formed as one of the blocks, the insulating substrate contains two of the blocks that are formed adjacent to each other, the second source pattern extends to an area between two of the blocks, and

[0061] Semiconductor chip groups adjacent to the area on both sides below the first and second semiconductor chip groups, and a section extending to the area in the second source pattern, are each connected via several sixth source wires and several fifth source wires. (Appendix 8)

[0062] Semiconductor device according to Appendix 7, wherein the first gate pattern and the second gate pattern are integrally formed in place of the first gate wire, and The drain pattern is designed in such a way that it surrounds three edges of the square shape of the second gate pattern. (Appendix 9)

[0063] Semiconductor device according to Appendix 1, wherein the second gate pattern and the drain pattern are formed as one of the blocks, the insulating substrate contains three first blocks formed side by side on the first edge side, and three second blocks formed side by side on the second edge side, the first semiconductor chip group is mounted on each of the first three blocks and the second semiconductor chip group is mounted on each of the second three blocks, the drain main connection contains a first and a second drain main connection, the source main connection contains a first and a second source main connection, the first drain main connection is connected to the first three blocks and the second drain main connection, which serves as the first source main connection, and the second source main connection are connected to the three second blocks. (Appendix 10)

[0064] Semiconductor device according to Appendix 9, wherein the insulating substrate comprises a first ceramic substrate and a second ceramic substrate, three of the first blocks are formed on the first ceramic substrates and three of the second blocks are formed on the second ceramic substrates and The first ceramic substrate and the second ceramic substrate are connected by a first drain wire, a second drain wire and a third drain wire. (Appendix 11)

[0065] Semiconductor device according to any one of claims 1 to 10, wherein each of the semiconductor chips contained in the first and second semiconductor chip group is formed from a wide bandgap semiconductor.

[0066] Although the revelation has been shown and described in detail, the foregoing description is illustrative in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be developed. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2018-117054 [0002, 0004]

Claims

[1] Semiconductor device comprising: an insulating substrate (1) formed in a top view in a rectangular shape and having a first gate pattern (4), a second gate pattern (5), a first source pattern (6), a second source pattern (7) and a drain pattern (8) formed on an upper surface; and a first and a second semiconductor chip group (11, 12) mounted on the drain pattern (8), where the first gate pattern (4) and the first source pattern (6) are formed linearly parallel to each other along a first edge of the insulating substrate (1), the second gate pattern (5) is formed in a square shape in the top view and extends from the first edge side of the insulating substrate (1) to a second edge side facing the first edge, the drain pattern (8) is designed such that it surrounds at least three edges of the square shape of the second gate pattern (5), the second source pattern (7) is formed along a different edge than the first edge of the insulating substrate (1) to surround the drain pattern (8), the first and second semiconductor chip groups (11, 12) are arranged in positions adjacent to the second source pattern (7), the first gate pattern (4) and the second gate pattern (5) are connected via a first gate wire (21), the second gate pattern (5) and the first and second semiconductor chip groups (11, 12) are connected via several second gate wires (22), the first and second semiconductor chip groups (11, 12) and the second source pattern (7) are connected via several first source wires (23), the first semiconductor chip group (11) and the second semiconductor chip group (12) are connected via several second source wires (24), the first and second semiconductor chip groups (11, 12) and the first source pattern (6) are connected via several third source wires (25), the semiconductor chips contained in the first and second semiconductor chip groups (11, 12) are connected via several fourth source wires (26), and a drain main connection (31) and a source main connection (32) are connected to the drain pattern (8) and the second source pattern (7), respectively. [2] Semiconductor device according to claim 1, wherein the drain pattern (8) is configured to surround four sides of the square shape of the second gate pattern (5). [3] Semiconductor device according to claim 1, wherein the first gate pattern (4) and the second gate pattern (5) are integrally formed in place of the first gate wire (21), and the drain pattern (8) is designed such that it surrounds three edges of the square shape of the second gate pattern (5). [4] Semiconductor device according to any one of claims 1 to 3, wherein the first semiconductor chip group (11) is arranged in a direction parallel to the third edge with a displacement from the second semiconductor chip group (12) by a length corresponding to 20% of the length of a third edge, wherein the third edge connects the first edge and the second edge of the insulating substrate (1). [5] Semiconductor device according to any one of claims 1 to 4, wherein the lengths of the multiple first source wires (23) are equal or have a deviation within ± 3%. [6] Semiconductor device according to any one of claims 1 to 5, wherein the lengths of the multiple second source wires (24) are equal or have a deviation within ± 3%. [7] Semiconductor device according to claim 1, wherein the second gate pattern (5) and the drain pattern (8) are formed as one of the blocks, the insulating substrate (1) contains two of the blocks (51, 52) which are formed adjacent to each other, the second source pattern (7) extends to an area between two of the blocks (51, 52) and Semiconductor chip groups (11, 12) adjacent to the area on both sides below the first and second semiconductor chip groups (11, 12) and a section extending to the area in the second source pattern (7) are each connected via several sixth source wires (28) and several fifth source wires (27). [8] Semiconductor device according to claim 7, wherein the first gate pattern (4) and the second gate pattern (5) are integrally formed in place of the first gate wire (21) and the drain pattern (8) is designed such that it surrounds three edges of the square shape of the second gate pattern (5). [9] Semiconductor device according to claim 1, wherein the second gate pattern (5) and the drain pattern (8) are formed as one of the blocks, the insulating substrate (1) contains three first blocks (53, 54, 55) formed side by side on the first edge side, and three second blocks (56, 57, 58) formed side by side on the second edge side, the first semiconductor chip group (11) is mounted on each of the first three blocks (53, 54, 55) and the second semiconductor chip group (12) is mounted on each of the second three blocks (56, 57, 58), the drain main connection (31) contains a first and a second drain main connection (31a, 31b), the source main terminal (32) contains a first and a second source main terminal (32a, 32b), the first drain main connection (31a) is connected to the first three blocks (53, 54, 55) and the second drain main connection (31b), which serves as the first source main connection (32a), and the second source main connection (32b) are connected to the three second blocks (56, 57, 58). [10] Semiconductor device according to claim 9, wherein the insulating substrate (1) contains a first ceramic substrate (3a) and a second ceramic substrate (3b), three of the first blocks (53, 54, 55) are formed on the first ceramic substrates (3a) and three of the second blocks (56, 57, 58) are formed on the second ceramic substrates (3b) and the first ceramic substrate (3a) and the second ceramic substrate (3b) are connected by a first drain wire (35), a second drain wire (36) and a third drain wire (37). [11] Semiconductor device according to any one of claims 1 to 10, wherein each of the semiconductor chips contained in the first and second semiconductor chip group (11, 12) is formed from a wide bandgap semiconductor.

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